coreboot-gerrit June 2019

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Change in ...coreboot[master]: nb/x4x: Rename {ddr,fsb}2mhz as {ddr,fsb}_to_mhz
by HAOUAS Elyes (Code Review) 21 Jun '19

21 Jun '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33491 Change subject: nb/x4x: Rename {ddr,fsb}2mhz as {ddr,fsb}_to_mhz ...................................................................... nb/x4x: Rename {ddr,fsb}2mhz as {ddr,fsb}_to_mhz Change-Id: I0442cc5bc54efd7e2c4e5496182c8df85acbcf91 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/x4x/raminit.c M src/northbridge/intel/x4x/raminit_ddr23.c M src/northbridge/intel/x4x/x4x.h 3 files changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/33491/1 diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index bd6536a..8013af9 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -461,9 +461,9 @@ { printk(BIOS_DEBUG, "Selected timings:\n"); printk(BIOS_DEBUG, "\tFSB: %dMHz\n", - fsb2mhz(s->selected_timings.fsb_clk)); + fsb_to_mhz(s->selected_timings.fsb_clk)); printk(BIOS_DEBUG, "\tDDR: %dMHz\n", - ddr2mhz(s->selected_timings.mem_clk)); + ddr_to_mhz(s->selected_timings.mem_clk)); printk(BIOS_DEBUG, "\tCAS: %d\n", s->selected_timings.CAS); printk(BIOS_DEBUG, "\ttRAS: %d\n", s->selected_timings.tRAS); diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index 422b0ff..42fb554 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -32,12 +32,12 @@ #define ME_UMA_SIZEMB 0 -u32 fsb2mhz(u32 speed) +u32 fsb_to_mhz(u32 speed) { return (speed * 267) + 800; } -u32 ddr2mhz(u32 speed) +u32 ddr_to_mhz(u32 speed) { static const u16 mhz[] = { 0, 0, 667, 800, 1067, 1333 }; @@ -578,8 +578,8 @@ reg32 = (u32)((s->selected_timings.CAS + 7 + reg8) * ddr); reg32 = (u32)((reg32 / fsb) << 8); reg32 |= 0x0e000000; - if ((fsb2mhz(s->selected_timings.fsb_clk) / - ddr2mhz(s->selected_timings.mem_clk)) > 2) { + if ((fsb_to_mhz(s->selected_timings.fsb_clk) / + ddr_to_mhz(s->selected_timings.mem_clk)) > 2) { reg32 |= 1 << 24; } MCHBAR32_AND_OR(0x400*i + 0x248, ~0x0f001f00, reg32); diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index a7efb17..5772336 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -378,8 +378,8 @@ void sdram_initialize(int boot_path, const u8 *spd_map); void do_raminit(struct sysinfo *, int fast_boot); void rcven(struct sysinfo *s); -u32 fsb2mhz(u32 speed); -u32 ddr2mhz(u32 speed); +u32 fsb_to_mhz(u32 speed); +u32 ddr_to_mhz(u32 speed); u32 test_address(int channel, int rank); void dqsset(u8 ch, u8 lane, const struct dll_setting *setting); void dqset(u8 ch, u8 lane, const struct dll_setting *setting); -- To view, visit https://review.coreboot.org/c/coreboot/+/33491 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0442cc5bc54efd7e2c4e5496182c8df85acbcf91 Gerrit-Change-Number: 33491 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 3

Change in ...coreboot[master]: mainboard/facebook/fbg1701: Remove unused includes
by Frans Hendriks (Code Review) 21 Jun '19

21 Jun '19

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33574 Change subject: mainboard/facebook/fbg1701: Remove unused includes ...................................................................... mainboard/facebook/fbg1701: Remove unused includes Files onboard.h and mainboard.h are not used for building. Remove these files as include. BUG=N/A TEST=Build and boot embedded Linux 4.20 on Facebook FBG-1701 Change-Id: Ifeb0047357e641cbe1affbbaf5402213802c774c Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/mainboard/facebook/fbg1701/mainboard.c 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/33574/1 diff --git a/src/mainboard/facebook/fbg1701/mainboard.c b/src/mainboard/facebook/fbg1701/mainboard.c index ff2564d..8524b24 100644 --- a/src/mainboard/facebook/fbg1701/mainboard.c +++ b/src/mainboard/facebook/fbg1701/mainboard.c @@ -17,8 +17,6 @@ */ #include <device/device.h> -#include "onboard.h" -#include "mainboard.h" /* * Declare the resources we are using -- To view, visit https://review.coreboot.org/c/coreboot/+/33574 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifeb0047357e641cbe1affbbaf5402213802c774c Gerrit-Change-Number: 33574 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

3 2

Change in ...coreboot[master]: mainboard/facebook/fbg1701/fadt.c: Use asl_revision
by Frans Hendriks (Code Review) 21 Jun '19

21 Jun '19

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33423 Change subject: mainboard/facebook/fbg1701/fadt.c: Use asl_revision ...................................................................... mainboard/facebook/fbg1701/fadt.c: Use asl_revision Fix value of 1 is used for asl_compiler_revision. Use asl_revision for this. BUG=N/A TEST=booting Linux 4.20 kernel on Facebook FBG1701 Change-Id: Iffd8fe637d4669b7099fb6eafc9873560502bf80 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/mainboard/facebook/fbg1701/fadt.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/33423/1 diff --git a/src/mainboard/facebook/fbg1701/fadt.c b/src/mainboard/facebook/fbg1701/fadt.c index 73adfad..7814106 100644 --- a/src/mainboard/facebook/fbg1701/fadt.c +++ b/src/mainboard/facebook/fbg1701/fadt.c @@ -16,6 +16,7 @@ */ #include <soc/acpi.h> +#include <version.h> void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) { @@ -28,7 +29,7 @@ memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); - header->asl_compiler_revision = 1; + header->asl_compiler_revision = asl_revision; fadt->firmware_ctrl = (unsigned long) facs; fadt->dsdt = (unsigned long) dsdt; -- To view, visit https://review.coreboot.org/c/coreboot/+/33423 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iffd8fe637d4669b7099fb6eafc9873560502bf80 Gerrit-Change-Number: 33423 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/skylake: Clean up Kconfig
by Arthur Heymans (Code Review) 21 Jun '19

21 Jun '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33561 Change subject: soc/intel/skylake: Clean up Kconfig ...................................................................... soc/intel/skylake: Clean up Kconfig This does the following: - select MAINBOARD_USES_FSP2_0 on Kabylake (does not support FSP1.1) - Remove stale Kconfig option on intel/saddlebrook - select SOC_INTEL_KABYLAKE on intel/kblrvp Change-Id: I64f48eeb00150aea039d533b0ac471fdd8483b90 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/asrock/h110m/Kconfig M src/mainboard/google/eve/Kconfig M src/mainboard/google/fizz/Kconfig M src/mainboard/google/poppy/Kconfig M src/mainboard/intel/kblrvp/Kconfig M src/mainboard/intel/saddlebrook/Kconfig M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/Makefile.inc 8 files changed, 8 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/33561/1 diff --git a/src/mainboard/asrock/h110m/Kconfig b/src/mainboard/asrock/h110m/Kconfig index 3d21113..487c90e 100644 --- a/src/mainboard/asrock/h110m/Kconfig +++ b/src/mainboard/asrock/h110m/Kconfig @@ -11,7 +11,6 @@ select INTEL_INT15 select SOC_INTEL_KABYLAKE select SKYLAKE_SOC_PCH_H - select MAINBOARD_USES_FSP2_0 select GENERIC_SPD_BIN select SUPERIO_NUVOTON_NCT6791D select SUPERIO_NUVOTON_NCT6776_COM_A diff --git a/src/mainboard/google/eve/Kconfig b/src/mainboard/google/eve/Kconfig index f7fb9c6..022493c 100644 --- a/src/mainboard/google/eve/Kconfig +++ b/src/mainboard/google/eve/Kconfig @@ -19,7 +19,6 @@ select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_I2C_TPM_CR50 select MAINBOARD_HAS_TPM2 - select MAINBOARD_USES_FSP2_0 select SOC_INTEL_KABYLAKE config VBOOT diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig index acaf8a6..b05cb6c 100644 --- a/src/mainboard/google/fizz/Kconfig +++ b/src/mainboard/google/fizz/Kconfig @@ -17,7 +17,6 @@ select INTEL_GMA_HAVE_VBT select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_CHROMEOS - select MAINBOARD_USES_FSP2_0 select NO_FADT_8042 select SOC_INTEL_KABYLAKE select MAINBOARD_HAS_SPI_TPM_CR50 diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index 6bc8269..e2ffe71 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -13,7 +13,6 @@ select INTEL_GMA_HAVE_VBT if BOARD_GOOGLE_NAMI select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_CHROMEOS - select MAINBOARD_USES_FSP2_0 select SOC_INTEL_KABYLAKE select MAINBOARD_HAS_TPM2 diff --git a/src/mainboard/intel/kblrvp/Kconfig b/src/mainboard/intel/kblrvp/Kconfig index 52cee2d..c0737cb 100644 --- a/src/mainboard/intel/kblrvp/Kconfig +++ b/src/mainboard/intel/kblrvp/Kconfig @@ -9,9 +9,8 @@ select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select SOC_INTEL_COMMON_BLOCK_HDA_VERB if !BOARD_INTEL_KBLRVP8 - select SOC_INTEL_SKYLAKE + select SOC_INTEL_KABYLAKE select SKYLAKE_SOC_PCH_H if BOARD_INTEL_KBLRVP8 || BOARD_INTEL_KBLRVP11 - select MAINBOARD_USES_FSP2_0 select MAINBOARD_HAS_CHROMEOS select GENERIC_SPD_BIN select MAINBOARD_HAS_LPC_TPM diff --git a/src/mainboard/intel/saddlebrook/Kconfig b/src/mainboard/intel/saddlebrook/Kconfig index f2b7344..934c15a 100644 --- a/src/mainboard/intel/saddlebrook/Kconfig +++ b/src/mainboard/intel/saddlebrook/Kconfig @@ -29,14 +29,10 @@ select SOC_INTEL_SKYLAKE select SUPERIO_NUVOTON_NCT6776 select SUPERIO_NUVOTON_NCT6776_COM_A - select SADDLEBROOK_USES_FSP1_1 select HAVE_CMOS_DEFAULT select MAINBOARD_USES_IFD_GBE_REGION select USE_INTEL_FSP_MP_INIT -config SADDLEBROOK_USES_FSP1_1 - bool "FSP driver 1.1" - config IRQ_SLOT_COUNT int default 18 diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 626b5f8..2c88e05 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -1,16 +1,19 @@ +config SOC_INTEL_COMMON_SKYLAKE_BASE + config SOC_INTEL_SKYLAKE bool + select SOC_INTEL_COMMON_SKYLAKE_BASE help Intel Skylake support config SOC_INTEL_KABYLAKE bool - default n - select SOC_INTEL_SKYLAKE + select SOC_INTEL_COMMON_SKYLAKE_BASE + select MAINBOARD_USES_FSP2_0 help Intel Kabylake support -if SOC_INTEL_SKYLAKE +if SOC_INTEL_COMMON_SKYLAKE_BASE config CPU_SPECIFIC_OPTIONS def_bool y diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index e9f555f..0a2839e 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -1,4 +1,4 @@ -ifeq ($(CONFIG_SOC_INTEL_SKYLAKE),y) +ifeq ($(CONFIG_SOC_INTEL_COMMON_SKYLAKE_BASE),y) subdirs-y += nhlt subdirs-y += romstage -- To view, visit https://review.coreboot.org/c/coreboot/+/33561 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I64f48eeb00150aea039d533b0ac471fdd8483b90 Gerrit-Change-Number: 33561 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/skylake: Remove ROMCCFLAGS
by Arthur Heymans (Code Review) 21 Jun '19

21 Jun '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33556 Change subject: soc/intel/skylake: Remove ROMCCFLAGS ...................................................................... soc/intel/skylake: Remove ROMCCFLAGS This is never used. Change-Id: I414acc38f72e206eb48cfd98214985c320862c91 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/skylake/Makefile.inc 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/33556/1 diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index e9f555f..04ad8e2 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -106,6 +106,4 @@ # Currently used for microcode path. CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(MAINBOARDDIR) -ROMCCFLAGS := -mcpu=p4 -fno-simplify-phi -O2 - endif -- To view, visit https://review.coreboot.org/c/coreboot/+/33556 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I414acc38f72e206eb48cfd98214985c320862c91 Gerrit-Change-Number: 33556 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 2

Change in ...coreboot[master]: src/security/vboot: Remove useless 'const'
by HAOUAS Elyes (Code Review) 21 Jun '19

21 Jun '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33540 Change subject: src/security/vboot: Remove useless 'const' ...................................................................... src/security/vboot: Remove useless 'const' Change-Id: I3b5ca272abffe46c6a63251cf4905780f87a6836 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/security/vboot/misc.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/33540/1 diff --git a/src/security/vboot/misc.h b/src/security/vboot/misc.h index acb6dbb..725f5fd 100644 --- a/src/security/vboot/misc.h +++ b/src/security/vboot/misc.h @@ -53,7 +53,7 @@ /* * Source: security/vboot/common.c */ -struct vboot_working_data * const vboot_get_working_data(void); +struct vboot_working_data *vboot_get_working_data(void); void vboot_init_work_context(struct vb2_context *ctx); void vboot_finalize_work_context(struct vb2_context *ctx); struct vb2_shared_data *vboot_get_shared_data(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/33540 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b5ca272abffe46c6a63251cf4905780f87a6836 Gerrit-Change-Number: 33540 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: qcs405: Update bootblock size
by Nitheesh Sekar (Code Review) 21 Jun '19

21 Jun '19

Nitheesh Sekar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33159 Change subject: qcs405: Update bootblock size ...................................................................... qcs405: Update bootblock size Increase the size of bootblock from 96K to 128K. Change-Id: Ifc6e7239ed2978a8490fa229945ebd5ed9182298 Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/mainboard/google/mistral/chromeos.fmd 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/33159/1 diff --git a/src/mainboard/google/mistral/chromeos.fmd b/src/mainboard/google/mistral/chromeos.fmd index 76cdd50..4d5f666 100644 --- a/src/mainboard/google/mistral/chromeos.fmd +++ b/src/mainboard/google/mistral/chromeos.fmd @@ -16,7 +16,7 @@ FLASH@0x0 8M { WP_RO 4M { RO_SECTION 0x204000 { - BOOTBLOCK 96K + BOOTBLOCK 128K COREBOOT(CBFS) FMAP@0x200000 0x1000 GBB 0x2f00 -- To view, visit https://review.coreboot.org/c/coreboot/+/33159 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc6e7239ed2978a8490fa229945ebd5ed9182298 Gerrit-Change-Number: 33159 Gerrit-PatchSet: 1 Gerrit-Owner: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/hatch: Do not pull down GPP_F2 internally
by Philip Chen (Code Review) 21 Jun '19

21 Jun '19

Philip Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33583 Change subject: mb/google/hatch: Do not pull down GPP_F2 internally ...................................................................... mb/google/hatch: Do not pull down GPP_F2 internally There is already an external pull-up/down resistor tied to this pin to identify if the board is single-channel or dual-channel memory SKU. BUG=b:135496271 BRANCH=none TEST=build Signed-off-by: Philip Chen <philipchen(a)google.com> Change-Id: Ie218657fd9dde113ab26cf5551d1dff1b6e392b6 --- M src/mainboard/google/hatch/variants/baseboard/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/33583/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 0b66075..c135d70 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -284,7 +284,7 @@ /* F1 : WWAN_RESET_1V8_ODL */ PAD_CFG_GPO(GPP_F1, 1, DEEP), /* F2 : MEM_CH_SEL */ - PAD_CFG_GPI(GPP_F2, DN_20K, PLTRST), + PAD_CFG_GPI(GPP_F2, NONE, PLTRST), /* F3 : GPP_F3 ==> NC */ PAD_NC(GPP_F3, NONE), /* F4 : CNV_BRI_DT */ -- To view, visit https://review.coreboot.org/c/coreboot/+/33583 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie218657fd9dde113ab26cf5551d1dff1b6e392b6 Gerrit-Change-Number: 33583 Gerrit-PatchSet: 1 Gerrit-Owner: Philip Chen <philipchen(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: x86/smmstub: Fix compiling with external toolchains
by Arthur Heymans (Code Review) 21 Jun '19

21 Jun '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30504 Change subject: x86/smmstub: Fix compiling with external toolchains ...................................................................... x86/smmstub: Fix compiling with external toolchains Change-Id: I298d24d54b8fb27da96257ccda65b7fbee988ebb Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/smm/Makefile.inc 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/30504/1 diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index 32f5ea7..e6add1d 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -47,8 +47,8 @@ # SMM Stub Module. The stub is used as a trampoline for relocation and normal # SMM handling. -$(obj)/smmstub/smmstub.o: $$(smmstub-objs) - $(CC_smmstub) $(CFLAGS_smmstub) -nostdlib -r -o $@ $^ +$(obj)/smmstub/smmstub.o: $$(smmstub-objs) $(COMPILER_RT_smmstub) + $(LD_smmstub) -nostdlib -r -o $@ $(COMPILER_RT_FLAGS_smmstub) --whole-archive --start-group $(smmstub-objs) --no-whole-archive $(COMPILER_RT_smmstub) --end-group # Link the SMM stub module with a 0-byte heap. ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) -- To view, visit https://review.coreboot.org/c/coreboot/+/30504 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I298d24d54b8fb27da96257ccda65b7fbee988ebb Gerrit-Change-Number: 30504 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mediatek/mt8183: modify vproc12 voltage
by hsin-hsiung wang (Code Review) 21 Jun '19

21 Jun '19

hsin-hsiung wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33168 Change subject: mediatek/mt8183: modify vproc12 voltage ...................................................................... mediatek/mt8183: modify vproc12 voltage Modify correct vproc12 register to set processor voltage. BUG=b:80501386 BRANCH=none Test=Boots correctly on Kukui Change-Id: I13867b11c44019875e0ed607343197950a3b38b2 Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang(a)mediatek.com> --- M src/soc/mediatek/mt8183/mt6358.c 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/33168/1 diff --git a/src/soc/mediatek/mt8183/mt6358.c b/src/soc/mediatek/mt8183/mt6358.c index 7054243..1258c3d 100644 --- a/src/soc/mediatek/mt8183/mt6358.c +++ b/src/soc/mediatek/mt8183/mt6358.c @@ -496,8 +496,10 @@ {0x1B6C, 0x6, 0x6, 0}, /* Vproc11/Vproc12 to 1.05V */ + /* [6:0]: RG_BUCK_VPROC11_VOSEL */ {0x13a6, 0x58, 0x7F, 0}, - {0x140a, 0x58, 0x7F, 0}, + /* [6:0]: RG_BUCK_VPROC12_VOSEL */ + {0x1426, 0x58, 0x7F, 0}, }; static struct pmic_setting lp_setting[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/33168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13867b11c44019875e0ed607343197950a3b38b2 Gerrit-Change-Number: 33168 Gerrit-PatchSet: 1 Gerrit-Owner: hsin-hsiung wang <hsin-hsiung.wang(a)mediatek.com> Gerrit-MessageType: newchange

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coreboot-gerrit June 2019