coreboot-gerrit June 2019

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Change in ...coreboot[master]: mb/asrock/h110m: Correct Kconfig symbol selection
by Felix Held (Code Review) 21 Jun '19

21 Jun '19

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33439 ) Change subject: mb/asrock/h110m: Correct Kconfig symbol selection ...................................................................... Patch Set 2: Code-Review+1 only +1 from me for now, so that it won't accidentally be merged before the other patch. when the other patch also has its +2, I'll also +2 this one -- To view, visit https://review.coreboot.org/c/coreboot/+/33439 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f3fde161844f919b070f2b6ce7e106411439a9a Gerrit-Change-Number: 33439 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Maxim Polyakov <m.poliakov(a)yahoo.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 20 Jun 2019 22:48:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: superio/nuvoton/nct6791d: Add symbol to select COM port
by Felix Held (Code Review) 21 Jun '19

21 Jun '19

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33640 ) Change subject: superio/nuvoton/nct6791d: Add symbol to select COM port ...................................................................... Patch Set 1: Code-Review+1 (2 comments) https://review.coreboot.org/#/c/33640/1/src/superio/nuvoton/common/early_se… File src/superio/nuvoton/common/early_serial.c: https://review.coreboot.org/#/c/33640/1/src/superio/nuvoton/common/early_se… PS1, Line 73: Route GPIO8 pin group to COM A isn't it the other way around? COM A gets routed to the pins of that GPIO group https://review.coreboot.org/#/c/33640/1/src/superio/nuvoton/common/early_se… PS1, Line 74: pnp_write_config(dev, 0x2a, 0x00); hmm, would it be better to only modify the bits corresponding to the serial port pinmux? -- To view, visit https://review.coreboot.org/c/coreboot/+/33640 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62dc18810026f9b1550da19950f66af605600ec8 Gerrit-Change-Number: 33640 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Maxim Polyakov <m.poliakov(a)yahoo.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 20 Jun 2019 22:46:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: superio/nuvoton/nct6776: Make Kconfig symbol dependent
by Angel Pons (Code Review) 20 Jun '19

20 Jun '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33440 ) Change subject: superio/nuvoton/nct6776: Make Kconfig symbol dependent ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/33440 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c52d596080360bf3fc25265749ced66ec44f5dc Gerrit-Change-Number: 33440 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 20 Jun 2019 18:30:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/asrock/h110m: Correct Kconfig symbol selection
by Angel Pons (Code Review) 20 Jun '19

20 Jun '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33439 ) Change subject: mb/asrock/h110m: Correct Kconfig symbol selection ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/33439 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f3fde161844f919b070f2b6ce7e106411439a9a Gerrit-Change-Number: 33439 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Maxim Polyakov <m.poliakov(a)yahoo.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 20 Jun 2019 18:29:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: superio/nuvoton/nct6791d: Add symbol to select COM port
by Angel Pons (Code Review) 20 Jun '19

20 Jun '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33640 ) Change subject: superio/nuvoton/nct6791d: Add symbol to select COM port ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/33640 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62dc18810026f9b1550da19950f66af605600ec8 Gerrit-Change-Number: 33640 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Comment-Date: Thu, 20 Jun 2019 18:28:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: {drivers,soc/intel/braswell}: Implement C_ENVIRONMENT_BOOTBLOCK support
by Matt DeVillier (Code Review) 20 Jun '19

20 Jun '19

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29662 ) Change subject: {drivers,soc/intel/braswell}: Implement C_ENVIRONMENT_BOOTBLOCK support ...................................................................... Patch Set 47: > I assume you used the downstream FSP binary for this test? Please also > mention your post-code findings here for reference. yes, using the Google BSW FSP binary. last post codes seen were 20 90 42 43 -- To view, visit https://review.coreboot.org/c/coreboot/+/29662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c Gerrit-Change-Number: 29662 Gerrit-PatchSet: 47 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: York Yang <yyang024(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 20 Jun 2019 16:10:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/braswell/smbus.c: Add support for i2c block write
by Frans Hendriks (Code Review) 20 Jun '19

20 Jun '19

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33225 Change subject: soc/intel/braswell/smbus.c: Add support for i2c block write ...................................................................... soc/intel/braswell/smbus.c: Add support for i2c block write Intel Braswell supports i2c block writes using SMBus controller. i2c_block_write() is added to configure SMBus controller in I2C mode before calling do_i2c_block_write(). Add smbus.c to ramstage. BUG=N/A TEST=Config eDP for LCD display on Facebook FBG-1701 Change-Id: I50c1a03f624b3ab3b987d4f3b1d15dac4374e48a Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/soc/intel/braswell/Makefile.inc M src/soc/intel/braswell/smbus.c 2 files changed, 34 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/33225/1 diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc index e479a3c..a7d6297 100644 --- a/src/soc/intel/braswell/Makefile.inc +++ b/src/soc/intel/braswell/Makefile.inc @@ -30,6 +30,7 @@ ramstage-y += emmc.c ramstage-y += gpio.c ramstage-y += gfx.c +ramstage-y += smbus.c ramstage-y += gpio_support.c ramstage-y += iosf.c diff --git a/src/soc/intel/braswell/smbus.c b/src/soc/intel/braswell/smbus.c index 7e1b0df..f849926 100644 --- a/src/soc/intel/braswell/smbus.c +++ b/src/soc/intel/braswell/smbus.c @@ -3,6 +3,7 @@ * * Copyright (C) 2017 Intel Corporation. * Copyright (C) 2019 3mdeb + * Copyright (C) 2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,6 +17,11 @@ #include <device/early_smbus.h> #include <soc/iomap.h> +#include <soc/pci_devs.h> +#include <device/pci_def.h> +#include <device/pci_type.h> +#include <device/pci_ops.h> +#include <soc/smbus.h> #include <southbridge/intel/common/smbus.h> u8 smbus_read_byte(u32 smbus_dev, u8 addr, u8 offset) @@ -27,3 +33,30 @@ { return do_smbus_write_byte(SMBUS_BASE_ADDRESS, addr, offset, value); } + +int i2c_block_write(u8 smbus_devnr, u8 smbus_func, unsigned int device, u8 cmd, + u32 bytes, const u8 *buf) +{ +#ifdef __SIMPLE_DEVICE__ + pci_devfn_t dev = PCI_DEV(0, SMBUS_DEV, SMBUS_FUNC); +#else + struct device *dev = pcidev_on_root(SMBUS_DEV, SMBUS_FUNC); +#endif + u32 reg; + u32 smb_ctlr_reg; + int status; + + /* SMBus I/O BAR */ + reg = pci_read_config32(dev, PCI_BASE_ADDRESS_4) & 0xFFFFFFFE; + + /* Enable I2C_EN bit in HOSTC register */ + smb_ctlr_reg = pci_read_config32(dev, HOSTC); + pci_write_config32(dev, HOSTC, smb_ctlr_reg | HOSTC_I2C_EN); + + status = do_i2c_block_write(reg, device, cmd, bytes, buf); + + /* Restore I2C_EN bit */ + pci_write_config32(dev, HOSTC, smb_ctlr_reg); + + return status; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/33225 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50c1a03f624b3ab3b987d4f3b1d15dac4374e48a Gerrit-Change-Number: 33225 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: southbridge/intel/common/smbus.{c,h}: Add support for I2C commands
by Frans Hendriks (Code Review) 20 Jun '19

20 Jun '19

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30800 Change subject: southbridge/intel/common/smbus.{c,h}: Add support for I2C commands ...................................................................... southbridge/intel/common/smbus.{c,h}: Add support for I2C commands Intel Braswell supports communication with I2C device using SMBus controller. This support is missing in actual smbus routines. Added i2c_block_read() and i2c_block_write() which configures the SMBus controller into I2C mode before sending the commands. Added do_i2c_block_write() for sending block writes in I2C mode. BUG=N/A TEST=Facebook FBG-1701 booting Embedded Linux Change-Id: I40f8c0f5257a62398189f36892b8159052481693 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/southbridge/intel/common/smbus.c M src/southbridge/intel/common/smbus.h 2 files changed, 124 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/30800/1 diff --git a/src/southbridge/intel/common/smbus.c b/src/southbridge/intel/common/smbus.c index de4ff91..3b50e6b 100644 --- a/src/southbridge/intel/common/smbus.c +++ b/src/southbridge/intel/common/smbus.c @@ -4,6 +4,7 @@ * Copyright (C) 2005 Yinghai Lu <yinghailu(a)gmail.com> * Copyright (C) 2009 coresystems GmbH * Copyright (C) 2013 Vladimir Serbinenko + * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,6 +17,7 @@ */ #include <arch/io.h> +#include <device/pci.h> #include <console/console.h> #include <device/smbus_def.h> #include <stdlib.h> @@ -96,9 +98,8 @@ unsigned char val; smbus_delay(); val = inb(smbus_base + SMBHSTSTAT); - if ((val & SMBHSTSTS_HOST_BUSY)) { + if ((val & SMBHSTSTS_HOST_BUSY)) break; - } } while (--loops); return loops ? 0 : -1; } @@ -208,6 +209,7 @@ int slave_bytes; int bytes_read = 0; unsigned int loops = SMBUS_TIMEOUT; + if (smbus_wait_until_ready(smbus_base) < 0) return SMBUS_WAIT_UNTIL_READY_TIMEOUT; @@ -220,7 +222,7 @@ /* Set the device I'm talking to */ outb(((device & 0x7f) << 1) | 1, smbus_base + SMBXMITADD); /* Set the command/address... */ - outb(cmd & 0xff, smbus_base + SMBHSTCMD); + outb(cmd, smbus_base + SMBHSTCMD); /* Set up for a block data read */ outb((inb(smbus_base + SMBHSTCTL) & 0xc3) | I801_BLOCK_DATA, (smbus_base + SMBHSTCTL)); @@ -350,6 +352,19 @@ } /* Only since ICH5 */ +int i2c_block_read(u8 smbus_devnr, u8 smbus_func, unsigned int device, u8 cmd, + u32 bytes, u8 *buf) +{ + struct device *smbus_dev; + u32 reg; + + /* SMBus I/O BAR */ + smbus_dev = dev_find_slot(0, PCI_DEVFN(smbus_devnr, smbus_func)); + reg = pci_read_config32(smbus_dev, PCI_BASE_ADDRESS_4) & 0xFFFFFFFE; + + return do_i2c_block_read((unsigned int)reg, device, cmd, bytes, buf); +} + int do_i2c_block_read(unsigned int smbus_base, u8 device, unsigned int offset, const unsigned int bytes, u8 *buf) { @@ -418,3 +433,102 @@ return bytes_read; } + +int i2c_block_write(u8 smbus_devnr, u8 smbus_func, unsigned int device, u8 cmd, + u32 bytes, u8 *buf) +{ + struct device *smbus_dev; + u32 reg; + u32 smb_ctlr_reg; + int status; + + /* SMBus I/O BAR */ + smbus_dev = dev_find_slot(0, PCI_DEVFN(smbus_devnr, smbus_func)); + reg = pci_read_config32(smbus_dev, PCI_BASE_ADDRESS_4) & 0xFFFFFFFE; + + smb_ctlr_reg = pci_read_config32(smbus_dev, 0x40); + + /* Enable I2C_EN bit */ + pci_write_config32(smbus_dev, 0x40, smb_ctlr_reg | 4); + + status = do_i2c_block_write((unsigned int)reg, device, cmd, bytes, + buf); + + /* Restore I2C_EN bit */ + pci_write_config32(smbus_dev, 0x40, smb_ctlr_reg); + + return status; +} + +int do_i2c_block_write(unsigned int smbus_base, u8 device, u8 cmd, + const unsigned int bytes, u8 *buf) +{ + u8 status; + int bytes_write; + unsigned int loops = SMBUS_TIMEOUT; + + if (smbus_wait_until_ready(smbus_base) < 0) + return SMBUS_WAIT_UNTIL_READY_TIMEOUT; + + /* Set up transaction */ + /* Disable interrupts */ + outb(inb(smbus_base + SMBHSTCTL) & ~SMBHSTCNT_INTREN, + smbus_base + SMBHSTCTL); + + /* Set the slave address */ + outb(((device & 0x7f) << 1), smbus_base + SMBXMITADD); + + outb(cmd, smbus_base + SMBHSTCMD); + outb(cmd, smbus_base + SMBHSTDAT1); + + /* Number of bytes to write */ + outb(bytes, smbus_base + SMBHSTDAT0); + + /* Set up for a smbus block data write */ + outb((inb(smbus_base + SMBHSTCTL) & 0xc3) | I801_BLOCK_DATA, + (smbus_base + SMBHSTCTL)); + + /* Clear any lingering errors, so the transaction will run */ + outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT); + + /* Send first byte from buffer */ + outb(*buf++, smbus_base + SMBBLKDAT); + + for (bytes_write = 0; bytes_write < bytes; bytes_write++) { + /* Start the command */ + outb((inb(smbus_base + SMBHSTCTL) | SMBHSTCNT_START), + smbus_base + SMBHSTCTL); + + /* poll for it to start */ + if (smbus_wait_until_active(smbus_base) < 0) + return SMBUS_WAIT_UNTIL_ACTIVE_TIMEOUT; + + loops = SMBUS_TIMEOUT; + do { + loops--; + status = inb(smbus_base + SMBHSTSTAT); + if (status & (SMBHSTSTS_FAILED | /* FAILED */ + SMBHSTSTS_BUS_ERR | /* BUS ERR */ + SMBHSTSTS_DEV_ERR)) /* DEV ERR */ + return SMBUS_ERROR; + } while (!(status & SMBHSTSTS_BYTE_DONE) && loops); + + if (status & SMBHSTSTS_BYTE_DONE) { + if (bytes_write+1 < bytes) + outb(*buf++, smbus_base + SMBBLKDAT); + if ((bytes_write + 1 >= bytes) && (bytes > 1)) { + /* indicate that next byte is the last one */ + outb(inb(smbus_base + SMBHSTCTL) | + SMBHSTCNT_LAST_BYTE, + smbus_base + SMBHSTCTL); + } + + outb(status & (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR), + smbus_base + SMBHSTSTAT); + } else { + return SMBUS_ERROR; + } + } + return (bytes_write+1); +} + diff --git a/src/southbridge/intel/common/smbus.h b/src/southbridge/intel/common/smbus.h index be1aa76..f272165 100644 --- a/src/southbridge/intel/common/smbus.h +++ b/src/southbridge/intel/common/smbus.h @@ -4,6 +4,7 @@ * Copyright (C) 2005 Yinghai Lu <yinghailu(a)gmail.com> * Copyright (C) 2009 coresystems GmbH * Copyright (C) 2013 Vladimir Serbinenko + * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -43,4 +44,10 @@ /* Only since ICH5 */ int do_i2c_block_read(unsigned int smbus_base, u8 device, unsigned int offset, unsigned int bytes, u8 *buf); +int do_i2c_block_write(unsigned int smbus_base, u8 device, u8 cmd, + const unsigned int bytes, u8 *buf); +int i2c_block_read(u8 smbus_devnr, u8 smbus_func, unsigned int device, u8 cmd, + u32 bytes, u8 *buf); +int i2c_block_write(u8 smbus_devnr, u8 smbus_func, unsigned int device, u8 cmd, + u32 bytes, u8 *buf); #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/30800 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40f8c0f5257a62398189f36892b8159052481693 Gerrit-Change-Number: 30800 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: {drivers,soc/intel/braswell}: Implement C_ENVIRONMENT_BOOTBLOCK support
by Kyösti Mälkki (Code Review) 20 Jun '19

20 Jun '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29662 ) Change subject: {drivers,soc/intel/braswell}: Implement C_ENVIRONMENT_BOOTBLOCK support ...................................................................... Patch Set 47: (1 comment) https://review.coreboot.org/#/c/29662/47/src/drivers/intel/fsp1_1/cache_as_… File src/drivers/intel/fsp1_1/cache_as_ram.S: https://review.coreboot.org/#/c/29662/47/src/drivers/intel/fsp1_1/cache_as_… PS47, Line 57: jmp find_fsp > > But it should have been. The called code is compiled by a different […] But you have %esp pointing to memory-mapped SPI flash space here? So you need to somehow convince compiler to build find_fsp() without stack. That very odd-looking union in the implementation is probably silently trying to achieve just that, it was just not commented at all. At the same time it should be declared with asmlinkage (regparm="0") to tell input parameters are on the stack... -- To view, visit https://review.coreboot.org/c/coreboot/+/29662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c Gerrit-Change-Number: 29662 Gerrit-PatchSet: 47 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: York Yang <yyang024(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 20 Jun 2019 12:00:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Frans Hendriks <fhendriks(a)eltan.com> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in ...coreboot[master]: {drivers,soc/intel/braswell}: Implement C_ENVIRONMENT_BOOTBLOCK support
by Nico Huber (Code Review) 20 Jun '19

20 Jun '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29662 ) Change subject: {drivers,soc/intel/braswell}: Implement C_ENVIRONMENT_BOOTBLOCK support ...................................................................... Patch Set 47: (1 comment) https://review.coreboot.org/#/c/29662/47/src/drivers/intel/fsp1_1/cache_as_… File src/drivers/intel/fsp1_1/cache_as_ram.S: https://review.coreboot.org/#/c/29662/47/src/drivers/intel/fsp1_1/cache_as_… PS47, Line 57: jmp find_fsp > > But it should have been. The called code is compiled by a different […] Oh dear, I'm sorry. I was confused by the fact that `fsp_util.c` was already added to the bootblock. But that wasn't for the ROMCC path, I guess? So this is just really bad code, not a regression. Sorry for the noise. -- To view, visit https://review.coreboot.org/c/coreboot/+/29662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c Gerrit-Change-Number: 29662 Gerrit-PatchSet: 47 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: York Yang <yyang024(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 20 Jun 2019 11:57:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Frans Hendriks <fhendriks(a)eltan.com> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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coreboot-gerrit June 2019