coreboot-gerrit June 2019

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Change in ...coreboot[master]: mb/intel/icelake_rvp: Add camera acpi support
by Subrata Banik (Code Review) 08 Jun '19

08 Jun '19

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29883 ) Change subject: mb/intel/icelake_rvp: Add camera acpi support ...................................................................... Patch Set 3: Aamir, do you like to make this CL also gets into review ? Not sure if other team like to make use of this code as well? -- To view, visit https://review.coreboot.org/c/coreboot/+/29883 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic70cc944ebbbe7784550a643f115d39ecbf989e9 Gerrit-Change-Number: 29883 Gerrit-PatchSet: 3 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 08 Jun 2019 14:54:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: [TESTME]soc/intel/braswell: Implement and use open source CAR
by Arthur Heymans (Code Review) 08 Jun '19

08 Jun '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30778 Change subject: [TESTME]soc/intel/braswell: Implement and use open source CAR ...................................................................... [TESTME]soc/intel/braswell: Implement and use open source CAR Copied from baytrail. Change-Id: I29eabb8960b5e98a9b50f7c7082b9e148a42fde2 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/intel/fsp1_1/car.c M src/drivers/intel/fsp1_1/include/fsp/car.h M src/soc/intel/braswell/Kconfig M src/soc/intel/braswell/Makefile.inc M src/soc/intel/braswell/romstage/Makefile.inc A src/soc/intel/braswell/romstage/cache_as_ram.inc 6 files changed, 242 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/30778/1 diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c index 6409ad5..10e3c60 100644 --- a/src/drivers/intel/fsp1_1/car.c +++ b/src/drivers/intel/fsp1_1/car.c @@ -21,36 +21,38 @@ #include <program_loading.h> #include <timestamp.h> -asmlinkage void cache_as_ram_main(struct cache_as_ram_params *car_params) +asmlinkage void cache_as_ram_main(unsigned long bist, uint64_t tsc) { + /* Need to locate the current FSP_INFO_HEADER. The cache-as-ram + * is still enabled. We can directly access work buffer here. */ + FSP_INFO_HEADER *fih; + struct prog fsp = PROG_INIT(PROG_REFCODE, "fsp.bin"); + /* Initialize timestamp book keeping only once. */ - timestamp_init(car_params->tsc); + timestamp_init(tsc); /* Call into pre-console init code then initialize console. */ car_soc_pre_console_init(); car_mainboard_pre_console_init(); console_init(); - printk(BIOS_DEBUG, "FSP TempRamInit successful\n"); + printk(BIOS_SPEW, "bist: 0x%08lx\n", bist); + printk(BIOS_SPEW, "tsc: 0x%016llx\n", tsc); - printk(BIOS_SPEW, "bist: 0x%08x\n", car_params->bist); - printk(BIOS_SPEW, "tsc: 0x%016llx\n", car_params->tsc); - - if (car_params->bootloader_car_start != CONFIG_DCACHE_RAM_BASE || - car_params->bootloader_car_end != - (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)) { - printk(BIOS_INFO, "CAR mismatch: %08x--%08x vs %08lx--%08lx\n", - CONFIG_DCACHE_RAM_BASE, - CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE, - (long)car_params->bootloader_car_start, - (long)car_params->bootloader_car_end); + if (prog_locate(&fsp)) { + fih = NULL; + printk(BIOS_ERR, "Unable to locate %s\n", prog_name(&fsp)); + } else { + /* This leaks a mapping which this code assumes is benign as + * the flash is memory mapped CPU's address space. */ + fih = find_fsp((uintptr_t)rdev_mmap_full(prog_rdev(&fsp))); } car_soc_post_console_init(); car_mainboard_post_console_init(); /* Return new stack value in RAM back to assembly stub. */ - cache_as_ram_stage_main(car_params->fih); + cache_as_ram_stage_main(fih); } /* Entry point taken when romstage is called after a separate verstage. */ diff --git a/src/drivers/intel/fsp1_1/include/fsp/car.h b/src/drivers/intel/fsp1_1/include/fsp/car.h index df5e0da..96c9cf9 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/car.h +++ b/src/drivers/intel/fsp1_1/include/fsp/car.h @@ -30,7 +30,7 @@ }; /* Entry points from the cache-as-ram assembly code. */ -asmlinkage void cache_as_ram_main(struct cache_as_ram_params *car_params); +asmlinkage void cache_as_ram_main(unsigned long bist, uint64_t tsc); asmlinkage void after_cache_as_ram(void *chipset_context); asmlinkage void romstage_c_entry(void); /* Per stage calls from the above two functions. The void * return from diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index d0a250a..b780038 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -39,7 +39,8 @@ select TSC_MONOTONIC_TIMER select TSC_SYNC_MFENCE select UDELAY_TSC - select USE_GENERIC_FSP_CAR_INC +# select USE_GENERIC_FSP_CAR_INC + select SKIP_FSP_CAR select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SPI_CONSOLE_SUPPORT select HAVE_FSP_GOP diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc index 3296331..1a5addb 100644 --- a/src/soc/intel/braswell/Makefile.inc +++ b/src/soc/intel/braswell/Makefile.inc @@ -18,6 +18,7 @@ postcar-y += memmap.c postcar-y += iosf.c +postcar-y += ../../../cpu/intel/car/non-evict/exit_car.S ramstage-y += acpi.c ramstage-y += chip.c diff --git a/src/soc/intel/braswell/romstage/Makefile.inc b/src/soc/intel/braswell/romstage/Makefile.inc index c3ed415..1ab1b45 100644 --- a/src/soc/intel/braswell/romstage/Makefile.inc +++ b/src/soc/intel/braswell/romstage/Makefile.inc @@ -1,3 +1,5 @@ romstage-y += early_spi.c romstage-y += pmc.c romstage-y += romstage.c + +cpu_incs-y += $(src)/soc/intel/braswell/romstage/cache_as_ram.inc diff --git a/src/soc/intel/braswell/romstage/cache_as_ram.inc b/src/soc/intel/braswell/romstage/cache_as_ram.inc new file mode 100644 index 0000000..9db7f85 --- /dev/null +++ b/src/soc/intel/braswell/romstage/cache_as_ram.inc @@ -0,0 +1,219 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich(a)gmail.com> + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/x86/mtrr.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/post_code.h> +#include <cpu/x86/msr.h> + +#include "fmap_config.h" + +/* The full cache-as-ram size includes the cache-as-ram portion from coreboot + * and the space used by the reference code. These 2 values combined should + * be a power of 2 because the MTRR setup assumes that. */ +#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE +#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE + +/* Cache all of CBFS just below 4GiB as Write-Protect type. */ +#define CODE_CACHE_SIZE _ALIGN_UP_POW2(___FMAP__COREBOOT_SIZE) +#define CODE_CACHE_BASE (-CODE_CACHE_SIZE) +#define CODE_CACHE_MASK (~(CODE_CACHE_SIZE - 1)) + +#define NoEvictMod_MSR 0x2e0 +#define BBL_CR_CTL3_MSR 0x11e + + /* Save the BIST result. */ + movl %eax, %ebp + +cache_as_ram: + post_code(0x20) + + /* Send INIT IPI to all excluding ourself. */ + movl $0x000C4500, %eax + movl $0xFEE00300, %esi + movl %eax, (%esi) + + /* All CPUs need to be in Wait for SIPI state */ +wait_for_sipi: + movl (%esi), %eax + bt $12, %eax + jc wait_for_sipi + + post_code(0x21) + /* Configure the default memory type to uncacheable as well as disable + * fixed and variable range mtrrs. */ + movl $MTRR_DEF_TYPE_MSR, %ecx + rdmsr + andl $(~0x00000cff), %eax + wrmsr + + post_code(0x22) + /* Zero the variable MTRRs. */ + movl $IA32_MCG_CAP, %ecx + rdmsr + movzx %al, %ebx + /* First variable MTRR. */ + movl $MTRR_PHYS_BASE(0), %ecx + xorl %eax, %eax + xorl %edx, %edx +1: + wrmsr + inc %ecx + dec %ebx + jnz 1b + + /* Clear/disable fixed MTRRs */ + mov $fixed_mtrr_list_size, %ebx + xor %eax, %eax + xor %edx, %edx + +clear_fixed_mtrr: + add $-2, %ebx + movzwl fixed_mtrr_list(%ebx), %ecx + wrmsr + jnz clear_fixed_mtrr + + /* Determine CPU_ADDR_BITS and load PHYSMASK high word to %edx. */ + movl $0x80000008, %eax + cpuid + movb %al, %cl + sub $32, %cl + movl $1, %edx + shl %cl, %edx + subl $1, %edx + + /* Preload high word of address mask (in %edx) for Variable + * MTRRs 0 and 1. + */ +addrsize_set_high: + xorl %eax, %eax + movl $MTRR_PHYS_MASK(0), %ecx + wrmsr + movl $MTRR_PHYS_MASK(1), %ecx + wrmsr + + + post_code(0x23) + /* Set Cache-as-RAM base address. */ + movl $(MTRR_PHYS_BASE(0)), %ecx + movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax + xorl %edx, %edx + wrmsr + + post_code(0x24) + /* Set Cache-as-RAM mask. */ + movl $(MTRR_PHYS_MASK(0)), %ecx + rdmsr + movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax + wrmsr + + post_code(0x25) + /* Set code caching up for romstage. */ + movl $(MTRR_PHYS_BASE(1)), %ecx + movl $(CODE_CACHE_BASE | MTRR_TYPE_WRPROT), %eax + xorl %edx, %edx + wrmsr + + movl $MTRR_PHYS_MASK(1), %ecx + rdmsr + movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax + wrmsr + + /* Enable MTRR. */ + movl $MTRR_DEF_TYPE_MSR, %ecx + rdmsr + orl $MTRR_DEF_TYPE_EN, %eax + wrmsr + + post_code(0x26) + + /* Enable the L2 cache. */ + movl $BBL_CR_CTL3_MSR, %ecx + rdmsr + orl $0x100, %eax + wrmsr + + post_code(0x27) + + /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ + movl %cr0, %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax + invd + movl %eax, %cr0 + + /* enable the 'no eviction' mode */ + movl $NoEvictMod_MSR, %ecx + rdmsr + orl $1, %eax + wrmsr + + post_code(0x28) + + /* Clear the cache memory region. This will also fill up the cache */ + movl $CACHE_AS_RAM_BASE, %esi + movl %esi, %edi + movl $(CACHE_AS_RAM_SIZE >> 2), %ecx + xorl %eax, %eax + rep stosl + + /* enable no evict mode */ + movl $NoEvictMod_MSR, %ecx + rdmsr + orl $2, %eax + wrmsr + + post_code(0x29) + + /* Setup the stack. */ + movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax + movl %eax, %esp + + /* Push the initial TSC value from boot block. The low 32 bits are + * in mm0, and the high 32 bits are in mm1. */ + movd %mm1, %eax + pushl %eax + movd %mm0, %eax + pushl %eax + /* Restore the BIST result. */ + movl %ebp, %eax + movl %esp, %ebp + pushl %eax + +before_romstage: + post_code(0x2a) + /* Call car.c main function. */ + call cache_as_ram_main + + /* Should never see this postcode */ + post_code(POST_DEAD_CODE) + +.Lhlt: + hlt + jmp .Lhlt + +fixed_mtrr_list: + .word MTRR_FIX_64K_00000 + .word MTRR_FIX_16K_80000 + .word MTRR_FIX_16K_A0000 + .word MTRR_FIX_4K_C0000 + .word MTRR_FIX_4K_C8000 + .word MTRR_FIX_4K_D0000 + .word MTRR_FIX_4K_D8000 + .word MTRR_FIX_4K_E0000 + .word MTRR_FIX_4K_E8000 + .word MTRR_FIX_4K_F0000 + .word MTRR_FIX_4K_F8000 +fixed_mtrr_list_size = . - fixed_mtrr_list -- To view, visit https://review.coreboot.org/c/coreboot/+/30778 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29eabb8960b5e98a9b50f7c7082b9e148a42fde2 Gerrit-Change-Number: 30778 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: {drivers,soc/intel/braswell}: Implement C_ENVIRONMENT_BOOTBLOCK support
by Arthur Heymans (Code Review) 08 Jun '19

08 Jun '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29662 ) Change subject: {drivers,soc/intel/braswell}: Implement C_ENVIRONMENT_BOOTBLOCK support ...................................................................... Patch Set 46: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c Gerrit-Change-Number: 29662 Gerrit-PatchSet: 46 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: York Yang <yyang024(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 08 Jun 2019 12:50:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: nb/intel/sandybridge: Drop iommu.c and rename functions
by Felix Held (Code Review) 08 Jun '19

08 Jun '19

Felix Held has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32068 ) Change subject: nb/intel/sandybridge: Drop iommu.c and rename functions ...................................................................... nb/intel/sandybridge: Drop iommu.c and rename functions * Move the contents of iommu.c to early_init.c. * Name the functions like done in intel/soc/common. * Move PAMx register setup to own function Preparations for integration in soc/intel/common/* Tested on Lenovo T520 (Intel Sandy Bridge). Still boots to OS, no errors visible in dmesg. Change-Id: I3ec395bf6722bceb84316e92733dcfcd7a093639 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32068 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/northbridge/intel/sandybridge/Makefile.inc M src/northbridge/intel/sandybridge/early_init.c D src/northbridge/intel/sandybridge/iommu.c M src/northbridge/intel/sandybridge/romstage.c M src/northbridge/intel/sandybridge/sandybridge.h 5 files changed, 47 insertions(+), 63 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index ba55466..c77f3ba 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -43,7 +43,6 @@ mrc.bin-type := mrc endif romstage-y += romstage.c -romstage-y += iommu.c romstage-y += early_init.c romstage-y += ../../../arch/x86/walkcbfs.S diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index fd3d34f..0c6ef7e 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -2,7 +2,9 @@ * This file is part of the coreboot project. * * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2015 secunet Security Networks AG * Copyright (C) 2011 Google Inc + * Copyright (C) 2018 Patrick Rudolph <patrick.rudolph(a)9elements.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,6 +19,8 @@ #include <stdlib.h> #include <console/console.h> #include <arch/io.h> +#include <device/mmio.h> +#include <device/device.h> #include <device/pci_ops.h> #include <device/pci_def.h> #include <pc80/mc146818rtc.h> @@ -25,6 +29,41 @@ #include "sandybridge.h" +static void systemagent_vtd_init(void) +{ + const u32 capid0_a = pci_read_config32(PCI_DEV(0, 0, 0), CAPID0_A); + if (capid0_a & (1 << 23)) + return; + + /* setup BARs */ + MCHBAR32(0x5404) = IOMMU_BASE1 >> 32; + MCHBAR32(0x5400) = IOMMU_BASE1 | 1; + MCHBAR32(0x5414) = IOMMU_BASE2 >> 32; + MCHBAR32(0x5410) = IOMMU_BASE2 | 1; + + /* lock policies */ + write32((void *)(IOMMU_BASE1 + 0xff0), 0x80000000); + + const struct device *const azalia = pcidev_on_root(0x1b, 0); + if (azalia && azalia->enabled) { + write32((void *)(IOMMU_BASE2 + 0xff0), 0x20000000); + write32((void *)(IOMMU_BASE2 + 0xff0), 0xa0000000); + } else { + write32((void *)(IOMMU_BASE2 + 0xff0), 0x80000000); + } +} + +static void enable_pam_region(void) +{ + pci_write_config8(PCI_DEV(0, 0x00, 0), PAM0, 0x30); + pci_write_config8(PCI_DEV(0, 0x00, 0), PAM1, 0x33); + pci_write_config8(PCI_DEV(0, 0x00, 0), PAM2, 0x33); + pci_write_config8(PCI_DEV(0, 0x00, 0), PAM3, 0x33); + pci_write_config8(PCI_DEV(0, 0x00, 0), PAM4, 0x33); + pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33); + pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33); +} + static void sandybridge_setup_bars(void) { printk(BIOS_DEBUG, "Setting up static northbridge registers..."); @@ -36,15 +75,6 @@ pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1); pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, (0LL+(uintptr_t)DEFAULT_DMIBAR) >> 32); - /* Set C0000-FFFFF to access RAM on both reads and writes */ - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM0, 0x30); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM1, 0x33); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM2, 0x33); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM3, 0x33); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM4, 0x33); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33); - printk(BIOS_DEBUG, " done\n"); } @@ -156,7 +186,7 @@ } } -void sandybridge_early_initialization(void) +void systemagent_early_init(void) { u32 capid0_a; u32 deven; @@ -179,8 +209,11 @@ /* Setup all BARs required for early PCIe and raminit */ sandybridge_setup_bars(); + /* Set C0000-FFFFF to access RAM on both reads and writes */ + enable_pam_region(); + /* Setup IOMMU BARs */ - sandybridge_init_iommu(); + systemagent_vtd_init(); /* Device Enable, don't touch PEG bits */ deven = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN) | DEVEN_IGD; diff --git a/src/northbridge/intel/sandybridge/iommu.c b/src/northbridge/intel/sandybridge/iommu.c deleted file mode 100644 index 339397d..0000000 --- a/src/northbridge/intel/sandybridge/iommu.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 secunet Security Networks AG - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> - -#include <device/mmio.h> -#include <device/pci_ops.h> -#include <device/device.h> -#include <device/pci_def.h> - -#include "sandybridge.h" - -void sandybridge_init_iommu(void) -{ - const u32 capid0_a = pci_read_config32(PCI_DEV(0, 0, 0), 0xe4); - if (capid0_a & (1 << 23)) - return; - - /* setup BARs */ - MCHBAR32(0x5404) = IOMMU_BASE1 >> 32; - MCHBAR32(0x5400) = IOMMU_BASE1 | 1; - MCHBAR32(0x5414) = IOMMU_BASE2 >> 32; - MCHBAR32(0x5410) = IOMMU_BASE2 | 1; - - /* lock policies */ - write32((void *)(IOMMU_BASE1 + 0xff0), 0x80000000); - - const struct device *const azalia = pcidev_on_root(0x1b, 0); - if (azalia && azalia->enabled) { - write32((void *)(IOMMU_BASE2 + 0xff0), 0x20000000); - write32((void *)(IOMMU_BASE2 + 0xff0), 0xa0000000); - } else { - write32((void *)(IOMMU_BASE2 + 0xff0), 0x80000000); - } -} diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 76b3088..2cef5f2 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -74,8 +74,8 @@ /* Perform some early chipset initialization required * before RAM initialization can work */ - sandybridge_early_initialization(); - printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n"); + systemagent_early_init(); + printk(BIOS_DEBUG, "Back from systemagent_early_init()\n"); s3resume = southbridge_detect_s3_resume(); diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 77165f6..88b7b56 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -216,7 +216,7 @@ void intel_sandybridge_finalize_smm(void); #else /* !__SMM__ */ int bridge_silicon_revision(void); -void sandybridge_early_initialization(void); +void systemagent_early_init(void); void sandybridge_init_iommu(void); void sandybridge_late_initialization(void); void northbridge_romstage_finalize(int s3resume); -- To view, visit https://review.coreboot.org/c/coreboot/+/32068 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ec395bf6722bceb84316e92733dcfcd7a093639 Gerrit-Change-Number: 32068 Gerrit-PatchSet: 6 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in ...coreboot[master]: src/soc/intel/skylake/acpi: Remove Return for PS0/3
by Christian Walter (Code Review) 08 Jun '19

08 Jun '19

Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33293 Change subject: src/soc/intel/skylake/acpi: Remove Return for PS0/3 ...................................................................... src/soc/intel/skylake/acpi: Remove Return for PS0/3 Remove the Return statement within the PS0, PS3 methods. PS0/3 are not allowed to return anything. Even an empty return will be resolved to Return(Null). In order to be conform with the specification, the code has been refactored to remove the return statements. Change-Id: I7b4820e8dd40a9169a7facce67282b8af5af67af Signed-off-by: Christian Walter <christian.walter(a)9elements.com> --- M src/soc/intel/skylake/acpi/xhci.asl 1 file changed, 74 insertions(+), 78 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/33293/1 diff --git a/src/soc/intel/skylake/acpi/xhci.asl b/src/soc/intel/skylake/acpi/xhci.asl index a23d78a..b5aa412 100644 --- a/src/soc/intel/skylake/acpi/xhci.asl +++ b/src/soc/intel/skylake/acpi/xhci.asl @@ -129,97 +129,93 @@ Method (_PS0, 0, Serialized) { - If (LEqual (^DVID, 0xFFFF)) { - Return - } - If (LOr (LEqual (^XMEM, 0xFFFF), LEqual (^XMEM, 0x0000))) { - Return - } + If (!LEqual (^DVID, 0xFFFF)) { + If (!LOr (LEqual (^XMEM, 0xFFFF), LEqual (^XMEM, 0x0000))) { - /* Disable d3hot and SS link trunk clock gating */ - Store(Zero, ^D3HE) - Store(Zero, ^STGE) + /* Disable d3hot and SS link trunk clock gating */ + Store(Zero, ^D3HE) + Store(Zero, ^STGE) - /* If device is in D3, set back to D0 */ - If (LEqual (^D0D3, 3)) { - Store (Zero, Local0) - Store (Local0, ^D0D3) - Store (^D0D3, Local0) - } - - /* Disable USB2 PHY SUS Well Power Gating */ - Store (Zero, ^UPSW) - - /* - * Apply USB2 PHPY Power Gating workaround if needed. - */ - If (^^PMC.UWAB) { - /* Write to MTPMC to have PMC disable power gating */ - Store (1, ^^PMC.MPMC) - - /* Wait for PCH_PM_STS.MSG_FULL_STS to be 0 */ - Store (10, Local0) - While (^^PMC.PMFS) { - If (LNot (Local0)) { - Break + /* If device is in D3, set back to D0 */ + If (LEqual (^D0D3, 3)) { + Store (Zero, Local0) + Store (Local0, ^D0D3) + Store (^D0D3, Local0) } - Decrement (Local0) - Sleep (10) + + /* Disable USB2 PHY SUS Well Power Gating */ + Store (Zero, ^UPSW) + + /* + * Apply USB2 PHPY Power Gating workaround if needed. + */ + If (^^PMC.UWAB) { + /* Write to MTPMC to have PMC disable power gating */ + Store (1, ^^PMC.MPMC) + + /* Wait for PCH_PM_STS.MSG_FULL_STS to be 0 */ + Store (10, Local0) + While (^^PMC.PMFS) { + If (LNot (Local0)) { + Break + } + Decrement (Local0) + Sleep (10) + } + } } } } Method (_PS3, 0, Serialized) { - If (LEqual (^DVID, 0xFFFF)) { - Return - } - If (LOr (LEqual (^XMEM, 0xFFFF), LEqual (^XMEM, 0x0000))) { - Return - } + If (!LEqual (^DVID, 0xFFFF)) { + If (!LOr (LEqual (^XMEM, 0xFFFF), LEqual (^XMEM, 0x0000))) { - /* Clear PME Status */ - Store (1, ^PMES) + /* Clear PME Status */ + Store (1, ^PMES) - /* Enable PME */ - Store (1, ^PMEE) + /* Enable PME */ + Store (1, ^PMEE) - /* If device is in D3, set back to D0 */ - If (LEqual (^D0D3, 3)) { - Store (Zero, Local0) - Store (Local0, ^D0D3) - Store (^D0D3, Local0) - } - - /* Enable USB2 PHY SUS Well Power Gating in D0/D0i2/D0i3/D3 */ - Store (3, ^UPSW) - - /* Enable d3hot and SS link trunk clock gating */ - Store(One, ^D3HE) - Store(One, ^STGE) - - /* Now put device in D3 */ - Store (3, Local0) - Store (Local0, ^D0D3) - Store (^D0D3, Local0) - - /* - * Apply USB2 PHPY Power Gating workaround if needed. - * This code assumes XDCI is disabled, if it is enabled - * then this must also check if it is in D3 state too. - */ - If (^^PMC.UWAB) { - /* Write to MTPMC to have PMC enable power gating */ - Store (3, ^^PMC.MPMC) - - /* Wait for PCH_PM_STS.MSG_FULL_STS to be 0 */ - Store (10, Local0) - While (^^PMC.PMFS) { - If (LNot (Local0)) { - Break + /* If device is in D3, set back to D0 */ + If (LEqual (^D0D3, 3)) { + Store (Zero, Local0) + Store (Local0, ^D0D3) + Store (^D0D3, Local0) } - Decrement (Local0) - Sleep (10) + + /* Enable USB2 PHY SUS Well Power Gating in D0/D0i2/D0i3/D3 */ + Store (3, ^UPSW) + + /* Enable d3hot and SS link trunk clock gating */ + Store(One, ^D3HE) + Store(One, ^STGE) + + /* Now put device in D3 */ + Store (3, Local0) + Store (Local0, ^D0D3) + Store (^D0D3, Local0) + + /* + * Apply USB2 PHPY Power Gating workaround if needed. + * This code assumes XDCI is disabled, if it is enabled + * then this must also check if it is in D3 state too. + */ + If (^^PMC.UWAB) { + /* Write to MTPMC to have PMC enable power gating */ + Store (3, ^^PMC.MPMC) + + /* Wait for PCH_PM_STS.MSG_FULL_STS to be 0 */ + Store (10, Local0) + While (^^PMC.PMFS) { + If (LNot (Local0)) { + Break + } + Decrement (Local0) + Sleep (10) + } + } } } } -- To view, visit https://review.coreboot.org/c/coreboot/+/33293 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b4820e8dd40a9169a7facce67282b8af5af67af Gerrit-Change-Number: 33293 Gerrit-PatchSet: 1 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/soc/intel/skylake/bootblock: Add KBL C236 to PCH Table
by Christian Walter (Code Review) 08 Jun '19

08 Jun '19

Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33248 Change subject: src/soc/intel/skylake/bootblock: Add KBL C236 to PCH Table ...................................................................... src/soc/intel/skylake/bootblock: Add KBL C236 to PCH Table Add Kabylake C236 to the PCH Table. Change-Id: I435927f15e9d3219886375426b09c68632dfe3d9 Signed-off-by: Christian Walter <christian.walter(a)9elements.com> --- M src/soc/intel/skylake/bootblock/report_platform.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/33248/1 diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c index 1e81809..11355b5 100644 --- a/src/soc/intel/skylake/bootblock/report_platform.c +++ b/src/soc/intel/skylake/bootblock/report_platform.c @@ -90,6 +90,7 @@ { PCI_DEVICE_ID_INTEL_KBP_LP_U_PREMIUM, "Kabylake-U Premium" }, { PCI_DEVICE_ID_INTEL_KBP_LP_Y_PREMIUM, "Kabylake-Y Premium" }, { PCI_DEVICE_ID_INTEL_KBP_LP_SUPER_SKU, "Kabylake Super Sku" }, + { PCI_DEVICE_ID_INTEL_KBP_H_C236, "Kabylake PCH-H C236" }, { PCI_DEVICE_ID_INTEL_SPT_LP_Y_PREMIUM_HDCP22, "Kabylake-Y iHDCP 2.2 Premium" }, { PCI_DEVICE_ID_INTEL_SPT_LP_U_PREMIUM_HDCP22, -- To view, visit https://review.coreboot.org/c/coreboot/+/33248 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I435927f15e9d3219886375426b09c68632dfe3d9 Gerrit-Change-Number: 33248 Gerrit-PatchSet: 1 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: northbridge/gm45: document that raminit doesn't support mirrored ranks
by Felix Held (Code Review) 08 Jun '19

08 Jun '19

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33294 Change subject: northbridge/gm45: document that raminit doesn't support mirrored ranks ...................................................................... northbridge/gm45: document that raminit doesn't support mirrored ranks Change-Id: I8a66a1355974f6771c5e4bae0dc60da2447122d1 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/northbridge/intel/gm45/raminit.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/33294/1 diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index 2826d74..b7ccdec 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -1593,7 +1593,8 @@ int ch, r; FOR_EACH_POPULATED_RANK(dimms, ch, r) { /* We won't do this in dual-interleaved mode, - so don't care about the offset. */ + so don't care about the offset. + Mirrored ranks aren't taken into account here. */ const u32 rankaddr = raminit_get_rank_addr(ch, r); printk(BIOS_DEBUG, "JEDEC init @0x%08x\n", rankaddr); MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_SET_EREG_MASK) | DCC_SET_EREGx(2); -- To view, visit https://review.coreboot.org/c/coreboot/+/33294 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8a66a1355974f6771c5e4bae0dc60da2447122d1 Gerrit-Change-Number: 33294 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Rampayload: Able to build coreboot without ramstage
by Subrata Banik (Code Review) 08 Jun '19

08 Jun '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33143 Change subject: Rampayload: Able to build coreboot without ramstage ...................................................................... Rampayload: Able to build coreboot without ramstage This patch removes all possible dependency in order to build platform with CONFIG_RAMSTAGE enable (without ramstage). Change-Id: Id000dfac2eb57a8eaaa505c89d798fb30b3706fe Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M Makefile.inc M src/Kconfig M toolchain.inc 3 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/33143/1 diff --git a/Makefile.inc b/Makefile.inc index d4f7597..c0797fe 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -1058,7 +1058,11 @@ FIT_OPTIONS += -q $(FIT_ENTRY) endif +ifeq ($(CONFIG_RAMPAYLOAD),y) +$(obj)/coreboot.rom: $(obj)/coreboot.pre $(CBFSTOOL) $$(INTERMEDIATE) +else $(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/ramstage.elf $(CBFSTOOL) $$(INTERMEDIATE) +endif @printf " CBFS $(subst $(obj)/,,$(@))\n" # The full ROM may be larger than the CBFS part, so create an empty # file (filled with \377 = 0xff) and copy the CBFS image over it. @@ -1128,10 +1132,12 @@ endif # CONFIG_NO_XIP_EARLY_STAGES endif # CONFIG_ARCH_ROMSTAGE_X86_32 / CONFIG_ARCH_ROMSTAGE_X86_64 +ifneq ($(CONFIG_RAMPAYLOAD),y) cbfs-files-y += $(CONFIG_CBFS_PREFIX)/ramstage $(CONFIG_CBFS_PREFIX)/ramstage-file := $(objcbfs)/ramstage.elf $(CONFIG_CBFS_PREFIX)/ramstage-type := stage $(CONFIG_CBFS_PREFIX)/ramstage-compression := $(CBFS_COMPRESS_FLAG) +endif cbfs-files-$(CONFIG_HAVE_REFCODE_BLOB) += $(CONFIG_CBFS_PREFIX)/refcode $(CONFIG_CBFS_PREFIX)/refcode-file := $(REFCODE_BLOB) diff --git a/src/Kconfig b/src/Kconfig index 4ec6b76..2442a63 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -314,6 +314,7 @@ config RAMPAYLOAD bool "Enable coreboot flow without executing ramstage" + default y if !STAGE_RAMSTAGE default n depends on ARCH_X86 help diff --git a/toolchain.inc b/toolchain.inc index 0486287..9b53d4a 100644 --- a/toolchain.inc +++ b/toolchain.inc @@ -47,7 +47,11 @@ ROMCC=CCC_CC="$(ROMCC_BIN)" $(CC) endif +ifeq ($(CONFIG_RAMPAYLOAD),y) +COREBOOT_STANDARD_STAGES := decompressor bootblock verstage romstage +else COREBOOT_STANDARD_STAGES := decompressor bootblock verstage romstage ramstage +endif MAP-decompressor := bootblock ARCHDIR-i386 := x86 -- To view, visit https://review.coreboot.org/c/coreboot/+/33143 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id000dfac2eb57a8eaaa505c89d798fb30b3706fe Gerrit-Change-Number: 33143 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Makefile.inc: Fix compilation issue with !CONFIG_ARCH_RAMSTAGE_X86_32/64
by Subrata Banik (Code Review) 08 Jun '19

08 Jun '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33114 Change subject: Makefile.inc: Fix compilation issue with !CONFIG_ARCH_RAMSTAGE_X86_32/64 ...................................................................... Makefile.inc: Fix compilation issue with !CONFIG_ARCH_RAMSTAGE_X86_32/64 Change-Id: Ia6ad9b43dde2d2af40a7b2bc1773c0338ae9552b Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/cpu/x86/Makefile.inc 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/33114/1 diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc index 3e8a664..5ba8ccf 100644 --- a/src/cpu/x86/Makefile.inc +++ b/src/cpu/x86/Makefile.inc @@ -17,6 +17,8 @@ SIPI_BIN=$(SIPI_ELF:.elf=) SIPI_DOTO=$(SIPI_ELF:.elf=.o) +ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32)$(CONFIG_ARCH_RAMSTAGE_X86_64),y) + ifeq ($(CONFIG_PARALLEL_MP),y) ramstage-srcs += $(SIPI_BIN).manual endif @@ -37,3 +39,4 @@ $(call src-to-obj,ramstage,$(SIPI_BIN).manual): $(SIPI_BIN) @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" cd $(dir $<); $(OBJCOPY_rmodules_$(ARCH-ramstage-y)) -I binary $(notdir $<) $(target-objcopy) $(abspath $@) +endif -- To view, visit https://review.coreboot.org/c/coreboot/+/33114 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia6ad9b43dde2d2af40a7b2bc1773c0338ae9552b Gerrit-Change-Number: 33114 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sb/amd/sb700: Fix misleading formatting
by Marshall Dawson (Code Review) 07 Jun '19

07 Jun '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33268 Change subject: sb/amd/sb700: Fix misleading formatting ...................................................................... sb/amd/sb700: Fix misleading formatting Change-Id: I65872d6f1d71d050c8589d3616340648cf95048b Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/southbridge/amd/sb700/sm.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/33268/1 diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c index 6b7ce68..6631682 100644 --- a/src/southbridge/amd/sb700/sm.c +++ b/src/southbridge/amd/sb700/sm.c @@ -306,7 +306,7 @@ } byte = pci_read_config8(dev, 0xAE); if (CONFIG(ENABLE_APIC_EXT_ID)) - byte |= 1 << 4; + byte |= 1 << 4; byte |= 1 << 5; /* ACPI_DISABLE_TIMER_IRQ_ENHANCEMENT_FOR_8254_TIMER */ byte |= 1 << 6; /* Enable arbiter between APIC and PIC interrupts */ pci_write_config8(dev, 0xAE, byte); -- To view, visit https://review.coreboot.org/c/coreboot/+/33268 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65872d6f1d71d050c8589d3616340648cf95048b Gerrit-Change-Number: 33268 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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