coreboot-gerrit June 2019

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Change in ...coreboot[master]: device/pci_ops: Define pci_find_capability() just once
by Angel Pons (Code Review) 09 Jun '19

09 Jun '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31755 ) Change subject: device/pci_ops: Define pci_find_capability() just once ...................................................................... Patch Set 5: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/31755 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iadadf3d550416850d6c37233bd4eda025f4d3960 Gerrit-Change-Number: 31755 Gerrit-PatchSet: 5 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: York Yang <yyang024(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 09 Jun 2019 20:29:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: acpigen: Add support for IndexField
by Patrick Rudolph (Code Review) 09 Jun '19

09 Jun '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33032 Change subject: acpigen: Add support for IndexField ...................................................................... acpigen: Add support for IndexField Add support for generating IndexField, which is similar to Field. Change-Id: If66a627e64953696b0b68488256bd5c141e4c205 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/arch/x86/acpigen.c M src/arch/x86/include/arch/acpigen.h 2 files changed, 63 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/33032/1 diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c index e283f4d..74cd25a 100644 --- a/src/arch/x86/acpigen.c +++ b/src/arch/x86/acpigen.c @@ -514,6 +514,63 @@ acpigen_pop_len(); } +/* + * Generate ACPI AML code for IndexField + * Arg0: region name + * Arg1: Pointer to struct fieldlist. + * Arg2: no. of entries in Arg1 + * Arg3: flags which indicate filed access type, lock rule & update rule. + * Example with fieldlist + * struct fieldlist l[] = { + * FIELDLIST_OFFSET(0x84), + * FIELDLIST_NAMESTR("PMCS", 2), + * }; + * acpigen_write_field("IDX", "DATA" l, ARRAY_SIZE(l), FIELD_ANYACC | + * FIELD_NOLOCK | + * FIELD_PRESERVE); + * Output: + * IndexField (IDX, DATA, AnyAcc, NoLock, Preserve) + * { + * Offset (0x84), + * PMCS, 2 + * } + */ +void acpigen_write_indexfield(const char *idx, const char *data, + struct fieldlist *l, size_t count, uint8_t flags) +{ + uint16_t i; + uint32_t current_bit_pos = 0; + + /* FieldOp */ + acpigen_emit_ext_op(INDEX_FIELD_OP); + /* Package Length */ + acpigen_write_len_f(); + /* NameString 4 chars only */ + acpigen_emit_simple_namestring(idx); + /* NameString 4 chars only */ + acpigen_emit_simple_namestring(data); + /* Field Flag */ + acpigen_emit_byte(flags); + + for (i = 0; i < count; i++) { + switch (l[i].type) { + case NAME_STRING: + acpigen_write_field_name(l[i].name, l[i].bits); + current_bit_pos += l[i].bits; + break; + case OFFSET: + acpigen_write_field_offset(l[i].bits, current_bit_pos); + current_bit_pos = l[i].bits; + break; + default: + printk(BIOS_ERR, "%s: Invalid field type 0x%X\n" + , __func__, l[i].type); + break; + } + } + acpigen_pop_len(); +} + void acpigen_write_empty_PCT(void) { /* diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h index 6114667..db003fe 100644 --- a/src/arch/x86/include/arch/acpigen.h +++ b/src/arch/x86/include/arch/acpigen.h @@ -420,6 +420,12 @@ */ void acpigen_write_field(const char *name, struct fieldlist *l, size_t count, uint8_t flags); +/* + * Generate ACPI AML code for IndexField + * This function takes input index name, data name, fieldlist, count & flags. + */ +void acpigen_write_indexfield(const char *idx, const char *data, + struct fieldlist *l, size_t count, uint8_t flags); int get_cst_entries(acpi_cstate_t **); -- To view, visit https://review.coreboot.org/c/coreboot/+/33032 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If66a627e64953696b0b68488256bd5c141e4c205 Gerrit-Change-Number: 33032 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: autoport: Generate a libgfxinit template
by Iru Cai (vimacs) (Code Review) 09 Jun '19

09 Jun '19

Hello Iru Cai, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/30912 to review the following change. Change subject: autoport: Generate a libgfxinit template ...................................................................... autoport: Generate a libgfxinit template Change-Id: I213628e525cc11c502de7d538bd60f49f3a930b9 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- M util/autoport/main.go 1 file changed, 42 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/30912/1 diff --git a/util/autoport/main.go b/util/autoport/main.go index 05a829b..c1a7907 100644 --- a/util/autoport/main.go +++ b/util/autoport/main.go @@ -748,6 +748,10 @@ ScanRoot(ctx) + KconfigBool["MAINBOARD_HAS_LIBGFXINIT"] = true + KconfigComment["MAINBOARD_HAS_LIBGFXINIT"] = "FIXME: check this" + AddRAMStageFile("gma-mainboard.ads", "CONFIG_MAINBOARD_USE_LIBGFXINIT") + if len(ROMStageFiles) > 0 || len(RAMStageFiles) > 0 || len(SMMFiles) > 0 { mf := Create(ctx, "Makefile.inc") defer mf.Close() @@ -882,4 +886,42 @@ } `) + gma := Create(ctx, "gma-mainboard.ads") + defer gma.Close() + + gma.WriteString(`-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + Internal, + others => Disabled); + +end GMA.Mainboard; +`) } -- To view, visit https://review.coreboot.org/c/coreboot/+/30912 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I213628e525cc11c502de7d538bd60f49f3a930b9 Gerrit-Change-Number: 30912 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mainboard/Kconfig: add option for a 6144 KB(6 MB) ROM size
by Kacper Słomiński (Code Review) 09 Jun '19

09 Jun '19

Kacper Słomiński has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30980 Change subject: mainboard/Kconfig: add option for a 6144 KB(6 MB) ROM size ...................................................................... mainboard/Kconfig: add option for a 6144 KB(6 MB) ROM size Signed-off-by: Kacper Słomiński <kacper.slominski72(a)gmail.com> Change-Id: I7a1949c3512528b6b73955d907efc21728eed739 --- M src/mainboard/Kconfig 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/30980/1 diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index 363df55..c88d317 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -24,6 +24,8 @@ bool config BOARD_ROMSIZE_KB_4096 bool +config BOARD_ROMSIZE_KB_6144 + bool config BOARD_ROMSIZE_KB_8192 bool config BOARD_ROMSIZE_KB_10240 @@ -47,6 +49,7 @@ default COREBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024 default COREBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048 default COREBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096 + default COREBOOT_ROMSIZE_KB_6144 if BOARD_ROMSIZE_KB_6144 default COREBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192 default COREBOOT_ROMSIZE_KB_10240 if BOARD_ROMSIZE_KB_10240 default COREBOOT_ROMSIZE_KB_12288 if BOARD_ROMSIZE_KB_12288 @@ -94,6 +97,11 @@ help Choose this option if you have a 4096 KB (4 MB) ROM chip. +config COREBOOT_ROMSIZE_KB_6144 + bool "6144 KB (6 MB)" + help + Choose this option if you have a 6144 KB (6 MB) ROM chip. + config COREBOOT_ROMSIZE_KB_8192 bool "8192 KB (8 MB)" help @@ -136,6 +144,7 @@ default 1024 if COREBOOT_ROMSIZE_KB_1024 default 2048 if COREBOOT_ROMSIZE_KB_2048 default 4096 if COREBOOT_ROMSIZE_KB_4096 + default 6144 if COREBOOT_ROMSIZE_KB_6144 default 8192 if COREBOOT_ROMSIZE_KB_8192 default 10240 if COREBOOT_ROMSIZE_KB_10240 default 12288 if COREBOOT_ROMSIZE_KB_12288 @@ -153,6 +162,7 @@ default 0x100000 if COREBOOT_ROMSIZE_KB_1024 default 0x200000 if COREBOOT_ROMSIZE_KB_2048 default 0x400000 if COREBOOT_ROMSIZE_KB_4096 + default 0x600000 if COREBOOT_ROMSIZE_KB_6144 default 0x800000 if COREBOOT_ROMSIZE_KB_8192 default 0xa00000 if COREBOOT_ROMSIZE_KB_10240 default 0xc00000 if COREBOOT_ROMSIZE_KB_12288 -- To view, visit https://review.coreboot.org/c/coreboot/+/30980 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a1949c3512528b6b73955d907efc21728eed739 Gerrit-Change-Number: 30980 Gerrit-PatchSet: 1 Gerrit-Owner: Kacper Słomiński <kacper.slominski72(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Documentation: libgfxinit timing parameters
by Daniel Maslowski (Code Review) 09 Jun '19

09 Jun '19

Daniel Maslowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33265 Change subject: Documentation: libgfxinit timing parameters ...................................................................... Documentation: libgfxinit timing parameters Change-Id: If1a393578556d51499c700b68187034830d19215 Signed-off-by: Daniel Maslowski <daniel.maslowski(a)img.ly> --- A Documentation/gfx/intel-gma.md M Documentation/gfx/libgfxinit.md M Documentation/index.md 3 files changed, 43 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/33265/1 diff --git a/Documentation/gfx/intel-gma.md b/Documentation/gfx/intel-gma.md new file mode 100644 index 0000000..d6a3992 --- /dev/null +++ b/Documentation/gfx/intel-gma.md @@ -0,0 +1,39 @@ +Intel GMA (Graphics Media Accelerator) Specifics +================================================ + +Timing Parameters +----------------- + +From the binary file `edid` in the sys filesystem on Linux, the panel can be +identified. The exact path may differ slightly. Here is an example: + +```sh +$ strings /sys/devices/pci0000:00/0000:00:02.0/drm/card0/card0-eDP-1/edid +@0 5 +LG Display +LP140WF3-SPD1 +``` + +To figure out the timing parameters, refer to the [Intel Programmer's Reference +Manuals](https://01.org/linuxgraphics/documentation/hardware-specification-prms) +and try to find the datasheet of the panel using the information from `edid`. +In the example above, you would search for `LP140WF3-SPD1`. Find a table listing +the power sequence timing parameters, which are usually named T[N] and also +referenced in Intel's respective registers listing. You need the values for +`PP_ON_DELAYS`, `PP_OFF_DELAYS` and `PP_DIVISOR` for your `devicetree.cb`: + +```eval_rst ++----------------------------+---------------------------------------+--------+ +|Intel docs | devicetree.cb | Haswell| ++----------------------------+---------------------------------------+--------+ +|Power up delay | `gpu_panel_power_up_delay` | T3 | ++----------------------------+---------------------------------------+--------+ +|Power on to backlight on | `gpu_panel_power_backlight_on_delay` | T7 | ++----------------------------+---------------------------------------+--------+ +|Power Down delay | `gpu_panel_power_down_delay` | T10 | ++----------------------------+---------------------------------------+--------+ +|Backlight off to power down | `gpu_panel_power_backlight_off_delay` | T7 | ++----------------------------+---------------------------------------+--------+ +|Power Cycle Delay | `gpu_panel_power_cycle_delay` | T12 | ++----------------------------+---------------------------------------+--------+ +``` diff --git a/Documentation/gfx/libgfxinit.md b/Documentation/gfx/libgfxinit.md index c50761a..a80291c 100644 --- a/Documentation/gfx/libgfxinit.md +++ b/Documentation/gfx/libgfxinit.md @@ -55,6 +55,9 @@ GMA: Per Board Configuration ---------------------------- +In order to set up the display panel, see the +[specifics for Intel GMA](gfx/intel-gma.md). + There are a few Kconfig symbols to consider. To indicate that a board can initialize graphics through *libgfxinit*: diff --git a/Documentation/index.md b/Documentation/index.md index 6dbbf4d..8e18f4a 100644 --- a/Documentation/index.md +++ b/Documentation/index.md @@ -173,6 +173,7 @@ * [Dealing with Untrusted Input in SMM](technotes/2017-02-dealing-with-untrusted-input-in-smm.md) * [GPIO toggling in ACPI AML](acpi/gpio.md) * [Native Graphics Initialization with libgfxinit](gfx/libgfxinit.md) +* [Intel GMA specifics](gfx/intel-gma.md) * [Architecture-specific documentation](arch/index.md) * [Northbridge-specific documentation](northbridge/index.md) * [System on Chip-specific documentation](soc/index.md) -- To view, visit https://review.coreboot.org/c/coreboot/+/33265 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1a393578556d51499c700b68187034830d19215 Gerrit-Change-Number: 33265 Gerrit-PatchSet: 1 Gerrit-Owner: Daniel Maslowski <info(a)orangecms.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: device/cpu_device.c: Use 'unsigned int' instead of 'unsigned'
by Arthur Heymans (Code Review) 09 Jun '19

09 Jun '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33329 ) Change subject: device/cpu_device.c: Use 'unsigned int' instead of 'unsigned' ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/33329 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f96d8c8e6cf2715e62ab3715da83740db8cce40 Gerrit-Change-Number: 33329 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 09 Jun 2019 09:14:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: Add option to disable CPU AES
by Name of user not set (Code Review) 09 Jun '19

09 Jun '19

Name of user not set #1002424 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33162 Change subject: Add option to disable CPU AES ...................................................................... Add option to disable CPU AES Added an option(CPU_DISABLE_HW_AES) to cpu/Kconfig to allow to disable CPU hardware-accelerated AES. For Intel CPUs, this is named "AES-NI", and it's controlled via a Model Specific Register(MSR) called MSR_FEATURE_CONFIG. I have modified some Intel CPU's code to disable AES-NI if that Kconfig option is checked in. Change-Id: I61da765b4c6efc73b2379c075c3ab46d16764dc4 Signed-off-by: Vladocb <vladocb(a)protonmail.com> --- M src/cpu/Kconfig M src/cpu/intel/fsp_model_406dx/model_406dx_init.c M src/cpu/intel/haswell/finalize.c M src/cpu/intel/model_2065x/finalize.c M src/cpu/intel/model_206ax/finalize.c M src/soc/intel/apollolake/cpu.c 6 files changed, 55 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/33162/1 diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index 6078022..5d5b338 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -223,3 +223,10 @@ microcode binary files to include, separated by spaces. If unsure, leave this blank. + +config CPU_DISABLE_HW_AES + bool "Disable CPU hardware-accelerated AES cryptographic instructions" + default n + help + Check this in to disable AES cryptographic hardware acceleration on the CPU. + diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx_init.c b/src/cpu/intel/fsp_model_406dx/model_406dx_init.c index efa8693..e923e50 100644 --- a/src/cpu/intel/fsp_model_406dx/model_406dx_init.c +++ b/src/cpu/intel/fsp_model_406dx/model_406dx_init.c @@ -56,16 +56,26 @@ msr.lo = 0; msr.hi = 0; wrmsr(IA32_THERM_INTERRUPT, msr); + + /* AES_NI */ +#if CONFIG(CPU_DISABLE_HW_AES) + /* disable AES-NI, and lock feature bit using mask 11b=0x3 */ + msr.lo = 0x3u; + msr.hi = 0x0u; + wrmsr(MSR_FEATURE_CONFIG, msr); +#else + /* enable AES-NI */ + msr_set_bit(MSR_FEATURE_CONFIG, 0); +#endif } static void configure_mca(void) { msr_t msr; - int i; - msr.lo = msr.hi = 0; + msr.lo = msr.hi = 0x0u; /* This should only be done on a cold boot */ - for (i = 0; i < 6; i++) + for (int i = 0; i < 6; i++) wrmsr(IA32_MC0_STATUS + (i * 4), msr); } diff --git a/src/cpu/intel/haswell/finalize.c b/src/cpu/intel/haswell/finalize.c index cc2d1a4..3a18eda 100644 --- a/src/cpu/intel/haswell/finalize.c +++ b/src/cpu/intel/haswell/finalize.c @@ -51,8 +51,16 @@ msr_set_bit(MSR_PKG_CST_CONFIG_CONTROL, 15); /* Lock AES-NI only if supported */ - if (cpuid_ecx(1) & (1 << 25)) + if (cpuid_ecx(1) & (1 << 25)) { +#if CONFIG(CPU_DISABLE_HW_AES) + /* disable AES-NI, and lock feature bit using mask 11b=0x3 */ + const msr_t myMsr = { 0x3u, 0x0u }; + wrmsr(MSR_FEATURE_CONFIG, myMsr); +#else + /* keep AES-NI enabled */ msr_set_bit(MSR_FEATURE_CONFIG, 0); +#endif + } #ifdef LOCK_POWER_CONTROL_REGISTERS /* diff --git a/src/cpu/intel/model_2065x/finalize.c b/src/cpu/intel/model_2065x/finalize.c index 5b85601..ced5ee3 100644 --- a/src/cpu/intel/model_2065x/finalize.c +++ b/src/cpu/intel/model_2065x/finalize.c @@ -49,8 +49,15 @@ msr_set_bit(MSR_PKG_CST_CONFIG_CONTROL, 15); /* Lock AES-NI only if supported */ - if (cpuid_ecx(1) & (1 << 25)) + if (cpuid_ecx(1) & (1 << 25)) { +#if CONFIG(CPU_DISABLE_HW_AES) + /* disable AES-NI, and lock feature bit using mask 11b=0x3 */ + const msr_t myMsr = { 0x3u, 0x0u }; + wrmsr(MSR_FEATURE_CONFIG, myMsr); +#else msr_set_bit(MSR_FEATURE_CONFIG, 0); +#endif + } /* Lock TM interrupts - route thermal events to all processors */ msr_set_bit(MSR_MISC_PWR_MGMT, 22); diff --git a/src/cpu/intel/model_206ax/finalize.c b/src/cpu/intel/model_206ax/finalize.c index 30b00bb..0e370b7 100644 --- a/src/cpu/intel/model_206ax/finalize.c +++ b/src/cpu/intel/model_206ax/finalize.c @@ -49,8 +49,16 @@ msr_set_bit(MSR_PKG_CST_CONFIG_CONTROL, 15); /* Lock AES-NI only if supported */ - if (cpuid_ecx(1) & (1 << 25)) + if (cpuid_ecx(1) & (1 << 25)) { +#if CONFIG(CPU_DISABLE_HW_AES) + /* disable AES-NI, and lock feature bit using mask 11b=0x3 */ + const msr_t myMsr = { 0x3u, 0x0u }; + wrmsr(MSR_FEATURE_CONFIG, myMsr); +#else + /* keep AES-NI enabled */ msr_set_bit(MSR_FEATURE_CONFIG, 0); +#endif + } #ifdef LOCK_POWER_CONTROL_REGISTERS /* diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index aad0f6b..96f9d9f 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -60,12 +60,21 @@ #endif /* Disable C1E */ REG_MSR_RMW(MSR_POWER_CTL, ~POWER_CTL_C1E_MASK, 0), +#if CONFIG(CPU_DISABLE_HW_AES) + /* + * Disable and Lock the Advanced Encryption Standard (AES-NI) + * feature register + */ + REG_MSR_RMW(MSR_FEATURE_CONFIG, FEATURE_CONFIG_RESERVED_MASK, + FEATURE_CONFIG_LOCK), +#else /* * Enable and Lock the Advanced Encryption Standard (AES-NI) * feature register */ REG_MSR_RMW(MSR_FEATURE_CONFIG, ~FEATURE_CONFIG_RESERVED_MASK, FEATURE_CONFIG_LOCK), +#endif REG_SCRIPT_END }; -- To view, visit https://review.coreboot.org/c/coreboot/+/33162 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I61da765b4c6efc73b2379c075c3ab46d16764dc4 Gerrit-Change-Number: 33162 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1002424 Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/hatch: Add 16G 2666 LPDDR3 SPD
by Shelley Chen (Code Review) 09 Jun '19

09 Jun '19

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33274 Change subject: mb/google/hatch: Add 16G 2666 LPDDR3 SPD ...................................................................... mb/google/hatch: Add 16G 2666 LPDDR3 SPD One variant is asking for support for 16G 2666 LPDDR3, so adding generic SPD for that. BUG=b:133455595 BRANCH=None TEST=None as this is not being used yet Change-Id: If16a101119aabc30d6ea83e95e9ded2e089a982d Signed-off-by: Shelley Chen <shchen(a)google.com> --- A src/mainboard/google/hatch/spd/LP_16G_2133.spd.hex 1 file changed, 32 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/33274/1 diff --git a/src/mainboard/google/hatch/spd/LP_16G_2133.spd.hex b/src/mainboard/google/hatch/spd/LP_16G_2133.spd.hex new file mode 100644 index 0000000..04d640f --- /dev/null +++ b/src/mainboard/google/hatch/spd/LP_16G_2133.spd.hex @@ -0,0 +1,32 @@ +24 01 0F 0E 15 1A B4 08 00 00 00 0B 0A 03 00 00 +00 00 08 FF D4 01 00 00 78 00 90 A8 90 90 06 D0 +02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 08 7F C2 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -- To view, visit https://review.coreboot.org/c/coreboot/+/33274 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If16a101119aabc30d6ea83e95e9ded2e089a982d Gerrit-Change-Number: 33274 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/hatch: Add 8G 3200 SPD
by Shelley Chen (Code Review) 09 Jun '19

09 Jun '19

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33258 Change subject: mb/google/hatch: Add 8G 3200 SPD ...................................................................... mb/google/hatch: Add 8G 3200 SPD One variant is asking for support for 8G 3200 DDR4, so adding generic SPD for that. BUG=b:132920013 BRANCH=None TEST=None as this is not being used yet Change-Id: I89cd3287aaf0baf384c4fe82d0881b0c48e09753 Signed-off-by: Shelley Chen <shchen(a)google.com> --- A src/mainboard/google/hatch/spd/8G_3200.spd.hex 1 file changed, 32 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/33258/1 diff --git a/src/mainboard/google/hatch/spd/8G_3200.spd.hex b/src/mainboard/google/hatch/spd/8G_3200.spd.hex new file mode 100644 index 0000000..7388ad6 --- /dev/null +++ b/src/mainboard/google/hatch/spd/8G_3200.spd.hex @@ -0,0 +1,32 @@ +23 11 0C 03 45 21 00 08 00 60 00 03 02 03 00 00 +00 00 05 0D F8 FF 2B 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 D0 19 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -- To view, visit https://review.coreboot.org/c/coreboot/+/33258 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I89cd3287aaf0baf384c4fe82d0881b0c48e09753 Gerrit-Change-Number: 33258 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/intel/icelake_rvp: Update FSP-M UPDs to support iclrvp memory init
by Subrata Banik (Code Review) 08 Jun '19

08 Jun '19

Subrata Banik has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32522 ) Change subject: mb/intel/icelake_rvp: Update FSP-M UPDs to support iclrvp memory init ...................................................................... mb/intel/icelake_rvp: Update FSP-M UPDs to support iclrvp memory init Change-Id: Ib55fdfae6e9320c44761682fc134be0731de0fcf Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32522 Reviewed-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/intel/icelake_rvp/romstage_fsp_params.c 1 file changed, 44 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Wonkyu Kim: Looks good to me, approved diff --git a/src/mainboard/intel/icelake_rvp/romstage_fsp_params.c b/src/mainboard/intel/icelake_rvp/romstage_fsp_params.c index b9ce394..fd1638b 100644 --- a/src/mainboard/intel/icelake_rvp/romstage_fsp_params.c +++ b/src/mainboard/intel/icelake_rvp/romstage_fsp_params.c @@ -14,12 +14,55 @@ */ #include <arch/byteorder.h> +#include <console/console.h> #include <fsp/api.h> #include <soc/romstage.h> #include <spd_bin.h> - +#include "board_id.h" #include "spd/spd.h" void mainboard_memory_init_params(FSPM_UPD *mupd) { + FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; + u8 spd_index = (get_board_id() & 0x1F) & 0x7; + printk(BIOS_DEBUG, "spd index is 0x%x\n", spd_index); + + if (spd_index > 0 && spd_index != 2) { + struct region_device spd_rdev; + + if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) + die("spd.bin not found\n"); + + mem_cfg->MemorySpdDataLen = region_device_sz(&spd_rdev); + + /* Memory leak is ok since we have memory mapped boot media */ + mem_cfg->MemorySpdPtr00 = (uintptr_t)rdev_mmap_full(&spd_rdev); + mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; + + mem_cfg->SpdAddressTable[0] = 0x0; + mem_cfg->SpdAddressTable[1] = 0x0; + mem_cfg->SpdAddressTable[2] = 0x0; + mem_cfg->SpdAddressTable[3] = 0x0; + } else { + mem_cfg->MemorySpdPtr00 = 0; + mem_cfg->MemorySpdPtr01 = 0; + mem_cfg->MemorySpdPtr10 = 0; + mem_cfg->MemorySpdPtr11 = 0; + + mem_cfg->SpdAddressTable[0] = 0xA0; + mem_cfg->SpdAddressTable[1] = 0xA2; + mem_cfg->SpdAddressTable[2] = 0xA4; + mem_cfg->SpdAddressTable[3] = 0xA6; + } + mem_cfg->DqPinsInterleaved = 0; + mem_cfg->CaVrefConfig = 0x2; /* VREF_CA->CHA/CHB */ + mem_cfg->ECT = 1; /* Early Command Training Enabled */ + mem_cfg->RefClk = 0; /* Auto Select CLK freq */ + + mainboard_fill_dq_map_ch0(&mem_cfg->DqByteMapCh0); + mainboard_fill_dq_map_ch1(&mem_cfg->DqByteMapCh1); + mainboard_fill_dqs_map_ch0(&mem_cfg->DqsMapCpu2DramCh0); + mainboard_fill_dqs_map_ch1(&mem_cfg->DqsMapCpu2DramCh1); + mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); } -- To view, visit https://review.coreboot.org/c/coreboot/+/32522 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib55fdfae6e9320c44761682fc134be0731de0fcf Gerrit-Change-Number: 32522 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamirbohra(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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coreboot-gerrit June 2019