coreboot-gerrit June 2019

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Change in ...coreboot[master]: util/lint: Update checkpatch max line length from 80 to 96
by Martin Roth (Code Review) 11 Jun '19

11 Jun '19

Hello Kyösti Mälkki, Aaron Durbin, Julius Werner, Arthur Heymans, Paul Menzel, Stefan Reinauer, build bot (Jenkins), Patrick Georgi, Werner Zeh, ron minnich, Marc Jones, Nico Huber, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/27533 to look at the new patch set (#4). Change subject: util/lint: Update checkpatch max line length from 80 to 96 ...................................................................... util/lint: Update checkpatch max line length from 80 to 96 coreboot has decided to go with a max line length of 96 characters so update checkpatch. Change-Id: Ic76f9544a609f4c941902c45d5f77df0b644f6a8 Signed-off-by: Martin Roth <martin(a)coreboot.org> --- M util/lint/checkpatch.pl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/27533/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/27533 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic76f9544a609f4c941902c45d5f77df0b644f6a8 Gerrit-Change-Number: 27533 Gerrit-PatchSet: 4 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Alex Thiessen <alex.thiessen.de+coreboot(a)gmail.com> Gerrit-CC: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-CC: Vadim Bendebury <vbendeb(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: util/lint: Update checkpatch max line length from 80 to 96
by Martin Roth (Code Review) 11 Jun '19

11 Jun '19

Martin Roth has restored this change. ( https://review.coreboot.org/c/coreboot/+/27533 ) Change subject: util/lint: Update checkpatch max line length from 80 to 96 ...................................................................... Restored -- To view, visit https://review.coreboot.org/c/coreboot/+/27533 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic76f9544a609f4c941902c45d5f77df0b644f6a8 Gerrit-Change-Number: 27533 Gerrit-PatchSet: 2 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Alex Thiessen <alex.thiessen.de+coreboot(a)gmail.com> Gerrit-CC: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-CC: Vadim Bendebury <vbendeb(a)chromium.org> Gerrit-MessageType: restore

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Change in ...coreboot[master]: console: Allow using vprintk() with disabled console
by Jacob Garber (Code Review) 11 Jun '19

11 Jun '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33181 Change subject: console: Allow using vprintk() with disabled console ...................................................................... console: Allow using vprintk() with disabled console The prototype of vprintk() is currently declared unconditionally, which prevents it from being used in situations where the console is disabled. The code will compile correctly, but not link, since the definition in console.c isn't being provided. This adds a shim around the declaration so that, like printk(), a call to vprintk() in this situation will expand to a no-op function instead. Change-Id: Ib4a9aa96a5b9dbb9b937ff45854bf6a407938b37 Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> --- M src/console/printk.c M src/include/console/console.h 2 files changed, 7 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/33181/1 diff --git a/src/console/printk.c b/src/console/printk.c index 0952215..8606bbb 100644 --- a/src/console/printk.c +++ b/src/console/printk.c @@ -45,7 +45,7 @@ __cbmemc_tx_byte(byte); } -int vprintk(int msg_level, const char *fmt, va_list args) +int do_vprintk(int msg_level, const char *fmt, va_list args) { int i, log_this; @@ -91,7 +91,7 @@ int i; va_start(args, fmt); - i = vprintk(msg_level, fmt, args); + i = do_vprintk(msg_level, fmt, args); va_end(args); return i; diff --git a/src/include/console/console.h b/src/include/console/console.h index 082ba29..ba884d6 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -62,8 +62,8 @@ int console_log_level(int msg_level); void do_putchar(unsigned char byte); -#define printk(LEVEL, fmt, args...) \ - do { do_printk(LEVEL, fmt, ##args); } while (0) +#define printk(LEVEL, fmt, args...) do_printk(LEVEL, fmt, ##args) +#define vprintk(LEVEL, fmt, args) do_vprintk(LEVEL, fmt, args) enum { CONSOLE_LOG_NONE = 0, CONSOLE_LOG_FAST, CONSOLE_LOG_ALL }; @@ -83,14 +83,15 @@ static inline void console_init(void) {} static inline int console_log_level(int msg_level) { return 0; } static inline void printk(int LEVEL, const char *fmt, ...) {} +static inline void vprintk(int LEVEL, const char *fmt, args) {} static inline void do_putchar(unsigned char byte) {} #endif -int vprintk(int msg_level, const char *fmt, va_list args); - int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3))); +int do_vprintk(int msg_level, const char *fmt, va_list args); + #endif /* !__ROMCC__ */ #endif /* CONSOLE_CONSOLE_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/33181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4a9aa96a5b9dbb9b937ff45854bf6a407938b37 Gerrit-Change-Number: 33181 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: console: Make die() and friends variadic
by Jacob Garber (Code Review) 11 Jun '19

11 Jun '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33153 Change subject: console: Make die() and friends variadic ...................................................................... console: Make die() and friends variadic die() currently only accepts a fixed message string, which is rather inconvenient when there is extra information that would be helpful to print in the error message. This currently requires an extra call to printk(), which is somewhat awkward: printk(BIOS_EMERG, "Bad table, opcode %d at %d", id, i); die(""); // what do I say here? die() already has a printk() inside it to print the error message, so let's just make it variadic to combine the two. die("Bad table, opcode %d at %d", id, i); // much better Forwarding variadic arguments from one function to another is rather tricky, so die_with_post_code() is redefined as a variadic macro instead. Change-Id: I28b9eac32899a1aa89e086e0d3889b75459581aa Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> --- M src/console/die.c M src/include/console/console.h 2 files changed, 10 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/33153/1 diff --git a/src/console/die.c b/src/console/die.c index 513d1c4..3a17126 100644 --- a/src/console/die.c +++ b/src/console/die.c @@ -30,17 +30,15 @@ } /* Report a fatal error */ -void __noreturn die(const char *msg) +void __noreturn die(const char *fmt, ...) { - printk(BIOS_EMERG, "%s", msg); + va_list args; + + va_start(args, fmt); + vprintk(BIOS_EMERG, fmt, args); + va_end(args); + die_notify(); halt(); } - -/* Report a fatal error with a post code */ -void __noreturn die_with_post_code(uint8_t value, const char *msg) -{ - post_code(value); - die(msg); -} #endif diff --git a/src/include/console/console.h b/src/include/console/console.h index 082ba29..369ce5b 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -42,8 +42,9 @@ #endif /* this function is weak and can be overridden by a mainboard function. */ void mainboard_post(u8 value); -void __noreturn die(const char *msg); -void __noreturn die_with_post_code(uint8_t value, const char *msg); +void __noreturn die(const char *fmt, ...); +#define die_with_post_code(value, fmt, ...) \ + do { post_code(value); die(fmt, ##__VA_ARGS__); } while (0) /* * This function is weak and can be overridden to provide additional -- To view, visit https://review.coreboot.org/c/coreboot/+/33153 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28b9eac32899a1aa89e086e0d3889b75459581aa Gerrit-Change-Number: 33153 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: ACPI: Add SPCR table
by Martin Roth (Code Review) 11 Jun '19

11 Jun '19

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25344 ) Change subject: ACPI: Add SPCR table ...................................................................... Patch Set 6: (1 comment) This change is ready for review. https://review.coreboot.org/#/c/25344/3/src/arch/x86/acpi.c File src/arch/x86/acpi.c: https://review.coreboot.org/#/c/25344/3/src/arch/x86/acpi.c@1328 PS3, Line 1328: Error > From the subsequent commit this does seem to be called every time, so I suspect you want to make thi […] Ultimately we want it to supply the correct serial port even if console is disabled. For now, I'm adding a check that will exit the routine if the coreboot serial console is disabled. -- To view, visit https://review.coreboot.org/c/coreboot/+/25344 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ff31da061c88a6f3e3cf76285f8ab78ee35509c Gerrit-Change-Number: 25344 Gerrit-PatchSet: 6 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)chromium.org> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Comment-Date: Tue, 11 Jun 2019 17:16:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/amd/stoneyridge: Generate SPCR table
by Martin Roth (Code Review) 11 Jun '19

11 Jun '19

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25345 ) Change subject: soc/amd/stoneyridge: Generate SPCR table ...................................................................... Patch Set 6: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/25345 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc98bcf4f8c070b8002bcc795254b19f928c741b Gerrit-Change-Number: 25345 Gerrit-PatchSet: 6 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)chromium.org> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 11 Jun 2019 17:16:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: Kconfig: Create coreboot separate stage kconfigs
by Subrata Banik (Code Review) 11 Jun '19

11 Jun '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33142 Change subject: Kconfig: Create coreboot separate stage kconfigs ...................................................................... Kconfig: Create coreboot separate stage kconfigs This patch creates seperate stage configs as below 1. STAGE_BOOTBLOCK 2. STAGE_VERSTAGE 3. STAGE_ROMSTAGE 4. STAGE_RAMSTAGE A stage can only be enabled if soc has selected its supported architecture(example: arm, ppc, riscv, x86) Change-Id: I0f7e4174619016c5a54c28bedd52699df417a5b7 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/Kconfig 1 file changed, 32 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/33142/1 diff --git a/src/Kconfig b/src/Kconfig index d30aa99..4c1fe32 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -18,6 +18,38 @@ menu "General setup" +config STAGE_BOOTBLOCK + bool "Enable bootblock stage" + default y if ARCH_BOOTBLOCK_PPC64 || ARCH_BOOTBLOCK_ARMV8_64 || ARCH_BOOTBLOCK_ARM64 || ARCH_BOOTBLOCK_ARMV7 || ARCH_BOOTBLOCK_ARMV7_M || ARCH_BOOTBLOCK_ARMV7_R || ARCH_BOOTBLOCK_ARM || ARCH_BOOTBLOCK_ARMV4 || ARCH_BOOTBLOCK_RISCV || ARCH_BOOTBLOCK_X86_32 || ARCH_BOOTBLOCK_X86_64 || ARCH_BOOTBLOCK_MIPS + default n + help + This option is enabled if soc has selected any of supported + bootblock architecture (example: arm, ppc, riscv, x86). + +config STAGE_VERSTAGE + bool "Enable verstage stage" + default y if ARCH_VERSTAGE_PPC64 || ARCH_VERSTAGE_ARMV8_64 || ARCH_VERSTAGE_ARM64 || ARCH_VERSTAGE_ARMV7 || ARCH_VERSTAGE_ARMV7_M || ARCH_VERSTAGE_ARMV7_R || ARCH_VERSTAGE_ARM || ARCH_VERSTAGE_ARMV4 || ARCH_VERSTAGE_RISCV || ARCH_VERSTAGE_X86_32 || ARCH_VERSTAGE_X86_64 || ARCH_VERSTAGE_MIPS + default n + help + This option is enabled if soc has selected any of supported + verstage architecture (example: arm, ppc, riscv, x86). + +config STAGE_ROMSTAGE + bool "Enable romstage stage" + default y if ARCH_ROMSTAGE_PPC64 || ARCH_ROMSTAGE_ARMV8_64 || ARCH_ROMSTAGE_ARM64 || ARCH_ROMSTAGE_ARMV7 || ARCH_ROMSTAGE_ARMV7_R || ARCH_ROMSTAGE_ARM || ARCH_ROMSTAGE_ARMV4 || ARCH_ROMSTAGE_RISCV || ARCH_ROMSTAGE_X86_32 || ARCH_ROMSTAGE_X86_64 || ARCH_ROMSTAGE_MIPS + default n + help + This option is enabled if soc has selected any of supported + romstage architecture (example: arm, ppc, riscv, x86). + +config STAGE_RAMSTAGE + bool "Enable ramstage stage" + default y if ARCH_RAMSTAGE_PPC64 || ARCH_RAMSTAGE_ARMV8_64 || ARCH_RAMSTAGE_ARM64 || ARCH_RAMSTAGE_ARMV7 || ARCH_RAMSTAGE_ARMV7_R || ARCH_RAMSTAGE_ARM || ARCH_RAMSTAGE_ARMV4 || ARCH_RAMSTAGE_RISCV || ARCH_RAMSTAGE_X86_32 || ARCH_RAMSTAGE_X86_64 || ARCH_RAMSTAGE_MIPS + default n + help + This option is enabled if soc has selected any of supported + ramstage architecture (example: arm, ppc, riscv, x86). + config COREBOOT_BUILD bool default y -- To view, visit https://review.coreboot.org/c/coreboot/+/33142 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f7e4174619016c5a54c28bedd52699df417a5b7 Gerrit-Change-Number: 33142 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/amd/stoneyridge: Add DRAM check for s3
by Marshall Dawson (Code Review) 11 Jun '19

11 Jun '19

Marshall Dawson has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/29406 ) Change subject: soc/amd/stoneyridge: Add DRAM check for s3 ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/29406 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I375dd7ea9a3ab8992f1616126bcbd9724e4fc9a0 Gerrit-Change-Number: 29406 Gerrit-PatchSet: 5 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in ...coreboot[master]: soc/amd/common: Add errors for invalid AcpiMmio access
by Marshall Dawson (Code Review) 11 Jun '19

11 Jun '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32934 Change subject: soc/amd/common: Add errors for invalid AcpiMmio access ...................................................................... soc/amd/common: Add errors for invalid AcpiMmio access Print an error when accessing a reserved or unexpected AcpiMmio register block. At a minimum, require the soc to indicate in its iomap.h file which register blocks it allows coreboot to use. It may optionally indicate all that are supported/documented or may treat unused blocks as reserved. This patch attempts to dissuade accessing unsupported blocks without requiring the complexity of structures or reinitializing at the beginning of a new stage. TEST=inspect grunt build with objdump with supported and unsupported blocks BUG=b:131682806 Change-Id: I2121df108fd3caf07e5588bc3201bcdd8dcaaa00 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/block/acpimmio/mmio_util.c M src/soc/amd/common/block/include/amdblocks/acpimmio.h M src/soc/amd/stoneyridge/include/soc/iomap.h 3 files changed, 185 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/32934/1 diff --git a/src/soc/amd/common/block/acpimmio/mmio_util.c b/src/soc/amd/common/block/acpimmio/mmio_util.c index c8c6988..89edf396 100644 --- a/src/soc/amd/common/block/acpimmio/mmio_util.c +++ b/src/soc/amd/common/block/acpimmio/mmio_util.c @@ -16,6 +16,7 @@ #include <types.h> #include <arch/io.h> #include <device/mmio.h> +#include <console/console.h> #include <amdblocks/acpimmio_map.h> #include <amdblocks/acpimmio.h> @@ -65,37 +66,55 @@ pm_io_write16(reg + sizeof(uint16_t), value & 0xffff); } +static void print_error(uintptr_t base, uint8_t reg) +{ + printk(BIOS_ERR, "Error: attempting to access offset 0x%x of unsupported AcpiMmio at 0x%lx\n", + reg, base); +} + /* smbus pci read/write - access registers at 0xfed80000 - currently unused */ /* smi read/write - access registers at 0xfed80200 */ uint8_t smi_read8(uint8_t reg) { + if (!SUPPORTS_ACPIMMIO_SMI_BASE) + print_error(ACPIMMIO_SMI_BASE, reg); return read8((void *)(ACPIMMIO_SMI_BASE + reg)); } uint16_t smi_read16(uint8_t reg) { + if (!SUPPORTS_ACPIMMIO_SMI_BASE) + print_error(ACPIMMIO_SMI_BASE, reg); return read16((void *)(ACPIMMIO_SMI_BASE + reg)); } uint32_t smi_read32(uint8_t reg) { + if (!SUPPORTS_ACPIMMIO_SMI_BASE) + print_error(ACPIMMIO_SMI_BASE, reg); return read32((void *)(ACPIMMIO_SMI_BASE + reg)); } void smi_write8(uint8_t reg, uint8_t value) { + if (!SUPPORTS_ACPIMMIO_SMI_BASE) + print_error(ACPIMMIO_SMI_BASE, reg); write8((void *)(ACPIMMIO_SMI_BASE + reg), value); } void smi_write16(uint8_t reg, uint16_t value) { + if (!SUPPORTS_ACPIMMIO_SMI_BASE) + print_error(ACPIMMIO_SMI_BASE, reg); write16((void *)(ACPIMMIO_SMI_BASE + reg), value); } void smi_write32(uint8_t reg, uint32_t value) { + if (!SUPPORTS_ACPIMMIO_SMI_BASE) + print_error(ACPIMMIO_SMI_BASE, reg); write32((void *)(ACPIMMIO_SMI_BASE + reg), value); } @@ -103,31 +122,43 @@ u8 pm_read8(u8 reg) { + if (!SUPPORTS_ACPIMMIO_PMIO_BASE) + print_error(ACPIMMIO_PMIO_BASE, reg); return read8((void *)(ACPIMMIO_PMIO_BASE + reg)); } u16 pm_read16(u8 reg) { + if (!SUPPORTS_ACPIMMIO_PMIO_BASE) + print_error(ACPIMMIO_PMIO_BASE, reg); return read16((void *)(ACPIMMIO_PMIO_BASE + reg)); } u32 pm_read32(u8 reg) { + if (!SUPPORTS_ACPIMMIO_PMIO_BASE) + print_error(ACPIMMIO_PMIO_BASE, reg); return read32((void *)(ACPIMMIO_PMIO_BASE + reg)); } void pm_write8(u8 reg, u8 value) { + if (!SUPPORTS_ACPIMMIO_PMIO_BASE) + print_error(ACPIMMIO_PMIO_BASE, reg); write8((void *)(ACPIMMIO_PMIO_BASE + reg), value); } void pm_write16(u8 reg, u16 value) { + if (!SUPPORTS_ACPIMMIO_PMIO_BASE) + print_error(ACPIMMIO_PMIO_BASE, reg); write16((void *)(ACPIMMIO_PMIO_BASE + reg), value); } void pm_write32(u8 reg, u32 value) { + if (!SUPPORTS_ACPIMMIO_PMIO_BASE) + print_error(ACPIMMIO_PMIO_BASE, reg); write32((void *)(ACPIMMIO_PMIO_BASE + reg), value); } @@ -137,6 +168,8 @@ uint8_t biosram_read8(uint8_t reg) { + if (!SUPPORTS_ACPIMMIO_BIOSRAM_BASE) + print_error(ACPIMMIO_BIOSRAM_BASE, reg); /* could see 1/2/4x */ return read8((void *)(ACPIMMIO_BIOSRAM_BASE + reg)); } @@ -153,6 +186,8 @@ void biosram_write8(uint8_t reg, uint8_t value) { + if (!SUPPORTS_ACPIMMIO_BIOSRAM_BASE) + print_error(ACPIMMIO_BIOSRAM_BASE, reg); /* could see 1/2/4x */ write8((void *)(ACPIMMIO_BIOSRAM_BASE + reg), value); } @@ -178,31 +213,43 @@ u8 acpi_read8(u8 reg) { + if (!SUPPORTS_ACPIMMIO_ACPI_BASE) + print_error(ACPIMMIO_ACPI_BASE, reg); return read8((void *)(ACPIMMIO_ACPI_BASE + reg)); } u16 acpi_read16(u8 reg) { + if (!SUPPORTS_ACPIMMIO_ACPI_BASE) + print_error(ACPIMMIO_ACPI_BASE, reg); return read16((void *)(ACPIMMIO_ACPI_BASE + reg)); } u32 acpi_read32(u8 reg) { + if (!SUPPORTS_ACPIMMIO_ACPI_BASE) + print_error(ACPIMMIO_ACPI_BASE, reg); return read32((void *)(ACPIMMIO_ACPI_BASE + reg)); } void acpi_write8(u8 reg, u8 value) { + if (!SUPPORTS_ACPIMMIO_ACPI_BASE) + print_error(ACPIMMIO_ACPI_BASE, reg); write8((void *)(ACPIMMIO_ACPI_BASE + reg), value); } void acpi_write16(u8 reg, u16 value) { + if (!SUPPORTS_ACPIMMIO_ACPI_BASE) + print_error(ACPIMMIO_ACPI_BASE, reg); write16((void *)(ACPIMMIO_ACPI_BASE + reg), value); } void acpi_write32(u8 reg, u32 value) { + if (!SUPPORTS_ACPIMMIO_ACPI_BASE) + print_error(ACPIMMIO_ACPI_BASE, reg); write32((void *)(ACPIMMIO_ACPI_BASE + reg), value); } @@ -210,21 +257,29 @@ u8 asf_read8(u8 reg) { + if (!SUPPORTS_ACPIMMIO_ASF_BASE) + print_error(ACPIMMIO_ASF_BASE, reg); return read8((void *)(ACPIMMIO_ASF_BASE + reg)); } u16 asf_read16(u8 reg) { + if (!SUPPORTS_ACPIMMIO_ASF_BASE) + print_error(ACPIMMIO_ASF_BASE, reg); return read16((void *)(ACPIMMIO_ASF_BASE + reg)); } void asf_write8(u8 reg, u8 value) { + if (!SUPPORTS_ACPIMMIO_ASF_BASE) + print_error(ACPIMMIO_ASF_BASE, reg); write8((void *)(ACPIMMIO_ASF_BASE + reg), value); } void asf_write16(u8 reg, u16 value) { + if (!SUPPORTS_ACPIMMIO_ASF_BASE) + print_error(ACPIMMIO_ASF_BASE, reg); write16((void *)(ACPIMMIO_ASF_BASE + reg), value); } @@ -232,21 +287,29 @@ u8 smbus_read8(u8 reg) { + if (!SUPPORTS_ACPIMMIO_SMBUS_BASE) + print_error(ACPIMMIO_SMBUS_BASE, reg); return read8((void *)(ACPIMMIO_SMBUS_BASE + reg)); } u16 smbus_read16(u8 reg) { + if (!SUPPORTS_ACPIMMIO_SMBUS_BASE) + print_error(ACPIMMIO_SMBUS_BASE, reg); return read16((void *)(ACPIMMIO_SMBUS_BASE + reg)); } void smbus_write8(u8 reg, u8 value) { + if (!SUPPORTS_ACPIMMIO_SMBUS_BASE) + print_error(ACPIMMIO_SMBUS_BASE, reg); write8((void *)(ACPIMMIO_SMBUS_BASE + reg), value); } void smbus_write16(u8 reg, u16 value) { + if (!SUPPORTS_ACPIMMIO_SMBUS_BASE) + print_error(ACPIMMIO_SMBUS_BASE, reg); write16((void *)(ACPIMMIO_SMBUS_BASE + reg), value); } @@ -258,31 +321,43 @@ u8 iomux_read8(u8 reg) { + if (!SUPPORTS_ACPIMMIO_IOMUX_BASE) + print_error(ACPIMMIO_IOMUX_BASE, reg); return read8((void *)(ACPIMMIO_IOMUX_BASE + reg)); } u16 iomux_read16(u8 reg) { + if (!SUPPORTS_ACPIMMIO_IOMUX_BASE) + print_error(ACPIMMIO_IOMUX_BASE, reg); return read16((void *)(ACPIMMIO_IOMUX_BASE + reg)); } u32 iomux_read32(u8 reg) { + if (!SUPPORTS_ACPIMMIO_IOMUX_BASE) + print_error(ACPIMMIO_IOMUX_BASE, reg); return read32((void *)(ACPIMMIO_IOMUX_BASE + reg)); } void iomux_write8(u8 reg, u8 value) { + if (!SUPPORTS_ACPIMMIO_IOMUX_BASE) + print_error(ACPIMMIO_IOMUX_BASE, reg); write8((void *)(ACPIMMIO_IOMUX_BASE + reg), value); } void iomux_write16(u8 reg, u16 value) { + if (!SUPPORTS_ACPIMMIO_IOMUX_BASE) + print_error(ACPIMMIO_IOMUX_BASE, reg); write16((void *)(ACPIMMIO_IOMUX_BASE + reg), value); } void iomux_write32(u8 reg, u32 value) { + if (!SUPPORTS_ACPIMMIO_IOMUX_BASE) + print_error(ACPIMMIO_IOMUX_BASE, reg); write32((void *)(ACPIMMIO_IOMUX_BASE + reg), value); } @@ -290,31 +365,43 @@ u8 misc_read8(u8 reg) { + if (!SUPPORTS_ACPIMMIO_MISC_BASE) + print_error(ACPIMMIO_MISC_BASE, reg); return read8((void *)(ACPIMMIO_MISC_BASE + reg)); } u16 misc_read16(u8 reg) { + if (!SUPPORTS_ACPIMMIO_MISC_BASE) + print_error(ACPIMMIO_MISC_BASE, reg); return read16((void *)(ACPIMMIO_MISC_BASE + reg)); } u32 misc_read32(u8 reg) { + if (!SUPPORTS_ACPIMMIO_MISC_BASE) + print_error(ACPIMMIO_MISC_BASE, reg); return read32((void *)(ACPIMMIO_MISC_BASE + reg)); } void misc_write8(u8 reg, u8 value) { + if (!SUPPORTS_ACPIMMIO_MISC_BASE) + print_error(ACPIMMIO_MISC_BASE, reg); write8((void *)(ACPIMMIO_MISC_BASE + reg), value); } void misc_write16(u8 reg, u16 value) { + if (!SUPPORTS_ACPIMMIO_MISC_BASE) + print_error(ACPIMMIO_MISC_BASE, reg); write16((void *)(ACPIMMIO_MISC_BASE + reg), value); } void misc_write32(u8 reg, u32 value) { + if (!SUPPORTS_ACPIMMIO_MISC_BASE) + print_error(ACPIMMIO_MISC_BASE, reg); write32((void *)(ACPIMMIO_MISC_BASE + reg), value); } @@ -328,31 +415,43 @@ uint8_t xhci_pm_read8(uint8_t reg) { + if (!SUPPORTS_ACPIMMIO_XHCIPM_BASE) + print_error(ACPIMMIO_XHCIPM_BASE, reg); return read8((void *)(ACPIMMIO_XHCIPM_BASE + reg)); } uint16_t xhci_pm_read16(uint8_t reg) { + if (!SUPPORTS_ACPIMMIO_XHCIPM_BASE) + print_error(ACPIMMIO_XHCIPM_BASE, reg); return read16((void *)(ACPIMMIO_XHCIPM_BASE + reg)); } uint32_t xhci_pm_read32(uint8_t reg) { + if (!SUPPORTS_ACPIMMIO_XHCIPM_BASE) + print_error(ACPIMMIO_XHCIPM_BASE, reg); return read32((void *)(ACPIMMIO_XHCIPM_BASE + reg)); } void xhci_pm_write8(uint8_t reg, uint8_t value) { + if (!SUPPORTS_ACPIMMIO_XHCIPM_BASE) + print_error(ACPIMMIO_XHCIPM_BASE, reg); write8((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); } void xhci_pm_write16(uint8_t reg, uint16_t value) { + if (!SUPPORTS_ACPIMMIO_XHCIPM_BASE) + print_error(ACPIMMIO_XHCIPM_BASE, reg); write16((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); } void xhci_pm_write32(uint8_t reg, uint32_t value) { + if (!SUPPORTS_ACPIMMIO_XHCIPM_BASE) + print_error(ACPIMMIO_XHCIPM_BASE, reg); write32((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); } @@ -362,10 +461,14 @@ u8 aoac_read8(u8 reg) { + if (!SUPPORTS_ACPIMMIO_AOAC_BASE) + print_error(ACPIMMIO_AOAC_BASE, reg); return read8((void *)(ACPIMMIO_AOAC_BASE + reg)); } void aoac_write8(u8 reg, u8 value) { + if (!SUPPORTS_ACPIMMIO_AOAC_BASE) + print_error(ACPIMMIO_AOAC_BASE, reg); write8((void *)(ACPIMMIO_AOAC_BASE + reg), value); } diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h index 6be856b..32da867 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -18,6 +18,69 @@ #ifndef __AMDBLOCKS_ACPIMMIO_H__ #define __AMDBLOCKS_ACPIMMIO_H__ +/* iomap.h must indicate if the device uses a block, optional if unused. */ +#include <soc/iomap.h> +#ifndef SUPPORTS_ACPIMMIO_SMI_BASE + #define SUPPORTS_ACPIMMIO_SMI_BASE 0 +#endif +#ifndef SUPPORTS_ACPIMMIO_PMIO_BASE + #define SUPPORTS_ACPIMMIO_PMIO_BASE 0 +#endif +#ifndef SUPPORTS_ACPIMMIO_PMIO2_BASE + #define SUPPORTS_ACPIMMIO_PMIO2_BASE 0 +#endif +#ifndef SUPPORTS_ACPIMMIO_BIOSRAM_BASE + #define SUPPORTS_ACPIMMIO_BIOSRAM_BASE 0 +#endif +#ifndef SUPPORTS_ACPIMMIO_CMOSRAM_BASE + #define SUPPORTS_ACPIMMIO_CMOSRAM_BASE 0 +#endif +#ifndef SUPPORTS_ACPIMMIO_CMOS_BASE + #define SUPPORTS_ACPIMMIO_CMOS_BASE 0 +#endif +#ifndef SUPPORTS_ACPIMMIO_ACPI_BASE + #define SUPPORTS_ACPIMMIO_ACPI_BASE 0 +#endif +#ifndef SUPPORTS_ACPIMMIO_ASF_BASE + #define SUPPORTS_ACPIMMIO_ASF_BASE 0 +#endif +#ifndef SUPPORTS_ACPIMMIO_SMBUS_BASE + #define SUPPORTS_ACPIMMIO_SMBUS_BASE 0 +#endif +#ifndef SUPPORTS_ACPIMMIO_WDT_BASE + #define SUPPORTS_ACPIMMIO_WDT_BASE 0 +#endif +#ifndef SUPPORTS_ACPIMMIO_HPET_BASE + #define SUPPORTS_ACPIMMIO_HPET_BASE 0 +#endif +#ifndef SUPPORTS_ACPIMMIO_IOMUX_BASE + #define SUPPORTS_ACPIMMIO_IOMUX_BASE 0 +#endif +#ifndef SUPPORTS_ACPIMMIO_MISC_BASE + #define SUPPORTS_ACPIMMIO_MISC_BASE 0 +#endif +#ifndef SUPPORTS_ACPIMMIO_DPVGA_BASE + #define SUPPORTS_ACPIMMIO_DPVGA_BASE 0 +#endif +#ifndef SUPPORTS_ACPIMMIO_GPIO0_BASE + #define SUPPORTS_ACPIMMIO_GPIO0_BASE 0 +#endif +#ifndef SUPPORTS_ACPIMMIO_GPIO1_BASE + #define SUPPORTS_ACPIMMIO_GPIO1_BASE 0 +#endif +#ifndef SUPPORTS_ACPIMMIO_GPIO2_BASE + #define SUPPORTS_ACPIMMIO_GPIO2_BASE 0 +#endif +#ifndef SUPPORTS_ACPIMMIO_XHCIPM_BASE + #define SUPPORTS_ACPIMMIO_XHCIPM_BASE 0 +#endif +#ifndef SUPPORTS_ACPIMMIO_ACDCTMR_BASE + #define SUPPORTS_ACPIMMIO_ACDCTMR_BASE 0 +#endif +#ifndef SUPPORTS_ACPIMMIO_AOAC_BASE + #define SUPPORTS_ACPIMMIO_AOAC_BASE 0 +#endif + /* * The following AcpiMmio register block mapping represents definitions * that have been documented in AMD publications. All blocks aren't diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h index 3856a22..da8906a 100644 --- a/src/soc/amd/stoneyridge/include/soc/iomap.h +++ b/src/soc/amd/stoneyridge/include/soc/iomap.h @@ -22,8 +22,26 @@ #define SPI_BASE_ADDRESS 0xfec10000 #define IO_APIC2_ADDR 0xfec20000 -/* AcpiMmio blocks are at fixed offsets from FED8_0000h, enabled in PMx04[1] */ +/* + * AcpiMmio blocks are at fixed offsets from FED8_0000h, enabled in PMx04[1]. + * All ranges not specified as supported below may, or may not, be listed in + * any documentation but should be considered reserved through FED8_1FFFh. + */ #include <amdblocks/acpimmio_map.h> +#define SUPPORTS_ACPIMMIO_SMI_BASE 1 /* 0xfed80100 */ +#define SUPPORTS_ACPIMMIO_PMIO_BASE 1 /* 0xfed80300 */ +#define SUPPORTS_ACPIMMIO_PMIO2_BASE 1 /* 0xfed80400 */ +#define SUPPORTS_ACPIMMIO_BIOSRAM_BASE 1 /* 0xfed80500 */ +#define SUPPORTS_ACPIMMIO_ACPI_BASE 1 /* 0xfed80800 */ +#define SUPPORTS_ACPIMMIO_ASF_BASE 1 /* 0xfed80900 */ +#define SUPPORTS_ACPIMMIO_SMBUS_BASE 1 /* 0xfed80a00 */ +#define SUPPORTS_ACPIMMIO_IOMUX_BASE 1 /* 0xfed80d00 */ +#define SUPPORTS_ACPIMMIO_MISC_BASE 1 /* 0xfed80e00 */ +#define SUPPORTS_ACPIMMIO_GPIO0_BASE 1 /* 0xfed81500 */ +#define SUPPORTS_ACPIMMIO_GPIO1_BASE 1 /* 0xfed81800 */ +#define SUPPORTS_ACPIMMIO_GPIO2_BASE 1 /* 0xfed81700 */ +#define SUPPORTS_ACPIMMIO_XHCIPM_BASE 1 /* 0xfed81c00 */ +#define SUPPORTS_ACPIMMIO_AOAC_BASE 1 /* 0xfed81e00 */ #define ALINK_AHB_ADDRESS 0xfedc0000 -- To view, visit https://review.coreboot.org/c/coreboot/+/32934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2121df108fd3caf07e5588bc3201bcdd8dcaaa00 Gerrit-Change-Number: 32934 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

5 10

Change in ...coreboot[master]: libpayload: Add UART for qcs405
by Prudhvi Yarlagadda (Code Review) 11 Jun '19

11 Jun '19

Prudhvi Yarlagadda has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29957 ) Change subject: libpayload: Add UART for qcs405 ...................................................................... Patch Set 26: (1 comment) https://review.coreboot.org/#/c/29957/20/payloads/libpayload/drivers/serial… File payloads/libpayload/drivers/serial/qcs405.c: https://review.coreboot.org/#/c/29957/20/payloads/libpayload/drivers/serial… PS20, Line 544: /* For simplicity sake let's rely on coreboot initalizing the UART. */ > Thanks ! we will release the remaining changes and continue to debug the current issue. We have identified that uart rx command registers are getting reset at the end of coreboot stage due to which we are facing issues if we remove the initialization here. Please let us know if we can go ahead by initializing only the UART rx command registers or do the complete UART initialization as it is there at present? -- To view, visit https://review.coreboot.org/c/coreboot/+/29957 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43164cf9eacc844af1d048f7b6ebbda96fc9d202 Gerrit-Change-Number: 29957 Gerrit-PatchSet: 26 Gerrit-Owner: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Mukesh Savaliya <msavaliy(a)qualcomm.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Prudhvi Yarlagadda <pyarlaga(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Tue, 11 Jun 2019 13:19:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Prudhvi Yarlagadda <pyarlaga(a)qualcomm.corp-partner.google.com> Comment-In-Reply-To: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: comment

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coreboot-gerrit June 2019