Subrata Banik has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/33326 )
Change subject: mb/google/hatch: Disable dynamic clock gating for cr50's GPIO
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mb/google/hatch: Disable dynamic clock gating for cr50's GPIO
Disable dynamic clock gating for the community cr50's IRQ lives on.
That IRQ is pulsed very quickly, and with clock gating enabled pulses
tend to be missed. This is expecially true on the default 0.0.22
firmware that cr50 comes with out of the factory.
BUG=b:130764684 b:130338605
BRANCH=None
TEST=Boot hatch with cr50 "intap" firmware that can vary the pulse width,
observe that even with sub-microsecond pulses no IRQs are missed.
Change-Id: I34d14fb7cc97e33eecfda2c99cc53a541c87662d
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
Signed-off-by: Evan Green <evgreen(a)chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33326
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Furquan Shaikh <furquan(a)google.com>
---
M src/mainboard/google/hatch/variants/baseboard/devicetree.cb
1 file changed, 3 insertions(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Furquan Shaikh: Looks good to me, approved
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
index 1123d53..61b712d 100644
--- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
@@ -99,7 +99,9 @@
register "gpio_pm[COMM_1]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
register "gpio_pm[COMM_2]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
register "gpio_pm[COMM_3]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
- register "gpio_pm[COMM_4]" = "MISCCFG_GPSIDEDPCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN"
+ # Disable clock gating on this community so that cr50's short irq
+ # pulses won't be missed.
+ register "gpio_pm[COMM_4]" = "0"
device cpu_cluster 0 on
device lapic 0 on end
--
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Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29957 )
Change subject: libpayload: Add UART for qcs405
......................................................................
Patch Set 26:
(1 comment)
https://review.coreboot.org/#/c/29957/20/payloads/libpayload/drivers/serial…
File payloads/libpayload/drivers/serial/qcs405.c:
https://review.coreboot.org/#/c/29957/20/payloads/libpayload/drivers/serial…
PS20, Line 544: /* For simplicity sake let's rely on coreboot initalizing the UART. */
> We have identified that uart rx command registers are getting reset at the end of coreboot stage due […]
It's fine to only do the initialization that's needed at this point.
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Martin Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/27533 )
Change subject: util/lint: Update checkpatch max line length from 80 to 96
......................................................................
Abandoned
Re-uploaded patrick's patch instead. https://review.coreboot.org/c/coreboot/+/33405
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Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27533 )
Change subject: util/lint: Update checkpatch max line length from 80 to 96
......................................................................
Patch Set 4:
> Patch Set 4:
>
> Note that this can be done with a command line flag like Patrick did in CB:31651. That's probably the preferable way.
I'm fine with that.
> Are you planning to check this in before the whole codebase is converted? I would prefer that we do both at once so we don't have inconsistent lengths everywhere.
Yes, I'm planning on doing it immediately.
- The codebase will be updated incrementally, directory by directory, not all at once. It makes sense to do this before we start updating line lengths so we don't get a slew of warnings when we update the files.
- We've decided to allow 96 characters, so let's get checkpatch to stop complaining about it.
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Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27533 )
Change subject: util/lint: Update checkpatch max line length from 80 to 96
......................................................................
Patch Set 4:
Note that this can be done with a command line flag like Patrick did in CB:31651. That's probably the preferable way.
Are you planning to check this in before the whole codebase is converted? I would prefer that we do both at once so we don't have inconsistent lengths everywhere.
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