coreboot-gerrit June 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: qcs405: Add bl31 stage and elf
by Nitheesh Sekar (Code Review) 12 Jun '19

12 Jun '19

Hello Julius Werner, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29981 to look at the new patch set (#28). Change subject: qcs405: Add bl31 stage and elf ...................................................................... qcs405: Add bl31 stage and elf Change-Id: I967c0b78a3561574609bf8332a22838c85e43429 Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> --- M src/soc/qualcomm/qcs405/Kconfig M src/soc/qualcomm/qcs405/Makefile.inc A src/soc/qualcomm/qcs405/bl31_plat_params.c A src/soc/qualcomm/qcs405/include/soc/bl31_plat_params.h M src/soc/qualcomm/qcs405/soc.c 5 files changed, 91 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/29981/28 -- To view, visit https://review.coreboot.org/c/coreboot/+/29981 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I967c0b78a3561574609bf8332a22838c85e43429 Gerrit-Change-Number: 29981 Gerrit-PatchSet: 28 Gerrit-Owner: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: qcs405: Add RPM support
by Nitheesh Sekar (Code Review) 12 Jun '19

12 Jun '19

Hello Julius Werner, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29970 to look at the new patch set (#29). Change subject: qcs405: Add RPM support ...................................................................... qcs405: Add RPM support This patch adds support to read RPM image from 3rdparty/blobs and load it. It takes RPM out of reset. Note that, clock_reset_rpm function to touch the GCC registers actually should reside in clock.c, but for now keeping it here till clock patches are posted. Change-Id: I17f491f0a4bd0dce7522b7e80e1bac97ec18b945 Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/soc/qualcomm/qcs405/Makefile.inc M src/soc/qualcomm/qcs405/include/soc/memlayout.ld A src/soc/qualcomm/qcs405/include/soc/rpm.h M src/soc/qualcomm/qcs405/include/soc/symbols.h M src/soc/qualcomm/qcs405/mmu.c A src/soc/qualcomm/qcs405/rpm_load_reset.c M src/soc/qualcomm/qcs405/soc.c 7 files changed, 106 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/29970/29 -- To view, visit https://review.coreboot.org/c/coreboot/+/29970 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I17f491f0a4bd0dce7522b7e80e1bac97ec18b945 Gerrit-Change-Number: 29970 Gerrit-PatchSet: 29 Gerrit-Owner: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sricharan Ramabadhran <srichara(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: qclib: Add qclib support with interface tables
by Nitheesh Sekar (Code Review) 12 Jun '19

12 Jun '19

Hello Julius Werner, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29967 to look at the new patch set (#29). Change subject: qclib: Add qclib support with interface tables ...................................................................... qclib: Add qclib support with interface tables Add to load and execute qclib blob to configure pmic, clocks and ddr.This also loads the qcsdi, cdt blob. Added support for interface tables to read ddr info from qclib and do ddr one time training based on it. Change-Id: I534af71163d034ea04420dda6a94ce31b08c8a07 Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> --- M src/mainboard/google/mistral/Makefile.inc M src/mainboard/google/mistral/romstage.c M src/soc/qualcomm/common/qclib.c M src/soc/qualcomm/qcs405/Makefile.inc M src/soc/qualcomm/qcs405/include/soc/memlayout.ld M src/soc/qualcomm/qcs405/include/soc/symbols.h M src/soc/qualcomm/qcs405/mmu.c A src/soc/qualcomm/qcs405/soc_blob_load.c 8 files changed, 119 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/29967/29 -- To view, visit https://review.coreboot.org/c/coreboot/+/29967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I534af71163d034ea04420dda6a94ce31b08c8a07 Gerrit-Change-Number: 29967 Gerrit-PatchSet: 29 Gerrit-Owner: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sricharan Ramabadhran <srichara(a)qualcomm.corp-partner.google.com> Gerrit-CC: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: qcs405: memlayout: Make bootblock 64k aligned
by Nitheesh Sekar (Code Review) 12 Jun '19

12 Jun '19

Hello Julius Werner, build bot (Jenkins), Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29969 to look at the new patch set (#27). Change subject: qcs405: memlayout: Make bootblock 64k aligned ...................................................................... qcs405: memlayout: Make bootblock 64k aligned The qc_sec in qcs405 expects the bootblock to be 64k aligned. So adjust the memlayout accordingly. Change-Id: I1599242bb5158477318867508c72dc14f1244b00 Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> --- M src/soc/qualcomm/qcs405/include/soc/memlayout.ld 1 file changed, 9 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/29969/27 -- To view, visit https://review.coreboot.org/c/coreboot/+/29969 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1599242bb5158477318867508c72dc14f1244b00 Gerrit-Change-Number: 29969 Gerrit-PatchSet: 27 Gerrit-Owner: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sricharan Ramabadhran <srichara(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: util/superiotool/nuvoton.c: added NCT5539D chip registers Change-Id: ...
by Pavel Sayekat (Code Review) 12 Jun '19

12 Jun '19

Hello Jacob Garber, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/33406 to review the following change. Change subject: util/superiotool/nuvoton.c: added NCT5539D chip registers Change-Id: I28446e6744fe58d954971fbff8b73413e64f5468 Signed-off-by: Pavel Sayekat <pavelsayekat(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33181 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> ...................................................................... util/superiotool/nuvoton.c: added NCT5539D chip registers Change-Id: I28446e6744fe58d954971fbff8b73413e64f5468 Signed-off-by: Pavel Sayekat <pavelsayekat(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33181 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Change-Id: I9dbcc1c5514b96ddf63a5ab2cb263f5f17002389 --- M src/console/printk.c M src/include/console/console.h M util/superiotool/nuvoton.c 3 files changed, 57 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/33406/1 diff --git a/src/console/printk.c b/src/console/printk.c index 0952215..8606bbb 100644 --- a/src/console/printk.c +++ b/src/console/printk.c @@ -45,7 +45,7 @@ __cbmemc_tx_byte(byte); } -int vprintk(int msg_level, const char *fmt, va_list args) +int do_vprintk(int msg_level, const char *fmt, va_list args) { int i, log_this; @@ -91,7 +91,7 @@ int i; va_start(args, fmt); - i = vprintk(msg_level, fmt, args); + i = do_vprintk(msg_level, fmt, args); va_end(args); return i; diff --git a/src/include/console/console.h b/src/include/console/console.h index 369ce5b..e5b753e 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -63,8 +63,8 @@ int console_log_level(int msg_level); void do_putchar(unsigned char byte); -#define printk(LEVEL, fmt, args...) \ - do { do_printk(LEVEL, fmt, ##args); } while (0) +#define printk(LEVEL, fmt, args...) do_printk(LEVEL, fmt, ##args) +#define vprintk(LEVEL, fmt, args) do_vprintk(LEVEL, fmt, args) enum { CONSOLE_LOG_NONE = 0, CONSOLE_LOG_FAST, CONSOLE_LOG_ALL }; @@ -84,14 +84,15 @@ static inline void console_init(void) {} static inline int console_log_level(int msg_level) { return 0; } static inline void printk(int LEVEL, const char *fmt, ...) {} +static inline void vprintk(int LEVEL, const char *fmt, va_list args) {} static inline void do_putchar(unsigned char byte) {} #endif -int vprintk(int msg_level, const char *fmt, va_list args); - int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3))); +int do_vprintk(int msg_level, const char *fmt, va_list args); + #endif /* !__ROMCC__ */ #endif /* CONSOLE_CONSOLE_H_ */ diff --git a/util/superiotool/nuvoton.c b/util/superiotool/nuvoton.c index 82772e7..01d195c 100644 --- a/util/superiotool/nuvoton.c +++ b/util/superiotool/nuvoton.c @@ -582,6 +582,56 @@ {0x30,0xe0,0xe1,0xe2,0xe3,EOT}, {0x20,0x20,0x04,0x05,0x01,EOT}}, {EOT}}}, + {0xd121, "NCT5539D (not all LDNs supported)", { + {NOLDN, NULL, + {0x07,0x10,0x11,0x13,0x14,0x1a,0x1b,0x1c,0x1d,0x20,0x21,0x22,0x24,0x25,0x26,0x27,0x28,0x2a,0x2b,0x2c,0x2d,0x2f,EOT}, + {0x00,0xff,0xff,0x00,0x00,0x30,0x50,0x10,0x00,0xd1,0x21,0xff,0x04,0x00,MISC,0x03,0x00,0xc0,0x00,0x01,MISC,MISC,EOT}}, + {0x02, "UART A", + {0x30,0x60,0x61,0x70,0xf0,0xf2,EOT}, + {0x01,0x03,0xf8,0x04,0x00,0x00,EOT}}, + {0x05, "Keyboard Controller", + {0x30,0x60,0x61,0x62,0x63,0x70,0x72,0xf0,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x83,EOT}}, + {0x06, "CIR", + {0x30,0x60,0x61,0x70,EOT}, + {0x00,0x00,0x00,0x00,EOT}}, + {0x07, "GPIO 7, GPIO 8", + {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xec,0xed,EOT}, + {0x00,0xff,0x00,0x00,0x00,0xff,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x08, "WDT1, WDT3, WDT3, GPIO 0, KBC P20", + {0x30,0x60,0x61,0xe0,0xe1,0xe2,0xe3,0xe4,0xf5,0xf6,0xf7,0xf8,0xf9,0xfa,0xfe,0xff,EOT}, + {0x00,0x00,0x00,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x09, "GPIO 2, GPIO 3, GPIO 4, GPIO 5", + {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8,0xe9,0xea,0xeb,0xee,0xf0,0xf1,0xf2,0xf4,0xf5,0xf6,0xf7,EOT}, + {0x00,0xff,0x00,0x00,0x00,0x7f,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xff,0x00,0x00,0xff,0x00,0x00,0x00,EOT}}, + {0x0a, "ACPI", + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe9,0xec,0xed,0xee,0xf0,0xf1,0xf2,0xf3,0xf6,0xf7,0xfc,EOT}, + {0x01,0x00,0x00,0x00,0x00,0x02,0x1a,0x00,0x00,0x00,0x01,0x00,0x10,0x48,0x5c,0x00,0x00,0xc0,0x80,EOT}}, + {0x0b, "Hardware Monitor, Front Panel LED", + {0x30,0x60,0x61,0x70,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xec,0xed,0xf0,0xf1,0xf2,0xf6,0xf7,0xf8,0xf9,0xfa,0xfb,0xfc,EOT}, + {0x00,0x00,0x00,0x00,0x7f,0x7f,0x7f,0x7f,0x7f,0xa8,0x08,0x7f,0x00,0x81,0x00,0x00,0x00,0x00,0x87,0x47,0x00,0x00,0x00,0x02,EOT}}, + {0x0d, "BCLK, WDT2", + {0xe7,0xe8,0xeb,0xed,0xf0,0xf3,EOT}, + {0x10,0x32,0x14,0x00,0x00,0x00,EOT}}, + {0x0e, "CIR Wake-Up", + {0x30,0x60,0x61,0x70,EOT}, + {0x00,0x00,0x00,0x00,EOT}}, + {0x0f, "GPIO Push-Pull or Open-Drain selection", + {0xe1,0xe2,0xe3,0xe4,0xe6,0xe7,0xe9,EOT}, + {0xff,0x7f,0xff,0xff,0xff,0xff,0xff,EOT}}, + {0x11, "GPIO, RI PSOUT Wake-Up Status Register", + {0xe1,0xe2,0xe9,EOT}, + {0x00,0x00,0x00,EOT}}, + {0x12, "SW Error Control Register", + {0xe1,0xe7,0xea,0xeb,0xec,EOT}, + {0x00,0x00,0x10,0x00,0x00,EOT}}, + {0x15, "Fading Led Maximun Duty Cycle Value Register", + {0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,EOT}, + {0xff,0x7f,0x00,0x56,0x56,0x17,0x00,0x0f,0x10,EOT}}, + {0x16, "Deep Sleep", + {0x30,0xe0,0xe1,0xe2,0xe3,EOT}, + {0xa0,0x20,0x04,0x05,0x01,EOT}}, + {EOT}}}, {EOT} }; -- To view, visit https://review.coreboot.org/c/coreboot/+/33406 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9dbcc1c5514b96ddf63a5ab2cb263f5f17002389 Gerrit-Change-Number: 33406 Gerrit-PatchSet: 1 Gerrit-Owner: Pavel Sayekat Gerrit-Reviewer: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mainboard/portwell/m107: Do initial mainboard commit
by Frans Hendriks (Code Review) 12 Jun '19

12 Jun '19

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29470 ) Change subject: mainboard/portwell/m107: Do initial mainboard commit ...................................................................... Patch Set 15: (2 comments) https://review.coreboot.org/#/c/29470/15/src/mainboard/portwell/m107/irqrou… File src/mainboard/portwell/m107/irqroute.h: https://review.coreboot.org/#/c/29470/15/src/mainboard/portwell/m107/irqrou… PS15, Line 40: #define PCI_DEV_PIRQ_ROUTES \ > Macros with complex values should be enclosed in parentheses Ack https://review.coreboot.org/#/c/29470/15/src/mainboard/portwell/m107/irqrou… PS15, Line 62: #define PIRQ_PIC_ROUTES \ > Macros with complex values should be enclosed in parentheses Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/29470 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d3173fdcf881f894a75cd9798ba173b425d4e62 Gerrit-Change-Number: 29470 Gerrit-PatchSet: 15 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 12 Jun 2019 10:04:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: comment

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Change in ...coreboot[master]: postcarpayload: Boot to payload from postcar stage directly [WIP]
by Subrata Banik (Code Review) 12 Jun '19

12 Jun '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30985 Change subject: postcarpayload: Boot to payload from postcar stage directly [WIP] ...................................................................... postcarpayload: Boot to payload from postcar stage directly [WIP] Changes: 1. Make only required changes to load generic payload [payload_init.c] 2. Compile required functions in postcar stage 3. Call postcar_payload_init() from postcar stage 4. soc and mainboard related changes TEST=Able to boot iclrvp and dragonegg to chrome os with limited FW changes. Change-Id: I27479187461ceb078167f2d726f40839865a9233 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/arch/x86/Makefile.inc M src/arch/x86/acpi.c M src/arch/x86/c_start.S M src/arch/x86/cpu.c M src/arch/x86/include/arch/acpi.h M src/arch/x86/include/arch/cpu.h M src/arch/x86/postcar.c M src/commonlib/Makefile.inc M src/console/post.c M src/cpu/intel/microcode/Makefile.inc M src/cpu/intel/turbo/Makefile.inc M src/cpu/x86/Makefile.inc M src/cpu/x86/lapic/Makefile.inc M src/cpu/x86/mp_init.c M src/cpu/x86/mtrr/Makefile.inc M src/cpu/x86/name/Makefile.inc M src/cpu/x86/smm/Makefile.inc M src/device/Makefile.inc M src/device/pci_early.c M src/drivers/elog/Makefile.inc M src/drivers/intel/fsp2_0/Makefile.inc M src/drivers/intel/fsp2_0/silicon_init.c M src/drivers/intel/gma/Makefile.inc M src/drivers/mrc_cache/Makefile.inc M src/drivers/mrc_cache/mrc_cache.c M src/drivers/pc80/pc/Makefile.inc M src/drivers/uart/uart8250io.c M src/drivers/uart/uart8250mem.c M src/ec/google/chromeec/Makefile.inc M src/include/memlayout.h M src/include/mrc_cache.h M src/include/rules.h M src/include/stddef.h M src/lib/Makefile.inc M src/lib/bootmode.c M src/lib/imd_cbmem.c M src/lib/memrange.c M src/lib/prog_loaders.c M src/lib/program.ld M src/mainboard/google/dragonegg/Kconfig M src/mainboard/google/dragonegg/Makefile.inc M src/mainboard/google/dragonegg/chromeos.c M src/mainboard/google/dragonegg/variants/baseboard/Makefile.inc M src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb M src/mainboard/intel/icelake_rvp/Kconfig M src/security/vboot/Makefile.inc M src/soc/intel/common/Makefile.inc M src/soc/intel/common/block/acpi/Makefile.inc M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/common/block/cpu/Makefile.inc M src/soc/intel/common/block/gpio/Makefile.inc M src/soc/intel/common/block/graphics/Makefile.inc M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/include/intelblocks/acpi.h M src/soc/intel/common/block/include/intelblocks/systemagent.h M src/soc/intel/common/block/itss/Makefile.inc M src/soc/intel/common/block/lpc/Makefile.inc M src/soc/intel/common/block/pcr/Makefile.inc M src/soc/intel/common/block/systemagent/Makefile.inc M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/common/block/systemagent/systemagent_early.c M src/soc/intel/icelake/Makefile.inc M src/soc/intel/icelake/acpi.c A src/soc/intel/icelake/include/soc/payload_init.h A src/soc/intel/icelake/payload_init.c M src/southbridge/intel/common/Makefile.inc M src/vendorcode/google/chromeos/Makefile.inc 67 files changed, 477 insertions(+), 57 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/30985/1 diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 8dafac8..2ee4921 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -260,6 +260,11 @@ $(eval $(call create_class_compiler,postcar,x86_32)) postcar-generic-ccopts += -D__POSTCAR__ +postcar-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c +postcar-$(CONFIG_HAVE_ACPI_TABLES) += acpigen.c +postcar-$(CONFIG_HAVE_ACPI_TABLES) += acpigen_dsm.c +postcar-$(CONFIG_HAVE_ACPI_TABLES) += acpi_device.c +postcar-$(CONFIG_HAVE_ACPI_TABLES) += acpi_pld.c postcar-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c postcar-y += boot.c postcar-y += gdt_init.S @@ -270,6 +275,7 @@ postcar-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c postcar-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S postcar-y += exit_car.S +postcar-y += c_start.S postcar-y += memcpy.c postcar-y += memmove.c postcar-y += memset.c @@ -310,11 +316,13 @@ ramstage-y += c_start.S ramstage-y += cbmem.c ramstage-y += cpu.c +postcar-y += cpu.c ramstage-y += cpu_common.c ramstage-y += ebda.c ramstage-y += exception.c ramstage-y += idt.S ramstage-y += gdt.c +postcar-$(CONFIG_IOAPIC) += ioapic.c ramstage-$(CONFIG_IOAPIC) += ioapic.c ramstage-y += memcpy.c ramstage-y += memlayout.ld @@ -327,10 +335,13 @@ ramstage-$(CONFIG_GENERATE_PIRQ_TABLE) += pirq_routing.c ramstage-y += rdrand.c ramstage-$(CONFIG_GENERATE_SMBIOS_TABLES) += smbios.c +postcar-$(CONFIG_GENERATE_SMBIOS_TABLES) += smbios.c ramstage-y += tables.c +postcar-y += tables.c ramstage-$(CONFIG_COOP_MULTITASKING) += thread.c ramstage-$(CONFIG_COOP_MULTITASKING) += thread_switch.S ramstage-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c +postcar-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.S ramstage-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.S smm-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 3b33f1b..e8c7cb4 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -48,6 +48,9 @@ #include <cpu/cpu.h> #include <cbfs.h> +#include <soc/pci_devs.h> +#include <intelblocks/graphics.h> + u8 acpi_checksum(u8 *table, u32 length) { u8 ret = 0; @@ -1264,6 +1267,7 @@ printk(BIOS_DEBUG, "current = %lx\n", current); +#if 0 // TODO: Bad hack to enable GFX for (dev = all_devices; dev; dev = dev->next) { if (dev->ops && dev->ops->write_acpi_tables) { current = dev->ops->write_acpi_tables(dev, current, @@ -1271,6 +1275,9 @@ current = acpi_align_current(current); } } +#endif + graphics_soc_write_acpi_opregion(SA_DEV_IGD, current, rsdp); + current = acpi_align_current(current); printk(BIOS_INFO, "ACPI: done.\n"); return current; diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S index 86147ec..5bb3cfd 100644 --- a/src/arch/x86/c_start.S +++ b/src/arch/x86/c_start.S @@ -37,8 +37,8 @@ #else .code32 #endif - .globl _start -_start: + .globl _start1 +_start1: cli lgdt %cs:gdtaddr #ifndef __x86_64__ diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c index 018ce9e..d9d0762 100644 --- a/src/arch/x86/cpu.c +++ b/src/arch/x86/cpu.c @@ -227,15 +227,11 @@ * from secondary cpus to a minimum, when debugging is * disabled. */ - struct device *cpu; - struct cpu_info *info; + struct device *cpu = dev_find_path(NULL, DEVICE_PATH_CPU_CLUSTER); struct cpuinfo_x86 c; - info = cpu_info(); - printk(BIOS_INFO, "Initializing CPU #%d\n", index); - cpu = info->cpu; if (!cpu) die("CPU: missing CPU device structure"); diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index a061a27..7ddda19 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -837,7 +837,7 @@ unsigned long (*acpi_fill_ivrs)(acpi_ivrs_t *ivrs_struct, unsigned long current)); -#if ENV_RAMSTAGE && !defined(__SIMPLE_DEVICE__) +#if (ENV_RAMSTAGE || ENV_POSTCAR) && !defined(__SIMPLE_DEVICE__) void acpi_create_hpet(acpi_hpet_t *hpet); unsigned long acpi_write_hpet(struct device *device, unsigned long start, acpi_rsdp_t *rsdp); diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 3ee5cea..b10b984 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -210,7 +210,7 @@ ); return ci; } - +#if !ENV_POSTCAR static inline unsigned long cpu_index(void) { struct cpu_info *ci; @@ -218,6 +218,7 @@ return ci->index; } #endif +#endif #ifndef __ROMCC__ // romcc is segfaulting in some cases struct cpuinfo_x86 { diff --git a/src/arch/x86/postcar.c b/src/arch/x86/postcar.c index ea05824..da02d6b 100644 --- a/src/arch/x86/postcar.c +++ b/src/arch/x86/postcar.c @@ -19,6 +19,7 @@ #include <cpu/x86/mtrr.h> #include <main_decl.h> #include <program_loading.h> +#include <soc/payload_init.h> /* * Systems without a native coreboot cache-as-ram teardown may implement @@ -37,6 +38,8 @@ display_mtrrs(); + postcar_payload_init(); + /* Load and run ramstage. */ run_ramstage(); } diff --git a/src/commonlib/Makefile.inc b/src/commonlib/Makefile.inc index 4d89c48..3d68cb4 100644 --- a/src/commonlib/Makefile.inc +++ b/src/commonlib/Makefile.inc @@ -23,6 +23,8 @@ ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp_relocate.c ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp_relocate.c +postcar-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp_relocate.c + bootblock-y += cbfs.c verstage-y += cbfs.c romstage-y += cbfs.c diff --git a/src/console/post.c b/src/console/post.c index 4c37535..50c84df 100644 --- a/src/console/post.c +++ b/src/console/post.c @@ -41,7 +41,7 @@ DECLARE_SPIN_LOCK(cmos_post_lock) -#if ENV_RAMSTAGE +#if ENV_RAMSTAGE || ENV_POSTCAR void cmos_post_log(void) { u8 code = 0; diff --git a/src/cpu/intel/microcode/Makefile.inc b/src/cpu/intel/microcode/Makefile.inc index 2df1d5e..cdef0e0 100644 --- a/src/cpu/intel/microcode/Makefile.inc +++ b/src/cpu/intel/microcode/Makefile.inc @@ -3,3 +3,4 @@ ramstage-$(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS) += microcode.c romstage-$(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS) += microcode.c +postcar-$(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS) += microcode.c diff --git a/src/cpu/intel/turbo/Makefile.inc b/src/cpu/intel/turbo/Makefile.inc index 48ec55d..6a62f59 100644 --- a/src/cpu/intel/turbo/Makefile.inc +++ b/src/cpu/intel/turbo/Makefile.inc @@ -1 +1,2 @@ +postcar-y += turbo.c ramstage-y += turbo.c diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc index 3e8a664..639d1f8 100644 --- a/src/cpu/x86/Makefile.inc +++ b/src/cpu/x86/Makefile.inc @@ -6,9 +6,11 @@ subdirs-y += pae subdirs-$(CONFIG_PARALLEL_MP) += name +postcar-$(CONFIG_PARALLEL_MP) += mp_init.c ramstage-$(CONFIG_PARALLEL_MP) += mp_init.c ramstage-$(CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING) += mirror_payload.c ramstage-y += backup_default_smm.c +postcar-y += backup_default_smm.c additional-dirs += $(obj)/cpu/x86 @@ -19,6 +21,7 @@ ifeq ($(CONFIG_PARALLEL_MP),y) ramstage-srcs += $(SIPI_BIN).manual +postcar-srcs += $(SIPI_BIN).manual endif rmodules_$(ARCH-ramstage-y)-$(CONFIG_PARALLEL_MP) += sipi_vector.S @@ -37,3 +40,22 @@ $(call src-to-obj,ramstage,$(SIPI_BIN).manual): $(SIPI_BIN) @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" cd $(dir $<); $(OBJCOPY_rmodules_$(ARCH-ramstage-y)) -I binary $(notdir $<) $(target-objcopy) $(abspath $@) + + +rmodules_$(ARCH-postcar-y)-$(CONFIG_PARALLEL_MP) += sipi_vector.S + +$(SIPI_DOTO): $(call src-to-obj,rmodules_$(ARCH-postcar-y),src/cpu/x86/sipi_vector.S) + $(CC_rmodules_$(ARCH-postcar-y)) $(CFLAGS_rmodules_$(ARCH-postcar-y)) -nostdlib -r -o $@ $^ + +ifeq ($(CONFIG_ARCH_POSTCAR_X86_32),y) +$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_DOTO), 0,x86_32)) +else +$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_DOTO), 0,x86_64)) +endif + +$(SIPI_BIN): $(SIPI_RMOD) + $(OBJCOPY_postcar) -O binary $< $@ + +$(call src-to-obj,postcar,$(SIPI_BIN).manual): $(SIPI_BIN) + @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" + cd $(dir $<); $(OBJCOPY_rmodules_$(ARCH-postcar-y)) -I binary $(notdir $<) $(target-objcopy) $(abspath $@) diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc index 9454f8f..3381d04 100644 --- a/src/cpu/x86/lapic/Makefile.inc +++ b/src/cpu/x86/lapic/Makefile.inc @@ -1,4 +1,5 @@ ramstage-y += lapic.c +postcar-y += lapic.c ramstage-y += lapic_cpu_init.c ramstage-$(CONFIG_SMP) += secondary.S romstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 3889c7d..0042f49 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -194,6 +194,19 @@ } } +#if ENV_POSTCAR +static inline unsigned long cpu_index(void) +{ + int i; + + for (i=0; i < CONFIG_MAX_CPUS; i++) { + if (mp_get_apic_id(i) == lapicid()) + return i; + } + return 0; +} +#endif + static void park_this_cpu(void *unused) { stop_this_cpu(); @@ -203,12 +216,11 @@ * been loaded. */ static void asmlinkage ap_init(unsigned int cpu) { - struct cpu_info *info; + static struct cpu_info *info; /* Ensure the local APIC is enabled */ enable_lapic(); - info = cpu_info(); info->index = cpu; info->cpu = cpus[cpu].dev; @@ -399,7 +411,7 @@ /* Assuming linear APIC space allocation. AP will set its own APIC id in the ap_init() path above. */ - cpu_path.apic.apic_id = info->cpu->path.apic.apic_id + i; + cpu_path.apic.apic_id = lapicid() + i; /* Allocate the new CPU device structure */ new = alloc_find_dev(cpu_bus, &cpu_path); @@ -565,7 +577,7 @@ static void init_bsp(struct bus *cpu_bus) { struct device_path cpu_path; - struct cpu_info *info; + static struct cpu_info *info; /* Print processor name */ fill_processor_name(processor_name); @@ -579,9 +591,9 @@ cpu_path.apic.apic_id = lapicid(); /* Find the device structure for the boot CPU. */ - info = cpu_info(); info->cpu = alloc_find_dev(cpu_bus, &cpu_path); info->cpu->name = processor_name; + info->index = cpu_index(); if (info->index != 0) printk(BIOS_CRIT, "BSP index(%d) != 0!\n", info->index); @@ -661,8 +673,7 @@ static void mp_initialize_cpu(void) { /* Call back into driver infrastructure for the AP initialization. */ - struct cpu_info *info = cpu_info(); - cpu_initialize(info->index); + cpu_initialize(cpu_index()); } /* Returns APIC id for coreboot CPU number or < 0 on failure. */ diff --git a/src/cpu/x86/mtrr/Makefile.inc b/src/cpu/x86/mtrr/Makefile.inc index caa6e9c..15ee4e1 100644 --- a/src/cpu/x86/mtrr/Makefile.inc +++ b/src/cpu/x86/mtrr/Makefile.inc @@ -1,4 +1,5 @@ ramstage-y += mtrr.c +postcar-y += mtrr.c romstage-y += earlymtrr.c bootblock-y += earlymtrr.c diff --git a/src/cpu/x86/name/Makefile.inc b/src/cpu/x86/name/Makefile.inc index 5dba1a2..6c62814 100644 --- a/src/cpu/x86/name/Makefile.inc +++ b/src/cpu/x86/name/Makefile.inc @@ -14,3 +14,4 @@ ## ramstage-y += name.c +postcar-y += name.c diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index 32f5ea7..83b7ff8 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -14,6 +14,7 @@ ## ramstage-y += smm_module_loader.c +postcar-y += smm_module_loader.c ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) $(eval $(call create_class_compiler,smm,x86_32)) @@ -23,6 +24,14 @@ $(eval $(call create_class_compiler,smmstub,x86_64)) endif +ifeq ($(CONFIG_ARCH_POSTCAR_X86_32),y) +$(eval $(call create_class_compiler,smm,x86_32)) +$(eval $(call create_class_compiler,smmstub,x86_32)) +else +$(eval $(call create_class_compiler,smm,x86_64)) +$(eval $(call create_class_compiler,smmstub,x86_64)) +endif + smmstub-generic-ccopts += -D__SMM__ smm-generic-ccopts += -D__SMM__ smm-c-deps:=$$(OPTION_TABLE_H) @@ -36,6 +45,10 @@ @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" cd $(dir $<); $(OBJCOPY_smm) -I binary $(notdir $<) $(target-objcopy) $(abspath $@) +$(call src-to-obj,postcar,$(obj)/cpu/x86/smm/smm.manual): $(obj)/smm/smm + @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" + cd $(dir $<); $(OBJCOPY_smm) -I binary $(notdir $<) $(target-objcopy) $(abspath $@) + ifeq ($(CONFIG_SMM_TSEG),y) smmstub-y += smm_stub.S @@ -45,6 +58,9 @@ ramstage-srcs += $(obj)/cpu/x86/smm/smm.manual ramstage-srcs += $(obj)/cpu/x86/smm/smmstub.manual +postcar-srcs += $(obj)/cpu/x86/smm/smm.manual +postcar-srcs += $(obj)/cpu/x86/smm/smmstub.manual + # SMM Stub Module. The stub is used as a trampoline for relocation and normal # SMM handling. $(obj)/smmstub/smmstub.o: $$(smmstub-objs) @@ -57,6 +73,13 @@ $(eval $(call rmodule_link,$(obj)/smmstub/smmstub.elf, $(obj)/smmstub/smmstub.o, 0,x86_64)) endif +ifeq ($(CONFIG_ARCH_POSTCAR_X86_32),y) +$(eval $(call rmodule_link,$(obj)/smmstub/smmstub.elf, $(obj)/smmstub/smmstub.o, 0,x86_32)) +else +$(eval $(call rmodule_link,$(obj)/smmstub/smmstub.elf, $(obj)/smmstub/smmstub.o, 0,x86_64)) +endif + + $(obj)/smmstub/smmstub: $(obj)/smmstub/smmstub.elf.rmod $(OBJCOPY_smmstub) -O binary $< $@ @@ -64,6 +87,10 @@ @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" cd $(dir $<); $(OBJCOPY_smmstub) -I binary $(notdir $<) $(target-objcopy) $(abspath $@) +$(call src-to-obj,postcar,$(obj)/cpu/x86/smm/smmstub.manual): $(obj)/smmstub/smmstub + @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" + cd $(dir $<); $(OBJCOPY_smmstub) -I binary $(notdir $<) $(target-objcopy) $(abspath $@) + # C-based SMM handler. ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) @@ -72,6 +99,12 @@ $(eval $(call rmodule_link,$(obj)/smm/smm.elf, $(obj)/smm/smm.o, $(CONFIG_SMM_MODULE_HEAP_SIZE),x86_64)) endif +ifeq ($(CONFIG_ARCH_POSTCAR_X86_32),y) +$(eval $(call rmodule_link,$(obj)/smm/smm.elf, $(obj)/smm/smm.o, $(CONFIG_SMM_MODULE_HEAP_SIZE),x86_32)) +else +$(eval $(call rmodule_link,$(obj)/smm/smm.elf, $(obj)/smm/smm.o, $(CONFIG_SMM_MODULE_HEAP_SIZE),x86_64)) +endif + $(obj)/smm/smm: $(obj)/smm/smm.elf.rmod $(OBJCOPY_smm) -O binary $< $@ @@ -84,6 +117,7 @@ ifeq ($(CONFIG_HAVE_SMI_HANDLER),y) ramstage-srcs += $(obj)/cpu/x86/smm/smm.manual +postcar-srcs += $(obj)/cpu/x86/smm/smm.manual endif smm-y += smmhandler.S diff --git a/src/device/Makefile.inc b/src/device/Makefile.inc index bed0f71..3a2636c 100644 --- a/src/device/Makefile.inc +++ b/src/device/Makefile.inc @@ -1,9 +1,14 @@ ramstage-y += device.c +postcar-y += device.c ramstage-y += root_device.c +postcar-y += root_device.c ramstage-y += cpu_device.c +postcar-y += cpu_device.c ramstage-y += device_util.c +postcar-y += device_util.c ramstage-$(CONFIG_PCI) += pci_class.c ramstage-$(CONFIG_PCI) += pci_device.c +postcar-$(CONFIG_PCI) += pci_device.c ramstage-$(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT) += hypertransport.c ramstage-$(CONFIG_PCIX_PLUGIN_SUPPORT) += pcix_device.c ramstage-$(CONFIG_PCIEXP_PLUGIN_SUPPORT) += pciexp_device.c @@ -12,9 +17,13 @@ ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_32) += pnp_device.c ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_64) += pnp_device.c ramstage-$(CONFIG_PCI) += pci_ops.c +postcar-$(CONFIG_PCI) += pci_ops.c +postcar-$(CONFIG_MMCONF_SUPPORT) += pci_ops_mmconf.c ramstage-$(CONFIG_MMCONF_SUPPORT) += pci_ops_mmconf.c +postcar-$(CONFIG_PCI) += pci_early.c ramstage-$(CONFIG_PCI) += pci_early.c ramstage-$(CONFIG_PCI) += pci_rom.c +postcar-$(CONFIG_PCI) += pci_rom.c ramstage-y += smbus_ops.c ifeq ($(CONFIG_AZALIA_PLUGIN_SUPPORT),y) diff --git a/src/device/pci_early.c b/src/device/pci_early.c index 4cf8c7e..568b517 100644 --- a/src/device/pci_early.c +++ b/src/device/pci_early.c @@ -20,7 +20,7 @@ #include <device/pci_def.h> #include <delay.h> -#if !ENV_RAMSTAGE +#if !ENV_RAMSTAGE && !ENV_POSTCAR unsigned pci_find_next_capability(pci_devfn_t dev, unsigned cap, unsigned last) { unsigned pos = 0; diff --git a/src/drivers/elog/Makefile.inc b/src/drivers/elog/Makefile.inc index cce1c3d..191a89a 100644 --- a/src/drivers/elog/Makefile.inc +++ b/src/drivers/elog/Makefile.inc @@ -1,7 +1,7 @@ bootblock-$(CONFIG_ELOG_PRERAM) += elog.c verstage-$(CONFIG_ELOG_PRERAM) += elog.c romstage-$(CONFIG_ELOG_PRERAM) += elog.c -postcar-$(CONFIG_ELOG_PRERAM) += elog.c +postcar-$(CONFIG_ELOG) += elog.c ramstage-$(CONFIG_ELOG) += elog.c smm-$(CONFIG_ELOG_GSMI) += elog.c gsmi.c diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index 79fe5f8..efe6208 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -28,6 +28,7 @@ ramstage-y += debug.c ramstage-$(CONFIG_RUN_FSP_GOP) += graphics.c +postcar-$(CONFIG_RUN_FSP_GOP) += graphics.c ramstage-y += hand_off_block.c ramstage-$(CONFIG_DISPLAY_FSP_HEADER) += header_display.c ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c @@ -39,6 +40,10 @@ ramstage-y += util.c ramstage-$(CONFIG_MMA) += mma_core.c +postcar-y += silicon_init.c +postcar-y += util.c +postcar-y += debug.c + postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c postcar-$(CONFIG_FSP_CAR) += temp_ram_exit.c postcar-$(CONFIG_FSP_CAR) += util.c diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index 0670663..834dbb0 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -54,13 +54,14 @@ post_code(POST_FSP_SILICON_EXIT); fsp_debug_after_silicon_init(status); - +#if 0 // TODO: bad hack /* Handle any errors returned by FspSiliconInit */ fsp_handle_reset(status); if (status != FSP_SUCCESS) { printk(BIOS_SPEW, "FspSiliconInit returned 0x%08x\n", status); die("FspSiliconINit returned an error!\n"); } +#endif } void fsps_load(bool s3wake) diff --git a/src/drivers/intel/gma/Makefile.inc b/src/drivers/intel/gma/Makefile.inc index 274955a..c9dbb13 100644 --- a/src/drivers/intel/gma/Makefile.inc +++ b/src/drivers/intel/gma/Makefile.inc @@ -20,7 +20,7 @@ endif ramstage-$(CONFIG_INTEL_GMA_ACPI) += acpi.c ramstage-$(CONFIG_INTEL_GMA_ACPI) += opregion.c - +postcar-$(CONFIG_INTEL_GMA_ACPI) += opregion.c # add_vbt_to_cbfs, first argument is the filename in cbfs, the second one # is the filename in the coreboot tree. add_vbt_to_cbfs= \ diff --git a/src/drivers/mrc_cache/Makefile.inc b/src/drivers/mrc_cache/Makefile.inc index 0d226fe..f3a6dd9 100644 --- a/src/drivers/mrc_cache/Makefile.inc +++ b/src/drivers/mrc_cache/Makefile.inc @@ -1,2 +1,3 @@ romstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c +postcar-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c diff --git a/src/drivers/mrc_cache/mrc_cache.c b/src/drivers/mrc_cache/mrc_cache.c index 4dd0dbc..549470a 100644 --- a/src/drivers/mrc_cache/mrc_cache.c +++ b/src/drivers/mrc_cache/mrc_cache.c @@ -542,7 +542,7 @@ printk(BIOS_ERR, "MRC: invalidation failed for '%s'.\n", name); } -static void update_mrc_cache(void *unused) +void update_mrc_cache(void *unused) { update_mrc_cache_by_type(MRC_TRAINING_DATA); diff --git a/src/drivers/pc80/pc/Makefile.inc b/src/drivers/pc80/pc/Makefile.inc index 8c348e3..70cc516 100644 --- a/src/drivers/pc80/pc/Makefile.inc +++ b/src/drivers/pc80/pc/Makefile.inc @@ -1,5 +1,6 @@ ifeq ($(CONFIG_ARCH_X86),y) +postcar-y += isa-dma.c ramstage-y += isa-dma.c ramstage-y += i8254.c ramstage-y += i8259.c diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c index 9b5f57c..62f315f 100644 --- a/src/drivers/uart/uart8250io.c +++ b/src/drivers/uart/uart8250io.c @@ -124,7 +124,7 @@ uart8250_tx_flush(uart_platform_base(idx)); } -#if ENV_RAMSTAGE +#if ENV_RAMSTAGE || ENV_POSTCAR void uart_fill_lb(void *data) { struct lb_serial serial; diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c index 94a7fc9..2db824a 100644 --- a/src/drivers/uart/uart8250mem.c +++ b/src/drivers/uart/uart8250mem.c @@ -147,7 +147,7 @@ uart8250_mem_tx_flush(base); } -#if ENV_RAMSTAGE +#if ENV_RAMSTAGE || ENV_POSTCAR void uart_fill_lb(void *data) { struct lb_serial serial; diff --git a/src/ec/google/chromeec/Makefile.inc b/src/ec/google/chromeec/Makefile.inc index 85e2599..949525f 100644 --- a/src/ec/google/chromeec/Makefile.inc +++ b/src/ec/google/chromeec/Makefile.inc @@ -6,7 +6,9 @@ smm-$(CONFIG_EC_GOOGLE_CHROMEEC_BOARDID) += ec_boardid.c bootblock-y += ec.c +postcar-y += ec.c bootblock-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c +postcar-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c ramstage-y += ec.c crosec_proto.c vstore.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c @@ -31,6 +33,7 @@ verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SWITCHES) += switches.c romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SWITCHES) += switches.c +postcar-$(CONFIG_EC_GOOGLE_CHROMEEC_SWITCHES) += switches.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SWITCHES) += switches.c CHROMEEC_SOURCE ?= $(top)/3rdparty/chromeec diff --git a/src/include/memlayout.h b/src/include/memlayout.h index a8b3a60..7d65fbd 100644 --- a/src/include/memlayout.h +++ b/src/include/memlayout.h @@ -40,7 +40,7 @@ /* Default is that currently ramstage, smm, and rmodules have a heap. */ #ifndef ARCH_STAGE_HAS_HEAP_SECTION -#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM || ENV_RMODULE) +#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM || ENV_RMODULE || ENV_POSTCAR) #endif #define STR(x) #x diff --git a/src/include/mrc_cache.h b/src/include/mrc_cache.h index 498ecbf..6ecb132 100644 --- a/src/include/mrc_cache.h +++ b/src/include/mrc_cache.h @@ -41,4 +41,6 @@ int mrc_cache_stash_data(int type, uint32_t version, const void *data, size_t size); +void update_mrc_cache(void *unused); + #endif /* _COMMON_MRC_CACHE_H_ */ diff --git a/src/include/rules.h b/src/include/rules.h index deea50b..424fa39 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -270,7 +270,7 @@ * For now only x86 is supported. */ -#if ENV_X86 && (defined(__PRE_RAM__) || ENV_SMM || ENV_POSTCAR) +#if ENV_X86 && (defined(__PRE_RAM__) || ENV_SMM) #define __SIMPLE_DEVICE__ #endif diff --git a/src/include/stddef.h b/src/include/stddef.h index a82a68d..865ab12 100644 --- a/src/include/stddef.h +++ b/src/include/stddef.h @@ -23,10 +23,10 @@ /* The devicetree data structures are only mutable in ramstage. All other stages have a constant devicetree. */ -#if !ENV_RAMSTAGE -#define DEVTREE_EARLY 1 -#else +#if ENV_RAMSTAGE || ENV_POSTCAR #define DEVTREE_EARLY 0 +#else +#define DEVTREE_EARLY 1 #endif #if DEVTREE_EARLY diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 2fd4e4c..4be2fc9 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -86,6 +86,7 @@ romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c romstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c ramstage-y += region_file.c +postcar-y += region_file.c romstage-y += region_file.c ramstage-y += romstage_handoff.c romstage-y += romstage_handoff.c @@ -113,20 +114,27 @@ ramstage-y += prog_ops.c ramstage-y += hardwaremain.c ramstage-y += selfboot.c +postcar-y += selfboot.c ramstage-y += coreboot_table.c +postcar-y += coreboot_table.c ramstage-y += bootmem.c +postcar-y += bootmem.c ramstage-y += fmap.c ramstage-y += memchr.c ramstage-y += memcmp.c ramstage-y += malloc.c +postcar-y += malloc.c smm-$(CONFIG_SMM_TSEG) += malloc.c ramstage-y += dimm_info_util.c ramstage-y += delay.c ramstage-y += fallback_boot.c +postcar-y += fallback_boot.c ramstage-y += compute_ip_checksum.c +postcar-y += compute_ip_checksum.c ramstage-y += cbfs.c ramstage-y += lzma.c lzmadecode.c ramstage-y += stack.c +postcar-y += stack.c ramstage-y += hexstrtobin.c ramstage-y += wrdd.c ramstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c @@ -139,6 +147,7 @@ ramstage-y += edid_fill_fb.c endif ramstage-y += memrange.c +postcar-y += memrange.c ramstage-$(CONFIG_COOP_MULTITASKING) += thread.c ramstage-$(CONFIG_TIMER_QUEUE) += timer_queue.c ramstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c diff --git a/src/lib/bootmode.c b/src/lib/bootmode.c index 29682eb..3b1b4c3 100644 --- a/src/lib/bootmode.c +++ b/src/lib/bootmode.c @@ -16,7 +16,7 @@ #include <bootmode.h> #include <vendorcode/google/chromeos/chromeos.h> -#if ENV_RAMSTAGE +#if ENV_RAMSTAGE || ENV_POSTCAR static int gfx_init_done = -1; int gfx_get_init_done(void) diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index ff1cb95..ae1b416 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -303,8 +303,8 @@ imd_region_used(cbmem_get_imd(), baseptr, size); } -#if ENV_RAMSTAGE || (IS_ENABLED(CONFIG_EARLY_CBMEM_LIST) \ - && (ENV_POSTCAR || ENV_ROMSTAGE)) +#if ENV_RAMSTAGE || ENV_POSTCAR || (IS_ENABLED(CONFIG_EARLY_CBMEM_LIST) \ + && (ENV_ROMSTAGE)) /* * -fdata-sections doesn't work so well on read only strings. They all * get put in the same section even though those strings may never be diff --git a/src/lib/memrange.c b/src/lib/memrange.c index 96d7524..a32f284 100644 --- a/src/lib/memrange.c +++ b/src/lib/memrange.c @@ -47,7 +47,7 @@ range_entry_unlink(&ranges->free_list, r); return r; } - if (ENV_RAMSTAGE) + if (ENV_RAMSTAGE || ENV_POSTCAR) return malloc(sizeof(struct range_entry)); return NULL; } diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index ac80a62..a9a6681 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -160,7 +160,7 @@ die("Ramstage was not loaded!\n"); } -#ifdef __RAMSTAGE__ // gc-sections should take care of this +#if ENV_RAMSTAGE || ENV_POSTCAR // gc-sections should take care of this static struct prog global_payload = PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/payload"); @@ -213,10 +213,12 @@ timestamp_add_now(TS_SELFBOOT_JUMP); +#if ENV_RAMSTAGE /* Before we go off to run the payload, see if * we stayed within our bounds. */ checkstack(_estack, 0); +#endif prog_run(payload); } diff --git a/src/lib/program.ld b/src/lib/program.ld index 156b862..5694e72 100644 --- a/src/lib/program.ld +++ b/src/lib/program.ld @@ -55,7 +55,7 @@ KEEP(*(.rsbe_init)); _ersbe_init_begin = .; -#if ENV_RAMSTAGE +#if ENV_RAMSTAGE || ENV_POSTCAR . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _pci_drivers = .; KEEP(*(.rodata.pci_driver)); diff --git a/src/mainboard/google/dragonegg/Kconfig b/src/mainboard/google/dragonegg/Kconfig index 39228f4..2b51841 100644 --- a/src/mainboard/google/dragonegg/Kconfig +++ b/src/mainboard/google/dragonegg/Kconfig @@ -28,15 +28,15 @@ default 512 # Select this option to enable use of cr50 SPI TPM on dragon egg. -config DRAGONEGG_USE_SPI_TPM - bool - default y - select MAINBOARD_HAS_SPI_TPM_CR50 - select MAINBOARD_HAS_TPM2 +#config DRAGONEGG_USE_SPI_TPM +# bool +# default y +# select MAINBOARD_HAS_SPI_TPM_CR50 +# select MAINBOARD_HAS_TPM2 -config DRIVER_TPM_SPI_BUS - depends on DRAGONEGG_USE_SPI_TPM - default 0x1 +#config DRIVER_TPM_SPI_BUS +# depends on DRAGONEGG_USE_SPI_TPM +# default 0x1 config GBB_HWID string @@ -78,6 +78,7 @@ config VBOOT select VBOOT_LID_SWITCH select EC_GOOGLE_CHROMEEC_SWITCHES + select VBOOT_MOCK_SECDATA select HAS_RECOVERY_MRC_CACHE select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN diff --git a/src/mainboard/google/dragonegg/Makefile.inc b/src/mainboard/google/dragonegg/Makefile.inc index 39e94d0..0388de3 100644 --- a/src/mainboard/google/dragonegg/Makefile.inc +++ b/src/mainboard/google/dragonegg/Makefile.inc @@ -21,10 +21,12 @@ romstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-y += romstage_fsp_params.c +postcar-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c ramstage-y += mainboard.c ramstage-y += ramstage.c +postcar-y += ramstage.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c diff --git a/src/mainboard/google/dragonegg/chromeos.c b/src/mainboard/google/dragonegg/chromeos.c index 657320c..ac26a7d 100644 --- a/src/mainboard/google/dragonegg/chromeos.c +++ b/src/mainboard/google/dragonegg/chromeos.c @@ -21,7 +21,7 @@ #include <variant/gpio.h> -#if ENV_RAMSTAGE +#if ENV_RAMSTAGE || ENV_POSTCAR #include <boot/coreboot_tables.h> void fill_lb_gpios(struct lb_gpios *gpios) diff --git a/src/mainboard/google/dragonegg/variants/baseboard/Makefile.inc b/src/mainboard/google/dragonegg/variants/baseboard/Makefile.inc index 22736b9..f86ac87 100644 --- a/src/mainboard/google/dragonegg/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/dragonegg/variants/baseboard/Makefile.inc @@ -18,3 +18,5 @@ romstage-y += memory.c ramstage-y += gpio.c + +postcar-y += gpio.c diff --git a/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb b/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb index 257ad1d..722956e 100644 --- a/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb @@ -12,14 +12,14 @@ device lapic 0 on end end - register "PchHdaDspEnable" = "1" - register "PchHdaAudioLinkSsp0" = "1" - register "PchHdaAudioLinkSsp1" = "1" + register "PchHdaDspEnable" = "0" + register "PchHdaAudioLinkSsp0" = "0" + register "PchHdaAudioLinkSsp1" = "0" # FSP configuration register "SaGv" = "SaGv_Enabled" register "SmbusEnable" = "1" - register "ScsEmmcHs400Enabled" = "1" + register "ScsEmmcHs400Enabled" = "0" register "usb2_ports[0]" = "USB2_PORT_LONG(OC2)" # Type-C Port 1 register "usb2_ports[1]" = "USB2_PORT_LONG(OC2)" # Type-C Port 2 @@ -278,7 +278,7 @@ device pci 19.0 on end # I2C #4 device pci 19.1 off end # I2C #5 device pci 19.2 on end # UART #2 - device pci 1a.0 on end # eMMC + device pci 1a.0 off end # eMMC device pci 1c.0 on chip drivers/intel/wifi register "wake" = "GPE0_DW0_06" @@ -311,7 +311,7 @@ device pci 1f.0 on end # LPC Interface device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA + device pci 1f.3 off end # Intel HDA device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI device pci 1f.6 off end # GbE diff --git a/src/mainboard/intel/icelake_rvp/Kconfig b/src/mainboard/intel/icelake_rvp/Kconfig index 7cc4e53..0e1b69d 100644 --- a/src/mainboard/intel/icelake_rvp/Kconfig +++ b/src/mainboard/intel/icelake_rvp/Kconfig @@ -15,7 +15,7 @@ select SOC_INTEL_ICELAKE select MAINBOARD_USES_IFD_EC_REGION select INTEL_LPSS_UART_FOR_CONSOLE - + select EC_ACPI config MAINBOARD_DIR string default "intel/icelake_rvp" diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index ae80a02..570e47f 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -29,16 +29,19 @@ bootblock-y += vbnv.c verstage-y += vbnv.c romstage-y += vbnv.c +postcar-y += vbnv.c ramstage-y += vbnv.c bootblock-$(CONFIG_VBOOT_VBNV_CMOS) += vbnv_cmos.c verstage-$(CONFIG_VBOOT_VBNV_CMOS) += vbnv_cmos.c romstage-$(CONFIG_VBOOT_VBNV_CMOS) += vbnv_cmos.c +postcar-$(CONFIG_VBOOT_VBNV_CMOS) += vbnv_cmos.c ramstage-$(CONFIG_VBOOT_VBNV_CMOS) += vbnv_cmos.c bootblock-$(CONFIG_VBOOT_VBNV_CMOS_BACKUP_TO_FLASH) += vbnv_flash.c verstage-$(CONFIG_VBOOT_VBNV_CMOS_BACKUP_TO_FLASH) += vbnv_flash.c romstage-$(CONFIG_VBOOT_VBNV_CMOS_BACKUP_TO_FLASH) += vbnv_flash.c +postcar-$(CONFIG_VBOOT_VBNV_CMOS_BACKUP_TO_FLASH) += vbnv_flash.c ramstage-$(CONFIG_VBOOT_VBNV_CMOS_BACKUP_TO_FLASH) += vbnv_flash.c bootblock-$(CONFIG_VBOOT_VBNV_EC) += vbnv_ec.c diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index 22d350c..f55e41a 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -18,7 +18,9 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c ramstage-$(CONFIG_MMA) += mma.c ramstage-$(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) += acpi_wake_source.c +postcar-$(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) += acpi_wake_source.c ramstage-y += vbt.c +postcar-y += vbt.c ramstage-$(CONFIG_SOC_INTEL_COMMON_NHLT) += nhlt.c bootblock-$(CONFIG_TPM_CR50) += tpm_tis.c diff --git a/src/soc/intel/common/block/acpi/Makefile.inc b/src/soc/intel/common/block/acpi/Makefile.inc index c6bdac5..d792111 100644 --- a/src/soc/intel/common/block/acpi/Makefile.inc +++ b/src/soc/intel/common/block/acpi/Makefile.inc @@ -1 +1,2 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI) += acpi.c +postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI) += acpi.c diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 0ea6cb9..247e9e4 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -446,7 +446,7 @@ #if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) /* Save wake source data for ACPI _SWS methods in NVS */ -static void acpi_save_wake_source(void *unused) +void acpi_save_wake_source(void *unused) { global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); uint32_t pm1, *gpe0; diff --git a/src/soc/intel/common/block/cpu/Makefile.inc b/src/soc/intel/common/block/cpu/Makefile.inc index 5207227..57f1386 100644 --- a/src/soc/intel/common/block/cpu/Makefile.inc +++ b/src/soc/intel/common/block/cpu/Makefile.inc @@ -7,6 +7,8 @@ postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CAR) += car/exit_car.S postcar-$(CONFIG_FSP_CAR) += car/exit_car_fsp.S +postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c +postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT) += mp_init.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT) += mp_init.c diff --git a/src/soc/intel/common/block/gpio/Makefile.inc b/src/soc/intel/common/block/gpio/Makefile.inc index b0ffee3..8db62fd 100644 --- a/src/soc/intel/common/block/gpio/Makefile.inc +++ b/src/soc/intel/common/block/gpio/Makefile.inc @@ -1,4 +1,5 @@ bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO) += gpio.c +postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO) += gpio.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO) += gpio.c romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO) += gpio.c smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO) += gpio.c diff --git a/src/soc/intel/common/block/graphics/Makefile.inc b/src/soc/intel/common/block/graphics/Makefile.inc index 44dfc7e..f58b3e7 100644 --- a/src/soc/intel/common/block/graphics/Makefile.inc +++ b/src/soc/intel/common/block/graphics/Makefile.inc @@ -1 +1,2 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GRAPHICS) += graphics.c +postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GRAPHICS) += graphics.c diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c index f72adfc..a6df4ee 100644 --- a/src/soc/intel/common/block/i2c/i2c.c +++ b/src/soc/intel/common/block/i2c/i2c.c @@ -47,7 +47,7 @@ return EARLY_I2C_BASE(bus); } -#if !ENV_RAMSTAGE +#if !ENV_RAMSTAGE && !ENV_POSTCAR static int lpss_i2c_early_init_bus(unsigned int bus) { const struct dw_i2c_bus_config *config; diff --git a/src/soc/intel/common/block/include/intelblocks/acpi.h b/src/soc/intel/common/block/include/intelblocks/acpi.h index 6b1b9bd..cfbdf15 100644 --- a/src/soc/intel/common/block/include/intelblocks/acpi.h +++ b/src/soc/intel/common/block/include/intelblocks/acpi.h @@ -91,4 +91,6 @@ */ void soc_power_states_generation(int core_id, int cores_per_package); +void acpi_save_wake_source(void *unused); + #endif /* _SOC_INTEL_COMMON_BLOCK_ACPI_H_ */ diff --git a/src/soc/intel/common/block/include/intelblocks/systemagent.h b/src/soc/intel/common/block/include/intelblocks/systemagent.h index babf9ce..329051f 100644 --- a/src/soc/intel/common/block/include/intelblocks/systemagent.h +++ b/src/soc/intel/common/block/include/intelblocks/systemagent.h @@ -64,6 +64,8 @@ */ void sa_add_fixed_mmio_resources(struct device *dev, int *resource_cnt, const struct sa_mmio_descriptor *sa_fixed_resources, size_t count); + +void systemagent_read_resources(struct device *dev); /* * API to set BIOS Reset CPL through MCHBAR * SoC to provide BIOS_RESET_CPL register offset through soc/systemagent.h diff --git a/src/soc/intel/common/block/itss/Makefile.inc b/src/soc/intel/common/block/itss/Makefile.inc index bc0e97a..ba3bcb9 100644 --- a/src/soc/intel/common/block/itss/Makefile.inc +++ b/src/soc/intel/common/block/itss/Makefile.inc @@ -1,3 +1,4 @@ bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_ITSS) += itss.c romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_ITSS) += itss.c +postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_ITSS) += itss.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_ITSS) += itss.c diff --git a/src/soc/intel/common/block/lpc/Makefile.inc b/src/soc/intel/common/block/lpc/Makefile.inc index 428ade9..400dfe4 100644 --- a/src/soc/intel/common/block/lpc/Makefile.inc +++ b/src/soc/intel/common/block/lpc/Makefile.inc @@ -1,6 +1,7 @@ bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPC) += lpc_lib.c romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPC) += lpc_lib.c +postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPC) += lpc_lib.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPC) += lpc_lib.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPC) += lpc.c diff --git a/src/soc/intel/common/block/pcr/Makefile.inc b/src/soc/intel/common/block/pcr/Makefile.inc index 0577e0a..3da14ea 100644 --- a/src/soc/intel/common/block/pcr/Makefile.inc +++ b/src/soc/intel/common/block/pcr/Makefile.inc @@ -1,5 +1,6 @@ bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCR) += pcr.c romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCR) += pcr.c +postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCR) += pcr.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCR) += pcr.c smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCR) += pcr.c verstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCR) += pcr.c diff --git a/src/soc/intel/common/block/systemagent/Makefile.inc b/src/soc/intel/common/block/systemagent/Makefile.inc index 0c29636..e4d4b0b 100644 --- a/src/soc/intel/common/block/systemagent/Makefile.inc +++ b/src/soc/intel/common/block/systemagent/Makefile.inc @@ -3,3 +3,4 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA) += systemagent_early.c postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA) += systemagent_early.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA) += systemagent.c +postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA) += systemagent.c diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 9608359..cfbbbe9 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -250,7 +250,7 @@ *resource_cnt = index; } -static void systemagent_read_resources(struct device *dev) +void systemagent_read_resources(struct device *dev) { int index = 0; diff --git a/src/soc/intel/common/block/systemagent/systemagent_early.c b/src/soc/intel/common/block/systemagent/systemagent_early.c index c1cef5d..7884961 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_early.c +++ b/src/soc/intel/common/block/systemagent/systemagent_early.c @@ -24,7 +24,7 @@ #include "systemagent_def.h" #include <timer.h> -#if !ENV_RAMSTAGE +#if !ENV_RAMSTAGE && !ENV_POSTCAR void bootblock_systemagent_early_init(void) { uint32_t reg; diff --git a/src/soc/intel/icelake/Makefile.inc b/src/soc/intel/icelake/Makefile.inc index 74c9182..84458aa 100644 --- a/src/soc/intel/icelake/Makefile.inc +++ b/src/soc/intel/icelake/Makefile.inc @@ -33,12 +33,15 @@ romstage-y += uart.c ramstage-y += acpi.c +postcar-y += acpi.c ramstage-y += chip.c ramstage-y += cpu.c +postcar-y += cpu.c ramstage-y += finalize.c ramstage-y += fsp_params.c ramstage-y += gpio.c ramstage-y += graphics.c +postcar-y += graphics.c ramstage-y += gspi.c ramstage-y += gpio.c ramstage-y += i2c.c @@ -50,17 +53,22 @@ ramstage-y += pmutil.c ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c ramstage-y += smmrelocate.c +postcar-y += smmrelocate.c ramstage-y += spi.c ramstage-y += systemagent.c ramstage-y += uart.c ramstage-y += sd.c +ramstage-y += payload_init.c + smm-y += gpio.c smm-y += p2sb.c smm-y += pmutil.c smm-y += smihandler.c smm-y += uart.c - +postcar-y += fsp_params.c +postcar-y += gpio.c +postcar-y += payload_init.c postcar-y += memmap.c postcar-y += pmutil.c postcar-y += i2c.c diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c index 39ec58a..c147692 100644 --- a/src/soc/intel/icelake/acpi.c +++ b/src/soc/intel/icelake/acpi.c @@ -220,7 +220,7 @@ gnvs->dpte = config->dptf_enable; /* Fill in the Wifi Region id */ - gnvs->cid1 = wifi_regulatory_domain(); +// gnvs->cid1 = wifi_regulatory_domain(); // TODO: bad hack /* Set USB2/USB3 wake enable bitmaps. */ gnvs->u2we = config->usb2_wake_enable_bitmap; diff --git a/src/soc/intel/icelake/include/soc/payload_init.h b/src/soc/intel/icelake/include/soc/payload_init.h new file mode 100644 index 0000000..4e838cd --- /dev/null +++ b/src/soc/intel/icelake/include/soc/payload_init.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#ifndef _PAYLOAD_INIT_H_ +#define _PAYLOAD_INIT_H_ + +#include <stdint.h> + +void postcar_payload_init(void); +#endif diff --git a/src/soc/intel/icelake/payload_init.c b/src/soc/intel/icelake/payload_init.c new file mode 100644 index 0000000..20fe90c --- /dev/null +++ b/src/soc/intel/icelake/payload_init.c @@ -0,0 +1,237 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootstate.h> +#include <boot/tables.h> +#include <console/console.h> +#include <cpu/cpu.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mp.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <intelblocks/systemagent.h> +#include <fsp/api.h> +#include <fsp/util.h> +#include <romstage_handoff.h> +#include <soc/pci_devs.h> +#include <string.h> +#include <program_loading.h> +#include <soc/payload_init.h> + +#include <cpu/intel/microcode.h> +#include <intelblocks/cpulib.h> +#include <intelblocks/mp_init.h> +#include <intelblocks/msr.h> +#include <intelblocks/acpi.h> +#include <soc/cpu.h> +#include <vendorcode/google/chromeos/chromeos.h> + +#include "mrc_cache.h" +#include <soc/intel/common/acpi.h> + +#define XHCI_FIXED_BAR 0xb2310000 +#define XHCI_BAR_SIZE 0x10000 + +#define IGD_FIXED_BAR 0xb0000000 +#define IGD_BAR_SIZE 0x1000000 +#define IGD_FIXED_BAR_2 0xa0000000 +#define IGD_BAR_SIZE_2 0x10000000 + +static void pch_set_bar(struct device *dev, uintptr_t tempbar, + uintptr_t tempbar_1, uintptr_t tempbar_2) +{ + uint8_t pcireg; + + /* Assign Resources to Thermal Device */ + /* Clear BIT 1-2 of Command Register */ + pcireg = pci_read_config8(dev, PCI_COMMAND); + pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + pci_write_config8(dev, PCI_COMMAND, pcireg); + + /* Program Temporary BAR for Thermal Device */ + pci_write_config32(dev, PCI_BASE_ADDRESS_0, tempbar); + pci_write_config32(dev, PCI_BASE_ADDRESS_1, tempbar_1); + pci_write_config32(dev, PCI_BASE_ADDRESS_2, tempbar_2); + + /* Enable Bus Master and MMIO Space */ + pcireg = pci_read_config8(dev, PCI_COMMAND); + pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config8(dev, PCI_COMMAND, pcireg); +} + +static void allocate_device_resource(struct device *dev, int offset, + uint32_t base, uint32_t size) +{ + struct resource *res; + + res = new_resource(dev, offset); + res->base = base; + res->size = size; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | + IORESOURCE_FIXED; +} + +static void set_device_resource(struct device *dev, int offset, + uint32_t base) +{ + struct resource *res; + + res = find_resource(dev, offset); + dev->command |= 2; + res->flags = IORESOURCE_STORED; + report_resource_stored(dev, res, "Device BAR 0"); + + pci_dev_enable_resources(dev); +} + +static void enable_xhci_device(void) +{ + struct device *dev = PCH_DEV_XHCI; + + allocate_device_resource(dev, PCI_BASE_ADDRESS_0, + XHCI_FIXED_BAR, XHCI_BAR_SIZE); + set_device_resource(dev, PCI_BASE_ADDRESS_0, + XHCI_FIXED_BAR); + + pch_set_bar(dev, XHCI_FIXED_BAR, 0, 0); +} + +static void enable_igd_device(void) +{ + struct device *dev = SA_DEV_IGD; + + allocate_device_resource(dev, PCI_BASE_ADDRESS_0, + IGD_FIXED_BAR, IGD_BAR_SIZE); + set_device_resource(dev, PCI_BASE_ADDRESS_0, + IGD_FIXED_BAR); + + allocate_device_resource(dev, PCI_BASE_ADDRESS_2, + IGD_FIXED_BAR_2, IGD_BAR_SIZE_2); + set_device_resource(dev, PCI_BASE_ADDRESS_2, + IGD_FIXED_BAR_2); + + pch_set_bar(dev, IGD_FIXED_BAR, 0, IGD_FIXED_BAR_2); +} + +static void wrapper_x86_core_init(void *unused) +{ + struct device *dev = dev_find_path(NULL, DEVICE_PATH_CPU_CLUSTER); + + soc_core_init(dev); +} + +static void init_cpus(void) +{ + struct device *dev = dev_find_path(NULL, DEVICE_PATH_CPU_CLUSTER); + static const void *microcode_patch; + + intel_microcode_load_unlocked(microcode_patch); + + if (dev && dev->link_list) + soc_init_cpus(dev->link_list); + + if (mp_run_on_all_cpus(&wrapper_x86_core_init, NULL, 5000) < 0) + printk(BIOS_ERR, "CPU Init failure\n"); +} + +static void wrapper_x86_setup_mtrrs(void *unused) +{ + x86_setup_mtrrs_with_detect(); +} + +/* Ensure to re-program all MTRRs based on DRAM resource settings */ +static void post_cpus_init(void) +{ + if (mp_run_on_all_cpus(&wrapper_x86_setup_mtrrs, NULL, 5000) < 0) + printk(BIOS_ERR, "MTRR programming failure\n"); + + x86_mtrr_check(); +} + +static void wake_from_s3(void) +{ +#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) + void *wake_vector; + + wake_vector = acpi_find_wakeup_vector(); + + if (wake_vector != NULL) { + acpi_save_wake_source(NULL); + arch_bootstate_coreboot_exit(); + acpi_resume(wake_vector); + } +#endif +} + +static void finaize_smm(void) +{ + printk(BIOS_DEBUG, "Finalizing SMM.\n"); + outb(0xcb, 0xb2); +} + +void postcar_payload_init(void) +{ + struct device *dev = SA_DEV_ROOT; + int is_s3_resume = romstage_handoff_is_resume(); + + /* Initialize CPU cores */ + init_cpus(); + + /* Perform silicon specific init. */ + fsp_silicon_init(is_s3_resume); + + /* Save MRC cache into SPI*/ + update_mrc_cache(NULL); + + /* Read Resources for Root Device 0:0:0 */ + systemagent_read_resources(dev); + pci_dev_set_resources(dev); + pci_dev_enable_resources(dev); + + /* Make IGD Enable */ + enable_igd_device(); + + /* Make USB bootable */ + enable_xhci_device(); + + /* Add S3 Resume logic */ + if (is_s3_resume) { + finaize_smm(); + wake_from_s3(); + } + + acpi_prepare_resume_backup(); + + /* DSDT generation */ + southbridge_inject_dsdt(dev); + mainboard_chromeos_acpi_generate(); + + /* Post MP Init to program MTRR on APs */ + post_cpus_init(); + + /* Create coreboot tables */ + write_tables(); + + /* Load Payload */ + payload_load(); + + finaize_smm(); + + /* Run Payload */ + payload_run(); +} diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index 3224e1f..bc43da6 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -34,6 +34,7 @@ ramstage-$(CONFIG_USBDEBUG) += usb_debug.c romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c +postcar-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index 000d056..28abd2e 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -13,10 +13,13 @@ ## GNU General Public License for more details. ## +postcar-$(CONFIG_HAVE_ACPI_TABLES) += gnvs.c ramstage-$(CONFIG_ELOG) += elog.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += gnvs.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c +postcar-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-$(CONFIG_CHROMEOS_RAMOOPS) += ramoops.c +postcar-$(CONFIG_CHROMEOS_RAMOOPS) += ramoops.c ramstage-y += vpd_mac.c vpd_serialno.c vpd_calibration.c ramstage-$(CONFIG_CHROMEOS_DISABLE_PLATFORM_HIERARCHY_ON_RESUME) += tpm2.c ramstage-$(CONFIG_HAVE_REGULATORY_DOMAIN) += wrdd.c -- To view, visit https://review.coreboot.org/c/coreboot/+/30985 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27479187461ceb078167f2d726f40839865a9233 Gerrit-Change-Number: 30985 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

3 10

Change in ...coreboot[master]: {drivers,soc/intel/braswell}: Implement C_ENVIRONMENT_BOOTBLOCK support
by Arthur Heymans (Code Review) 12 Jun '19

12 Jun '19

Arthur Heymans has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29662 ) Change subject: {drivers,soc/intel/braswell}: Implement C_ENVIRONMENT_BOOTBLOCK support ...................................................................... {drivers,soc/intel/braswell}: Implement C_ENVIRONMENT_BOOTBLOCK support No C_ENVIRONMENT_BOOTBLOCK support for Braswell is available. Enable support and add required files for the Braswell Bootblock in C. The next changes are made support C_ENVIRONMENT_BOOTBLOCK: - Add car_stage_entry() function bootblock-c_entry() functions. - Specify config DCACHE_BSP_STACK_SIZE and C_ENV_BOOTBLOCK_SIZE. - Add bootblock_c_entry(). - Move init from car_soc_XXX_console_init() to bootblock_soc_XXX_Init() Removed the unused cache_as_ram_main() and weak car_XXX_XXX_console_init() BUG=NA TEST=Booting Embedded Linux on Facebook FBG-1701 Building Google Banos Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29662 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/intel/fsp1_1/Makefile.inc R src/drivers/intel/fsp1_1/cache_as_ram.S M src/drivers/intel/fsp1_1/car.c M src/drivers/intel/fsp1_1/include/fsp/car.h M src/mainboard/google/cyan/Makefile.inc M src/mainboard/google/cyan/com_init.c M src/mainboard/intel/strago/Makefile.inc M src/mainboard/intel/strago/com_init.c M src/soc/intel/braswell/Kconfig M src/soc/intel/braswell/Makefile.inc M src/soc/intel/braswell/bootblock/bootblock.c R src/soc/intel/braswell/include/soc/bootblock.h M src/soc/intel/braswell/include/soc/romstage.h M src/soc/intel/braswell/romstage/Makefile.inc M src/soc/intel/braswell/romstage/romstage.c 15 files changed, 138 insertions(+), 195 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc index 93f3b59..10877b9 100644 --- a/src/drivers/intel/fsp1_1/Makefile.inc +++ b/src/drivers/intel/fsp1_1/Makefile.inc @@ -21,6 +21,7 @@ verstage-$(CONFIG_SEPARATE_VERSTAGE) += verstage.c bootblock-y += bootblock.c +bootblock-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += cache_as_ram.S bootblock-y += fsp_util.c romstage-y += car.c @@ -42,8 +43,6 @@ CPPFLAGS_common += -Isrc/drivers/intel/fsp1_1/include -cpu_incs-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += $(src)/drivers/intel/fsp1_1/cache_as_ram.inc - postcar-y += stage_cache.c ifneq ($(CONFIG_SKIP_FSP_CAR),y) postcar-y += temp_ram_exit.c diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.inc b/src/drivers/intel/fsp1_1/cache_as_ram.S similarity index 93% rename from src/drivers/intel/fsp1_1/cache_as_ram.inc rename to src/drivers/intel/fsp1_1/cache_as_ram.S index 493dbc8..3460b9d 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.inc +++ b/src/drivers/intel/fsp1_1/cache_as_ram.S @@ -5,6 +5,7 @@ * Copyright (C) 2007-2008 coresystems GmbH * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018-2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,6 +17,8 @@ * GNU General Public License for more details. */ +#include <cpu/x86/post_code.h> + /* * Replacement for cache_as_ram.inc when using the FSP binary. This code * locates the FSP binary, initializes the cache as RAM and performs the @@ -24,8 +27,10 @@ * performs the final stage of initialization. */ -/* I/O delay between post codes on failure */ -#define LHLT_DELAY 0x50000 +#define LHLT_DELAY 0x50000 /* I/O delay between post codes on failure */ + +.global bootblock_pre_c_entry +bootblock_pre_c_entry: /* * Per FSP1.1 specs, following registers are preserved: * EBX, EDI, ESI, EBP, MM0, MM1 @@ -129,10 +134,9 @@ /* Need to align stack to 16 bytes at call instruction. Account for the pushes below. */ andl $0xfffffff0, %esp - subl $4, %esp + subl $8, %esp - /* Push BIST and initial timestamp on the stack */ - pushl %ebx /* bist */ + /* Push initial timestamp on the stack */ movd %mm1, %eax pushl %eax /* tsc[63:32] */ movd %mm0, %eax @@ -141,12 +145,10 @@ before_romstage: post_code(0x2A) - /* Call bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist) - in cpu/intel/car/romstage.c */ - call bootblock_c_entry_bist + /* Call bootblock_c_entry(uint64_t base_timestamp) */ + call bootblock_c_entry - movb $0x69, %ah - jmp .Lhlt + /* Never reached */ halt1: /* diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c index dd1766403..67ed099 100644 --- a/src/drivers/intel/fsp1_1/car.c +++ b/src/drivers/intel/fsp1_1/car.c @@ -101,18 +101,6 @@ * is still enabled. We can directly access work buffer here. */ struct prog fsp = PROG_INIT(PROG_REFCODE, "fsp.bin"); - if (!CONFIG(C_ENVIRONMENT_BOOTBLOCK)) { - /* Call into pre-console init code then initialize console. */ - car_soc_pre_console_init(); - car_mainboard_pre_console_init(); - console_init(); - - display_mtrrs(); - - car_soc_post_console_init(); - car_mainboard_post_console_init(); - } - if (prog_locate(&fsp)) die_with_post_code(POST_INVALID_CBFS, "Unable to locate fsp.bin"); @@ -125,19 +113,3 @@ cache_as_ram_stage_main(fih); } - -void __weak car_mainboard_pre_console_init(void) -{ -} - -void __weak car_soc_pre_console_init(void) -{ -} - -void __weak car_mainboard_post_console_init(void) -{ -} - -void __weak car_soc_post_console_init(void) -{ -} diff --git a/src/drivers/intel/fsp1_1/include/fsp/car.h b/src/drivers/intel/fsp1_1/include/fsp/car.h index 8d7a683..3d99fa6 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/car.h +++ b/src/drivers/intel/fsp1_1/include/fsp/car.h @@ -24,12 +24,4 @@ * cache_as_ram_stage_main() is the stack pointer to use in RAM after * exiting cache-as-ram mode. */ void cache_as_ram_stage_main(FSP_INFO_HEADER *fih); - -/* Mainboard and SoC initialization prior to console. */ -void car_mainboard_pre_console_init(void); -void car_soc_pre_console_init(void); -/* Mainboard and SoC initialization post console initialization. */ -void car_mainboard_post_console_init(void); -void car_soc_post_console_init(void); - #endif diff --git a/src/mainboard/google/cyan/Makefile.inc b/src/mainboard/google/cyan/Makefile.inc index 92b0422..027c49c 100644 --- a/src/mainboard/google/cyan/Makefile.inc +++ b/src/mainboard/google/cyan/Makefile.inc @@ -14,8 +14,9 @@ ## GNU General Public License for more details. ## +bootblock-$(CONFIG_ENABLE_BUILTIN_COM1) += com_init.c + romstage-$(CONFIG_CHROMEOS) += chromeos.c -romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += com_init.c romstage-y += spd/spd.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c diff --git a/src/mainboard/google/cyan/com_init.c b/src/mainboard/google/cyan/com_init.c index 44260bb..b08dbce 100644 --- a/src/mainboard/google/cyan/com_init.c +++ b/src/mainboard/google/cyan/com_init.c @@ -14,14 +14,14 @@ * GNU General Public License for more details. */ +#include <bootblock_common.h> #include <device/mmio.h> #include <device/pci_ops.h> #include <soc/gpio.h> #include <soc/lpc.h> #include <soc/pci_devs.h> -#include <soc/romstage.h> -void car_mainboard_pre_console_init(void) +void bootblock_mainboard_early_init(void) { uint32_t reg; uint32_t *pad_config_reg; diff --git a/src/mainboard/intel/strago/Makefile.inc b/src/mainboard/intel/strago/Makefile.inc index bbef8b9..e6f0c9e 100644 --- a/src/mainboard/intel/strago/Makefile.inc +++ b/src/mainboard/intel/strago/Makefile.inc @@ -14,8 +14,9 @@ ## GNU General Public License for more details. ## +bootblock-$(CONFIG_ENABLE_BUILTIN_COM1) += com_init.c + romstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += chromeos.c -romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += com_init.c ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += chromeos.c ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += ec.c diff --git a/src/mainboard/intel/strago/com_init.c b/src/mainboard/intel/strago/com_init.c index b89d655..695ea98 100644 --- a/src/mainboard/intel/strago/com_init.c +++ b/src/mainboard/intel/strago/com_init.c @@ -14,12 +14,12 @@ * GNU General Public License for more details. */ +#include <bootblock_common.h> #include <device/mmio.h> #include <device/pci_ops.h> #include <soc/gpio.h> #include <soc/lpc.h> #include <soc/pci_devs.h> -#include <soc/romstage.h> /* * return family number and internal pad number in that community @@ -30,7 +30,7 @@ /* family number in high byte and inner pad number in lowest byte */ -void car_mainboard_pre_console_init(void) +void bootblock_mainboard_early_init(void) { uint32_t reg; uint32_t *pad_config_reg; diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index ed5c972..920179f83 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -51,15 +51,23 @@ select INTEL_GMA_SWSMISCI select CPU_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS + select C_ENVIRONMENT_BOOTBLOCK + +config DCACHE_BSP_STACK_SIZE + hex + default 0x2000 + help + The amount of anticipated stack usage in CAR by bootblock and + other stages. + +config C_ENV_BOOTBLOCK_SIZE + hex + default 0x8000 config VBOOT select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_ROMSTAGE -config BOOTBLOCK_CPU_INIT - string - default "soc/intel/braswell/bootblock/bootblock.c" - config MMCONF_BASE_ADDRESS hex default 0xe0000000 diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc index e479a3c..1017d80 100644 --- a/src/soc/intel/braswell/Makefile.inc +++ b/src/soc/intel/braswell/Makefile.inc @@ -9,9 +9,14 @@ subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/intel/common +bootblock-y += gpio_support.c +bootblock-y += bootblock/bootblock.c +bootblock-y += lpc_init.c +bootblock-y += pmutil.c +bootblock-y += tsc_freq.c + romstage-y += gpio_support.c romstage-y += iosf.c -romstage-y += lpc_init.c romstage-y += memmap.c romstage-y += pmutil.c romstage-y += smbus.c diff --git a/src/soc/intel/braswell/bootblock/bootblock.c b/src/soc/intel/braswell/bootblock/bootblock.c index 457b8b8..2d1a3e8 100644 --- a/src/soc/intel/braswell/bootblock/bootblock.c +++ b/src/soc/intel/braswell/bootblock/bootblock.c @@ -3,6 +3,7 @@ * * Copyright (C) 2013 Google, Inc. * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -14,37 +15,93 @@ * GNU General Public License for more details. */ +#include <bootblock_common.h> +#include <build.h> +#include <console/console.h> #include <device/pci_ops.h> -#include <cpu/x86/cache.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/mtrr.h> +#include <pc80/mc146818rtc.h> +#include <soc/bootblock.h> +#include <soc/gpio.h> +#include <soc/iomap.h> #include <soc/iosf.h> -#include <cpu/intel/microcode/microcode.c> +#include <soc/lpc.h> +#include <soc/pm.h> +#include <soc/spi.h> -static void set_var_mtrr(int reg, uint32_t base, uint32_t size, int type) +asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { - msr_t basem, maskm; - basem.lo = base | type; - basem.hi = 0; - wrmsr(MTRR_PHYS_BASE(reg), basem); - maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID; - maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; - wrmsr(MTRR_PHYS_MASK(reg), maskm); + /* Call lib/bootblock.c main */ + bootblock_main_with_timestamp(base_timestamp, NULL, 0); } -static void enable_rom_caching(void) +static void program_base_addresses(void) { - msr_t msr; + uint32_t reg; + const uint32_t lpc_dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); - disable_cache(); - /* Why only top 4MiB ? */ - set_var_mtrr(1, 0xffc00000, 4*1024*1024, MTRR_TYPE_WRPROT); - enable_cache(); + /* Memory Mapped IO registers. */ + reg = PMC_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, PBASE, reg); + reg = IO_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, IOBASE, reg); + reg = ILB_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, IBASE, reg); + reg = SPI_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, SBASE, reg); + reg = MPHY_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, MPBASE, reg); + reg = PUNIT_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, PUBASE, reg); + reg = RCBA_BASE_ADDRESS | 1; + pci_write_config32(lpc_dev, RCBA, reg); - /* Enable Variable MTRRs */ - msr.hi = 0x00000000; - msr.lo = 0x00000800; - wrmsr(MTRR_DEF_TYPE_MSR, msr); + /* IO Port Registers. */ + reg = ACPI_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, ABASE, reg); + reg = GPIO_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, GBASE, reg); +} + +static void tco_disable(void) +{ + uint32_t reg; + + reg = inl(ACPI_BASE_ADDRESS + TCO1_CNT); + reg |= TCO_TMR_HALT; + outl(reg, ACPI_BASE_ADDRESS + TCO1_CNT); +} + +static void spi_init(void) +{ + void *scs = (void *)(SPI_BASE_ADDRESS + SCS); + void *bcr = (void *)(SPI_BASE_ADDRESS + BCR); + uint32_t reg; + + /* Disable generating SMI when setting WPD bit. */ + write32(scs, read32(scs) & ~SMIWPEN); + /* + * Enable caching and prefetching in the SPI controller. Disable + * the SMM-only BIOS write and set WPD bit. + */ + reg = (read32(bcr) & ~SRC_MASK) | SRC_CACHE_PREFETCH | BCR_WPD; + reg &= ~EISS; + write32(bcr, reg); +} + +static void soc_rtc_init(void) +{ + int rtc_failed = rtc_failure(); + + if (rtc_failed) { + printk(BIOS_ERR, + "RTC Failure detected. Resetting date to %x/%x/%x%x\n", + COREBOOT_BUILD_MONTH_BCD, + COREBOOT_BUILD_DAY_BCD, + 0x20, + COREBOOT_BUILD_YEAR_BCD); + } + + cmos_init(rtc_failed); } static void setup_mmconfig(void) @@ -67,12 +124,22 @@ pci_io_write_config32(IOSF_PCI_DEV, MCR_REG, reg); } -static void bootblock_cpu_init(void) + +void bootblock_soc_early_init(void) { /* Allow memory-mapped PCI config access. */ setup_mmconfig(); - /* Load microcode before any caching. */ - intel_update_microcode_from_cbfs(); - enable_rom_caching(); + /* Early chipset initialization */ + program_base_addresses(); + tco_disable(); +} +void bootblock_soc_init(void) +{ + /* Continue chipset initialization */ + soc_rtc_init(); + set_max_freq(); + spi_init(); + + lpc_init(); } diff --git a/src/soc/intel/braswell/romstage/pmc.c b/src/soc/intel/braswell/include/soc/bootblock.h similarity index 67% rename from src/soc/intel/braswell/romstage/pmc.c rename to src/soc/intel/braswell/include/soc/bootblock.h index 127458e..e6e25cc 100644 --- a/src/soc/intel/braswell/romstage/pmc.c +++ b/src/soc/intel/braswell/include/soc/bootblock.h @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2015-2016 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -14,15 +14,9 @@ * GNU General Public License for more details. */ -#include <arch/io.h> -#include <soc/iomap.h> -#include <soc/romstage.h> +#ifndef _SOC_BOOTBLOCK_H_ +#define _SOC_BOOTBLOCK_H_ -void tco_disable(void) -{ - uint32_t reg; +void set_max_freq(void); - reg = inl(ACPI_BASE_ADDRESS + TCO1_CNT); - reg |= TCO_TMR_HALT; - outl(reg, ACPI_BASE_ADDRESS + TCO1_CNT); -} +#endif /* _SOC_BOOTBLOCK_H_ */ diff --git a/src/soc/intel/braswell/include/soc/romstage.h b/src/soc/intel/braswell/include/soc/romstage.h index 4ecbd2c..9fad9bc 100644 --- a/src/soc/intel/braswell/include/soc/romstage.h +++ b/src/soc/intel/braswell/include/soc/romstage.h @@ -23,12 +23,10 @@ #include <soc/pm.h> void gfx_init(void); -void tco_disable(void); void punit_init(void); void set_max_freq(void); -/* romstage_common.c functions */ -void program_base_addresses(void); +/* romstage.c functions */ int chipset_prev_sleep_state(struct chipset_power_state *ps); /* Values for FSP's PcdMemoryTypeEnable */ diff --git a/src/soc/intel/braswell/romstage/Makefile.inc b/src/soc/intel/braswell/romstage/Makefile.inc index 3d3e407..d405133 100644 --- a/src/soc/intel/braswell/romstage/Makefile.inc +++ b/src/soc/intel/braswell/romstage/Makefile.inc @@ -1,3 +1,2 @@ romstage-y += ../../../../cpu/intel/car/romstage.c -romstage-y += pmc.c romstage-y += romstage.c diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c index 8dfc291..e0e22f2 100644 --- a/src/soc/intel/braswell/romstage/romstage.c +++ b/src/soc/intel/braswell/romstage/romstage.c @@ -19,90 +19,13 @@ #include <stddef.h> #include <arch/io.h> #include <device/mmio.h> -#include <device/pci_ops.h> -#include <arch/cbfs.h> -#include <cpu/x86/mtrr.h> #include <console/console.h> -#include <device/device.h> -#include <device/pci_def.h> -#include <elog.h> -#include <mrc_cache.h> -#include <string.h> -#include <vendorcode/google/chromeos/chromeos.h> -#include <fsp/util.h> -#include <soc/gpio.h> #include <soc/iomap.h> #include <soc/iosf.h> -#include <soc/lpc.h> -#include <soc/pci_devs.h> #include <soc/romstage.h> -#include <soc/smm.h> -#include <soc/spi.h> -#include <build.h> -#include <pc80/mc146818rtc.h> #include "../chip.h" -void program_base_addresses(void) -{ - uint32_t reg; - const uint32_t lpc_dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); - - /* Memory Mapped IO registers. */ - reg = PMC_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, PBASE, reg); - reg = IO_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, IOBASE, reg); - reg = ILB_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, IBASE, reg); - reg = SPI_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, SBASE, reg); - reg = MPHY_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, MPBASE, reg); - reg = PUNIT_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, PUBASE, reg); - reg = RCBA_BASE_ADDRESS | 1; - pci_write_config32(lpc_dev, RCBA, reg); - - /* IO Port Registers. */ - reg = ACPI_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, ABASE, reg); - reg = GPIO_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, GBASE, reg); -} - -static void spi_init(void) -{ - void *scs = (void *)(SPI_BASE_ADDRESS + SCS); - void *bcr = (void *)(SPI_BASE_ADDRESS + BCR); - uint32_t reg; - - /* Disable generating SMI when setting WPD bit. */ - write32(scs, read32(scs) & ~SMIWPEN); - /* - * Enable caching and prefetching in the SPI controller. Disable - * the SMM-only BIOS write and set WPD bit. - */ - reg = (read32(bcr) & ~SRC_MASK) | SRC_CACHE_PREFETCH | BCR_WPD; - reg &= ~EISS; - write32(bcr, reg); -} - -static void soc_rtc_init(void) -{ - int rtc_failed = rtc_failure(); - - if (rtc_failed) { - printk(BIOS_ERR, - "RTC Failure detected. Resetting date to %x/%x/%x%x\n", - COREBOOT_BUILD_MONTH_BCD, - COREBOOT_BUILD_DAY_BCD, - 0x20, - COREBOOT_BUILD_YEAR_BCD); - } - - cmos_init(rtc_failed); -} static struct chipset_power_state power_state; @@ -171,24 +94,6 @@ return prev_sleep_state; } -/* SOC initialization before the console is enabled */ -void car_soc_pre_console_init(void) -{ - /* Early chipset initialization */ - program_base_addresses(); - tco_disable(); -} - -/* SOC initialization after console is enabled */ -void car_soc_post_console_init(void) -{ - /* Continue chipset initialization */ - soc_rtc_init(); - set_max_freq(); - spi_init(); - - lpc_init(); -} /* SOC initialization after RAM is enabled */ void soc_after_ram_init(struct romstage_params *params) -- To view, visit https://review.coreboot.org/c/coreboot/+/29662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c Gerrit-Change-Number: 29662 Gerrit-PatchSet: 47 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: York Yang <yyang024(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in ...coreboot[master]: {drivers,soc/intel/braswell}: Implement C_ENVIRONMENT_BOOTBLOCK support
by Frans Hendriks (Code Review) 12 Jun '19

12 Jun '19

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29662 ) Change subject: {drivers,soc/intel/braswell}: Implement C_ENVIRONMENT_BOOTBLOCK support ...................................................................... Patch Set 46: > Patch Set 46: Code-Review+2 Ready to merge this patch? -- To view, visit https://review.coreboot.org/c/coreboot/+/29662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c Gerrit-Change-Number: 29662 Gerrit-PatchSet: 46 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: York Yang <yyang024(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 12 Jun 2019 07:39:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: sdm845: Add QUPv3 FW load & config
by Akash Asthana (Code Review) 12 Jun '19

12 Jun '19

Akash Asthana has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25372 ) Change subject: sdm845: Add QUPv3 FW load & config ...................................................................... Patch Set 73: (1 comment) https://review.coreboot.org/#/c/25372/6/src/mainboard/google/cheza/qupv3_co… File src/mainboard/google/cheza/qupv3_config.c: https://review.coreboot.org/#/c/25372/6/src/mainboard/google/cheza/qupv3_co… PS6, Line 18: struct se_cfg se_mappings[QUPV3_SE_MAX] = > This is the first SoC we ever had that has to load firmware to get basic peripherals working, so the […] >>>> To load QUPV3 firmware from respective driver init function We have been discussing with the Firmware/HW team and came to the conclusion that this can’t be supported. Right now, the FW loading sequence is fixed and doesn’t allow initialization of few Registers on every FW load separately. It’s recommended to be done only once and hence forces to load firmware at one go. -- To view, visit https://review.coreboot.org/c/coreboot/+/25372 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e87f868ecbe2a8e51d94c045ad76b99bb1b345d Gerrit-Change-Number: 25372 Gerrit-PatchSet: 73 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mukesh Savaliya <msavaliy(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Akash Asthana <akashast(a)qualcomm.corp-partner.google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Wed, 12 Jun 2019 07:34:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Akash Asthana <akashast(a)qualcomm.corp-partner.google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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coreboot-gerrit June 2019