Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25345 )
Change subject: soc/amd/stoneyridge: Generate SPCR table
......................................................................
Patch Set 6:
(3 comments)
Sorry for another round of questions. The source LGTM though.
https://review.coreboot.org/#/c/25345/6//COMMIT_MSG
Commit Message:
https://review.coreboot.org/#/c/25345/6//COMMIT_MSG@11
PS6, Line 11: custom input clock
maybe a nit - is this comment left over from a previews version of the patch? or did I miss the clock somewhere?
https://review.coreboot.org/#/c/25345/6//COMMIT_MSG@11
PS6, Line 11: of of
nit
https://review.coreboot.org/#/c/25345/6/src/soc/amd/stoneyridge/uart.c
File src/soc/amd/stoneyridge/uart.c:
https://review.coreboot.org/#/c/25345/6/src/soc/amd/stoneyridge/uart.c@41
PS6, Line 41: AMDCZ
> The glib answer is to make this work: https://lkml. […]
thanks
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Daniel Kurtz has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25345 )
Change subject: soc/amd/stoneyridge: Generate SPCR table
......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/#/c/25345/6/src/soc/amd/stoneyridge/uart.c
File src/soc/amd/stoneyridge/uart.c:
https://review.coreboot.org/#/c/25345/6/src/soc/amd/stoneyridge/uart.c@41
PS6, Line 41: AMDCZ
> Is this to indicate AMD Carrizo(ish) since the FCHs are the same? Not that I see a problem, but won […]
The glib answer is to make this work: https://lkml.org/lkml/2018/3/14/1248
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Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25345 )
Change subject: soc/amd/stoneyridge: Generate SPCR table
......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/#/c/25345/6/src/soc/amd/stoneyridge/uart.c
File src/soc/amd/stoneyridge/uart.c:
https://review.coreboot.org/#/c/25345/6/src/soc/amd/stoneyridge/uart.c@41
PS6, Line 41: AMDCZ
Is this to indicate AMD Carrizo(ish) since the FCHs are the same? Not that I see a problem, but wondering why aren't these simply COREv4 and COREBOOT like in many other other tables?
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Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25344 )
Change subject: ACPI: Add SPCR table
......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/#/c/25344/6/src/arch/x86/acpi.c
File src/arch/x86/acpi.c:
https://review.coreboot.org/#/c/25344/6/src/arch/x86/acpi.c@1578
PS6, Line 1578: asl_compiler_revision = 0
> I have to question that, even though it would match with the other tables. […]
You're right. Never mind.
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Aaron Durbin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33370
Change subject: mb/google/octopus: default DRAM_PART_NUM_IN_CBI to y
......................................................................
mb/google/octopus: default DRAM_PART_NUM_IN_CBI to y
All new targets utilizing octopus mainboard support default
to using DRAM_PART_NUM_IN_CBI, including DRAM_PART_NUM_ALWAYS_IN_CBI.
This allows easier addition of new targets.
BUG=b:132668378
BRANCH=octopus
Change-Id: Idb136aa960260abe1657b16ded02a7dfb63c6849
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
M src/mainboard/google/octopus/Kconfig
1 file changed, 11 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/33370/1
diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig
index 48753ed..0ddfb3a 100644
--- a/src/mainboard/google/octopus/Kconfig
+++ b/src/mainboard/google/octopus/Kconfig
@@ -123,20 +123,22 @@
config DRAM_PART_NUM_IN_CBI
bool
- default y if BOARD_GOOGLE_PHASER
- default y if BOARD_GOOGLE_MEEP
- default y if BOARD_GOOGLE_AMPTON
- default y if BOARD_GOOGLE_FLEEX
+ default y
+
+config DRAM_PART_NUM_NOT_ALWAYS_IN_CBI
+ bool
+ depends on DRAM_PART_NUM_IN_CBI
default y if BOARD_GOOGLE_BOBBA
- default y if BOARD_GOOGLE_CASTA
- default y if BOARD_GOOGLE_BLOOG
+ default y if BOARD_GOOGLE_FLEEX
+ default y if BOARD_GOOGLE_MEEP
+ default y if BOARD_GOOGLE_OCTOPUS
+ default y if BOARD_GOOGLE_PHASER
+ default y if BOARD_GOOGLE_YORP
config DRAM_PART_NUM_ALWAYS_IN_CBI
bool
depends on DRAM_PART_NUM_IN_CBI
- default y if BOARD_GOOGLE_AMPTON
- default y if BOARD_GOOGLE_CASTA
- default y if BOARD_GOOGLE_BLOOG
+ default y if !DRAM_PART_NUM_NOT_ALWAYS_IN_CBI
config DRAM_PART_IN_CBI_BOARD_ID_MIN
int
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33208 )
Change subject: sb/intel/common: Exclude HAVE_ME_BIN on Apollolake
......................................................................
Patch Set 2:
What if one wants to put a ROM Bypass image into their
APL coreboot?
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