mturney mturney has uploaded a new patch set (#41) to the change originally created by mturney mturney. ( https://review.coreboot.org/c/coreboot/+/27588 )
Change subject: sdm845: Add display hardware pipe line initialization [patch 3 of 3]
......................................................................
sdm845: Add display hardware pipe line initialization [patch 3 of 3]
Add sdm845 display hardware pipeline programming support
and invoke the display initialization from soc_init for
cheza boards.
Change-Id: I432095d177bbbcfc1a00dc5db506f9736feef558
Signed-off-by: Sravan Kumar D.V.N <sravank1(a)codeaurora.org>
---
M src/soc/qualcomm/sdm845/Kconfig
M src/soc/qualcomm/sdm845/Makefile.inc
A src/soc/qualcomm/sdm845/display.c
A src/soc/qualcomm/sdm845/display/mdss.c
A src/soc/qualcomm/sdm845/display/oem_panel.c
A src/soc/qualcomm/sdm845/include/soc/display.h
A src/soc/qualcomm/sdm845/include/soc/display/panel_sn65dsix6_2k_innolux_dsi_video.h
M src/soc/qualcomm/sdm845/soc.c
8 files changed, 1,503 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/27588/41
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mturney mturney has uploaded a new patch set (#64) to the change originally created by mturney mturney. ( https://review.coreboot.org/c/coreboot/+/25817 )
Change subject: libpayload: Add UART for sdm845
......................................................................
libpayload: Add UART for sdm845
TEST=build
Change-Id: Ifb982bccd489048833a78b6f8c5a903e5d3cdf94
Signed-off-by: T Michael Turney <mturney(a)codeaurora.org>
Signed-off-by: Akash Asthana <akashast(a)codeaurora.org>
---
M payloads/libpayload/Kconfig
M payloads/libpayload/configs/config.cheza
M payloads/libpayload/drivers/Makefile.inc
A payloads/libpayload/drivers/serial/sdm845.c
4 files changed, 281 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/25817/64
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mturney mturney has uploaded a new patch set (#74) to the change originally created by mturney mturney. ( https://review.coreboot.org/c/coreboot/+/25373 )
Change subject: sdm845: Add UART support
......................................................................
sdm845: Add UART support
TEST=build & run
Change-Id: I827906e820bc15b7f60fdd7876a54c9ed36a48a1
Signed-off-by: Mukesh Savaliya <msavaliy(a)codeaurora.org>
Signed-off-by: Akash Asthana <akashast(a)codeaurora.org>
---
M src/mainboard/google/cheza/Kconfig
M src/soc/qualcomm/sdm845/Kconfig
M src/soc/qualcomm/sdm845/Makefile.inc
M src/soc/qualcomm/sdm845/include/soc/qcom_qup_se.h
M src/soc/qualcomm/sdm845/include/soc/qupv3_fw_config.h
M src/soc/qualcomm/sdm845/qcom_qup_se.c
A src/soc/qualcomm/sdm845/uart.c
7 files changed, 239 insertions(+), 33 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/25373/74
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mturney mturney has uploaded a new patch set (#74) to the change originally created by mturney mturney. ( https://review.coreboot.org/c/coreboot/+/25372 )
Change subject: sdm845: Add QUPv3 FW load & config
......................................................................
sdm845: Add QUPv3 FW load & config
UART driver requires FW loading
TEST=build
Change-Id: I6e87f868ecbe2a8e51d94c045ad76b99bb1b345d
Signed-off-by: Mukesh Savaliya <msavaliy(a)codeaurora.org>
---
M src/mainboard/google/cheza/Makefile.inc
M src/mainboard/google/cheza/mainboard.c
A src/mainboard/google/cheza/qupv3_config.c
M src/soc/qualcomm/sdm845/Makefile.inc
M src/soc/qualcomm/sdm845/bootblock.c
A src/soc/qualcomm/sdm845/include/soc/qupv3_config.h
A src/soc/qualcomm/sdm845/include/soc/qupv3_fw_config.h
A src/soc/qualcomm/sdm845/qupv3_fw_config.c
8 files changed, 588 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/25372/74
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33440 )
Change subject: superio/nuvoton/nct6776: Make Kconfig symbol dependent
......................................................................
Patch Set 1: Code-Review+1
just saw that this is a bit more complicated than i thought. see my comment on the other patch
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33439 )
Change subject: mb/asrock/h110m: Unselect incorrect Kconfig symbol
......................................................................
Patch Set 1: Code-Review-1
this changes behaviour in src/superio/nuvoton/common/early_serial.c:67
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Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33402
Change subject: util/superiotool: clarify usage of MISC and NANA defines
......................................................................
util/superiotool: clarify usage of MISC and NANA defines
Change-Id: I0b3c5c810bfb05eaec13511391ecd55d7b9eb4e8
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
---
M util/superiotool/superiotool.h
1 file changed, 3 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/33402/1
diff --git a/util/superiotool/superiotool.h b/util/superiotool/superiotool.h
index 1a10fb6..d6e150f 100644
--- a/util/superiotool/superiotool.h
+++ b/util/superiotool/superiotool.h
@@ -127,9 +127,10 @@
#define EOT -1 /* End Of Table */
#define NOLDN -2 /* NO LDN needed */
-#define NANA -3 /* Not Available */
+#define NANA -3 /* Not Available: Used for GPIO input value registers. */
#define RSVD -4 /* Reserved */
-#define MISC -5 /* Needs special comment in output */
+#define MISC -5 /* Needs special comment in output:
+ Used for registers depending on external pin straps. */
#define MAXLDN 0x14 /* Biggest LDN */
#define LDNSIZE (MAXLDN + 3) /* Biggest LDN + 0 + NOLDN + EOT */
#define MAXNUMIDX 170 /* Maximum number of indices */
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33440 )
Change subject: superio/nuvoton/nct6776: Make Kconfig symbol dependent
......................................................................
Patch Set 1: Code-Review+2
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Akash Asthana has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25372 )
Change subject: sdm845: Add QUPv3 FW load & config
......................................................................
Patch Set 73:
(1 comment)
https://review.coreboot.org/#/c/25372/6/src/mainboard/google/cheza/qupv3_co…
File src/mainboard/google/cheza/qupv3_config.c:
https://review.coreboot.org/#/c/25372/6/src/mainboard/google/cheza/qupv3_co…
PS6, Line 18: struct se_cfg se_mappings[QUPV3_SE_MAX] =
> I don't understand this explanation, can you please clarify? What registers are you talking about? W […]
In SDM845, we have two QUPV3 wrappers HW, each wrapper QUPV3 wrapper HW has 8 Serial engines. What you're referring here as QUP is basically a serial engine and they all are independent. But in order to load FW into a particular SE, we have to touch few SE registers and few common QUPV3 wrappers register as well ( https://review.coreboot.org/c/coreboot/+/25372/6/src/soc/qualcomm/sdm845/qu… )
The problem here is with touching common QUPV3 wrappers register (which is suggested to be touched once only during init) when already some use cases are running on any of its SEs.
For example, say SPI use case is already running on SE1 of QUPV3_1 wrapper HW and we need to load I2C FW on SE2 of the same QUPV3_1 wrapper HW then accessing to those common QUPV3 register will impact our ongoing SPI use case.
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33439 )
Change subject: mb/asrock/h110m: Unselect incorrect Kconfig symbol
......................................................................
Patch Set 1:
FWIW, the NCT6791D seems to require bits 7 and 6 to zero in CR 2Ah to enable COM1
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