coreboot-gerrit June 2019

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Change in ...coreboot[master]: mb/asrock/h110m: Unselect incorrect Kconfig symbol
by Angel Pons (Code Review) 14 Jun '19

14 Jun '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33439 ) Change subject: mb/asrock/h110m: Unselect incorrect Kconfig symbol ...................................................................... Patch Set 1: > Patch Set 1: > > > Unfortunately, the early console doesn`t work without SUPERIO_NUVOTON_NCT6776_COM_A symbol. > > I'd suggest adding the proper SUPERIO_NUVOTON_NCT6791_COM_A symbol to both the NCT6791 Kconfig (with guards like the follow-up patch to this one) and the early init code where it sets both uart pinmux bits to the right setting (and not only one like in the currently used code path). @Maxim, could you please try this on your board? The quickest way to test would be to change the code in nuvoton/common/early_serial.c: if (CONFIG(SUPERIO_NUVOTON_NCT6776_COM_A)) /* Route GPIO8 pin group to COM A */ pnp_write_config(dev, 0x2a, 0x40); Replace the '0x40' inside pnp_write_config(dev, 0x2a, 0x40) with a '0x00'. If it works, I'll add SUPERIO_NUVOTON_NCT6791_COM_A. -- To view, visit https://review.coreboot.org/c/coreboot/+/33439 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f3fde161844f919b070f2b6ce7e106411439a9a Gerrit-Change-Number: 33439 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Maxim Polyakov <m.poliakov(a)yahoo.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 14 Jun 2019 17:17:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: drivers/fsp1_0: select CACHE_MRC_SETTINGS if MRC_CACHE_FMAP
by Matt DeVillier (Code Review) 14 Jun '19

14 Jun '19

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33453 Change subject: drivers/fsp1_0: select CACHE_MRC_SETTINGS if MRC_CACHE_FMAP ...................................................................... drivers/fsp1_0: select CACHE_MRC_SETTINGS if MRC_CACHE_FMAP Rather than force the user to create the RW_MRC_CACHE FMAP region, simply select CACHE_MRC_SETTINGS so it's done automatically for them. Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm> Change-Id: Iaa1da6015c1bfafe8ea81ca34ef8851f0c689487 --- M src/drivers/intel/fsp1_0/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/33453/1 diff --git a/src/drivers/intel/fsp1_0/Kconfig b/src/drivers/intel/fsp1_0/Kconfig index 361dd5e..df7617e 100644 --- a/src/drivers/intel/fsp1_0/Kconfig +++ b/src/drivers/intel/fsp1_0/Kconfig @@ -88,10 +88,10 @@ config MRC_CACHE_FMAP bool "Use MRC Cache in FMAP" depends on ENABLE_MRC_CACHE + select CACHE_MRC_SETTINGS default n help Use the region "RW_MRC_CACHE" in FMAP instead of "mrc.cache" in CBFS. - You must define a region in your FMAP named "RW_MRC_CACHE". config MRC_CACHE_SIZE hex "Fast Boot Data Cache Size" -- To view, visit https://review.coreboot.org/c/coreboot/+/33453 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa1da6015c1bfafe8ea81ca34ef8851f0c689487 Gerrit-Change-Number: 33453 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/asrock/h110m: Unselect incorrect Kconfig symbol
by Felix Held (Code Review) 14 Jun '19

14 Jun '19

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33439 ) Change subject: mb/asrock/h110m: Unselect incorrect Kconfig symbol ...................................................................... Patch Set 1: > Unfortunately, the early console doesn`t work without SUPERIO_NUVOTON_NCT6776_COM_A symbol. I'd suggest adding the proper SUPERIO_NUVOTON_NCT6791_COM_A symbol to both the NCT6791 Kconfig (with guards like the follow-up patch to this one) and the early init code where it sets both uart pinmux bits to the right setting (and not only one like in the currently used code path). -- To view, visit https://review.coreboot.org/c/coreboot/+/33439 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f3fde161844f919b070f2b6ce7e106411439a9a Gerrit-Change-Number: 33439 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Maxim Polyakov <m.poliakov(a)yahoo.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 14 Jun 2019 15:40:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/asrock/h110m: Unselect incorrect Kconfig symbol
by Maxim Polyakov (Code Review) 14 Jun '19

14 Jun '19

Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33439 ) Change subject: mb/asrock/h110m: Unselect incorrect Kconfig symbol ...................................................................... Patch Set 1: -Code-Review > Patch Set 1: > > > Patch Set 1: -Code-Review > > > > > AFAIUI, this is writing the value 0x40 to the global register 0x2A, which sets bit7=0 and bit6=1. > > > > > > For the NCT6776, this selects the COMA function on all the COMA pins. > > > > > > For the NCT6791, this selects the COMA function on pin 29, and selects the GPIO8 function on pins 30-36. > > > > > > Guess what happens to serial. > > > > Ok, that does indeed sound wrong, so this patch probably won't break things that aren't already broken. Would probably be good to ping the author of that board port to get things sorted out. > > @Maxim Polyakov, any comments? Unfortunately, the early console doesn`t work without SUPERIO_NUVOTON_NCT6776_COM_A symbol. -- To view, visit https://review.coreboot.org/c/coreboot/+/33439 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f3fde161844f919b070f2b6ce7e106411439a9a Gerrit-Change-Number: 33439 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Maxim Polyakov <m.poliakov(a)yahoo.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 14 Jun 2019 15:26:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: hatch: Fix pen eject polarity
by Tim Wawrzynczak (Code Review) 14 Jun '19

14 Jun '19

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33427 Change subject: hatch: Fix pen eject polarity ...................................................................... hatch: Fix pen eject polarity The gpio_key wakeup_event_action in the ACPI tables was backwards, causing devices to wake up on pen insertion instead of removal. Changed to EV_ACT_DEASSERTED. BUG=b:134547896 BRANCH=none TEST=Verified in OS, device only wakes up on pen removal Change-Id: I0816ed9fb23cf00fd8e40bcdd25ff7a9f48badbd Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/hatch/variants/hatch/overridetree.cb M src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb M src/mainboard/google/hatch/variants/helios/overridetree.cb M src/mainboard/google/hatch/variants/kindred/overridetree.cb 4 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/33427/1 diff --git a/src/mainboard/google/hatch/variants/hatch/overridetree.cb b/src/mainboard/google/hatch/variants/hatch/overridetree.cb index 562bb8b..3846b60 100644 --- a/src/mainboard/google/hatch/variants/hatch/overridetree.cb +++ b/src/mainboard/google/hatch/variants/hatch/overridetree.cb @@ -88,7 +88,7 @@ register "name" = ""PENH"" register "gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A8)" register "key.wake" = "GPE0_DW0_08" - register "key.wakeup_event_action" = "EV_ACT_ASSERTED" + register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" register "key.dev_name" = ""EJCT"" register "key.linux_code" = "SW_PEN_INSERTED" register "key.linux_input_type" = "EV_SW" diff --git a/src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb b/src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb index eec7880..fe7869d 100644 --- a/src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb +++ b/src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb @@ -73,7 +73,7 @@ register "name" = ""PENH"" register "gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A8)" register "key.wake" = "GPE0_DW0_08" - register "key.wakeup_event_action" = "EV_ACT_ASSERTED" + register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" register "key.dev_name" = ""EJCT"" register "key.linux_code" = "SW_PEN_INSERTED" register "key.linux_input_type" = "EV_SW" diff --git a/src/mainboard/google/hatch/variants/helios/overridetree.cb b/src/mainboard/google/hatch/variants/helios/overridetree.cb index 405f85f..2e46fd9 100644 --- a/src/mainboard/google/hatch/variants/helios/overridetree.cb +++ b/src/mainboard/google/hatch/variants/helios/overridetree.cb @@ -96,7 +96,7 @@ register "name" = ""PENH"" register "gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A8)" register "key.wake" = "GPE0_DW0_08" - register "key.wakeup_event_action" = "EV_ACT_ASSERTED" + register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" register "key.dev_name" = ""EJCT"" register "key.linux_code" = "SW_PEN_INSERTED" register "key.linux_input_type" = "EV_SW" diff --git a/src/mainboard/google/hatch/variants/kindred/overridetree.cb b/src/mainboard/google/hatch/variants/kindred/overridetree.cb index 562bb8b..3846b60 100644 --- a/src/mainboard/google/hatch/variants/kindred/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kindred/overridetree.cb @@ -88,7 +88,7 @@ register "name" = ""PENH"" register "gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A8)" register "key.wake" = "GPE0_DW0_08" - register "key.wakeup_event_action" = "EV_ACT_ASSERTED" + register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" register "key.dev_name" = ""EJCT"" register "key.linux_code" = "SW_PEN_INSERTED" register "key.linux_input_type" = "EV_SW" -- To view, visit https://review.coreboot.org/c/coreboot/+/33427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0816ed9fb23cf00fd8e40bcdd25ff7a9f48badbd Gerrit-Change-Number: 33427 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mainboard/google/hatch: Update Helios device tree
by Tim Wawrzynczak (Code Review) 14 Jun '19

14 Jun '19

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33050 Change subject: mainboard/google/hatch: Update Helios device tree ...................................................................... mainboard/google/hatch: Update Helios device tree Update Helios device tree override to match schematics. BUG=b:133182138 BRANCH=none TEST=Compiles Change-Id: I3d15fc43651a289d16ffb3cfadaea8f786e858fc Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/hatch/variants/helios/overridetree.cb 1 file changed, 88 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/33050/1 diff --git a/src/mainboard/google/hatch/variants/helios/overridetree.cb b/src/mainboard/google/hatch/variants/helios/overridetree.cb index 84f0e29..4fecab3 100644 --- a/src/mainboard/google/hatch/variants/helios/overridetree.cb +++ b/src/mainboard/google/hatch/variants/helios/overridetree.cb @@ -14,6 +14,9 @@ [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" + # No PCIe WiFi + register "PcieRpEnable[13]" = "0" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | @@ -42,5 +45,89 @@ }, }" - device domain 0 on end + device domain 0 on + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + # No Type-A port + device usb 2.2 off end + end + chip drivers/usb/acpi + # No Type-A Port + device usb 2.3 off end + end + chip drivers/usb/acpi + # No WWAN + device usb 2.5 off end + end + chip drivers/usb/acpi + # No WWAN + device usb 3.4 off end + end + end + end + end + + # Native SD Card interface unused + device pci 14.5 off end + + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A20_IRQ)" + register "wake" = "GPE0_DW0_21" + device i2c 15 on end + end + end + + device pci 15.1 on + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "generic.reset_delay_ms" = "10" + register "generic.reset_off_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 5d on end + end + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + register "gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A8)" + register "key.wake" = "GPE0_DW0_08" + register "key.wakeup_event_action" = "EV_ACT_ASSERTED" + register "key.dev_name" = ""EJCT"" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + device generic 0 on end + end + end # I2C 1 + + # I2C #2 unused + device pci 15.2 off end + + # I2C #3 unused + device pci 15.3 off end + + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" + register "property_count" = "1" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end #I2C #4 + end end -- To view, visit https://review.coreboot.org/c/coreboot/+/33050 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d15fc43651a289d16ffb3cfadaea8f786e858fc Gerrit-Change-Number: 33050 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/asrock/h110m: Unselect incorrect Kconfig symbol
by Maxim Polyakov (Code Review) 14 Jun '19

14 Jun '19

Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33439 ) Change subject: mb/asrock/h110m: Unselect incorrect Kconfig symbol ...................................................................... Patch Set 1: Code-Review+1 I'm sorry for the delay. I have some problems with my gerrit account. I think that it was a mistake to add this symbol to the configuration. It was taken from the configuration with the board with nct6776. The patch is correct, however, it will be better if I check this patch on real hardware. I will do it soon. Thanks -- To view, visit https://review.coreboot.org/c/coreboot/+/33439 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f3fde161844f919b070f2b6ce7e106411439a9a Gerrit-Change-Number: 33439 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Maxim Polyakov <m.poliakov(a)yahoo.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 14 Jun 2019 09:53:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: doc/mb/upsquared: Add documentation
by Patrick Rudolph (Code Review) 14 Jun '19

14 Jun '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32935 ) Change subject: doc/mb/upsquared: Add documentation ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/32935 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic708ddbd2616eee4e5ec2740b3eac18b408bde38 Gerrit-Change-Number: 32935 Gerrit-PatchSet: 8 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 14 Jun 2019 07:12:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: sdm845: Add UART support
by Akash Asthana (Code Review) 14 Jun '19

14 Jun '19

Akash Asthana has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25373 ) Change subject: sdm845: Add UART support ...................................................................... Patch Set 74: (8 comments) https://review.coreboot.org/#/c/25373/64/src/mainboard/google/cheza/Kconfig File src/mainboard/google/cheza/Kconfig: https://review.coreboot.org/#/c/25373/64/src/mainboard/google/cheza/Kconfig… PS64, Line 24: default 0x00A84000 > Since this is used by the SoC code it should also be defined in sdm845/Kconfig, so that this definit […] Done https://review.coreboot.org/#/c/25373/64/src/soc/qualcomm/sdm845/uart.c File src/soc/qualcomm/sdm845/uart.c: https://review.coreboot.org/#/c/25373/64/src/soc/qualcomm/sdm845/uart.c@120 PS64, Line 120: GENI_FW_REVISION_RO_REG > This is still not using a struct overlay. […] Done https://review.coreboot.org/#/c/25373/64/src/soc/qualcomm/sdm845/uart.c@128 PS64, Line 128: * we are discussing with clock team */ > How is this coming along? Ideally you should be using get_uart_baudrate() and approximate the clock […] Done https://review.coreboot.org/#/c/25373/64/src/soc/qualcomm/sdm845/uart.c@134 PS64, Line 134: write32((void *)0x00118148, 0x1); /* Update the clock */ > These are all GCC registers, right? This driver shouldn't update them itself. […] Done, We removed this part of code instead we are using clock APIs to configure the clock. https://review.coreboot.org/#/c/25373/64/src/soc/qualcomm/sdm845/uart.c@142 PS64, Line 142: gpio_configure(GPIO(5), 1, GPIO_PULL_UP, GPIO_2MA, GPIO_INPUT); > This needs to be dependent on the QUP you're actually using... […] Done https://review.coreboot.org/#/c/25373/64/src/soc/qualcomm/sdm845/uart.c@147 PS64, Line 147: * configuration > Can we put this check at the top of this function? Presumably, if the previous stage has set up this […] Done https://review.coreboot.org/#/c/25373/64/src/soc/qualcomm/sdm845/uart.c@213 PS64, Line 213: if (uart_initialized == false) { > This should be unnecessary. […] Done https://review.coreboot.org/#/c/25373/64/src/soc/qualcomm/sdm845/uart.c@245 PS64, Line 245: } > There's no need for all these wrapper functions. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/25373 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I827906e820bc15b7f60fdd7876a54c9ed36a48a1 Gerrit-Change-Number: 25373 Gerrit-PatchSet: 74 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mukesh Savaliya <msavaliy(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Akash Asthana <akashast(a)qualcomm.corp-partner.google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Fri, 14 Jun 2019 04:58:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/hatch/variants/helios: Use LPDDR3 memory
by Paul Fagerburg (Code Review) 14 Jun '19

14 Jun '19

Paul Fagerburg has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33456 Change subject: mb/google/hatch/variants/helios: Use LPDDR3 memory ...................................................................... mb/google/hatch/variants/helios: Use LPDDR3 memory Change the SPD makefile to use the LPDDR3 SPDs. Set up the arrays for mapping SoC DQS pins to LPDDR3 pins. BRANCH=none BUG=b:133455595 TEST=`FEATURES="noclean" FW_NAME="helios" emerge-hatch chromeos-ec depthcharge vboot_reference libpayload coreboot-private-files intel-cmlfsp coreboot-private-files-hatch coreboot chromeos-bootimage` Ensure the firmware builds without error. Change-Id: Iebaba2ec65dfcf36674b4733b421ada107b22b09 Signed-off-by: Paul Fagerburg <pfagerburg(a)chromium.org> --- M src/mainboard/google/hatch/variants/helios/Makefile.inc A src/mainboard/google/hatch/variants/helios/memory.c 2 files changed, 73 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/33456/1 diff --git a/src/mainboard/google/hatch/variants/helios/Makefile.inc b/src/mainboard/google/hatch/variants/helios/Makefile.inc index cf6ee5a..b2a4095 100644 --- a/src/mainboard/google/hatch/variants/helios/Makefile.inc +++ b/src/mainboard/google/hatch/variants/helios/Makefile.inc @@ -12,9 +12,8 @@ ## GNU General Public License for more details. ## -SPD_SOURCES = 4G_2400 # 0b000 -SPD_SOURCES += empty_ddr4 # 0b001 -SPD_SOURCES += 8G_2400 # 0b010 -SPD_SOURCES += 8G_2666 # 0b011 -SPD_SOURCES += 16G_2400 # 0b100 -SPD_SOURCES += 16G_2666 # 0b101 +SPD_SOURCES = LP_8G_2133 # 0b0000 +SPD_SOURCES += empty_ddr4 # 0b0001 +SPD_SOURCES += LP_16G_2133 # 0b0010 + +romstage-y += memory.c diff --git a/src/mainboard/google/hatch/variants/helios/memory.c b/src/mainboard/google/hatch/variants/helios/memory.c new file mode 100644 index 0000000..64b4cac --- /dev/null +++ b/src/mainboard/google/hatch/variants/helios/memory.c @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> +#include <baseboard/gpio.h> +#include <soc/cnl_memcfg_init.h> +#include <string.h> + +static const struct cnl_mb_cfg baseboard_memcfg = { + /* + * The dqs_map arrays map the SoC pins to the lpddr3 pins + * for both channels. + * + * "The index of the array is CPU byte number, the values are DRAM byte + * numbers." - doc #573387 + * + * the index = pin number on SoC + * the value = pin number on lpddr3 part + */ + .dqs_map[DDR_CH0] = {4, 7, 5, 6, 0, 3, 2, 1}, + .dqs_map[DDR_CH1] = {0, 3, 2, 1, 4, 7, 6, 5}, + + .dq_map[DDR_CH0] = { + {0xf0, 0xf}, + {0x0, 0xf}, + {0xf0, 0xf}, + {0xf0, 0x0}, + {0xff, 0x0}, + {0xff, 0x0} + }, + .dq_map[DDR_CH1] = { + {0xf, 0xf0}, + {0x0, 0xf0}, + {0xf, 0xf0}, + {0xf, 0x0}, + {0xff, 0x0}, + {0xff, 0x0} + }, + + /* Helios uses 200, 80.6 and 162 rcomp resistors */ + .rcomp_resistor = {200, 81, 162}, + + /* Helios Rcomp target values */ + .rcomp_targets = {100, 40, 40, 23, 40}, + + /* Set CaVref config to 0 for LPDDR3 */ + .vref_ca_config = 0, + + /* Disable Early Command Training */ + .ect = 0, +}; + +void variant_memory_params(struct cnl_mb_cfg *bcfg) +{ + memcpy(bcfg, &baseboard_memcfg, sizeof(baseboard_memcfg)); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/33456 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebaba2ec65dfcf36674b4733b421ada107b22b09 Gerrit-Change-Number: 33456 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-MessageType: newchange

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coreboot-gerrit June 2019