coreboot-gerrit June 2019

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Change in ...coreboot[master]: mb/google/octopus/variants/bloog: Set tcc offset for bloog
by Tony Huang (Code Review) 15 Jun '19

15 Jun '19

Tony Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33461 Change subject: mb/google/octopus/variants/bloog: Set tcc offset for bloog ...................................................................... mb/google/octopus/variants/bloog: Set tcc offset for bloog Change tcc offset from 0 to 10 degree celsius for bloog. BUG=b:135225497 BRANCH=octopus TEST=Build and verify test result by thermal team. Change-Id: I4cbff846914a776c67692005f8b40cd73cfaf231 Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/octopus/variants/bloog/overridetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/33461/1 diff --git a/src/mainboard/google/octopus/variants/bloog/overridetree.cb b/src/mainboard/google/octopus/variants/bloog/overridetree.cb index cf70bb3..6c64ba7 100644 --- a/src/mainboard/google/octopus/variants/bloog/overridetree.cb +++ b/src/mainboard/google/octopus/variants/bloog/overridetree.cb @@ -53,6 +53,9 @@ #| I2C6 | Trackpad | #| I2C7 | Touchscreen | #+-------------------+---------------------------+ + + register "tcc_offset" = "10" + register "common_soc_config" = "{ .gspi[0] = { .speed_mhz = 1, -- To view, visit https://review.coreboot.org/c/coreboot/+/33461 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4cbff846914a776c67692005f8b40cd73cfaf231 Gerrit-Change-Number: 33461 Gerrit-PatchSet: 1 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

4 6

Change in ...coreboot[master]: mainboard/google/hatch: Scrub Helios GPIOs
by Tim Wawrzynczak (Code Review) 15 Jun '19

15 Jun '19

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33485 Change subject: mainboard/google/hatch: Scrub Helios GPIOs ...................................................................... mainboard/google/hatch: Scrub Helios GPIOs Helios has a number of GPIO changes w/r/t to its baseboard. Override early, sleep and normal GPIOs as appropriate. BUG=b:135257452 BRANCH=none TEST=Compile only (no boards to test with) Change-Id: I45793ad6515df5af5b925d92106bd943374353d4 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/hatch/variants/helios/Makefile.inc A src/mainboard/google/hatch/variants/helios/gpio.c 2 files changed, 131 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/33485/1 diff --git a/src/mainboard/google/hatch/variants/helios/Makefile.inc b/src/mainboard/google/hatch/variants/helios/Makefile.inc index cf6ee5a..2f590bf 100644 --- a/src/mainboard/google/hatch/variants/helios/Makefile.inc +++ b/src/mainboard/google/hatch/variants/helios/Makefile.inc @@ -18,3 +18,6 @@ SPD_SOURCES += 8G_2666 # 0b011 SPD_SOURCES += 16G_2400 # 0b100 SPD_SOURCES += 16G_2666 # 0b101 + +bootblock-y += gpio.c +ramstage-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/helios/gpio.c b/src/mainboard/google/hatch/variants/helios/gpio.c new file mode 100644 index 0000000..9f39044 --- /dev/null +++ b/src/mainboard/google/hatch/variants/helios/gpio.c @@ -0,0 +1,128 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +static const struct pad_config gpio_table[] = { + /* H4 : I2C2_SDA ==> NC */ + PAD_NC(GPP_H4, NONE), + /* H5 : I2C2_SCL ==> NC */ + PAD_NC(GPP_H5, NONE), + /* H22 : MEM_STRAP_1 */ + PAD_CFG_GPI(GPP_H22, NONE, PLTRST), + /* H19 : TIMESYNC[0] ==> MEM_STRAP_0 */ + PAD_CFG_GPI(GPP_H19, NONE, PLTRST), + /* H14 : M2_SKT2_CFG2 ==> TOUCHSCREEN_STOP_L */ + PAD_CFG_TERM_GPO(GPP_H14, 1, UP_20K, PLTRST), + /* H13 : M2_SKT2_CFG1 ==> SPKR_RST_L */ + PAD_CFG_TERM_GPO(GPP_H13, 1, UP_20K, PLTRST), + /* G0 : GPP_G0 ==> NC */ + PAD_NC(GPP_G0, NONE), + /* G1 : GPP_G1 ==> NC */ + PAD_NC(GPP_G1, NONE), + /* G2 : GPP_G2 ==> NC */ + PAD_NC(GPP_G2, NONE), + /* G3 : GPP_G3 ==> NC */ + PAD_NC(GPP_G3, NONE), + /* G4 : GPP_G4 ==> NC */ + PAD_NC(GPP_G4, NONE), + /* G5 : GPP_G5 ==> NC */ + PAD_NC(GPP_G5, NONE), + /* G6 : GPP_G6 ==> NC */ + PAD_NC(GPP_G6, NONE), + /* F3 : GPP_F3 ==> MEM_STRAP_3 */ + PAD_CFG_GPI(GPP_F3, NONE, PLTRST), + /* F22 : EMMC_RESET# ==> NC */ + PAD_NC(GPP_F22, NONE), + /* F21 : EMMC_CLK ==> NC */ + PAD_NC(GPP_F21, NONE), + /* F20 : EMMC_RCLK ==> NC */ + PAD_NC(GPP_F20, NONE), + /* F11 : EMMC_CMD ==> NC */ + PAD_NC(GPP_F11, NONE), + /* F10 : GPP_F10 ==> MEM_STRAP_2 */ + PAD_CFG_GPI(GPP_F10, NONE, PLTRST), + /* F1 : GPP_F1 ==> NC */ + PAD_NC(GPP_F1, NONE), + /* F0 : GPP_F0 ==> NC */ + PAD_NC(GPP_F0, NONE), + /* D8 : ISH_I2C1_SCL ==> NC */ + PAD_NC(GPP_D8, NONE), + /* D7 : ISH_I2C1_SDA ==> NC */ + PAD_NC(GPP_D7, NONE), + /* D6 : ISH_I2C0_SCL ==> NC */ + PAD_NC(GPP_D6, NONE), + /* D5 : ISH_I2C0_SDA ==> NC */ + PAD_NC(GPP_D5, NONE), + /* D21 : SPI1_IO2 ==> NC */ + PAD_NC(GPP_D21, NONE), + /* D10 : ISH_SPI_CLK ==> EN_PP3300_PP1800_FP */ + PAD_CFG_TERM_GPO(GPP_D10, 0, DN_20K, DEEP), + /* C7 : GPP_C7 ==> NC */ + PAD_NC(GPP_C7, NONE), + /* C6 : GPP_C6 ==> NC */ + PAD_NC(GPP_C6, NONE), + /* C23 : UART2_CTS# ==> NC */ + PAD_NC(GPP_C23, NONE), + /* C15 : UART1_CTS# ==> NC */ + PAD_NC(GPP_C15, NONE), + /* C1 : SMBDATA ==> NC */ + PAD_NC(GPP_C1, NONE), + /* B19 : GSPI1_CS0# ==> NC */ + PAD_NC(GPP_B19, NONE), + /* A6 : SERIRQ ==> NC */ + PAD_NC(GPP_A6, NONE), + /* A20 : ISH_GP2 ==> NC */ + PAD_NC(GPP_A20, NONE), + /* A19 : ISH_GP1 ==> NC */ + PAD_NC(GPP_A19, NONE), + /* A18 : ISH_GP0 ==> NC */ + PAD_NC(GPP_A18, NONE), + /* A0 : RCIN# ==> NC */ + PAD_NC(GPP_A0, NONE), +}; + +const struct pad_config *override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +/* GPIOs configured before ramstage */ +static const struct pad_config early_gpio_table[] = { + PAD_NC(GPP_C23, NONE), +}; + +const struct pad_config *override_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +/* + * GPIO settings before entering all sleep states + */ +static const struct pad_config sleep_gpio_table[] = { + PAD_CFG_GPO(GPP_A12, 1, DEEP), /* FPMCU_RST_ODL */ +}; + +const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num) +{ + *num = ARRAY_SIZE(sleep_gpio_table); + return sleep_gpio_table; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/33485 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45793ad6515df5af5b925d92106bd943374353d4 Gerrit-Change-Number: 33485 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

3 11

Change in ...coreboot[master]: security: Add memory subfolder
by Nico Huber (Code Review) 14 Jun '19

14 Jun '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31548 ) Change subject: security: Add memory subfolder ...................................................................... Patch Set 11: (12 comments) https://review.coreboot.org/#/c/31548/3//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/31548/3//COMMIT_MSG@17 PS3, Line 17: TEE > explained Ack https://review.coreboot.org/#/c/31548/5/Documentation/security/memory_clear… File Documentation/security/memory_clearing.md: https://review.coreboot.org/#/c/31548/5/Documentation/security/memory_clear… PS5, Line 14: bringup > bring-up? Ack https://review.coreboot.org/#/c/31548/5/Documentation/security/memory_clear… PS5, Line 15: SoC > device? Ack https://review.coreboot.org/#/c/31548/5/Documentation/security/memory_clear… PS5, Line 26: platforms > singular Ack https://review.coreboot.org/#/c/31548/5/Documentation/security/memory_clear… PS5, Line 27: call > calls Ack https://review.coreboot.org/#/c/31548/3/src/security/memory/Kconfig File src/security/memory/Kconfig: https://review.coreboot.org/#/c/31548/3/src/security/memory/Kconfig@16 PS3, Line 16: initilization > Done Ack https://review.coreboot.org/#/c/31548/3/src/security/memory/Kconfig@23 PS3, Line 23: (as part of FSP or coreboot). > Done Ack https://review.coreboot.org/#/c/31548/3/src/security/memory/Kconfig@34 PS3, Line 34: endmenu #Memory initilization > Done Ack https://review.coreboot.org/#/c/31548/3/src/security/memory/memory.h File src/security/memory/memory.h: https://review.coreboot.org/#/c/31548/3/src/security/memory/memory.h@17 PS3, Line 17: #include <stddef.h> > Done Kind of. https://review.coreboot.org/#/c/31548/5/src/security/memory/memory.c File src/security/memory/memory.c: https://review.coreboot.org/#/c/31548/5/src/security/memory/memory.c@28 PS5, Line 28: return 1; : : /* TODO: Add TEE environments here */ : : return 0; > Use `true` and `false` as the type is `bool`? The macros are defined in `stdint.h`. Done https://review.coreboot.org/#/c/31548/8/src/security/memory/memory.c File src/security/memory/memory.c: https://review.coreboot.org/#/c/31548/8/src/security/memory/memory.c@27 PS8, Line 27: IS_ENABLED(CONFIG_ > CONFIG( Done https://review.coreboot.org/#/c/31548/10/src/security/memory/memory.c File src/security/memory/memory.c: https://review.coreboot.org/#/c/31548/10/src/security/memory/memory.c@17 PS10, Line 17: #include <stdint.h> > Needless include `true` and `false` are used here, and indirect includes are discouraged. (that those are defined in the wrong header file is out of scope of this change) -- To view, visit https://review.coreboot.org/c/coreboot/+/31548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifba25bfdd1057049f5cbae8968501bd9be487110 Gerrit-Change-Number: 31548 Gerrit-PatchSet: 11 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Roy Wen <rgzwen(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alex Thiessen <alex.thiessen.de+coreboot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 14 Jun 2019 21:10:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Alex Thiessen <alex.thiessen.de+coreboot(a)gmail.com> Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Comment-In-Reply-To: build bot (Jenkins) <no-reply(a)coreboot.org> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: mb/google/{sarien,arcada} Fix SSD's power off sequence before going t...
by Bora Guvendik (Code Review) 14 Jun '19

14 Jun '19

Bora Guvendik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33410 Change subject: mb/google/{sarien,arcada} Fix SSD's power off sequence before going to S5 ...................................................................... mb/google/{sarien,arcada} Fix SSD's power off sequence before going to S5 BUG=b:133389422 TEST=check SSD's power off sequence to meet PCIE requirement. SSD's reset should be cleared before clearing SSD's power EN Pin. Change-Id: I5697350b2e23d4dfb0e546d95e089c91cd0070c6 Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- M src/mainboard/google/sarien/smihandler.c M src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl M src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl 3 files changed, 14 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/33410/1 diff --git a/src/mainboard/google/sarien/smihandler.c b/src/mainboard/google/sarien/smihandler.c index 0efcaa9..aaa925c 100644 --- a/src/mainboard/google/sarien/smihandler.c +++ b/src/mainboard/google/sarien/smihandler.c @@ -13,10 +13,23 @@ * GNU General Public License for more details. */ +#include <arch/acpi.h> #include <cpu/x86/smm.h> +#include <delay.h> #include <ec/google/wilco/smm.h> +#include <gpio.h> #include <soc/smm.h> #include <variant/ec.h> +#include <variant/gpio.h> + +static void mainboard_gpio_smi_sleep(u8 slp_typ) +{ + if (slp_typ == ACPI_S5) { + gpio_set(GPIO_SSD_RESET, 0); + mdelay(1); + gpio_set(GPIO_SSD_POWER, 0); + } +} void mainboard_smi_espi_handler(void) { @@ -25,6 +38,7 @@ void mainboard_smi_sleep(u8 slp_typ) { + mainboard_gpio_smi_sleep(slp_typ); wilco_ec_smi_sleep(slp_typ); } diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl index 4b05ba8..41121d2 100644 --- a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl @@ -15,8 +15,6 @@ #define CAM_EN GPP_B11 /* Active low */ #define TS_PD GPP_E7 -#define SSD_EN GPP_H13 -#define SSD_RST GPP_H12 /* Method called from LPIT prior to enter s0ix state */ Method (MS0X, 1) @@ -37,13 +35,6 @@ /* Clear touch screen pd pin to avoid leakage */ \_SB.PCI0.CTXS (TS_PD) - - /* Clear SSD EN adn RST pin to avoid leakage */ - If (Arg0 == 5) { - \_SB.PCI0.CTXS (SSD_RST) - Sleep(1) - \_SB.PCI0.CTXS (SSD_EN) - } } /* Method called from _WAK prior to wakeup */ diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl index 4b05ba8..41121d2 100644 --- a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl @@ -15,8 +15,6 @@ #define CAM_EN GPP_B11 /* Active low */ #define TS_PD GPP_E7 -#define SSD_EN GPP_H13 -#define SSD_RST GPP_H12 /* Method called from LPIT prior to enter s0ix state */ Method (MS0X, 1) @@ -37,13 +35,6 @@ /* Clear touch screen pd pin to avoid leakage */ \_SB.PCI0.CTXS (TS_PD) - - /* Clear SSD EN adn RST pin to avoid leakage */ - If (Arg0 == 5) { - \_SB.PCI0.CTXS (SSD_RST) - Sleep(1) - \_SB.PCI0.CTXS (SSD_EN) - } } /* Method called from _WAK prior to wakeup */ -- To view, visit https://review.coreboot.org/c/coreboot/+/33410 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5697350b2e23d4dfb0e546d95e089c91cd0070c6 Gerrit-Change-Number: 33410 Gerrit-PatchSet: 1 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-MessageType: newchange

1 1

Change in ...coreboot[master]: [WIP] mb/google/{sarien, arcada} Fix for SSD can't be detected issue
by Bora Guvendik (Code Review) 14 Jun '19

14 Jun '19

Bora Guvendik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33382 Change subject: [WIP] mb/google/{sarien, arcada} Fix for SSD can't be detected issue ...................................................................... [WIP] mb/google/{sarien, arcada} Fix for SSD can't be detected issue In order to fix,SSD can't be detected during cold-reset issue, add the required delays between powering the SSD and resetting it for cold and warm reboot cases. BUG=b:132393441 TEST=Boot to OS with cold-reset Change-Id: I03dabe1f75c761617c1129547342dff3047e101d Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- M src/mainboard/google/sarien/ramstage.c M src/mainboard/google/sarien/romstage.c M src/mainboard/google/sarien/variants/arcada/gpio.c M src/mainboard/google/sarien/variants/sarien/gpio.c 4 files changed, 30 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/33382/1 diff --git a/src/mainboard/google/sarien/ramstage.c b/src/mainboard/google/sarien/ramstage.c index 1d22046..2ca6dfb 100644 --- a/src/mainboard/google/sarien/ramstage.c +++ b/src/mainboard/google/sarien/ramstage.c @@ -14,7 +14,9 @@ */ #include <arch/acpi.h> +#include <bootstate.h> #include <drivers/vpd/vpd.h> +#include <gpio.h> #include <smbios.h> #include <soc/gpio.h> #include <soc/ramstage.h> @@ -77,3 +79,10 @@ struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; + +static void ssd_reset(void* unused) +{ + gpio_set(GPP_H12, 1); +} + +BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, ssd_reset, NULL); diff --git a/src/mainboard/google/sarien/romstage.c b/src/mainboard/google/sarien/romstage.c index 20eee7f..7b6c96f 100644 --- a/src/mainboard/google/sarien/romstage.c +++ b/src/mainboard/google/sarien/romstage.c @@ -13,9 +13,13 @@ * GNU General Public License for more details. */ +#include <delay.h> #include <ec/google/wilco/romstage.h> #include <soc/cnl_memcfg_init.h> +#include <soc/pm.h> #include <soc/romstage.h> +#include <intelblocks/pmclib.h> +#include <gpio.h> static const struct cnl_mb_cfg memcfg = { /* Access memory info through SMBUS. */ @@ -57,6 +61,19 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) { + struct chipset_power_state *ps = pmc_get_power_state(); + + if(ps) { + if (ps->gen_pmcon_a & (PWR_FLR | SUS_PWR_FLR)) { + gpio_set(GPP_H13, 0); + mdelay(75); + gpio_set(GPP_H13, 1); + } + else { + gpio_set(GPP_H12, 1); + } + } + wilco_ec_romstage_init(); cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); diff --git a/src/mainboard/google/sarien/variants/arcada/gpio.c b/src/mainboard/google/sarien/variants/arcada/gpio.c index ff0240c..a0d21b4 100644 --- a/src/mainboard/google/sarien/variants/arcada/gpio.c +++ b/src/mainboard/google/sarien/variants/arcada/gpio.c @@ -16,6 +16,7 @@ #include <variant/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> + /* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* RCIN# */ PAD_NC(GPP_A0, NONE), @@ -240,7 +241,6 @@ static const struct pad_config early_gpio_table[] = { /* M2_SKT2_CFG1 */ PAD_CFG_GPO(GPP_H13, 1, DEEP), /* M.2 SSD D3 cold */ /* SSD RESET pin will stay low first */ -/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 0, DEEP), /* D3 cold RST */ /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */ /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */ /* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA_H1 */ @@ -252,7 +252,7 @@ /* CPU_GP0 */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */ /* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */ /* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* PCH_WP */ -/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 1, DEEP), /* D3 cold RST */ +/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 0, DEEP), /* D3 cold RST */ }; const struct pad_config *variant_gpio_table(size_t *num) diff --git a/src/mainboard/google/sarien/variants/sarien/gpio.c b/src/mainboard/google/sarien/variants/sarien/gpio.c index 78db12e..80d68d4 100644 --- a/src/mainboard/google/sarien/variants/sarien/gpio.c +++ b/src/mainboard/google/sarien/variants/sarien/gpio.c @@ -229,7 +229,7 @@ /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */ /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */ /* SSD RESET pin will stay low first */ -/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 0, DEEP), /* D3 cold RST */ +/* M2_SKT2_CFG0 */ //PAD_CFG_GPO(GPP_H12, 0, DEEP), /* D3 cold RST */ /* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA_H1 */ /* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */ /* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, PLTRST, @@ -240,7 +240,7 @@ /* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */ /* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* H1_FLASH_WP */ /* PWRBTN# */ PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* SIO_PWRBTN# */ -/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 1, DEEP), /* D3 cold RST */ +/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 0, DEEP), /* D3 cold RST */ }; const struct pad_config *variant_gpio_table(size_t *num) -- To view, visit https://review.coreboot.org/c/coreboot/+/33382 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I03dabe1f75c761617c1129547342dff3047e101d Gerrit-Change-Number: 33382 Gerrit-PatchSet: 1 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-MessageType: newchange

3 17

Change in ...coreboot[master]: mb/google/poppy: Ensure SPD index is non-zero
by Jacob Garber (Code Review) 14 Jun '19

14 Jun '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33183 Change subject: mb/google/poppy: Ensure SPD index is non-zero ...................................................................... mb/google/poppy: Ensure SPD index is non-zero Memory id's are 1-indexed, so we need to check that the SPD index is non-zero before converting it to the 0-indexed value in the bitmap. Change-Id: Icc542239d91c39b89c23f31856c28e7c20b2fc4d Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> Found-by: Coverity CID 1387028 --- M src/mainboard/google/poppy/variants/nami/memory.c 1 file changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/33183/1 diff --git a/src/mainboard/google/poppy/variants/nami/memory.c b/src/mainboard/google/poppy/variants/nami/memory.c index b7f5185..b6e3d2c 100644 --- a/src/mainboard/google/poppy/variants/nami/memory.c +++ b/src/mainboard/google/poppy/variants/nami/memory.c @@ -66,8 +66,12 @@ p->type = MEMORY_DDR4; p->use_sec_spd = 0; + int spd_index = variant_memory_sku(); + if (spd_index == 0) + die("SPD index is 0\n"); + /* Rcomp resistor values are different for SDP and DDP. */ - if (ddp_bitmap & MEM_ID(variant_memory_sku())) { + if (ddp_bitmap & MEM_ID(spd_index)) { p->rcomp_resistor = rcomp_resistor_ddp; p->rcomp_resistor_size = sizeof(rcomp_resistor_ddp); } else { -- To view, visit https://review.coreboot.org/c/coreboot/+/33183 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc542239d91c39b89c23f31856c28e7c20b2fc4d Gerrit-Change-Number: 33183 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

4 9

Change in ...coreboot[master]: device/cpu_device.c: Use 'unsigned int' instead of 'unsigned'
by Martin Roth (Code Review) 14 Jun '19

14 Jun '19

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/33329 ) Change subject: device/cpu_device.c: Use 'unsigned int' instead of 'unsigned' ...................................................................... device/cpu_device.c: Use 'unsigned int' instead of 'unsigned' Change-Id: I9f96d8c8e6cf2715e62ab3715da83740db8cce40 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33329 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Vlado Cibic --- M src/device/cpu_device.c 1 file changed, 4 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Vlado Cibic: Looks good to me, but someone else must approve diff --git a/src/device/cpu_device.c b/src/device/cpu_device.c index b07b555..f59cce3 100644 --- a/src/device/cpu_device.c +++ b/src/device/cpu_device.c @@ -17,7 +17,7 @@ #include <device/device.h> #include <console/console.h> -struct device *add_cpu_device(struct bus *cpu_bus, unsigned apic_id, +struct device *add_cpu_device(struct bus *cpu_bus, unsigned int apic_id, int enabled) { struct device_path cpu_path; @@ -42,8 +42,9 @@ return cpu; } -void set_cpu_topology(struct device *cpu, unsigned node, unsigned package, - unsigned core, unsigned thread) +void set_cpu_topology(struct device *cpu, unsigned int node, + unsigned int package, unsigned int core, + unsigned int thread) { cpu->path.apic.node_id = node; cpu->path.apic.package_id = package; -- To view, visit https://review.coreboot.org/c/coreboot/+/33329 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f96d8c8e6cf2715e62ab3715da83740db8cce40 Gerrit-Change-Number: 33329 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Vlado Cibic Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in ...libgfxinit[master]: gma pipe setup: Fix secondary pipe cursors <= Sandy Bridge
by Nico Huber (Code Review) 14 Jun '19

14 Jun '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/libgfxinit/+/27154 ) Change subject: gma pipe setup: Fix secondary pipe cursors <= Sandy Bridge ...................................................................... Patch Set 3: Registers are described in https://01.org/sites/default/files/documentation/snb_ihd_os_vol3_part2.pdf -- To view, visit https://review.coreboot.org/c/libgfxinit/+/27154 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I4d79f59a8cb693d73d6da666525f091021efb4fd Gerrit-Change-Number: 27154 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Adrian-Ken Rueegsegger <ken(a)codelabs.ch> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Reto Buerki <reet(a)codelabs.ch> Gerrit-Comment-Date: Fri, 14 Jun 2019 18:15:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: libpayload/i8042/keyboard: Log errors during initialization
by Paul Menzel (Code Review) 14 Jun '19

14 Jun '19

Hello Furquan Shaikh, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/33446 to review the following change. Change subject: libpayload/i8042/keyboard: Log errors during initialization ...................................................................... libpayload/i8042/keyboard: Log errors during initialization Add error messages for all failed commands in keyboard_init(). Change-Id: Ie42ccbc4d850912c83e00376b27f192d5b652057 Signed-off-by: Furquan Shaikh <furquan(a)google.com> Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M payloads/libpayload/drivers/i8042/keyboard.c 1 file changed, 12 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/33446/1 diff --git a/payloads/libpayload/drivers/i8042/keyboard.c b/payloads/libpayload/drivers/i8042/keyboard.c index 3e5f988..48d35a0 100644 --- a/payloads/libpayload/drivers/i8042/keyboard.c +++ b/payloads/libpayload/drivers/i8042/keyboard.c @@ -319,25 +319,33 @@ /* Set scancode set 1 */ ret = keyboard_cmd(I8042_KBCMD_SET_SCANCODE); - if (!ret && !CONFIG(LP_PC_KEYBOARD_IGNORE_INIT_FAILURE)) + if (!ret && !CONFIG(LP_PC_KEYBOARD_IGNORE_INIT_FAILURE)) { + printf("ERROR: Keyboard set scancode failed!\n"); return; + } ret = keyboard_cmd(I8042_SCANCODE_SET_1); - if (!ret && !CONFIG(LP_PC_KEYBOARD_IGNORE_INIT_FAILURE)) + if (!ret && !CONFIG(LP_PC_KEYBOARD_IGNORE_INIT_FAILURE)) { + printf("ERROR: Keyboard scancode set#1 failed!\n"); return; + } /* * Set default parameters. * Fix for broken QEMU ps/2 make scancodes. */ ret = keyboard_cmd(0xf6); - if (!ret) + if (!ret) { + printf("ERROR: Keyboard set default params failed!\n"); return; + } /* Enable scanning */ ret = keyboard_cmd(I8042_KBCMD_EN); - if (!ret && !CONFIG(LP_PC_KEYBOARD_IGNORE_INIT_FAILURE)) + if (!ret && !CONFIG(LP_PC_KEYBOARD_IGNORE_INIT_FAILURE)) { + printf("ERROR: Keyboard enable scanning failed!\n"); return; + } console_add_input_driver(&cons); } -- To view, visit https://review.coreboot.org/c/coreboot/+/33446 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie42ccbc4d850912c83e00376b27f192d5b652057 Gerrit-Change-Number: 33446 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

2 2

Change in ...coreboot[master]: mb/{i945}: Move CHANNEL_XOR_RANDOMIZATION selection to northbridge
by HAOUAS Elyes (Code Review) 14 Jun '19

14 Jun '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32928 Change subject: mb/{i945}: Move CHANNEL_XOR_RANDOMIZATION selection to northbridge ...................................................................... mb/{i945}: Move CHANNEL_XOR_RANDOMIZATION selection to northbridge Change-Id: I31e6ed6cb040dcba756cbfd2247d90753d372915 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/apple/macbook21/Kconfig M src/mainboard/asus/p5gc-mx/Kconfig M src/mainboard/getac/p470/Kconfig M src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig M src/mainboard/ibase/mb899/Kconfig M src/mainboard/intel/d945gclf/Kconfig M src/mainboard/kontron/986lcd-m/Kconfig M src/mainboard/lenovo/t60/Kconfig M src/mainboard/lenovo/x60/Kconfig M src/mainboard/lenovo/z61t/Kconfig M src/mainboard/roda/rk886ex/Kconfig M src/northbridge/intel/i945/Kconfig 12 files changed, 1 insertion(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/32928/1 diff --git a/src/mainboard/apple/macbook21/Kconfig b/src/mainboard/apple/macbook21/Kconfig index 6535f8f..84c00cf 100644 --- a/src/mainboard/apple/macbook21/Kconfig +++ b/src/mainboard/apple/macbook21/Kconfig @@ -13,7 +13,6 @@ select HAVE_CMOS_DEFAULT select HAVE_MP_TABLE select BOARD_ROMSIZE_KB_2048 - select CHANNEL_XOR_RANDOMIZATION select INTEL_INT15 select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME diff --git a/src/mainboard/asus/p5gc-mx/Kconfig b/src/mainboard/asus/p5gc-mx/Kconfig index 21e57bb..193364a 100644 --- a/src/mainboard/asus/p5gc-mx/Kconfig +++ b/src/mainboard/asus/p5gc-mx/Kconfig @@ -29,7 +29,6 @@ select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME select BOARD_ROMSIZE_KB_512 - select CHANNEL_XOR_RANDOMIZATION select MAINBOARD_HAS_NATIVE_VGA_INIT select INTEL_GMA_HAVE_VBT diff --git a/src/mainboard/getac/p470/Kconfig b/src/mainboard/getac/p470/Kconfig index a5eed1a..9fe40bc 100644 --- a/src/mainboard/getac/p470/Kconfig +++ b/src/mainboard/getac/p470/Kconfig @@ -32,7 +32,6 @@ select HAVE_ACPI_RESUME select UDELAY_LAPIC select BOARD_ROMSIZE_KB_1024 - select CHANNEL_XOR_RANDOMIZATION select INTEL_INT15 select I945_LVDS diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig b/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig index ea3142a..e9ed54d 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig @@ -29,7 +29,6 @@ select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME select BOARD_ROMSIZE_KB_512 - select CHANNEL_XOR_RANDOMIZATION select MAINBOARD_HAS_NATIVE_VGA_INIT select REALTEK_8168_RESET if BOARD_GIGABYTE_GA_945GCM_S2L select INTEL_GMA_HAVE_VBT diff --git a/src/mainboard/ibase/mb899/Kconfig b/src/mainboard/ibase/mb899/Kconfig index 621395d..fcc2e38 100644 --- a/src/mainboard/ibase/mb899/Kconfig +++ b/src/mainboard/ibase/mb899/Kconfig @@ -14,7 +14,6 @@ select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME select BOARD_ROMSIZE_KB_512 - select CHANNEL_XOR_RANDOMIZATION select INTEL_INT15 config MAINBOARD_DIR diff --git a/src/mainboard/intel/d945gclf/Kconfig b/src/mainboard/intel/d945gclf/Kconfig index 70fa848..46d82ec 100644 --- a/src/mainboard/intel/d945gclf/Kconfig +++ b/src/mainboard/intel/d945gclf/Kconfig @@ -28,7 +28,6 @@ select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME select BOARD_ROMSIZE_KB_512 - select CHANNEL_XOR_RANDOMIZATION select MAINBOARD_HAS_NATIVE_VGA_INIT select INTEL_GMA_HAVE_VBT diff --git a/src/mainboard/kontron/986lcd-m/Kconfig b/src/mainboard/kontron/986lcd-m/Kconfig index 43bdf14..9dadd55 100644 --- a/src/mainboard/kontron/986lcd-m/Kconfig +++ b/src/mainboard/kontron/986lcd-m/Kconfig @@ -14,7 +14,6 @@ select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME select BOARD_ROMSIZE_KB_1024 - select CHANNEL_XOR_RANDOMIZATION select INTEL_INT15 select OVERRIDE_CLOCK_DISABLE diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig index a6a88b3..e4e87c9 100644 --- a/src/mainboard/lenovo/t60/Kconfig +++ b/src/mainboard/lenovo/t60/Kconfig @@ -17,7 +17,6 @@ select INTEL_INT15 select HAVE_MP_TABLE select BOARD_ROMSIZE_KB_2048 - select CHANNEL_XOR_RANDOMIZATION select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME select H8_DOCK_EARLY_INIT diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index 6db7f11..e3aabf3 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -19,7 +19,6 @@ select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select BOARD_ROMSIZE_KB_2048 - select CHANNEL_XOR_RANDOMIZATION select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME select USE_OPTION_TABLE diff --git a/src/mainboard/lenovo/z61t/Kconfig b/src/mainboard/lenovo/z61t/Kconfig index a223077..de48d95 100644 --- a/src/mainboard/lenovo/z61t/Kconfig +++ b/src/mainboard/lenovo/z61t/Kconfig @@ -17,7 +17,6 @@ select INTEL_INT15 select HAVE_MP_TABLE select BOARD_ROMSIZE_KB_2048 - select CHANNEL_XOR_RANDOMIZATION select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME select H8_DOCK_EARLY_INIT diff --git a/src/mainboard/roda/rk886ex/Kconfig b/src/mainboard/roda/rk886ex/Kconfig index 821a9a1..9e97529 100644 --- a/src/mainboard/roda/rk886ex/Kconfig +++ b/src/mainboard/roda/rk886ex/Kconfig @@ -17,7 +17,6 @@ select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME select BOARD_ROMSIZE_KB_1024 - select CHANNEL_XOR_RANDOMIZATION select INTEL_INT15 config MAINBOARD_DIR diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index 2c21420..c004224 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -32,6 +32,7 @@ select SMM_TSEG select PARALLEL_MP select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM + select CHANNEL_XOR_RANDOMIZATION config NORTHBRIDGE_INTEL_SUBTYPE_I945GC def_bool n -- To view, visit https://review.coreboot.org/c/coreboot/+/32928 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31e6ed6cb040dcba756cbfd2247d90753d372915 Gerrit-Change-Number: 32928 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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