coreboot-gerrit June 2019

coreboot-gerrit@coreboot.org

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1454 discussions

Change in ...coreboot[master]: cbfstool: Add ifittool
by Philipp Deppenwiese (Code Review) 17 Jun '19

17 Jun '19

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31493 ) Change subject: cbfstool: Add ifittool ...................................................................... Patch Set 12: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/31493 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fe8cd70611d58823aca1147d5b830722ed72bd5 Gerrit-Change-Number: 31493 Gerrit-PatchSet: 12 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Amol N Sukerkar <amol.n.sukerkar(a)intel.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kai Michaelis <kai.michaelis(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Roy Wen <rgzwen(a)arista.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Mon, 17 Jun 2019 09:42:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: qcs405: memlayout: Make bootblock 64k aligned
by Patrick Georgi (Code Review) 17 Jun '19

17 Jun '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29969 ) Change subject: qcs405: memlayout: Make bootblock 64k aligned ...................................................................... Patch Set 27: (1 comment) https://review.coreboot.org/#/c/29969/21/src/soc/qualcomm/qcs405/include/so… File src/soc/qualcomm/qcs405/include/soc/memlayout.ld: https://review.coreboot.org/#/c/29969/21/src/soc/qualcomm/qcs405/include/so… PS21, Line 36: 0x8C3a000 > generally we tend to use lower case, but since everything else in this file is using upper case, ple […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/29969 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1599242bb5158477318867508c72dc14f1244b00 Gerrit-Change-Number: 29969 Gerrit-PatchSet: 27 Gerrit-Owner: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sricharan Ramabadhran <srichara(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Mon, 17 Jun 2019 09:41:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: comment

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Change in ...libgfxinit[master]: gma pipe setup: Fix secondary pipe cursors <= Sandy Bridge
by Reto Buerki (Code Review) 17 Jun '19

17 Jun '19

Reto Buerki has posted comments on this change. ( https://review.coreboot.org/c/libgfxinit/+/27154 ) Change subject: gma pipe setup: Fix secondary pipe cursors <= Sandy Bridge ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/#/c/27154/3/common/hw-gfx-gma.ads File common/hw-gfx-gma.ads: https://review.coreboot.org/#/c/27154/3/common/hw-gfx-gma.ads@141 PS3, Line 141: "Reading of Config_State depends on the platform configuration."); Just to be sure: And this configuration is only known at runtime right? -- To view, visit https://review.coreboot.org/c/libgfxinit/+/27154 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I4d79f59a8cb693d73d6da666525f091021efb4fd Gerrit-Change-Number: 27154 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Adrian-Ken Rueegsegger <ken(a)codelabs.ch> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Reto Buerki <reet(a)codelabs.ch> Gerrit-Comment-Date: Mon, 17 Jun 2019 09:30:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/asrock/h110m: Unselect incorrect Kconfig symbol
by Maxim Polyakov (Code Review) 17 Jun '19

17 Jun '19

Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33439 ) Change subject: mb/asrock/h110m: Unselect incorrect Kconfig symbol ...................................................................... Patch Set 1: > Patch Set 1: > > > Patch Set 1: > > > > > Unfortunately, the early console doesn`t work without SUPERIO_NUVOTON_NCT6776_COM_A symbol. > > > > I'd suggest adding the proper SUPERIO_NUVOTON_NCT6791_COM_A symbol to both the NCT6791 Kconfig (with guards like the follow-up patch to this one) and the early init code where it sets both uart pinmux bits to the right setting (and not only one like in the currently used code path). > > @Maxim, could you please try this on your board? The quickest way to test would be to change the code in nuvoton/common/early_serial.c: > > if (CONFIG(SUPERIO_NUVOTON_NCT6776_COM_A)) > /* Route GPIO8 pin group to COM A */ > pnp_write_config(dev, 0x2a, 0x40); > > Replace the '0x40' inside pnp_write_config(dev, 0x2a, 0x40) with a '0x00'. If it works, I'll add SUPERIO_NUVOTON_NCT6791_COM_A. I tested it on the board. Yes, it really works. It would be great if you added this. -- To view, visit https://review.coreboot.org/c/coreboot/+/33439 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f3fde161844f919b070f2b6ce7e106411439a9a Gerrit-Change-Number: 33439 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Maxim Polyakov <m.poliakov(a)yahoo.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 17 Jun 2019 09:04:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: src/mb/gigabyte/ga-h61m-s2pv: Correct devicetree
by Nico Huber (Code Review) 17 Jun '19

17 Jun '19

Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/33522 ) Change subject: src/mb/gigabyte/ga-h61m-s2pv: Correct devicetree ...................................................................... src/mb/gigabyte/ga-h61m-s2pv: Correct devicetree Subsystem IDs were missing and GPIO settings were wrong. Plus, the PCI bridge was erroneously enabled, this board uses an ITE IT8892E PCIe to PCI bridge instead. Tested, board still boots. Change-Id: Ieb9dd8c835bc3652e7a3a118feca5551196bb81b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33522 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb 1 file changed, 10 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, but someone else must approve Arthur Heymans: Looks good to me, approved diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb b/src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb index e382cbd..e4ec810 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb @@ -30,6 +30,7 @@ end register "pci_mmio_size" = "2048" device domain 0x0 on + subsystemid 0x1458 0x5000 inherit device pci 00.0 on end # Host bridge device pci 01.0 on end # PCIe Bridge for discrete graphics (PCIEX16) device pci 02.0 on end # Internal graphics VGA controller @@ -57,7 +58,7 @@ device pci 1c.6 off end # Unused PCIe Port device pci 1c.7 off end # Unused PCIe Port device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 on end # PCI bridge + device pci 1e.0 off end # PCI bridge device pci 1f.0 on # LPC bridge chip superio/ite/it8728f device pnp 2e.0 off end # Floppy, not routed. @@ -84,13 +85,15 @@ device pnp 2e.6 on # Mouse irq 0x70 = 12 end - device pnp 2e.7 off # GPIO - io 0x25 = 0x40 - io 0x27 = 0x10 - io 0x2c = 0x80 + device pnp 2e.7 on # GPIO + irq 0x25 = 0x40 + irq 0x27 = 0x10 + irq 0x2c = 0x80 + io 0x60 = 0x0000 io 0x62 = 0x0a00 - io 0xcb = 0x00 - io 0xf1 = 0x40 + io 0x64 = 0x0000 + irq 0xcb = 0x00 + irq 0xf1 = 0x40 end device pnp 2e.a off end # CIR, not routed. end -- To view, visit https://review.coreboot.org/c/coreboot/+/33522 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb9dd8c835bc3652e7a3a118feca5551196bb81b Gerrit-Change-Number: 33522 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: [NOTFORMERGE]3rdparty/blobs: Update submodulue
by Arthur Heymans (Code Review) 17 Jun '19

17 Jun '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33228 Change subject: [NOTFORMERGE]3rdparty/blobs: Update submodulue ...................................................................... [NOTFORMERGE]3rdparty/blobs: Update submodulue The sandybridge DACHE_RAM_BASE is relocated and allows for more flexible location of the stack. Change-Id: I17d240656575b69a24718d90e4f2d2b7339d05a7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M 3rdparty/blobs 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/33228/1 diff --git a/3rdparty/blobs b/3rdparty/blobs index ca6cfcd..62c370c 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit ca6cfcdbe1cdeb38c2622ee2e5236cc4657e3377 +Subproject commit 62c370c76a4dae72dffbb452e2b30bd911967290 -- To view, visit https://review.coreboot.org/c/coreboot/+/33228 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I17d240656575b69a24718d90e4f2d2b7339d05a7 Gerrit-Change-Number: 33228 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: qclib: Add qclib support with interface tables
by Nitheesh Sekar (Code Review) 17 Jun '19

17 Jun '19

Nitheesh Sekar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29967 ) Change subject: qclib: Add qclib support with interface tables ...................................................................... Patch Set 30: (6 comments) https://review.coreboot.org/#/c/29967/25/src/soc/qualcomm/qcs405/include/so… File src/soc/qualcomm/qcs405/include/soc/memlayout.ld: https://review.coreboot.org/#/c/29967/25/src/soc/qualcomm/qcs405/include/so… PS25, Line 43: 0x80000 > nit: prefer giving sizes in decimal (e.g. […] Done https://review.coreboot.org/#/c/29967/25/src/soc/qualcomm/qcs405/include/so… File src/soc/qualcomm/qcs405/include/soc/qclib.h: https://review.coreboot.org/#/c/29967/25/src/soc/qualcomm/qcs405/include/so… PS25, Line 19: void qclib_load_and_run(void); > Isn't this in some qualcomm/common header? This should be in some qualcomm/common header. Done https://review.coreboot.org/#/c/29967/25/src/soc/qualcomm/qcs405/mmu.c File src/soc/qualcomm/qcs405/mmu.c: https://review.coreboot.org/#/c/29967/25/src/soc/qualcomm/qcs405/mmu.c@31 PS25, Line 31: mmu_config_range((void *)0x80000000, 0x40000000, MA_MEM | MA_S | MA_RW); > You can't do this here. This runs in the bootblock before DRAM is initialized. […] Done https://review.coreboot.org/#/c/29967/25/src/soc/qualcomm/qcs405/mmu.c@39 PS25, Line 39: MA_MEM | MA_NS | MA_RW); > This seems to be the same line as above? Again, you don't need it, common code already does that. Done https://review.coreboot.org/#/c/29967/25/src/soc/qualcomm/qcs405/soc_blob_l… File src/soc/qualcomm/qcs405/soc_blob_load.c: https://review.coreboot.org/#/c/29967/25/src/soc/qualcomm/qcs405/soc_blob_l… PS25, Line 22: #define DCB_NAME "/dcb" > Strings should be inline for consistency with SDM845 code Done https://review.coreboot.org/#/c/29967/25/src/soc/qualcomm/qcs405/soc_blob_l… PS25, Line 29: printk(BIOS_INFO, "%s:qcs405\n", __func__); > Unnecessary Done -- To view, visit https://review.coreboot.org/c/coreboot/+/29967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I534af71163d034ea04420dda6a94ce31b08c8a07 Gerrit-Change-Number: 29967 Gerrit-PatchSet: 30 Gerrit-Owner: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sricharan Ramabadhran <srichara(a)qualcomm.corp-partner.google.com> Gerrit-CC: mturney mturney <mturney(a)codeaurora.org> Gerrit-Comment-Date: Mon, 17 Jun 2019 07:07:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/gigabyte/ga-h61ma-d3v: Add new mainboard as variant
by Angel Pons (Code Review) 16 Jun '19

16 Jun '19

Hello Arthur Heymans, Paul Menzel, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/31832 to look at the new patch set (#8). Change subject: mb/gigabyte/ga-h61ma-d3v: Add new mainboard as variant ...................................................................... mb/gigabyte/ga-h61ma-d3v: Add new mainboard as variant Tested with SeaBIOS as a payload, booting Arch Linux with a Linux kernel. The new code is based on autoport and the existing GA-H61M-S2PV code. The GA-H61M-S2PV has been boot-tested too, it still boots. Working: - S3 suspend/resume - USB ports and headers (Intel USB2 and EtronTech USB3) - Gigabit Ethernet - Integrated DVI/VGA graphics (libgfxinit) - PCIe x16 graphics - PCIe x1 ports - PS/2 port with a keyboard - SATA controllers (Intel SATA2 and Marvell SATA3) - User-space fan control (fancontrol on Linux) - Native raminit (4+4GB DDR3-1333) - flashrom, using the internal programmer. Tested with coreboot, as well as with the vendor firmware. Backup chip is untested. Untested: - VGA BIOS for integrated graphics init - Audio: Only front/read outputs has been tested. - Non-Linux OSes - ACPI thermal zone and OS-independent fan control Not working: - Default IFD defines the BIOS region as the entire flash chip. Using 'flashrom --ifd -i bios' is asking for a failed flash! Change-Id: I37928de158bb8fbb47fbda5d1ccd4efba7edab26 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig M src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig.name M src/mainboard/gigabyte/ga-h61m-s2pv/Makefile.inc M src/mainboard/gigabyte/ga-h61m-s2pv/hda_verb.c M src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c R src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/devicetree.cb R src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/gpio.c A src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/hda_verb.c A src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/devicetree.cb A src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/gpio.c A src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/hda_verb.c 11 files changed, 425 insertions(+), 80 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/31832/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/31832 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37928de158bb8fbb47fbda5d1ccd4efba7edab26 Gerrit-Change-Number: 31832 Gerrit-PatchSet: 8 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: mb/gigabyte/ga-h61ma-d3v: Add new mainboard as variant
by Angel Pons (Code Review) 16 Jun '19

16 Jun '19

Hello Arthur Heymans, Paul Menzel, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/31832 to look at the new patch set (#7). Change subject: mb/gigabyte/ga-h61ma-d3v: Add new mainboard as variant ...................................................................... mb/gigabyte/ga-h61ma-d3v: Add new mainboard as variant Tested with SeaBIOS as a payload, booting Arch Linux with a Linux kernel. The new code is based on autoport and the existing GA-H61M-S2PV code. The GA-H61M-S2PV has been boot-tested too, it still boots. Working: - S3 suspend/resume - USB ports and headers (Intel USB2 and EtronTech USB3) - Gigabit Ethernet - Integrated DVI/VGA graphics (libgfxinit) - PCIe x16 graphics - PCIe x1 ports - PS/2 port with a keyboard - SATA controllers (Intel SATA2 and Marvell SATA3) - Fan Control (fancontrol on linux works well) - Native raminit (4+4GB DDR3-1333) - flashrom, using the internal programmer. Tested with coreboot, as well as with the vendor firmware. Backup chip is untested. Untested: - VGA BIOS for integrated graphics init - Audio: Only front/read outputs has been tested. - Non-Linux OSes - ACPI thermal zone and fan control Not working: - Default IFD defines the BIOS region as the entire flash chip. Care should be taken when using flashrom and ifd-as-layout! Change-Id: I37928de158bb8fbb47fbda5d1ccd4efba7edab26 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig M src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig.name M src/mainboard/gigabyte/ga-h61m-s2pv/Makefile.inc M src/mainboard/gigabyte/ga-h61m-s2pv/hda_verb.c M src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c R src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/devicetree.cb R src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/gpio.c A src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/hda_verb.c A src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/devicetree.cb A src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/gpio.c A src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/hda_verb.c 11 files changed, 425 insertions(+), 80 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/31832/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/31832 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37928de158bb8fbb47fbda5d1ccd4efba7edab26 Gerrit-Change-Number: 31832 Gerrit-PatchSet: 7 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: src/include/uuid.h: Remove unnecessary packed attribute
by HAOUAS Elyes (Code Review) 16 Jun '19

16 Jun '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33547 Change subject: src/include/uuid.h: Remove unnecessary packed attribute ...................................................................... src/include/uuid.h: Remove unnecessary packed attribute Change-Id: I314e778ac24247defabe9a207b36296c1e77a1bd Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/include/uuid.h 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/33547/1 diff --git a/src/include/uuid.h b/src/include/uuid.h index 0209055..e7aca66 100644 --- a/src/include/uuid.h +++ b/src/include/uuid.h @@ -18,9 +18,9 @@ #include <string.h> -typedef struct { +typedef struct guid_t { uint8_t b[16]; -} __packed guid_t; +}; #define GUID_INIT(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7) \ ((guid_t) \ -- To view, visit https://review.coreboot.org/c/coreboot/+/33547 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I314e778ac24247defabe9a207b36296c1e77a1bd Gerrit-Change-Number: 33547 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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coreboot-gerrit June 2019