coreboot-gerrit June 2019

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Change in ...coreboot[master]: commonlib: define cbtable tags as enum to identify conflicts
by Patrick Georgi (Code Review) 18 Jun '19

18 Jun '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32958 Change subject: commonlib: define cbtable tags as enum to identify conflicts ...................................................................... commonlib: define cbtable tags as enum to identify conflicts We had a value that was overloaded thrice. By moving them in a common structure and ordering them by value such issues are hopefully avoided in the future. Also add a few values to libpayload that were only defined in commonlib. Change-Id: I227d078eebee2d92488454707d4dab8ecc24a4d8 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M payloads/libpayload/include/coreboot_tables.h M src/commonlib/include/commonlib/coreboot_tables.h 2 files changed, 55 insertions(+), 50 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/32958/1 diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index c12db03..03febde 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -63,6 +63,7 @@ CB_TAG_RAM_OOPS = 0x0023, CB_TAG_ACPI_GNVS = 0x0024, CB_TAG_BOARD_ID = 0x0025, + CB_TAG_VERSION_TIMESTAMP = 0x0026, CB_TAG_WIFI_CALIBRATION = 0x0027, CB_TAG_RAM_CODE = 0x0028, CB_TAG_SERIALNO = 0x002a, @@ -71,10 +72,12 @@ CB_TAG_VPD = 0x002c, CB_TAG_SKU_ID = 0x002d, CB_TAG_BOOT_MEDIA_PARAMS = 0x0030, + CB_TAG_CBMEM_ENTRY = 0x0031, CB_TAG_TSC_INFO = 0x0032, CB_TAG_MAC_ADDRS = 0x0033, CB_TAG_VBOOT_WORKBUF = 0x0034, CB_TAG_MMC_INFO = 0x0035, + CB_TAG_TCPA_LOG = 0x0036, CB_TAG_CMOS_OPTION_TABLE = 0x00c8, CB_TAG_OPTION = 0x00c9, CB_TAG_OPTION_ENUM = 0x00ca, diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index 277b746..d583e16 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -44,6 +44,58 @@ * table entries and be backwards compatible, but it is not required. */ +enum { + LB_TAG_UNUSED = 0x0000, + LB_TAG_MEMORY = 0x0001, + LB_TAG_HWRPB = 0x0002, + LB_TAG_MAINBOARD = 0x0003, + LB_TAG_VERSION = 0x0004, + LB_TAG_EXTRA_VERSION = 0x0005, + LB_TAG_BUILD = 0x0006, + LB_TAG_COMPILE_TIME = 0x0007, + LB_TAG_COMPILE_BY = 0x0008, + LB_TAG_COMPILE_HOST = 0x0009, + LB_TAG_COMPILE_DOMAIN = 0x000a, + LB_TAG_COMPILER = 0x000b, + LB_TAG_LINKER = 0x000c, + LB_TAG_ASSEMBLER = 0x000d, + LB_TAG_SERIAL = 0x000f, + LB_TAG_CONSOLE = 0x0010, + LB_TAG_FORWARD = 0x0011, + LB_TAG_FRAMEBUFFER = 0x0012, + LB_TAG_GPIO = 0x0013, + LB_TAG_TIMESTAMPS = 0x0016, + LB_TAG_CBMEM_CONSOLE = 0x0017, + LB_TAG_MRC_CACHE = 0x0018, + LB_TAG_VBNV = 0x0019, + LB_TAG_VBOOT_HANDOFF = 0x0020, + LB_TAG_X86_ROM_MTRR = 0x0021, + LB_TAG_DMA = 0x0022, + LB_TAG_RAM_OOPS = 0x0023, + LB_TAG_ACPI_GNVS = 0x0024, + LB_TAG_BOARD_ID = 0x0025, + LB_TAG_VERSION_TIMESTAMP = 0x0026, + LB_TAG_WIFI_CALIBRATION = 0x0027, + LB_TAG_RAM_CODE = 0x0028, + LB_TAG_SERIALNO = 0x002a, + LB_TAG_SPI_FLASH = 0x0029, + LB_TAG_MTC = 0x002b, + LB_TAG_VPD = 0x002c, + LB_TAG_SKU_ID = 0x002d, + LB_TAG_BOOT_MEDIA_PARAMS = 0x0030, + LB_TAG_CBMEM_ENTRY = 0x0031, + LB_TAG_TSC_INFO = 0x0032, + LB_TAG_MAC_ADDRS = 0x0033, + LB_TAG_VBOOT_WORKBUF = 0x0034, + LB_TAG_MMC_INFO = 0x0035, + LB_TAG_TCPA_LOG = 0x0036, + LB_TAG_CMOS_OPTION_TABLE = 0x00c8, + LB_TAG_OPTION = 0x00c9, + LB_TAG_OPTION_ENUM = 0x00ca, + LB_TAG_OPTION_DEFAULTS = 0x00cb, + LB_TAG_OPTION_CHECKSUM = 0x00cc, +}; + /* Since coreboot is usually compiled 32bit, gcc will align 64bit * types to 32bit boundaries. If the coreboot table is dumped on a * 64bit system, a uint64_t would be aligned to 64bit boundaries, @@ -97,9 +149,6 @@ uint32_t size; /* size of record (in bytes) */ }; -#define LB_TAG_UNUSED 0x0000 - -#define LB_TAG_MEMORY 0x0001 struct lb_memory_range { struct lb_uint64 start; @@ -120,14 +169,12 @@ struct lb_memory_range map[0]; }; -#define LB_TAG_HWRPB 0x0002 struct lb_hwrpb { uint32_t tag; uint32_t size; uint64_t hwrpb; }; -#define LB_TAG_MAINBOARD 0x0003 struct lb_mainboard { uint32_t tag; uint32_t size; @@ -136,23 +183,12 @@ uint8_t strings[0]; }; -#define LB_TAG_VERSION 0x0004 -#define LB_TAG_EXTRA_VERSION 0x0005 -#define LB_TAG_BUILD 0x0006 -#define LB_TAG_COMPILE_TIME 0x0007 -#define LB_TAG_COMPILE_BY 0x0008 -#define LB_TAG_COMPILE_HOST 0x0009 -#define LB_TAG_COMPILE_DOMAIN 0x000a -#define LB_TAG_COMPILER 0x000b -#define LB_TAG_LINKER 0x000c -#define LB_TAG_ASSEMBLER 0x000d struct lb_string { uint32_t tag; uint32_t size; uint8_t string[0]; }; -#define LB_TAG_VERSION_TIMESTAMP 0x0026 struct lb_timestamp { uint32_t tag; uint32_t size; @@ -162,7 +198,6 @@ /* 0xe is taken by v3 */ -#define LB_TAG_SERIAL 0x000f struct lb_serial { uint32_t tag; uint32_t size; @@ -189,7 +224,6 @@ uint32_t uart_pci_addr; }; -#define LB_TAG_CONSOLE 0x0010 struct lb_console { uint32_t tag; uint32_t size; @@ -204,7 +238,6 @@ #define LB_TAG_CONSOLE_EHCI 5 #define LB_TAG_CONSOLE_SERIAL8250MEM 6 -#define LB_TAG_FORWARD 0x0011 struct lb_forward { uint32_t tag; uint32_t size; @@ -250,7 +283,6 @@ * fields described above. It may, however, only implement a subset * of the possible color formats. */ -#define LB_TAG_FRAMEBUFFER 0x0012 struct lb_framebuffer { uint32_t tag; uint32_t size; @@ -270,7 +302,6 @@ uint8_t reserved_mask_size; }; -#define LB_TAG_GPIO 0x0013 struct lb_gpio { uint32_t port; @@ -290,12 +321,6 @@ struct lb_gpio gpios[0]; }; -#define LB_TAG_VBNV 0x0019 -#define LB_TAG_VBOOT_HANDOFF 0x0020 -#define LB_TAG_VBOOT_WORKBUF 0x0034 -#define LB_TAG_DMA 0x0022 -#define LB_TAG_RAM_OOPS 0x0023 -#define LB_TAG_MTC 0x002b struct lb_range { uint32_t tag; uint32_t size; @@ -306,13 +331,6 @@ void lb_ramoops(struct lb_header *header); -#define LB_TAG_TIMESTAMPS 0x0016 -#define LB_TAG_CBMEM_CONSOLE 0x0017 -#define LB_TAG_MRC_CACHE 0x0018 -#define LB_TAG_ACPI_GNVS 0x0024 -#define LB_TAG_TCPA_LOG 0x0036 -#define LB_TAG_WIFI_CALIBRATION 0x0027 -#define LB_TAG_VPD 0x002c struct lb_cbmem_ref { uint32_t tag; uint32_t size; @@ -320,7 +338,6 @@ uint64_t cbmem_addr; }; -#define LB_TAG_X86_ROM_MTRR 0x0021 struct lb_x86_rom_mtrr { uint32_t tag; uint32_t size; @@ -328,9 +345,6 @@ uint32_t index; }; -#define LB_TAG_BOARD_ID 0x0025 -#define LB_TAG_RAM_CODE 0x0028 -#define LB_TAG_SKU_ID 0x002d struct lb_strapping_id { uint32_t tag; @@ -338,7 +352,6 @@ uint32_t id_code; }; -#define LB_TAG_SPI_FLASH 0x0029 struct lb_spi_flash { uint32_t tag; uint32_t size; @@ -347,7 +360,6 @@ uint32_t erase_cmd; }; -#define LB_TAG_BOOT_MEDIA_PARAMS 0x0030 struct lb_boot_media_params { uint32_t tag; uint32_t size; @@ -361,7 +373,6 @@ /* * There can be more than one of these records as there is one per cbmem entry. */ -#define LB_TAG_CBMEM_ENTRY 0x0031 struct lb_cbmem_entry { uint32_t tag; uint32_t size; @@ -371,7 +382,6 @@ uint32_t id; }; -#define LB_TAG_TSC_INFO 0x0032 struct lb_tsc_info { uint32_t tag; uint32_t size; @@ -379,13 +389,11 @@ uint32_t freq_khz; }; -#define LB_TAG_MAC_ADDRS 0x0033 struct mac_address { uint8_t mac_addr[6]; uint8_t pad[2]; /* Pad it to 8 bytes to keep it simple. */ }; -#define LB_TAG_MMC_INFO 0x0035 struct lb_mmc_info { uint32_t tag; uint32_t size; @@ -407,11 +415,9 @@ struct mac_address mac_addrs[0]; }; -#define LB_TAG_SERIALNO 0x002a #define MAX_SERIALNO_LENGTH 32 /* The following structures are for the cmos definitions table */ -#define LB_TAG_CMOS_OPTION_TABLE 200 /* cmos header record */ struct cmos_option_table { uint32_t tag; /* CMOS definitions table type */ @@ -426,7 +432,6 @@ * starts at the beginning of the byte and the length is * fills complete bytes. */ -#define LB_TAG_OPTION 201 struct cmos_entries { uint32_t tag; /* entry type */ uint32_t size; /* length of this record */ @@ -444,7 +449,6 @@ * This record is variable length. The text field may be * shorter than CMOS_MAX_TEXT_LENGTH. */ -#define LB_TAG_OPTION_ENUM 202 struct cmos_enums { uint32_t tag; /* enumeration type */ uint32_t size; /* length of this record */ @@ -458,7 +462,6 @@ /* cmos defaults record * This record contains default settings for the cmos ram. */ -#define LB_TAG_OPTION_DEFAULTS 203 struct cmos_defaults { uint32_t tag; /* default type */ uint32_t size; /* length of this record */ @@ -468,7 +471,6 @@ uint8_t default_set[CMOS_IMAGE_BUFFER_SIZE]; /* default settings */ }; -#define LB_TAG_OPTION_CHECKSUM 204 struct cmos_checksum { uint32_t tag; uint32_t size; -- To view, visit https://review.coreboot.org/c/coreboot/+/32958 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I227d078eebee2d92488454707d4dab8ecc24a4d8 Gerrit-Change-Number: 32958 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 8

Change in ...coreboot[master]: libpayload: define cbtable tags as enum to identify conflicts
by Patrick Georgi (Code Review) 18 Jun '19

18 Jun '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32957 Change subject: libpayload: define cbtable tags as enum to identify conflicts ...................................................................... libpayload: define cbtable tags as enum to identify conflicts We had a value that was overloaded thrice. By moving them in a common structure and ordering them by value such issues are hopefully avoided in the future. Change-Id: I0c7762601d7620413989b458fa634d7606accc9d Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M payloads/libpayload/include/coreboot_tables.h 1 file changed, 49 insertions(+), 55 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/32957/1 diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index 8e5cec0..c12db03 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -33,6 +33,55 @@ #include <arch/types.h> #include <ipchksum.h> +enum { + CB_TAG_UNUSED = 0x0000, + CB_TAG_MEMORY = 0x0001, + CB_TAG_HWRPB = 0x0002, + CB_TAG_MAINBOARD = 0x0003, + CB_TAG_VERSION = 0x0004, + CB_TAG_EXTRA_VERSION = 0x0005, + CB_TAG_BUILD = 0x0006, + CB_TAG_COMPILE_TIME = 0x0007, + CB_TAG_COMPILE_BY = 0x0008, + CB_TAG_COMPILE_HOST = 0x0009, + CB_TAG_COMPILE_DOMAIN = 0x000a, + CB_TAG_COMPILER = 0x000b, + CB_TAG_LINKER = 0x000c, + CB_TAG_ASSEMBLER = 0x000d, + CB_TAG_SERIAL = 0x000f, + CB_TAG_CONSOLE = 0x0010, + CB_TAG_FORWARD = 0x0011, + CB_TAG_FRAMEBUFFER = 0x0012, + CB_TAG_GPIO = 0x0013, + CB_TAG_TIMESTAMPS = 0x0016, + CB_TAG_CBMEM_CONSOLE = 0x0017, + CB_TAG_MRC_CACHE = 0x0018, + CB_TAG_VBNV = 0x0019, + CB_TAG_VBOOT_HANDOFF = 0x0020, + CB_TAG_X86_ROM_MTRR = 0x0021, + CB_TAG_DMA = 0x0022, + CB_TAG_RAM_OOPS = 0x0023, + CB_TAG_ACPI_GNVS = 0x0024, + CB_TAG_BOARD_ID = 0x0025, + CB_TAG_WIFI_CALIBRATION = 0x0027, + CB_TAG_RAM_CODE = 0x0028, + CB_TAG_SERIALNO = 0x002a, + CB_TAG_SPI_FLASH = 0x0029, + CB_TAG_MTC = 0x002b, + CB_TAG_VPD = 0x002c, + CB_TAG_SKU_ID = 0x002d, + CB_TAG_BOOT_MEDIA_PARAMS = 0x0030, + CB_TAG_TSC_INFO = 0x0032, + CB_TAG_MAC_ADDRS = 0x0033, + CB_TAG_VBOOT_WORKBUF = 0x0034, + CB_TAG_MMC_INFO = 0x0035, + CB_TAG_CMOS_OPTION_TABLE = 0x00c8, + CB_TAG_OPTION = 0x00c9, + CB_TAG_OPTION_ENUM = 0x00ca, + CB_TAG_OPTION_DEFAULTS = 0x00cb, + CB_TAG_OPTION_CHECKSUM = 0x00cc, +}; + struct cbuint64 { u32 lo; u32 hi; @@ -52,9 +101,6 @@ u32 size; }; -#define CB_TAG_UNUSED 0x0000 -#define CB_TAG_MEMORY 0x0001 - struct cb_memory_range { struct cbuint64 start; struct cbuint64 size; @@ -75,16 +121,12 @@ struct cb_memory_range map[0]; }; -#define CB_TAG_HWRPB 0x0002 - struct cb_hwrpb { u32 tag; u32 size; u64 hwrpb; }; -#define CB_TAG_MAINBOARD 0x0003 - struct cb_mainboard { u32 tag; u32 size; @@ -93,25 +135,12 @@ u8 strings[0]; }; -#define CB_TAG_VERSION 0x0004 -#define CB_TAG_EXTRA_VERSION 0x0005 -#define CB_TAG_BUILD 0x0006 -#define CB_TAG_COMPILE_TIME 0x0007 -#define CB_TAG_COMPILE_BY 0x0008 -#define CB_TAG_COMPILE_HOST 0x0009 -#define CB_TAG_COMPILE_DOMAIN 0x000a -#define CB_TAG_COMPILER 0x000b -#define CB_TAG_LINKER 0x000c -#define CB_TAG_ASSEMBLER 0x000d - struct cb_string { u32 tag; u32 size; u8 string[0]; }; -#define CB_TAG_SERIAL 0x000f - struct cb_serial { u32 tag; u32 size; @@ -138,8 +167,6 @@ u32 uart_pci_addr; }; -#define CB_TAG_CONSOLE 0x00010 - struct cb_console { u32 tag; u32 size; @@ -153,15 +180,12 @@ #define CB_TAG_CONSOLE_SROM 4 // OBSOLETE #define CB_TAG_CONSOLE_EHCI 5 -#define CB_TAG_FORWARD 0x00011 - struct cb_forward { u32 tag; u32 size; u64 forward; }; -#define CB_TAG_FRAMEBUFFER 0x0012 struct cb_framebuffer { u32 tag; u32 size; @@ -181,7 +205,6 @@ u8 reserved_mask_size; }; -#define CB_TAG_GPIO 0x0013 #define CB_GPIO_ACTIVE_LOW 0 #define CB_GPIO_ACTIVE_HIGH 1 #define CB_GPIO_MAX_NAME_LENGTH 16 @@ -200,13 +223,6 @@ struct cb_gpio gpios[0]; }; -#define CB_TAG_VBNV 0x0019 -#define CB_TAG_VBOOT_HANDOFF 0x0020 -#define CB_TAG_VBOOT_WORKBUF 0x0034 -#define CB_TAG_DMA 0x0022 -#define CB_TAG_RAM_OOPS 0x0023 -#define CB_TAG_MTC 0x002b -#define CB_TAG_VPD 0x002c struct lb_range { uint32_t tag; uint32_t size; @@ -214,18 +230,12 @@ uint32_t range_size; }; -#define CB_TAG_TIMESTAMPS 0x0016 -#define CB_TAG_CBMEM_CONSOLE 0x0017 -#define CB_TAG_MRC_CACHE 0x0018 -#define CB_TAG_ACPI_GNVS 0x0024 -#define CB_TAG_WIFI_CALIBRATION 0x0027 struct cb_cbmem_tab { uint32_t tag; uint32_t size; uint64_t cbmem_tab; }; -#define CB_TAG_X86_ROM_MTRR 0x0021 struct cb_x86_rom_mtrr { uint32_t tag; uint32_t size; @@ -236,17 +246,12 @@ uint32_t index; }; - -#define CB_TAG_BOARD_ID 0x0025 -#define CB_TAG_RAM_CODE 0x0028 -#define CB_TAG_SKU_ID 0x002d struct cb_strapping_id { uint32_t tag; uint32_t size; uint32_t id_code; }; -#define CB_TAG_SPI_FLASH 0x0029 struct cb_spi_flash { uint32_t tag; uint32_t size; @@ -255,7 +260,6 @@ uint32_t erase_cmd; }; -#define CB_TAG_BOOT_MEDIA_PARAMS 0x0030 struct cb_boot_media_params { uint32_t tag; uint32_t size; @@ -266,7 +270,6 @@ uint64_t boot_media_size; }; -#define CB_TAG_TSC_INFO 0x0032 struct cb_tsc_info { uint32_t tag; uint32_t size; @@ -274,7 +277,6 @@ uint32_t freq_khz; }; -#define CB_TAG_MAC_ADDRS 0x0033 struct mac_address { uint8_t mac_addr[6]; uint8_t pad[2]; /* Pad it to 8 bytes to keep it simple. */ @@ -287,7 +289,6 @@ struct mac_address mac_addrs[0]; }; -#define CB_TAG_MMC_INFO 0x0035 struct cb_mmc_info { uint32_t tag; uint32_t size; @@ -302,17 +303,14 @@ int32_t early_cmd1_status; }; -#define CB_TAG_SERIALNO 0x002a #define CB_MAX_SERIALNO_LENGTH 32 -#define CB_TAG_CMOS_OPTION_TABLE 0x00c8 struct cb_cmos_option_table { u32 tag; u32 size; u32 header_length; }; -#define CB_TAG_OPTION 0x00c9 #define CB_CMOS_MAX_NAME_LENGTH 32 struct cb_cmos_entries { u32 tag; @@ -324,8 +322,6 @@ u8 name[CB_CMOS_MAX_NAME_LENGTH]; }; - -#define CB_TAG_OPTION_ENUM 0x00ca #define CB_CMOS_MAX_TEXT_LENGTH 32 struct cb_cmos_enums { u32 tag; @@ -335,7 +331,6 @@ u8 text[CB_CMOS_MAX_TEXT_LENGTH]; }; -#define CB_TAG_OPTION_DEFAULTS 0x00cb #define CB_CMOS_IMAGE_BUFFER_SIZE 128 struct cb_cmos_defaults { u32 tag; @@ -345,7 +340,6 @@ u8 default_set[CB_CMOS_IMAGE_BUFFER_SIZE]; }; -#define CB_TAG_OPTION_CHECKSUM 0x00cc #define CB_CHECKSUM_NONE 0 #define CB_CHECKSUM_PCBIOS 1 struct cb_cmos_checksum { -- To view, visit https://review.coreboot.org/c/coreboot/+/32957 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c7762601d7620413989b458fa634d7606accc9d Gerrit-Change-Number: 32957 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: {drivers,soc/intel/braswell}: Implement C_ENVIRONMENT_BOOTBLOCK support
by Frans Hendriks (Code Review) 18 Jun '19

18 Jun '19

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29662 ) Change subject: {drivers,soc/intel/braswell}: Implement C_ENVIRONMENT_BOOTBLOCK support ...................................................................... Patch Set 47: > Patch Set 47: > > this change breaks google/cyan variants, bootloops and no console output to triage (even with BOOTBLOCK_CONSOLE added) Can this be related to VBOOT? Or is VBOOT disabled? -- To view, visit https://review.coreboot.org/c/coreboot/+/29662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c Gerrit-Change-Number: 29662 Gerrit-PatchSet: 47 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: York Yang <yyang024(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 18 Jun 2019 07:16:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: MAINTAINERS: Add maintainers to ELTAN VENDORCODE
by Frans Hendriks (Code Review) 18 Jun '19

18 Jun '19

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33441 Change subject: MAINTAINERS: Add maintainers to ELTAN VENDORCODE ...................................................................... MAINTAINERS: Add maintainers to ELTAN VENDORCODE Add maintainers to the new vendorcode. Change-Id: Ie3f99dd99c708f93bfcd19f52c57504e157e1eca Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M MAINTAINERS 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/33441/1 diff --git a/MAINTAINERS b/MAINTAINERS index f1ae076..e7780a8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -624,6 +624,12 @@ F: */memlayout.h F: *.ld +ELTAN VENDORCODE +M: Frans Hendriks <fhendriks(a)eltan.com> +M: Wim Vervoorn <wvervoorn(a)eltan.com> +S: Maintained +F: src/vendorcode/eltan + MISSING: TIMERS / DELAYS MISSING: TIMESTAMPS -- To view, visit https://review.coreboot.org/c/coreboot/+/33441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3f99dd99c708f93bfcd19f52c57504e157e1eca Gerrit-Change-Number: 33441 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: drivers/ipmi: Fix multiple issues
by Patrick Rudolph (Code Review) 18 Jun '19

18 Jun '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33488 Change subject: drivers/ipmi: Fix multiple issues ...................................................................... drivers/ipmi: Fix multiple issues * Set abort command define * Set debug level to SPEW * Support zero length data packet in ipmi_kcs_send_message That's required for commands like GET_DEVICE_ID, which have no additional data to send. * Read reply even if given no receive buffer * Prevent buffer overflow in read reply processing Tested on Wedge100s. Change-Id: Iefddd88a744c3b96751d3fe8c2951ca2115548ce Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/drivers/ipmi/ipmi_kcs.c 1 file changed, 40 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/33488/1 diff --git a/src/drivers/ipmi/ipmi_kcs.c b/src/drivers/ipmi/ipmi_kcs.c index 8d106837..bde18d2 100644 --- a/src/drivers/ipmi/ipmi_kcs.c +++ b/src/drivers/ipmi/ipmi_kcs.c @@ -22,7 +22,7 @@ #define IPMI_KCS_STATE(_x) ((_x) >> 6) -#define IPMI_KCS_GET_STATUS_ABORT +#define IPMI_KCS_GET_STATUS_ABORT 0x60 #define IPMI_KCS_START_WRITE 0x61 #define IPMI_KCS_END_WRITE 0x62 #define IPMI_KCS_READ_BYTE 0x68 @@ -43,7 +43,7 @@ static unsigned char ipmi_kcs_status(int port) { unsigned char status = inb(IPMI_STAT(port)); - printk(BIOS_DEBUG, "%s: 0x%02x\n", __func__, status); + printk(BIOS_SPEW, "%s: 0x%02x\n", __func__, status); return status; } @@ -77,7 +77,7 @@ { unsigned char status; - printk(BIOS_DEBUG, "%s: %02x\n", __func__, byte); + printk(BIOS_SPEW, "%s: 0x%02x\n", __func__, byte); outb(byte, IPMI_DATA(port)); @@ -100,7 +100,7 @@ { unsigned char status; - printk(BIOS_DEBUG, "%s: %02x\n", __func__, byte); + printk(BIOS_SPEW, "%s: 0x%02x\n", __func__, byte); if (wait_ibf_timeout(port)) return 1; @@ -121,7 +121,7 @@ static int ipmi_kcs_send_cmd_byte(int port, const unsigned char byte) { - printk(BIOS_DEBUG, "%s: 0x%02x\n", __func__, byte); + printk(BIOS_SPEW, "%s: 0x%02x\n", __func__, byte); if (wait_ibf_timeout(port)) return 1; @@ -154,27 +154,43 @@ return ret; } - if ((ret = ipmi_kcs_send_data_byte(port, cmd))) { - printk(BIOS_ERR, "IPMI CMD failed\n"); - return ret; + if (!len) { + if ((ret = ipmi_kcs_send_cmd_byte(port, IPMI_KCS_END_WRITE))) { + printk(BIOS_ERR, "IPMI END WRITE failed\n"); + return ret; + } + + if ((ret = ipmi_kcs_send_last_data_byte(port, cmd))) { + printk(BIOS_ERR, "IPMI BYTE WRITE failed\n"); + return ret; + } + } else { + if ((ret = ipmi_kcs_send_data_byte(port, cmd))) { + printk(BIOS_ERR, "IPMI CMD failed\n"); + return ret; + } } - while (len-- > 1) { + while (len > 1) { if ((ret = ipmi_kcs_send_data_byte(port, *msg++))) { printk(BIOS_ERR, "IPMI BYTE WRITE failed\n"); return ret; } + len--; + } + + if (len) { + if ((ret = ipmi_kcs_send_cmd_byte(port, IPMI_KCS_END_WRITE))) { + printk(BIOS_ERR, "IPMI END WRITE failed\n"); + return ret; + } + + if ((ret = ipmi_kcs_send_last_data_byte(port, *msg++))) { + printk(BIOS_ERR, "IPMI BYTE WRITE failed\n"); + return ret; + } } - if ((ret = ipmi_kcs_send_cmd_byte(port, IPMI_KCS_END_WRITE))) { - printk(BIOS_ERR, "IPMI END WRITE failed\n"); - return ret; - } - - if ((ret = ipmi_kcs_send_last_data_byte(port, *msg++))) { - printk(BIOS_ERR, "IPMI BYTE WRITE failed\n"); - return ret; - } return 0; } @@ -182,9 +198,6 @@ { int status, ret = 0; - if (!msg) - return 0; - if (wait_ibf_timeout(port)) return 1; @@ -195,15 +208,18 @@ return ret; if (IPMI_KCS_STATE(status) != IPMI_KCS_STATE_READ) { - printk(BIOS_ERR, "%s: wrong state: 0x%02x\n", __func__, status); + printk(BIOS_ERR, "%s: wrong state: 0x%02x\n", __func__, + status); return -1; } if (wait_obf_timeout(port)) return -1; - *msg++ = inb(IPMI_DATA(port)); - ret++; + if (msg && (ret < len)) { + *msg++ = inb(IPMI_DATA(port)); + ret++; + } if (wait_ibf_timeout(port)) return -1; -- To view, visit https://review.coreboot.org/c/coreboot/+/33488 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iefddd88a744c3b96751d3fe8c2951ca2115548ce Gerrit-Change-Number: 33488 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mediatek/mt8183: Set small core _normal mode_ regulator value
by Nicolas Boichat (Code Review) 18 Jun '19

18 Jun '19

Nicolas Boichat has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33569 Change subject: mediatek/mt8183: Set small core _normal mode_ regulator value ...................................................................... mediatek/mt8183: Set small core _normal mode_ regulator value dcb2eef582 ("mediatek/mt8183: Set processor voltage to 1.05v") incorrectly sets the VPROC12 (small core) regulator sleep mode voltage value (0x140a) to 1.05V, instead of the normal mode value (0x1426), causing the regulator to be stuck at 1.05V. The big core register is correct, let's not touch that. BUG=b:80501386,b:135404378 BRANCH=none Test=Boots correctly on Kukui, see that regulator is not stuck anymore: grep vproc12 /sys/kernel/debug/regulator/regulator_summary Change-Id: I2cd40db2cec70a878b4b3b895e83cd648f1bc25c Signed-off-by: Nicolas Boichat <drinkcat(a)chromium.org> --- M src/soc/mediatek/mt8183/mt6358.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/33569/1 diff --git a/src/soc/mediatek/mt8183/mt6358.c b/src/soc/mediatek/mt8183/mt6358.c index 7054243..774f636 100644 --- a/src/soc/mediatek/mt8183/mt6358.c +++ b/src/soc/mediatek/mt8183/mt6358.c @@ -497,7 +497,7 @@ /* Vproc11/Vproc12 to 1.05V */ {0x13a6, 0x58, 0x7F, 0}, - {0x140a, 0x58, 0x7F, 0}, + {0x1426, 0x58, 0x7F, 0}, }; static struct pmic_setting lp_setting[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/33569 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2cd40db2cec70a878b4b3b895e83cd648f1bc25c Gerrit-Change-Number: 33569 Gerrit-PatchSet: 1 Gerrit-Owner: Nicolas Boichat <drinkcat(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/sconfig: Emit array of PNP UART devices
by Patrick Georgi (Code Review) 17 Jun '19

17 Jun '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31934 ) Change subject: util/sconfig: Emit array of PNP UART devices ...................................................................... Patch Set 4: Code-Review+2 interesting approach -- To view, visit https://review.coreboot.org/c/coreboot/+/31934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9330bcd5545ec3f94c1c14ed4a639f1ef0548e43 Gerrit-Change-Number: 31934 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 17 Jun 2019 21:54:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: util/sconfig: Expose usable PCI and PNP device names
by Patrick Georgi (Code Review) 17 Jun '19

17 Jun '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31933 ) Change subject: util/sconfig: Expose usable PCI and PNP device names ...................................................................... Patch Set 4: (2 comments) https://review.coreboot.org/#/c/31933/4/util/sconfig/main.c File util/sconfig/main.c: https://review.coreboot.org/#/c/31933/4/util/sconfig/main.c@847 PS4, Line 847: pass2 expose_device_names or something like that? https://review.coreboot.org/#/c/31933/4/util/sconfig/main.c@1357 PS4, Line 1357: pass 2 ditto? -- To view, visit https://review.coreboot.org/c/coreboot/+/31933 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I711058f5c809fa9bc7ea4333aaebad6847ebdfd4 Gerrit-Change-Number: 31933 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 17 Jun 2019 21:53:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: util/sconfig: Add commonlib/helpers.h
by Patrick Georgi (Code Review) 17 Jun '19

17 Jun '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31932 ) Change subject: util/sconfig: Add commonlib/helpers.h ...................................................................... Patch Set 4: okay, I guess, but maybe add why we need this? -- To view, visit https://review.coreboot.org/c/coreboot/+/31932 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifbcaa1b613aef312d3876e8b536499a9f01a8d19 Gerrit-Change-Number: 31932 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 17 Jun 2019 21:51:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: util/sconfig: Declare the repeated devicetree storage
by Patrick Georgi (Code Review) 17 Jun '19

17 Jun '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31931 ) Change subject: util/sconfig: Declare the repeated devicetree storage ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/#/c/31931/4/util/sconfig/main.c File util/sconfig/main.c: https://review.coreboot.org/#/c/31931/4/util/sconfig/main.c@932 PS4, Line 932: static so everything is now static all the time? -- To view, visit https://review.coreboot.org/c/coreboot/+/31931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4cb9e75f179f44edf4f8256ad8320bc2d4ae71a Gerrit-Change-Number: 31931 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 17 Jun 2019 21:49:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit June 2019