coreboot-gerrit June 2019

coreboot-gerrit@coreboot.org

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1454 discussions

Change in ...coreboot[master]: qclib: Add qclib support with interface tables
by Julius Werner (Code Review) 17 Jun '19

17 Jun '19

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29967 ) Change subject: qclib: Add qclib support with interface tables ...................................................................... Patch Set 30: (2 comments) https://review.coreboot.org/#/c/29967/30/src/mainboard/google/mistral/romst… File src/mainboard/google/mistral/romstage.c: https://review.coreboot.org/#/c/29967/30/src/mainboard/google/mistral/romst… PS30, Line 32: qclib_load_and_run(); Normally this should be the last call in this function. https://review.coreboot.org/#/c/29967/30/src/soc/qualcomm/common/qclib.c File src/soc/qualcomm/common/qclib.c: https://review.coreboot.org/#/c/29967/30/src/soc/qualcomm/common/qclib.c@147 PS30, Line 147: _ddr_training, ssize, QCLIB_BA_SAVE_TO_STORAGE); Still wrong -- To view, visit https://review.coreboot.org/c/coreboot/+/29967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I534af71163d034ea04420dda6a94ce31b08c8a07 Gerrit-Change-Number: 29967 Gerrit-PatchSet: 30 Gerrit-Owner: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sricharan Ramabadhran <srichara(a)qualcomm.corp-partner.google.com> Gerrit-CC: mturney mturney <mturney(a)codeaurora.org> Gerrit-Comment-Date: Mon, 17 Jun 2019 21:38:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: arm64: make comment match code
by Marty E. Plummer (Code Review) 17 Jun '19

17 Jun '19

Marty E. Plummer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33486 Change subject: arm64: make comment match code ...................................................................... arm64: make comment match code Change-Id: I37b8d5715cb6a32d4853e77098094cd5cffb9a4c Signed-off-by: Marty E. Plummer <hanetzer(a)startmail.com> --- M src/arch/arm64/armv8/bootblock.S 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/33486/1 diff --git a/src/arch/arm64/armv8/bootblock.S b/src/arch/arm64/armv8/bootblock.S index e5758bc..3950f55 100644 --- a/src/arch/arm64/armv8/bootblock.S +++ b/src/arch/arm64/armv8/bootblock.S @@ -19,7 +19,7 @@ /* NOTE: When making changes to general ARM64 initialization, keep in mind that * there are other CPU entry points, using BOOTBLOCK_CUSTOM or entering the CPU * in a later stage (like Tegra). Changes should generally be put into - * arm64_cpu_init so they can be shared between those instances. */ + * arm64_init_cpu so they can be shared between those instances. */ ENTRY(_start) /* Initialize PSTATE, SCTLR and caches to clean state, set up stack. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/33486 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37b8d5715cb6a32d4853e77098094cd5cffb9a4c Gerrit-Change-Number: 33486 Gerrit-PatchSet: 1 Gerrit-Owner: Marty E. Plummer <hanetzer(a)startmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Fix SSDTGen
by Christian Walter (Code Review) 17 Jun '19

17 Jun '19

Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33566 Change subject: Fix SSDTGen ...................................................................... Fix SSDTGen Change-Id: I76282189c6426650c66680e2aad4f5cfbc22a3e4 Signed-off-by: Christian Walter <christian.walter(a)9elements.com> --- M src/superio/common/ssdt.c 1 file changed, 10 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/33566/1 diff --git a/src/superio/common/ssdt.c b/src/superio/common/ssdt.c index 8febbde..0184269 100644 --- a/src/superio/common/ssdt.c +++ b/src/superio/common/ssdt.c @@ -33,11 +33,11 @@ }; static const struct superio_dev superio_devs[] = { - {"PNP0700", {0x3f0, 0x3f2, 0x3f7}, {6, }}, - {"PNP0303", {60, 64, }, {1, }}, - {"PNP0F03", {60, 64, }, {12, }}, - {"PNP0501", {0x3f8, 0x2f8, 0x3e8, 0x2e8}, {4, 3}}, - {"PNP0400", {0x378, }, {7, }}, + {"PNP0700", {0x3f0, 0x3f2, 0x3f7}, {6, } }, + {"PNP0303", {60, 64, }, {1, } }, + {"PNP0F03", {60, 64, }, {12, } }, + {"PNP0501", {0x3f8, 0x2f8, 0x3e8, 0x2e8}, {4, 3} }, + {"PNP0400", {0x378, }, {7, } }, }; static const u8 io_idx[NUM_IO] = {PNP_IDX_IO0, PNP_IDX_IO1, PNP_IDX_IO2, @@ -51,7 +51,8 @@ const char *name = acpi_device_name(dev); if (!scope || !name) { - printk(BIOS_ERR, "%s: Missing ACPI path/scope\n", dev_path(dev)); + printk(BIOS_ERR, "%s: Missing ACPI path/scope\n", + dev_path(dev)); return; } @@ -108,7 +109,7 @@ FIELDLIST_OFFSET(0x70), FIELDLIST_NAMESTR("INTR", 4), FIELDLIST_NAMESTR("INTT", 4), - FIELDLIST_OFFSET (0x74), + FIELDLIST_OFFSET(0x74), FIELDLIST_NAMESTR("DMCH", 8), FIELDLIST_OFFSET(0xE0), FIELDLIST_NAMESTR("RGE0", 8), @@ -263,7 +264,8 @@ bool has_resources; if (!scope || !name) { - printk(BIOS_ERR, "%s: Missing ACPI path/scope\n", dev_path(dev)); + printk(BIOS_ERR, "%s: Missing ACPI path/scope\n", + dev_path(dev)); return; } if (vldn) { -- To view, visit https://review.coreboot.org/c/coreboot/+/33566 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I76282189c6426650c66680e2aad4f5cfbc22a3e4 Gerrit-Change-Number: 33566 Gerrit-PatchSet: 1 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/poppy/variants/atlas: Update DPTF parameter
by Puthikorn Voravootivat (Code Review) 17 Jun '19

17 Jun '19

Puthikorn Voravootivat has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33180 Change subject: mb/google/poppy/variants/atlas: Update DPTF parameter ...................................................................... mb/google/poppy/variants/atlas: Update DPTF parameter The temperature delta between on-board thermistor and surface temp change, so update DPTF parameter accordingly. BUG=b:113101335 TEST=Tested in thermal chamber by thermal team. See comment 144 / 146 in the bug. Change-Id: Ie18be94fc1e7476755fb0e6947cce559854a82dd Signed-off-by: Puthikorn Voravootivat <puthik(a)chromium.org> --- M src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/33180/1 diff --git a/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl b/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl index 570fbbb..d8b6137 100644 --- a/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl @@ -29,12 +29,12 @@ #define DPTF_TSR2_SENSOR_ID 3 #define DPTF_TSR2_SENSOR_NAME "DRAM" -#define DPTF_TSR2_PASSIVE 55 +#define DPTF_TSR2_PASSIVE 53 #define DPTF_TSR2_CRITICAL 75 #define DPTF_TSR3_SENSOR_ID 4 #define DPTF_TSR3_SENSOR_NAME "eMMC" -#define DPTF_TSR3_PASSIVE 52 +#define DPTF_TSR3_PASSIVE 51 #define DPTF_TSR3_CRITICAL 75 #undef DPTF_ENABLE_FAN_CONTROL -- To view, visit https://review.coreboot.org/c/coreboot/+/33180 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie18be94fc1e7476755fb0e6947cce559854a82dd Gerrit-Change-Number: 33180 Gerrit-PatchSet: 1 Gerrit-Owner: Puthikorn Voravootivat <puthik(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: {drivers,soc/intel/braswell}: Implement C_ENVIRONMENT_BOOTBLOCK support
by Matt DeVillier (Code Review) 17 Jun '19

17 Jun '19

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29662 ) Change subject: {drivers,soc/intel/braswell}: Implement C_ENVIRONMENT_BOOTBLOCK support ...................................................................... Patch Set 47: this change breaks google/cyan variants, bootloops and no console output to triage (even with BOOTBLOCK_CONSOLE added) -- To view, visit https://review.coreboot.org/c/coreboot/+/29662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c Gerrit-Change-Number: 29662 Gerrit-PatchSet: 47 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: York Yang <yyang024(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 17 Jun 2019 17:34:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/hatch: Move memory strap GPIOs under variant gpio header
by Aamir Bohra (Code Review) 17 Jun '19

17 Jun '19

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33541 Change subject: mb/google/hatch: Move memory strap GPIOs under variant gpio header ...................................................................... mb/google/hatch: Move memory strap GPIOs under variant gpio header Move the memory strap gpios to variant/gpio.h, as the memory straps are different for helios. Change-Id: I1833c9539687011ee27fd3e88c0581e30ca59354 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/mainboard/google/hatch/romstage.c M src/mainboard/google/hatch/variants/hatch/include/variant/gpio.h M src/mainboard/google/hatch/variants/hatch_whl/include/variant/gpio.h M src/mainboard/google/hatch/variants/helios/include/variant/gpio.h M src/mainboard/google/hatch/variants/kindred/include/variant/gpio.h M src/mainboard/google/hatch/variants/kohaku/include/variant/gpio.h 6 files changed, 32 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/33541/1 diff --git a/src/mainboard/google/hatch/romstage.c b/src/mainboard/google/hatch/romstage.c index 2c630a8..69fee28 100644 --- a/src/mainboard/google/hatch/romstage.c +++ b/src/mainboard/google/hatch/romstage.c @@ -21,12 +21,7 @@ #include <soc/cnl_memcfg_init.h> #include <soc/romstage.h> #include <string.h> - -/* Memory configuration board straps */ -#define GPIO_MEM_CONFIG_0 GPP_F20 -#define GPIO_MEM_CONFIG_1 GPP_F21 -#define GPIO_MEM_CONFIG_2 GPP_F11 -#define GPIO_MEM_CONFIG_3 GPP_F22 +#include <variant/gpio.h> /* * GPIO_MEM_CH_SEL is set to 1 for single channel skus diff --git a/src/mainboard/google/hatch/variants/hatch/include/variant/gpio.h b/src/mainboard/google/hatch/variants/hatch/include/variant/gpio.h index 5d69eed..e7d8a75 100644 --- a/src/mainboard/google/hatch/variants/hatch/include/variant/gpio.h +++ b/src/mainboard/google/hatch/variants/hatch/include/variant/gpio.h @@ -18,4 +18,10 @@ #include <baseboard/gpio.h> +/* Memory configuration board straps */ +#define GPIO_MEM_CONFIG_0 GPP_F20 +#define GPIO_MEM_CONFIG_1 GPP_F21 +#define GPIO_MEM_CONFIG_2 GPP_F11 +#define GPIO_MEM_CONFIG_3 GPP_F22 + #endif diff --git a/src/mainboard/google/hatch/variants/hatch_whl/include/variant/gpio.h b/src/mainboard/google/hatch/variants/hatch_whl/include/variant/gpio.h index d99e2bb..6bff04e 100644 --- a/src/mainboard/google/hatch/variants/hatch_whl/include/variant/gpio.h +++ b/src/mainboard/google/hatch/variants/hatch_whl/include/variant/gpio.h @@ -18,4 +18,11 @@ #include <baseboard/gpio.h> + +/* Memory configuration board straps */ +#define GPIO_MEM_CONFIG_0 GPP_F20 +#define GPIO_MEM_CONFIG_1 GPP_F21 +#define GPIO_MEM_CONFIG_2 GPP_F11 +#define GPIO_MEM_CONFIG_3 GPP_F22 + #endif diff --git a/src/mainboard/google/hatch/variants/helios/include/variant/gpio.h b/src/mainboard/google/hatch/variants/helios/include/variant/gpio.h index d99e2bb..92f9d41 100644 --- a/src/mainboard/google/hatch/variants/helios/include/variant/gpio.h +++ b/src/mainboard/google/hatch/variants/helios/include/variant/gpio.h @@ -18,4 +18,10 @@ #include <baseboard/gpio.h> +/* Memory configuration board straps */ +#define GPIO_MEM_CONFIG_0 GPP_H19 +#define GPIO_MEM_CONFIG_1 GPP_H22 +#define GPIO_MEM_CONFIG_2 GPP_F10 +#define GPIO_MEM_CONFIG_3 GPP_F3 + #endif diff --git a/src/mainboard/google/hatch/variants/kindred/include/variant/gpio.h b/src/mainboard/google/hatch/variants/kindred/include/variant/gpio.h index d99e2bb..29e5904 100644 --- a/src/mainboard/google/hatch/variants/kindred/include/variant/gpio.h +++ b/src/mainboard/google/hatch/variants/kindred/include/variant/gpio.h @@ -18,4 +18,10 @@ #include <baseboard/gpio.h> +/* Memory configuration board straps */ +#define GPIO_MEM_CONFIG_0 GPP_F20 +#define GPIO_MEM_CONFIG_1 GPP_F21 +#define GPIO_MEM_CONFIG_2 GPP_F11 +#define GPIO_MEM_CONFIG_3 GPP_F22 + #endif diff --git a/src/mainboard/google/hatch/variants/kohaku/include/variant/gpio.h b/src/mainboard/google/hatch/variants/kohaku/include/variant/gpio.h index d99e2bb..29e5904 100644 --- a/src/mainboard/google/hatch/variants/kohaku/include/variant/gpio.h +++ b/src/mainboard/google/hatch/variants/kohaku/include/variant/gpio.h @@ -18,4 +18,10 @@ #include <baseboard/gpio.h> +/* Memory configuration board straps */ +#define GPIO_MEM_CONFIG_0 GPP_F20 +#define GPIO_MEM_CONFIG_1 GPP_F21 +#define GPIO_MEM_CONFIG_2 GPP_F11 +#define GPIO_MEM_CONFIG_3 GPP_F22 + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/33541 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1833c9539687011ee27fd3e88c0581e30ca59354 Gerrit-Change-Number: 33541 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/up/squared: Remove unnecessary code
by Patrick Rudolph (Code Review) 17 Jun '19

17 Jun '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33136 ) Change subject: mb/up/squared: Remove unnecessary code ...................................................................... Patch Set 5: (9 comments) https://review.coreboot.org/#/c/33136/5/src/mainboard/up/squared/ramstage.c File src/mainboard/up/squared/ramstage.c: https://review.coreboot.org/#/c/33136/5/src/mainboard/up/squared/ramstage.c… PS5, Line 32: silconfig->IpuEn = 0x0; // 0x1 set to zero by soc if ipu pci device is set to off in devicetree https://review.coreboot.org/#/c/33136/5/src/mainboard/up/squared/ramstage.c… PS5, Line 46: silconfig->IshEnable = 0x0; // 0x1 set to zero by soc if ish pci device is set to off in devicetree https://review.coreboot.org/#/c/33136/5/src/mainboard/up/squared/ramstage.c… PS5, Line 47: silconfig->SpiEiss = 0x0; // 0x1 set by soc tp zero https://review.coreboot.org/#/c/33136/5/src/mainboard/up/squared/ramstage.c… PS5, Line 49: silconfig->SdcardEnabled = 0x0; // 0x1 set to zero by soc if sdcard pci device is set to off in devicetree https://review.coreboot.org/#/c/33136/5/src/mainboard/up/squared/ramstage.c… PS5, Line 52: silconfig->VtdEnable = 0x1; // 0x0 set by soc if enable_vtd is set in devicetree https://review.coreboot.org/#/c/33136/5/src/mainboard/up/squared/ramstage.c… PS5, Line 53: silconfig->MonitorMwaitEnable = 0x0; // 0x1 set by soc code https://review.coreboot.org/#/c/33136/5/src/mainboard/up/squared/ramstage.c… PS5, Line 57: silconfig->PcieRootPortEn[0] = 0x1; // 0x0 set by soc if PCIe device in devicetree https://review.coreboot.org/#/c/33136/5/src/mainboard/up/squared/ramstage.c… PS5, Line 62: silconfig->PcieRpHotPlug[1] = 0x0; // 0x1 set by soc to register "pcie_rp_hotplug_enable" in devicetree https://review.coreboot.org/#/c/33136/5/src/mainboard/up/squared/ramstage.c… PS5, Line 65: silconfig->PcieRpClkReqNumber[1] = 0x3; // 0x5 set by soc if register "pcie_rp_clkreq_pin" is in devicetree -- To view, visit https://review.coreboot.org/c/coreboot/+/33136 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7dae4f24a9fcb01d2d47063dd3a0f4ce6c120d2 Gerrit-Change-Number: 33136 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 17 Jun 2019 15:42:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: doc/mb/upsquared: Add documentation
by Patrick Rudolph (Code Review) 17 Jun '19

17 Jun '19

Patrick Rudolph has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32935 ) Change subject: doc/mb/upsquared: Add documentation ...................................................................... doc/mb/upsquared: Add documentation This patch adds documentation about the UP² mainboard and the IFWI used by Apollolake platform. Change-Id: Ic708ddbd2616eee4e5ec2740b3eac18b408bde38 Signed-off-by: Felix Singer <felix.singer(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32935 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> --- A Documentation/mainboard/up/squared/bottom.dia M Documentation/mainboard/up/squared/bottom.jpg A Documentation/mainboard/up/squared/header_40pin_gpio_uart1.dia A Documentation/mainboard/up/squared/header_40pin_gpio_uart1.svg A Documentation/mainboard/up/squared/header_cn16_10pin_uart0.dia A Documentation/mainboard/up/squared/header_cn16_10pin_uart0.svg A Documentation/mainboard/up/squared/header_cn22_12pin_spi.dia A Documentation/mainboard/up/squared/header_cn22_12pin_spi.svg M Documentation/mainboard/up/squared/index.md A Documentation/soc/intel/apollolake/flash_layout.dia A Documentation/soc/intel/apollolake/flash_layout.svg A Documentation/soc/intel/apollolake/index.md M Documentation/soc/intel/index.md 13 files changed, 629 insertions(+), 16 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/Documentation/mainboard/up/squared/bottom.dia b/Documentation/mainboard/up/squared/bottom.dia new file mode 100644 index 0000000..f298d66 --- /dev/null +++ b/Documentation/mainboard/up/squared/bottom.dia Binary files differ diff --git a/Documentation/mainboard/up/squared/bottom.jpg b/Documentation/mainboard/up/squared/bottom.jpg index f9aa85d..3c066a2 100644 --- a/Documentation/mainboard/up/squared/bottom.jpg +++ b/Documentation/mainboard/up/squared/bottom.jpg Binary files differ diff --git a/Documentation/mainboard/up/squared/header_40pin_gpio_uart1.dia b/Documentation/mainboard/up/squared/header_40pin_gpio_uart1.dia new file mode 100644 index 0000000..4efc018 --- /dev/null +++ b/Documentation/mainboard/up/squared/header_40pin_gpio_uart1.dia Binary files differ diff --git a/Documentation/mainboard/up/squared/header_40pin_gpio_uart1.svg b/Documentation/mainboard/up/squared/header_40pin_gpio_uart1.svg new file mode 100644 index 0000000..16f6397 --- /dev/null +++ b/Documentation/mainboard/up/squared/header_40pin_gpio_uart1.svg @@ -0,0 +1,126 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?> +<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.0//EN" "http://www.w3.org/TR/2001/PR-SVG-20010719/DTD/svg10.dtd"> +<svg width="14cm" height="10cm" viewBox="399 -216 262 199" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"> + <text font-size="12.8" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:700" x="460" y="-20"> + <tspan x="460" y="-20">40 pin GPIO header</tspan> + </text> + <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="520" y="-175.575"> + <tspan x="520" y="-175.575">GND</tspan> + </text> + <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="560" y="-203.575"> + <tspan x="560" y="-203.575">UART1</tspan> + <tspan x="560" y="-187.575">TX</tspan> + </text> + <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="600" y="-183.575"> + <tspan x="600" y="-183.575">UART1</tspan> + <tspan x="600" y="-167.575">RX</tspan> + </text> + <g> + <rect style="fill: #ffffff" x="400" y="-140" width="260" height="100"/> + <rect style="fill: none; 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Make sure that you have a fully working dump. +```bash +[upsquared]$ ls +firmware_vendor.rom +``` + +```bash +[upsquared]$ mkdir extracted && cd extracted +[extracted]$ ifdtool -x ../firmware_vendor.rom +File ../firmware_vendor.rom is 16777216 bytes +Peculiar firmware descriptor, assuming Ibex Peak compatibility. + Flash Region 0 (Flash Descriptor): 00000000 - 00000fff + Flash Region 1 (BIOS): 00001000 - 00efefff + Flash Region 2 (Intel ME): 07fff000 - 00000fff (unused) + Flash Region 3 (GbE): 07fff000 - 00000fff (unused) + Flash Region 4 (Platform Data): 07fff000 - 00000fff (unused) + Flash Region 5 (Reserved): 00eff000 - 00ffefff + Flash Region 6 (Reserved): 07fff000 - 00000fff (unused) + Flash Region 7 (Reserved): 07fff000 - 00000fff (unused) + Flash Region 8 (EC): 07fff000 - 00000fff (unused) +``` + +```bash +flashregion_0_flashdescriptor.bin +flashregion_1_bios.bin +flashregion_5_reserved.bin +``` + +### Clean up +```bash +[coreboot]$ make distclean +``` + +### Configuring +```bash +[coreboot]$ touch .config +[coreboot]$ ./util/scripts/config --enable VENDOR_UP +[coreboot]$ ./util/scripts/config --enable BOARD_UP_SQUARED +[coreboot]$ ./util/scripts/config --enable NEED_IFWI +[coreboot]$ ./util/scripts/config --enable HAVE_IFD_BIN +[coreboot]$ ./util/scripts/config --set-str IFWI_FILE_NAME "<flashregion_1_bios.bin>" +[coreboot]$ ./util/scripts/config --set-str IFD_BIN_PATH "<flashregion_0_flashdescriptor.bin>" +[coreboot]$ make olddefconfig +``` + +### Building +```bash +[coreboot]$ make +``` + +Now you should have a working and ready to use coreboot build at `build/coreboot.rom`. + +### Flashing +```bash +[coreboot]$ flashrom -p <your_programmer> -w build/coreboot.rom +``` + ## Board status ### Working - bootblock, romstage, ramstage @@ -78,22 +157,13 @@ - mini PCIe - flashing with flashrom internally using Linux -## Building and flashing coreboot -### Building -```bash -make distclean -touch .config -./util/scripts/config --enable VENDOR_UP -./util/scripts/config --enable BOARD_UP_SQUARED -./util/scripts/config --enable NEED_IFWI -./util/scripts/config --enable HAVE_IFD_BIN -./util/scripts/config --set-str IFWI_FILE_NAME "<path_to_your_bios_region>" -./util/scripts/config --set-str IFD_BIN_PATH "<path_to_your_ifd_region>" -make olddefconfig -``` - -### Flashing - +[header_cn16]: header_cn16_10pin_uart0.svg +[header_cn16_link]: #uart0-cn16 +[header_cn22]: header_cn22_12pin_spi.svg +[header_cn22_link]: #using-the-spi-header +[header_gpio]: header_40pin_gpio_uart1.svg +[header_gpio_link]: #uart1-gpio-header [overview_top]: top.jpg [overview_bottom]: bottom.jpg +[overview_bottom_link]: #bottom diff --git a/Documentation/soc/intel/apollolake/flash_layout.dia b/Documentation/soc/intel/apollolake/flash_layout.dia new file mode 100644 index 0000000..4ea5440 --- /dev/null +++ b/Documentation/soc/intel/apollolake/flash_layout.dia Binary files differ diff --git a/Documentation/soc/intel/apollolake/flash_layout.svg b/Documentation/soc/intel/apollolake/flash_layout.svg new file mode 100644 index 0000000..9322875 --- /dev/null +++ b/Documentation/soc/intel/apollolake/flash_layout.svg @@ -0,0 +1,122 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?> +<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.0//EN" "http://www.w3.org/TR/2001/PR-SVG-20010719/DTD/svg10.dtd"> +<svg width="38cm" height="18cm" viewBox="118 98 744 344" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"> + <g> + <rect style="fill: #ffffff" x="620" y="100" width="180" height="60"/> + <rect style="fill: none; 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fill-opacity:0; stroke-width: 2; stroke: #000000" d="M 120 380 C 120,320 240,360 240,311"/> + <polygon style="fill: #000000" points="245,311 240,301 235,311 "/> + <polygon style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" points="245,311 240,301 235,311 "/> + </g> +</svg> diff --git a/Documentation/soc/intel/apollolake/index.md b/Documentation/soc/intel/apollolake/index.md new file mode 100644 index 0000000..d4a5ee5 --- /dev/null +++ b/Documentation/soc/intel/apollolake/index.md @@ -0,0 +1,17 @@ +# Apollolake +## SPI flash layout + +![][apl_flash_layout] + +With Apollolake Intel invented another flash layout for x86 firmware called IFWI (Intel FirmWare Image). + +Usually on x86 platforms the bootblock is stored at the end of the bios region +and the Intel ME / TXE has its own IFD region. On Apollolake both have been +moved into the IFWI region, which is a subregion of "BIOS", since it allows to +store multiple firmware components. + +The IFWI region can be manipulated by `ifwitool`. + +[apl_flash_layout]: flash_layout.svg + + diff --git a/Documentation/soc/intel/index.md b/Documentation/soc/intel/index.md index 86f4de7..f30ff9a 100644 --- a/Documentation/soc/intel/index.md +++ b/Documentation/soc/intel/index.md @@ -9,3 +9,4 @@ - [Ice Lake/9th Gen Core-i series](icelake/index.md) - [MP Initialization](mp_init/mp_init.md) - [Firmware Interface Table](fit.md) +- [Apollolake](apollolake/index.md) -- To view, visit https://review.coreboot.org/c/coreboot/+/32935 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic708ddbd2616eee4e5ec2740b3eac18b408bde38 Gerrit-Change-Number: 32935 Gerrit-PatchSet: 9 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in ...libgfxinit[master]: gma pipe setup: Fix secondary pipe cursors <= Sandy Bridge
by Reto Buerki (Code Review) 17 Jun '19

17 Jun '19

Reto Buerki has posted comments on this change. ( https://review.coreboot.org/c/libgfxinit/+/27154 ) Change subject: gma pipe setup: Fix secondary pipe cursors <= Sandy Bridge ...................................................................... Patch Set 3: Code-Review+1 (1 comment) https://review.coreboot.org/#/c/27154/3/common/hw-gfx-gma-pipe_setup.ads File common/hw-gfx-gma-pipe_setup.ads: https://review.coreboot.org/#/c/27154/3/common/hw-gfx-gma-pipe_setup.ads@244 PS3, Line 244: FBC_CTL : Registers.Registers_Invalid_Index; > Everything is aligned to a multiple of 3 here. I don't have a written […] Ah ic, I did not know that it is aligned to a multiple of 3. I'm not aware of an internal style guide which applies here. -- To view, visit https://review.coreboot.org/c/libgfxinit/+/27154 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I4d79f59a8cb693d73d6da666525f091021efb4fd Gerrit-Change-Number: 27154 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Adrian-Ken Rueegsegger <ken(a)codelabs.ch> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Reto Buerki <reet(a)codelabs.ch> Gerrit-Comment-Date: Mon, 17 Jun 2019 13:29:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Reto Buerki <reet(a)codelabs.ch> Gerrit-MessageType: comment

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Change in ...libgfxinit[master]: gma pipe setup: Fix secondary pipe cursors <= Sandy Bridge
by Nico Huber (Code Review) 17 Jun '19

17 Jun '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/libgfxinit/+/27154 ) Change subject: gma pipe setup: Fix secondary pipe cursors <= Sandy Bridge ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/#/c/27154/3/common/hw-gfx-gma-pipe_setup.ads File common/hw-gfx-gma-pipe_setup.ads: https://review.coreboot.org/#/c/27154/3/common/hw-gfx-gma-pipe_setup.ads@244 PS3, Line 244: FBC_CTL : Registers.Registers_Invalid_Index; > Minor: Remove one whitespace before :? Everything is aligned to a multiple of 3 here. I don't have a written style guide, do you (or do we, internally)? -- To view, visit https://review.coreboot.org/c/libgfxinit/+/27154 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I4d79f59a8cb693d73d6da666525f091021efb4fd Gerrit-Change-Number: 27154 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Adrian-Ken Rueegsegger <ken(a)codelabs.ch> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Reto Buerki <reet(a)codelabs.ch> Gerrit-Comment-Date: Mon, 17 Jun 2019 13:18:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Reto Buerki <reet(a)codelabs.ch> Gerrit-MessageType: comment

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coreboot-gerrit June 2019