coreboot-gerrit June 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: superio/nuvoton/nct6776: Make Kconfig symbol dependent
by Angel Pons (Code Review) 13 Jun '19

13 Jun '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33440 ) Change subject: superio/nuvoton/nct6776: Make Kconfig symbol dependent ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/33440 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c52d596080360bf3fc25265749ced66ec44f5dc Gerrit-Change-Number: 33440 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 13 Jun 2019 12:13:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: Set ENV_PAYLOAD_LOADER to ENV_POSTCAR when CONFIG_RAMPAYLOAD is enable
by Subrata Banik (Code Review) 13 Jun '19

13 Jun '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32751 Change subject: Set ENV_PAYLOAD_LOADER to ENV_POSTCAR when CONFIG_RAMPAYLOAD is enable ...................................................................... Set ENV_PAYLOAD_LOADER to ENV_POSTCAR when CONFIG_RAMPAYLOAD is enable Change-Id: I416c74ea83ee68370bbeb53834054bcb18e631e1 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/include/rules.h 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/32751/1 diff --git a/src/include/rules.h b/src/include/rules.h index 801a7fe..5ee535b 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -257,9 +257,14 @@ #endif +#if CONFIG(RAMPAYLOAD) +/* ENV_PAYLOAD_LOADER is set to ENV_POSTCAR when CONFIG_RAMPAYLOAD is enable */ +#define ENV_PAYLOAD_LOADER ENV_POSTCAR +#else /* ENV_PAYLOAD_LOADER is set when you are in a stage that loads the payload. * For now, that is the ramstage. */ #define ENV_PAYLOAD_LOADER ENV_RAMSTAGE +#endif /** * For pre-DRAM stages and post-CAR always build with simple device model, ie. -- To view, visit https://review.coreboot.org/c/coreboot/+/32751 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I416c74ea83ee68370bbeb53834054bcb18e631e1 Gerrit-Change-Number: 32751 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

3 19

Change in ...coreboot[master]: stage_cache: Add into stage_cache if !CONFIG_NO_STAGE_CACHE
by Subrata Banik (Code Review) 13 Jun '19

13 Jun '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33394 Change subject: stage_cache: Add into stage_cache if !CONFIG_NO_STAGE_CACHE ...................................................................... stage_cache: Add into stage_cache if !CONFIG_NO_STAGE_CACHE Change-Id: I8e10ef2d261f9b204cecbeae6f65fda037753534 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/drivers/intel/fsp1_1/ramstage.c M src/drivers/intel/fsp2_0/silicon_init.c M src/soc/intel/baytrail/refcode.c M src/soc/intel/broadwell/refcode.c 4 files changed, 8 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/33394/1 diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c index 814bddf..a55df95 100644 --- a/src/drivers/intel/fsp1_1/ramstage.c +++ b/src/drivers/intel/fsp1_1/ramstage.c @@ -165,7 +165,8 @@ return; } - stage_cache_add(STAGE_REFCODE, fsp); + if (!CONFIG(NO_STAGE_CACHE)) + stage_cache_add(STAGE_REFCODE, fsp); } static int fsp_find_and_relocate(struct prog *fsp) diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index e72e4ac..ab9951d 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -128,7 +128,8 @@ prog_set_area(&fsps, dest, size); - stage_cache_add(STAGE_REFCODE, &fsps); + if (!CONFIG(NO_STAGE_CACHE)) + stage_cache_add(STAGE_REFCODE, &fsps); /* Signal that FSP component has been loaded. */ prog_segment_loaded(hdr->image_base, hdr->image_size, SEG_FINAL); diff --git a/src/soc/intel/baytrail/refcode.c b/src/soc/intel/baytrail/refcode.c index 24469ea..daf3d1a 100644 --- a/src/soc/intel/baytrail/refcode.c +++ b/src/soc/intel/baytrail/refcode.c @@ -65,7 +65,8 @@ } /* Cache loaded reference code. */ - stage_cache_add(STAGE_REFCODE, &prog); + if (!CONFIG(NO_STAGE_CACHE)) + stage_cache_add(STAGE_REFCODE, &prog); return prog_entry(&prog); } diff --git a/src/soc/intel/broadwell/refcode.c b/src/soc/intel/broadwell/refcode.c index 6d192cc..63decaf 100644 --- a/src/soc/intel/broadwell/refcode.c +++ b/src/soc/intel/broadwell/refcode.c @@ -61,7 +61,8 @@ } /* Cache loaded reference code. */ - stage_cache_add(STAGE_REFCODE, &prog); + if (!CONFIG(NO_STAGE_CACHE)) + stage_cache_add(STAGE_REFCODE, &prog); return (pei_wrapper_entry_t)prog_entry(&prog); } -- To view, visit https://review.coreboot.org/c/coreboot/+/33394 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e10ef2d261f9b204cecbeae6f65fda037753534 Gerrit-Change-Number: 33394 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

4 17

Change in ...coreboot[master]: mb/google/{hatch, sarien, arcada}: Make HECI1 chip config disable
by Subrata Banik (Code Review) 13 Jun '19

13 Jun '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33194 Change subject: mb/google/{hatch, sarien, arcada}: Make HECI1 chip config disable ...................................................................... mb/google/{hatch, sarien, arcada}: Make HECI1 chip config disable Change-Id: Ia88f3315a9dc3365d0acc13ed887e7c596c97c91 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb 3 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/33194/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 9d10cac..fba8d96 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -28,7 +28,7 @@ # Enable System Agent dynamic frequency register "SaGv" = "SaGv_Enabled" # Enable heci communication - register "HeciEnabled" = "1" + register "HeciEnabled" = "0" # Enable Speed Shift Technology support register "speed_shift_enable" = "1" # Enable S0ix diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 767df1f..ce960a7 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -15,7 +15,7 @@ # FSP configuration register "SaGv" = "SaGv_Enabled" - register "HeciEnabled" = "1" + register "HeciEnabled" = "0" register "SataSalpSupport" = "1" register "SataMode" = "Sata_AHCI" register "SataPortsEnable[2]" = "1" diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index c96423c..739a849 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -15,7 +15,7 @@ # FSP configuration register "SaGv" = "SaGv_Enabled" - register "HeciEnabled" = "1" + register "HeciEnabled" = "0" register "SataSalpSupport" = "1" register "SataMode" = "Sata_AHCI" register "SataPortsEnable[0]" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/33194 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia88f3315a9dc3365d0acc13ed887e7c596c97c91 Gerrit-Change-Number: 33194 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/{cml, whl}: Add option to skip HECI function disable in SMM
by Subrata Banik (Code Review) 13 Jun '19

13 Jun '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33193 Change subject: soc/intel/{cml, whl}: Add option to skip HECI function disable in SMM ...................................................................... soc/intel/{cml, whl}: Add option to skip HECI function disable in SMM This patch provides an additional option to skip HECI function disabling using SMM mode for WHL and CML platform, where FSP has dedicated UPD to make HECI function disable. User to select SKIP_HECI_FUNCTION_DISABLE_USING_SMM if FSP has provided dedicated UPD. Change-Id: If3b064f3c32877235916f966a01beb525156d188 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/smihandler.c M src/soc/intel/common/block/smm/Kconfig M src/soc/intel/icelake/smihandler.c 4 files changed, 15 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/33193/1 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 76906b2..fd87a5f 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -27,6 +27,7 @@ bool default n select SOC_INTEL_COMMON_CANNONLAKE_BASE + select SKIP_HECI_FUNCTION_DISABLE_USING_SMM if CHROMEOS help Intel Whiskeylake support @@ -34,6 +35,7 @@ bool default n select SOC_INTEL_COMMON_CANNONLAKE_BASE + select SKIP_HECI_FUNCTION_DISABLE_USING_SMM if CHROMEOS help Intel Cometlake support diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c index 9af2917..2673bc5 100644 --- a/src/soc/intel/cannonlake/smihandler.c +++ b/src/soc/intel/cannonlake/smihandler.c @@ -88,7 +88,8 @@ config = dev->chip_info; - if (config->HeciEnabled == 0) + if (!config->HeciEnabled && + !CONFIG(SKIP_HECI_FUNCTION_DISABLE_USING_SMM)) pch_disable_heci(); } diff --git a/src/soc/intel/common/block/smm/Kconfig b/src/soc/intel/common/block/smm/Kconfig index a58c631..ae522f4 100644 --- a/src/soc/intel/common/block/smm/Kconfig +++ b/src/soc/intel/common/block/smm/Kconfig @@ -23,3 +23,12 @@ Time in milliseconds that SLP_SMI for S5 waits for before enabling sleep. This is required to avoid any race between SLP_SMI and PWRBTN SMI. + +config SKIP_HECI_FUNCTION_DISABLE_USING_SMM + bool + depends on SOC_INTEL_COMMON_BLOCK_SMM + default n + help + This Kconfig will help to skip HECI function disable using + SMM mode. User to only select this option if FSP provide + dedicated UPD to perform HECI function disable. diff --git a/src/soc/intel/icelake/smihandler.c b/src/soc/intel/icelake/smihandler.c index 5c00b63..60e7f80 100644 --- a/src/soc/intel/icelake/smihandler.c +++ b/src/soc/intel/icelake/smihandler.c @@ -86,7 +86,8 @@ config = dev->chip_info; - if (config->HeciEnabled == 0) + if (!config->HeciEnabled && + !CONFIG(SKIP_HECI_FUNCTION_DISABLE_USING_SMM)) pch_disable_heci(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/33193 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3b064f3c32877235916f966a01beb525156d188 Gerrit-Change-Number: 33193 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

6 27

Change in ...coreboot[master]: soc/intel/icelake: Replace PCI device LPC to ESPI as per EDS
by Subrata Banik (Code Review) 13 Jun '19

13 Jun '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33190 Change subject: soc/intel/icelake: Replace PCI device LPC to ESPI as per EDS ...................................................................... soc/intel/icelake: Replace PCI device LPC to ESPI as per EDS As per Icelake EDS PCI device B:D:F (0:0x1f:0) referred as ESPI, hence modify SoC code to reflect the same. Change-Id: I4990ea6d9b7b4c0eac2b3eea559f5469f086e827 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/include/device/pci_ids.h M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/icelake/Makefile.inc M src/soc/intel/icelake/acpi.c R src/soc/intel/icelake/acpi/espi.asl M src/soc/intel/icelake/acpi/southbridge.asl M src/soc/intel/icelake/bootblock/pch.c M src/soc/intel/icelake/bootblock/report_platform.c M src/soc/intel/icelake/chip.c R src/soc/intel/icelake/espi.c R src/soc/intel/icelake/include/soc/espi.h M src/soc/intel/icelake/include/soc/pci_devs.h M src/soc/intel/icelake/pmutil.c M src/soc/intel/icelake/romstage/fsp_params.c 14 files changed, 60 insertions(+), 57 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/33190/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index a35e134..795e4c0 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2723,13 +2723,13 @@ #define PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC 0x9d83 #define PCI_DEVICE_ID_INTEL_CNP_H_LPC_Q370 0xa306 #define PCI_DEVICE_ID_INTEL_CNP_H_LPC_QM370 0xa30c -#define PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_LPC 0x3480 -#define PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_LPC_REV0 0x3481 -#define PCI_DEVICE_ID_INTEL_ICL_U_PREMIUM_LPC 0x3482 -#define PCI_DEVICE_ID_INTEL_ICL_BASE_Y_LPC 0x3483 -#define PCI_DEVICE_ID_INTEL_ICL_BASE_U_LPC 0x3484 -#define PCI_DEVICE_ID_INTEL_ICL_Y_PREMIUM_LPC 0x3487 -#define PCI_DEVICE_ID_INTEL_ICL_SUPER_Y_LPC 0x3486 +#define PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_ESPI 0x3480 +#define PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_ESPI_REV0 0x3481 +#define PCI_DEVICE_ID_INTEL_ICL_U_PREMIUM_ESPI 0x3482 +#define PCI_DEVICE_ID_INTEL_ICL_BASE_Y_ESPI 0x3483 +#define PCI_DEVICE_ID_INTEL_ICL_BASE_U_ESPI 0x3484 +#define PCI_DEVICE_ID_INTEL_ICL_Y_PREMIUM_ESPI 0x3487 +#define PCI_DEVICE_ID_INTEL_ICL_SUPER_Y_ESPI 0x3486 #define PCI_DEVICE_ID_INTEL_CMP_SUPER_U_LPC 0x0281 #define PCI_DEVICE_ID_INTEL_CMP_PREMIUM_Y_LPC 0x0283 #define PCI_DEVICE_ID_INTEL_CMP_PREMIUM_U_LPC 0x0284 diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index 86547a4..7e78bf9 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -156,13 +156,13 @@ PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC, PCI_DEVICE_ID_INTEL_CNP_H_LPC_Q370, PCI_DEVICE_ID_INTEL_CNP_H_LPC_QM370, - PCI_DEVICE_ID_INTEL_ICL_BASE_U_LPC, - PCI_DEVICE_ID_INTEL_ICL_BASE_Y_LPC, - PCI_DEVICE_ID_INTEL_ICL_U_PREMIUM_LPC, - PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_LPC, - PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_LPC_REV0, - PCI_DEVICE_ID_INTEL_ICL_SUPER_Y_LPC, - PCI_DEVICE_ID_INTEL_ICL_Y_PREMIUM_LPC, + PCI_DEVICE_ID_INTEL_ICL_BASE_U_ESPI, + PCI_DEVICE_ID_INTEL_ICL_BASE_Y_ESPI, + PCI_DEVICE_ID_INTEL_ICL_U_PREMIUM_ESPI, + PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_ESPI, + PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_ESPI_REV0, + PCI_DEVICE_ID_INTEL_ICL_SUPER_Y_ESPI, + PCI_DEVICE_ID_INTEL_ICL_Y_PREMIUM_ESPI, PCI_DEVICE_ID_INTEL_CMP_SUPER_U_LPC, PCI_DEVICE_ID_INTEL_CMP_PREMIUM_Y_LPC, PCI_DEVICE_ID_INTEL_CMP_PREMIUM_U_LPC, diff --git a/src/soc/intel/icelake/Makefile.inc b/src/soc/intel/icelake/Makefile.inc index cd6a6ba..0d4e32d 100644 --- a/src/soc/intel/icelake/Makefile.inc +++ b/src/soc/intel/icelake/Makefile.inc @@ -13,19 +13,19 @@ bootblock-y += bootblock/pch.c bootblock-y += pmutil.c bootblock-y += bootblock/report_platform.c +bootblock-y += espi.c bootblock-y += gpio.c bootblock-y += gspi.c bootblock-y += i2c.c bootblock-y += memmap.c bootblock-y += spi.c -bootblock-y += lpc.c bootblock-y += p2sb.c bootblock-y += uart.c +romstage-y += espi.c romstage-y += gpio.c romstage-y += gspi.c romstage-y += i2c.c -romstage-y += lpc.c romstage-y += memmap.c romstage-y += pmutil.c romstage-y += reset.c @@ -36,6 +36,7 @@ ramstage-y += chip.c ramstage-y += cpu.c ramstage-y += elog.c +ramstage-y += espi.c ramstage-y += finalize.c ramstage-y += fsp_params.c ramstage-y += gpio.c @@ -44,7 +45,6 @@ ramstage-y += gpio.c ramstage-y += i2c.c ramstage-y += lockdown.c -ramstage-y += lpc.c ramstage-y += memmap.c ramstage-y += p2sb.c ramstage-y += pmc.c diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c index f16469e..4dbd17e 100644 --- a/src/soc/intel/icelake/acpi.c +++ b/src/soc/intel/icelake/acpi.c @@ -169,7 +169,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt) { const uint16_t pmbase = ACPI_BASE_ADDRESS; - const struct device *dev = PCH_DEV_LPC; + const struct device *dev = PCH_DEV_ESPI; const struct soc_intel_icelake_config *config = dev->chip_info; if (!config->PmTimerDisabled) { @@ -194,7 +194,7 @@ void acpi_create_gnvs(struct global_nvs_t *gnvs) { - const struct device *dev = PCH_DEV_LPC; + const struct device *dev = PCH_DEV_ESPI; const struct soc_intel_icelake_config *config = dev->chip_info; /* Set unknown wake source */ diff --git a/src/soc/intel/icelake/acpi/lpc.asl b/src/soc/intel/icelake/acpi/espi.asl similarity index 96% rename from src/soc/intel/icelake/acpi/lpc.asl rename to src/soc/intel/icelake/acpi/espi.asl index f936392..4456812 100644 --- a/src/soc/intel/icelake/acpi/lpc.asl +++ b/src/soc/intel/icelake/acpi/espi.asl @@ -13,10 +13,12 @@ * GNU General Public License for more details. */ + +/* Device identifier is not changed to ESPI to maintain coherency with ec.asl */ Device (LPCB) { Name (_ADR, 0x001f0000) - Name (_DDN, "LPC Bus Device") + Name (_DDN, "ESPI Bus Device") Device (FWH) { diff --git a/src/soc/intel/icelake/acpi/southbridge.asl b/src/soc/intel/icelake/acpi/southbridge.asl index 1b9abe6..ffd2fcc 100644 --- a/src/soc/intel/icelake/acpi/southbridge.asl +++ b/src/soc/intel/icelake/acpi/southbridge.asl @@ -32,8 +32,8 @@ /* GPIO controller */ #include "gpio.asl" -/* LPC 0:1f.0 */ -#include "lpc.asl" +/* ESPI 0:1f.0 */ +#include "espi.asl" /* PCH HDA */ #include "pch_hda.asl" diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c index 0940791..60ab006 100644 --- a/src/soc/intel/icelake/bootblock/pch.c +++ b/src/soc/intel/icelake/bootblock/pch.c @@ -26,8 +26,8 @@ #include <intelblocks/smbus.h> #include <intelblocks/tco.h> #include <soc/bootblock.h> +#include <soc/espi.h> #include <soc/iomap.h> -#include <soc/lpc.h> #include <soc/p2sb.h> #include <soc/pch.h> #include <soc/pci_devs.h> diff --git a/src/soc/intel/icelake/bootblock/report_platform.c b/src/soc/intel/icelake/bootblock/report_platform.c index e7c010e..314a7b1 100644 --- a/src/soc/intel/icelake/bootblock/report_platform.c +++ b/src/soc/intel/icelake/bootblock/report_platform.c @@ -49,13 +49,13 @@ u16 lpcid; const char *name; } pch_table[] = { - { PCI_DEVICE_ID_INTEL_ICL_BASE_U_LPC, "Icelake-U Base" }, - { PCI_DEVICE_ID_INTEL_ICL_BASE_Y_LPC, "Icelake-Y Base" }, - { PCI_DEVICE_ID_INTEL_ICL_U_PREMIUM_LPC, "Icelake-U Premium" }, - { PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_LPC, "Icelake-U Super" }, - { PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_LPC_REV0, "Icelake-U Super REV0" }, - { PCI_DEVICE_ID_INTEL_ICL_SUPER_Y_LPC, "Icelake-Y Super" }, - { PCI_DEVICE_ID_INTEL_ICL_Y_PREMIUM_LPC, "Icelake-Y Premium" }, + { PCI_DEVICE_ID_INTEL_ICL_BASE_U_ESPI, "Icelake-U Base" }, + { PCI_DEVICE_ID_INTEL_ICL_BASE_Y_ESPI, "Icelake-Y Base" }, + { PCI_DEVICE_ID_INTEL_ICL_U_PREMIUM_ESPI, "Icelake-U Premium" }, + { PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_ESPI, "Icelake-U Super" }, + { PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_ESPI_REV0, "Icelake-U Super REV0" }, + { PCI_DEVICE_ID_INTEL_ICL_SUPER_Y_ESPI, "Icelake-Y Super" }, + { PCI_DEVICE_ID_INTEL_ICL_Y_PREMIUM_ESPI, "Icelake-Y Premium" }, }; static struct { @@ -170,7 +170,7 @@ static void report_pch_info(void) { int i; - pci_devfn_t dev = PCH_DEV_LPC; + pci_devfn_t dev = PCH_DEV_ESPI; uint16_t lpcid = get_dev_id(dev); const char *pch_type = "Unknown"; diff --git a/src/soc/intel/icelake/chip.c b/src/soc/intel/icelake/chip.c index 2616db1..eff1c7a 100644 --- a/src/soc/intel/icelake/chip.c +++ b/src/soc/intel/icelake/chip.c @@ -89,7 +89,8 @@ case PCH_DEVFN_GSPI2: return "SPI2"; case PCH_DEVFN_EMMC: return "EMMC"; case PCH_DEVFN_SDCARD: return "SDXC"; - case PCH_DEVFN_LPC: return "LPCB"; + /* Keeping ACPI device name coherent with ec.asl */ + case PCH_DEVFN_ESPI: return "LPCB"; case PCH_DEVFN_P2SB: return "P2SB"; case PCH_DEVFN_PMC: return "PMC_"; case PCH_DEVFN_HDA: return "HDAS"; diff --git a/src/soc/intel/icelake/lpc.c b/src/soc/intel/icelake/espi.c similarity index 99% rename from src/soc/intel/icelake/lpc.c rename to src/soc/intel/icelake/espi.c index 3d05824..cca185c 100644 --- a/src/soc/intel/icelake/lpc.c +++ b/src/soc/intel/icelake/espi.c @@ -24,9 +24,9 @@ #include <intelblocks/lpc_lib.h> #include <intelblocks/pcr.h> #include <reg_script.h> +#include <soc/espi.h> #include <soc/iomap.h> #include <soc/irq.h> -#include <soc/lpc.h> #include <soc/pci_devs.h> #include <soc/pcr_ids.h> diff --git a/src/soc/intel/icelake/include/soc/lpc.h b/src/soc/intel/icelake/include/soc/espi.h similarity index 93% rename from src/soc/intel/icelake/include/soc/lpc.h rename to src/soc/intel/icelake/include/soc/espi.h index ebfcaa8..9308433 100644 --- a/src/soc/intel/icelake/include/soc/lpc.h +++ b/src/soc/intel/icelake/include/soc/espi.h @@ -13,12 +13,10 @@ * GNU General Public License for more details. */ -#ifndef _SOC_ICELAKE_LPC_H_ -#define _SOC_ICELAKE_LPC_H_ +#ifndef _SOC_ICELAKE_ESPI_H_ +#define _SOC_ICELAKE_ESPI_H_ -#include <stdint.h> - -/* PCI Configuration Space (D31:F0): LPC */ +/* PCI Configuration Space (D31:F0): ESPI */ #define SCI_IRQ_SEL (7 << 0) #define SCIS_IRQ9 0 #define SCIS_IRQ10 1 diff --git a/src/soc/intel/icelake/include/soc/pci_devs.h b/src/soc/intel/icelake/include/soc/pci_devs.h index 3cb06172..889b5c5 100644 --- a/src/soc/intel/icelake/include/soc/pci_devs.h +++ b/src/soc/intel/icelake/include/soc/pci_devs.h @@ -171,22 +171,24 @@ #define PCH_DEV_GSPI0 _PCH_DEV(SIO3, 2) #define PCH_DEV_GSPI1 _PCH_DEV(SIO3, 3) -#define PCH_DEV_SLOT_LPC 0x1f -#define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0) -#define PCH_DEVFN_P2SB _PCH_DEVFN(LPC, 1) -#define PCH_DEVFN_PMC _PCH_DEVFN(LPC, 2) -#define PCH_DEVFN_HDA _PCH_DEVFN(LPC, 3) -#define PCH_DEVFN_SMBUS _PCH_DEVFN(LPC, 4) -#define PCH_DEVFN_SPI _PCH_DEVFN(LPC, 5) -#define PCH_DEVFN_GBE _PCH_DEVFN(LPC, 6) -#define PCH_DEVFN_TRACEHUB _PCH_DEVFN(LPC, 7) -#define PCH_DEV_LPC _PCH_DEV(LPC, 0) -#define PCH_DEV_P2SB _PCH_DEV(LPC, 1) -#define PCH_DEV_PMC _PCH_DEV(LPC, 2) -#define PCH_DEV_HDA _PCH_DEV(LPC, 3) -#define PCH_DEV_SMBUS _PCH_DEV(LPC, 4) -#define PCH_DEV_SPI _PCH_DEV(LPC, 5) -#define PCH_DEV_GBE _PCH_DEV(LPC, 6) -#define PCH_DEV_TRACEHUB _PCH_DEV(LPC, 7) +#define PCH_DEV_SLOT_ESPI 0x1f +#define PCH_DEV_SLOT_LPC PCH_DEV_SLOT_ESPI +#define PCH_DEVFN_ESPI _PCH_DEVFN(ESPI, 0) +#define PCH_DEVFN_P2SB _PCH_DEVFN(ESPI, 1) +#define PCH_DEVFN_PMC _PCH_DEVFN(ESPI, 2) +#define PCH_DEVFN_HDA _PCH_DEVFN(ESPI, 3) +#define PCH_DEVFN_SMBUS _PCH_DEVFN(ESPI, 4) +#define PCH_DEVFN_SPI _PCH_DEVFN(ESPI, 5) +#define PCH_DEVFN_GBE _PCH_DEVFN(ESPI, 6) +#define PCH_DEVFN_TRACEHUB _PCH_DEVFN(ESPI, 7) +#define PCH_DEV_ESPI _PCH_DEV(ESPI, 0) +#define PCH_DEV_LPC PCH_DEV_ESPI +#define PCH_DEV_P2SB _PCH_DEV(ESPI, 1) +#define PCH_DEV_PMC _PCH_DEV(ESPI, 2) +#define PCH_DEV_HDA _PCH_DEV(ESPI, 3) +#define PCH_DEV_SMBUS _PCH_DEV(ESPI, 4) +#define PCH_DEV_SPI _PCH_DEV(ESPI, 5) +#define PCH_DEV_GBE _PCH_DEV(ESPI, 6) +#define PCH_DEV_TRACEHUB _PCH_DEV(ESPI, 7) #endif diff --git a/src/soc/intel/icelake/pmutil.c b/src/soc/intel/icelake/pmutil.c index 1c47783..cdb39ad 100644 --- a/src/soc/intel/icelake/pmutil.c +++ b/src/soc/intel/icelake/pmutil.c @@ -30,10 +30,10 @@ #include <intelblocks/rtc.h> #include <intelblocks/tco.h> #include <stdlib.h> +#include <soc/espi.h> #include <soc/gpe.h> #include <soc/gpio.h> #include <soc/iomap.h> -#include <soc/lpc.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/smbus.h> diff --git a/src/soc/intel/icelake/romstage/fsp_params.c b/src/soc/intel/icelake/romstage/fsp_params.c index 86788a5..ba06803 100644 --- a/src/soc/intel/icelake/romstage/fsp_params.c +++ b/src/soc/intel/icelake/romstage/fsp_params.c @@ -66,7 +66,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { - const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC); + const struct device *dev = dev_find_slot(0, PCH_DEVFN_ESPI); assert(dev != NULL); const config_t *config = dev->chip_info; FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; -- To view, visit https://review.coreboot.org/c/coreboot/+/33190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4990ea6d9b7b4c0eac2b3eea559f5469f086e827 Gerrit-Change-Number: 33190 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

5 25

Change in ...coreboot[master]: ACPI: Add SPCR table
by Kyösti Mälkki (Code Review) 13 Jun '19

13 Jun '19

Kyösti Mälkki has removed a vote on this change. Change subject: ACPI: Add SPCR table ...................................................................... Removed Code-Review-2 by Kyösti Mälkki <kyosti.malkki(a)gmail.com> -- To view, visit https://review.coreboot.org/c/coreboot/+/25344 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ff31da061c88a6f3e3cf76285f8ab78ee35509c Gerrit-Change-Number: 25344 Gerrit-PatchSet: 6 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)chromium.org> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: deleteVote

1 0

Change in ...coreboot[master]: mb/google/hatch: Create kled variant
by David Wu (Code Review) 13 Jun '19

13 Jun '19

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33354 Change subject: mb/google/hatch: Create kled variant ...................................................................... mb/google/hatch: Create kled variant Create Kled (hatch variant). Currenly copy from kindred. Kled-specific changes will come later. BUG=b:134612133 BRANCH=NONE TEST=util/abuild/abuild -p none -t google/hatch -x -a make sure the build includes GOOGLE_KLED Change-Id: I9a4f25db768baeba598a0baa3ed23b64868cba4a Signed-off-by: David Wu <David_Wu(a)quanta.corp-partner.google.com> --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/Kconfig.name A src/mainboard/google/hatch/variants/kled/Makefile.inc A src/mainboard/google/hatch/variants/kled/include/variant/acpi/dptf.asl A src/mainboard/google/hatch/variants/kled/include/variant/ec.h A src/mainboard/google/hatch/variants/kled/include/variant/gpio.h A src/mainboard/google/hatch/variants/kled/overridetree.cb 7 files changed, 245 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/33354/1 diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 8045129..8eb3570 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -66,6 +66,7 @@ default "HATCH_WHL TEST 2374" if BOARD_GOOGLE_HATCH_WHL default "HELIOS TEST 0878" if BOARD_GOOGLE_HELIOS default "KINDRED TEST 2636" if BOARD_GOOGLE_KINDRED + default "KLED TEST 3074" if BOARD_GOOGLE_KLED default "KOHAKU TEST 1953" if BOARD_GOOGLE_KOHAKU config MAINBOARD_DIR @@ -82,6 +83,7 @@ default "Hatch_whl" if BOARD_GOOGLE_HATCH_WHL default "Helios" if BOARD_GOOGLE_HELIOS default "Kindred" if BOARD_GOOGLE_KINDRED + default "Kled" if BOARD_GOOGLE_KLED default "Kohaku" if BOARD_GOOGLE_KOHAKU config MAINBOARD_VENDOR @@ -106,6 +108,7 @@ default "hatch_whl" if BOARD_GOOGLE_HATCH_WHL default "helios" if BOARD_GOOGLE_HELIOS default "kindred" if BOARD_GOOGLE_KINDRED + default "kled" if BOARD_GOOGLE_KLED default "kohaku" if BOARD_GOOGLE_KOHAKU config VBOOT diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index 9a25725..bd6a6bb 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -29,3 +29,9 @@ select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_ROMSIZE_KB_16384 select SOC_INTEL_COMETLAKE + +config BOARD_GOOGLE_KLED + bool "-> Kled" + select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_ROMSIZE_KB_16384 + select SOC_INTEL_COMETLAKE diff --git a/src/mainboard/google/hatch/variants/kled/Makefile.inc b/src/mainboard/google/hatch/variants/kled/Makefile.inc new file mode 100644 index 0000000..8173ca4 --- /dev/null +++ b/src/mainboard/google/hatch/variants/kled/Makefile.inc @@ -0,0 +1,20 @@ +## This file is part of the coreboot project. +## +## Copyright 2019 Google LLC +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_SOURCES = 4G_2400 # 0b000 +SPD_SOURCES += empty_ddr4 # 0b001 +SPD_SOURCES += 8G_2400 # 0b010 +SPD_SOURCES += 8G_2666 # 0b011 +SPD_SOURCES += 16G_2400 # 0b100 +SPD_SOURCES += 16G_2666 # 0b101 diff --git a/src/mainboard/google/hatch/variants/kled/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/kled/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..f1f0943 --- /dev/null +++ b/src/mainboard/google/hatch/variants/kled/include/variant/acpi/dptf.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/acpi/dptf.asl> diff --git a/src/mainboard/google/hatch/variants/kled/include/variant/ec.h b/src/mainboard/google/hatch/variants/kled/include/variant/ec.h new file mode 100644 index 0000000..768987d --- /dev/null +++ b/src/mainboard/google/hatch/variants/kled/include/variant/ec.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_EC_H +#define VARIANT_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/hatch/variants/kled/include/variant/gpio.h b/src/mainboard/google/hatch/variants/kled/include/variant/gpio.h new file mode 100644 index 0000000..d99e2bb --- /dev/null +++ b/src/mainboard/google/hatch/variants/kled/include/variant/gpio.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +#endif diff --git a/src/mainboard/google/hatch/variants/kled/overridetree.cb b/src/mainboard/google/hatch/variants/kled/overridetree.cb new file mode 100644 index 0000000..562bb8b --- /dev/null +++ b/src/mainboard/google/hatch/variants/kled/overridetree.cb @@ -0,0 +1,158 @@ +chip soc/intel/cannonlake + + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexSPI0] = PchSerialIoPci, + [PchSerialIoIndexSPI1] = PchSerialIoPci, + [PchSerialIoIndexSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| GSPI1 | FP MCU | + #| I2C0 | Touchpad | + #| I2C1 | Touch screen | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, + }" + + # GPIO for SD card detect + register "sdcard_cd_gpio" = "vSD3_CD_B" + + device domain 0 on + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D21_IRQ)" + register "wake" = "GPE0_DW0_21" + device i2c 15 on end + end + end # I2C #0 + device pci 15.1 on + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "reset_delay_ms" = "100" + register "reset_off_delay_ms" = "5" + register "has_power_resource" = "1" + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)" + register "stop_off_delay_ms" = "5" + device i2c 49 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "generic.reset_delay_ms" = "10" + register "generic.reset_off_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 5d on end + end + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + register "gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A8)" + register "key.wake" = "GPE0_DW0_08" + register "key.wakeup_event_action" = "EV_ACT_ASSERTED" + register "key.dev_name" = ""EJCT"" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + device generic 0 on end + end + end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 on + chip drivers/i2c/sx9310 + register "desc" = ""SAR Proximity Sensor"" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A0)" + register "speed" = "I2C_SPEED_FAST" + register "uid" = "1" + register "reg_prox_ctrl0" = "0x10" + register "reg_prox_ctrl1" = "0x00" + register "reg_prox_ctrl2" = "0x84" + register "reg_prox_ctrl3" = "0x0e" + register "reg_prox_ctrl4" = "0x07" + register "reg_prox_ctrl5" = "0xc6" + register "reg_prox_ctrl6" = "0x20" + register "reg_prox_ctrl7" = "0x0d" + register "reg_prox_ctrl8" = "0x8d" + register "reg_prox_ctrl9" = "0x43" + register "reg_prox_ctrl10" = "0x1f" + register "reg_prox_ctrl11" = "0x00" + register "reg_prox_ctrl12" = "0x00" + register "reg_prox_ctrl13" = "0x00" + register "reg_prox_ctrl14" = "0x00" + register "reg_prox_ctrl15" = "0x00" + register "reg_prox_ctrl16" = "0x00" + register "reg_prox_ctrl17" = "0x00" + register "reg_prox_ctrl18" = "0x00" + register "reg_prox_ctrl19" = "0x00" + register "reg_sar_ctrl0" = "0x50" + register "reg_sar_ctrl1" = "0x8a" + register "reg_sar_ctrl2" = "0x3c" + device i2c 28 on end + end + end # I2C #3 + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" + register "property_count" = "1" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end #I2C #4 + device pci 1e.3 on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A23_IRQ)" + device spi 1 on end + end # FPMCU + end # GSPI #1 + end + +end -- To view, visit https://review.coreboot.org/c/coreboot/+/33354 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9a4f25db768baeba598a0baa3ed23b64868cba4a Gerrit-Change-Number: 33354 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sdm845: Add QUPv3 FW load & config
by Julius Werner (Code Review) 13 Jun '19

13 Jun '19

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25372 ) Change subject: sdm845: Add QUPv3 FW load & config ...................................................................... Patch Set 73: (1 comment) https://review.coreboot.org/#/c/25372/6/src/mainboard/google/cheza/qupv3_co… File src/mainboard/google/cheza/qupv3_config.c: https://review.coreboot.org/#/c/25372/6/src/mainboard/google/cheza/qupv3_co… PS6, Line 18: struct se_cfg se_mappings[QUPV3_SE_MAX] = > >>>> To load QUPV3 firmware from respective driver init function […] I don't understand this explanation, can you please clarify? What registers are you talking about? Which sequence is fixed -- do you mean the order the QUPs get initialized in? Why? Aren't they all independent? -- To view, visit https://review.coreboot.org/c/coreboot/+/25372 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e87f868ecbe2a8e51d94c045ad76b99bb1b345d Gerrit-Change-Number: 25372 Gerrit-PatchSet: 73 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mukesh Savaliya <msavaliy(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Akash Asthana <akashast(a)qualcomm.corp-partner.google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Thu, 13 Jun 2019 02:30:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Akash Asthana <akashast(a)qualcomm.corp-partner.google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in ...coreboot[master]: libpayload: Add USB support to mistral config
by Patrick Georgi (Code Review) 13 Jun '19

13 Jun '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33259 Change subject: libpayload: Add USB support to mistral config ...................................................................... libpayload: Add USB support to mistral config Change-Id: I2ef42f7d607eec6166d762ad71c0d9540906589d Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M payloads/libpayload/configs/config.mistral 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/33259/1 diff --git a/payloads/libpayload/configs/config.mistral b/payloads/libpayload/configs/config.mistral index e305fb6..23bf54e 100644 --- a/payloads/libpayload/configs/config.mistral +++ b/payloads/libpayload/configs/config.mistral @@ -3,3 +3,6 @@ CONFIG_LP_TIMER_ARM64_ARCH=y CONFIG_LP_SERIAL_CONSOLE=y CONFIG_LP_QCS405_SERIAL_CONSOLE=y +CONFIG_LP_USB=y +CONFIG_LP_USB_EHCI=y +CONFIG_LP_USB_XHCI=y -- To view, visit https://review.coreboot.org/c/coreboot/+/33259 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ef42f7d607eec6166d762ad71c0d9540906589d Gerrit-Change-Number: 33259 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit June 2019