Hello Aaron Durbin, Furquan Shaikh,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/33281
to review the following change.
Change subject: cbfs_spi: Enable speed logging by default for BIOS_DEBUG
......................................................................
cbfs_spi: Enable speed logging by default for BIOS_DEBUG
The SPI transfer speed logging in cbfs_spi is super useful, doesn't get
in the way (just adding one line per stage, essentially) and should have
no notable overhead. Let's enable it by default for the BIOS_DEBUG log
level rather than having to recompile to get it.
Change-Id: I03c77938afe01fdcecf917e8c4c25cc29cdc764e
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
---
M src/drivers/spi/cbfs_spi.c
1 file changed, 3 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/33281/1
diff --git a/src/drivers/spi/cbfs_spi.c b/src/drivers/spi/cbfs_spi.c
index e311752..175af25 100644
--- a/src/drivers/spi/cbfs_spi.c
+++ b/src/drivers/spi/cbfs_spi.c
@@ -31,21 +31,18 @@
static bool spi_flash_init_done;
/*
- * Set this to 1 to debug SPI speed, 0 to disable it
- * The format is:
+ * SPI speed logging for big transfers available with BIOS_DEBUG. The format is:
*
- * read SPI 62854 7db7: 10416 us, 3089 KB/s, 24.712 Mbps
+ * read SPI 0x62854 0x7db7: 10416 us, 3089 KB/s, 24.712 Mbps
*
* The important number is the last one. It should roughly match your SPI
* clock. If it doesn't, your driver might need a little tuning.
*/
-#define SPI_SPEED_DEBUG 0
-
static ssize_t spi_readat(const struct region_device *rd, void *b,
size_t offset, size_t size)
{
struct stopwatch sw;
- bool show = SPI_SPEED_DEBUG && size >= 4 * KiB;
+ bool show = size >= 4 * KiB && console_log_level(BIOS_DEBUG);
if (show)
stopwatch_init(&sw);
--
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I03c77938afe01fdcecf917e8c4c25cc29cdc764e
Gerrit-Change-Number: 33281
Gerrit-PatchSet: 1
Gerrit-Owner: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org>
Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com>
Gerrit-MessageType: newchange
Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33349
Change subject: mainboard/hp/z220_sff_workstation: remove unused header file
......................................................................
mainboard/hp/z220_sff_workstation: remove unused header file
Change-Id: I4c780afaccd604a1bf4da67eea713f809744ddb2
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
---
D src/mainboard/hp/z220_sff_workstation/mainboard.h
1 file changed, 0 insertions(+), 19 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/33349/1
diff --git a/src/mainboard/hp/z220_sff_workstation/mainboard.h b/src/mainboard/hp/z220_sff_workstation/mainboard.h
deleted file mode 100644
index b47a8f5..0000000
--- a/src/mainboard/hp/z220_sff_workstation/mainboard.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Vladimir Serbinenko
- * Copyright (C) 2018 Patrick Rudolph <siro(a)das-labor.org>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#define SUPERIO_DEV SIO0
-#define SUPERIO_PNP_BASE 0x2e
--
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Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33369
Change subject: mb/google/octopus: Enable DRAM_PART_NUM_IN_CBI feature for Garg
......................................................................
mb/google/octopus: Enable DRAM_PART_NUM_IN_CBI feature for Garg
Enable DRAM_PART_NUM_IN_CBI feature to get DRAM part number from CBI
BUG=b:132668378
BRANCH=octopus
TEST=emerge-octopus coreboot chromeos-bootimage
Change-Id: Ib78fcf015c90d0106e71c693a445caff6f48dcaa
Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com>
---
M src/mainboard/google/octopus/Kconfig
1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/33369/1
diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig
index 48753ed..8dd3dc6 100644
--- a/src/mainboard/google/octopus/Kconfig
+++ b/src/mainboard/google/octopus/Kconfig
@@ -130,6 +130,7 @@
default y if BOARD_GOOGLE_BOBBA
default y if BOARD_GOOGLE_CASTA
default y if BOARD_GOOGLE_BLOOG
+ default y if BOARD_GOOGLE_GARG
config DRAM_PART_NUM_ALWAYS_IN_CBI
bool
@@ -137,6 +138,7 @@
default y if BOARD_GOOGLE_AMPTON
default y if BOARD_GOOGLE_CASTA
default y if BOARD_GOOGLE_BLOOG
+ default y if BOARD_GOOGLE_GARG
config DRAM_PART_IN_CBI_BOARD_ID_MIN
int
--
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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30217 )
Change subject: mb/lenovo/x201: Remove unneeded includes
......................................................................
Patch Set 2: Code-Review+2
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Change subject: [TESTME]soc/intel/fsp_broadwell_de: Implement postcar stage
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Change subject: [TESTME]soc/intel/fsp_baytrail: Implement postcar stage
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29272 )
Change subject: src/cpu/amd/pi/00730F01: Add microcode update infrastructure for fam16h PI
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Patch Set 4:
(1 comment)
https://review.coreboot.org/#/c/29272/4/src/cpu/amd/pi/00730F01/update_micr…
File src/cpu/amd/pi/00730F01/update_microcode.c:
https://review.coreboot.org/#/c/29272/4/src/cpu/amd/pi/00730F01/update_micr…
PS4, Line 4: * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering
line over 80 characters
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