Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33273
Change subject: ifdtool: Enable GbE/PDR region access if they exist
......................................................................
ifdtool: Enable GbE/PDR region access if they exist
Instead of assuming GbE region is used and PDR region is not,
check if there is a valid region defined in the descriptor and
set the region access permissions based on that.
This enables the use of the PDR region on the sarien platform,
which also uses the GbE region.
This results in the following example changes:
mb/google/sarien (GbE and PDR)
. DESC BIOS ME GbE PDR EC
-BIOS r rw rw r
+BIOS r rw rw rw r
mb/google/eve: (no GbE, no PDR)
. DESC BIOS ME GbE PDR EC
-BIOS r rw rw
+BIOS r rw
Change-Id: I7aeffc8f8194638c6012340b43aea8f8460d268a
Signed-off-by: Duncan Laurie <dlaurie(a)google.com>
---
M util/ifdtool/ifdtool.c
M util/ifdtool/ifdtool.h
2 files changed, 40 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/33273/1
diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
index 6c5e784..0204a71 100644
--- a/util/ifdtool/ifdtool.c
+++ b/util/ifdtool/ifdtool.c
@@ -925,15 +925,28 @@
write_image(filename, image, size);
}
+static int check_region(const frba_t *frba, unsigned int region_type)
+{
+ region_t region;
+
+ if (!frba)
+ return 0;
+
+ region = get_region(frba, region_type);
+ return !!((region.base < region.limit) && (region.size > 0));
+}
+
static void lock_descriptor(const char *filename, char *image, int size)
{
- int wr_shift, rd_shift;
+ int wr_shift, rd_shift, rw_pdr, rw_gbe;
fmba_t *fmba = find_fmba(image, size);
+ const frba_t *frba = find_frba(image, size);
if (!fmba)
exit(EXIT_FAILURE);
- /* TODO: Dynamically take Platform Data Region and GbE Region
- * into regard.
- */
+
+ /* Check for valid PDR and GBE region */
+ rw_pdr = check_region(frba, REGION_PDR);
+ rw_gbe = check_region(frba, REGION_GBE);
if (ifd_version >= IFD_VERSION_2) {
wr_shift = FLMSTR_WR_SHIFT_V2;
@@ -969,10 +982,20 @@
case PLATFORM_CNL:
case PLATFORM_ICL:
case PLATFORM_SKLKBL:
- /* CPU/BIOS can read descriptor, BIOS, EC and GbE. */
- fmba->flmstr1 |= 0x10b << rd_shift;
- /* CPU/BIOS can write BIOS and Gbe. */
- fmba->flmstr1 |= 0xa << wr_shift;
+ /* CPU/BIOS can read descriptor, BIOS and EC */
+ fmba->flmstr1 |= 0x103 << rd_shift;
+ /* CPU/BIOS can write BIOS. */
+ fmba->flmstr1 |= 0x2 << wr_shift;
+ if (rw_gbe) {
+ /* Enable GBE RW if region is defined */
+ fmba->flmstr1 |= (1 << REGION_GBE) << rd_shift;
+ fmba->flmstr1 |= (1 << REGION_GBE) << wr_shift;
+ }
+ if (rw_pdr) {
+ /* Enable PDR RW if region is defined */
+ fmba->flmstr1 |= (1 << REGION_PDR) << rd_shift;
+ fmba->flmstr1 |= (1 << REGION_PDR) << wr_shift;
+ }
/* ME can read descriptor, ME and GbE. */
fmba->flmstr2 |= 0xd << rd_shift;
/* ME can write ME. */
diff --git a/util/ifdtool/ifdtool.h b/util/ifdtool/ifdtool.h
index 49463b9..6617319 100644
--- a/util/ifdtool/ifdtool.h
+++ b/util/ifdtool/ifdtool.h
@@ -94,6 +94,15 @@
#define MAX_REGIONS 9
#define MAX_REGIONS_OLD 5
+enum flash_regions {
+ REGION_DESCRIPTOR,
+ REGION_BIOS,
+ REGION_ME,
+ REGION_GBE,
+ REGION_PDR,
+ REGION_EC = 8,
+};
+
typedef struct {
uint32_t flreg[MAX_REGIONS];
} __attribute__((packed)) frba_t;
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I7aeffc8f8194638c6012340b43aea8f8460d268a
Gerrit-Change-Number: 33273
Gerrit-PatchSet: 1
Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org>
Gerrit-MessageType: newchange
Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32356
Change subject: drivers/usb/ucsi: Add driver to generate UCSI memory region
......................................................................
drivers/usb/ucsi: Add driver to generate UCSI memory region
The USB Type-C Connector System Software Interface (UCSI) defines a
required memory oregion for the OS UCSI driver to use to communicate
with the BIOS and EC.
This driver allocates a cbmem region for this required ACPI UCSI
memory and generates the ACPI AML code to describe it into the SSDT.
This driver must be paired with an EC implementation that actually
instantiates the UCSI device and provides the _DSM method that
translates from this shared memory to the EC. In order to connect
this driver to the EC the ACPI path of the UCSI device is provided
in the mainboard devicetree.
Change-Id: Id5b7fa19436443bc11a6ebe3ce89cd552cee4d85
Signed-off-by: Duncan Laurie <dlaurie(a)google.com>
---
M src/commonlib/include/commonlib/cbmem_id.h
A src/drivers/usb/ucsi/Kconfig
A src/drivers/usb/ucsi/Makefile.inc
A src/drivers/usb/ucsi/chip.h
A src/drivers/usb/ucsi/ucsi.c
5 files changed, 188 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/32356/1
diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h
index af79a59..fb2d3e3 100644
--- a/src/commonlib/include/commonlib/cbmem_id.h
+++ b/src/commonlib/include/commonlib/cbmem_id.h
@@ -19,6 +19,7 @@
#define CBMEM_ID_ACPI 0x41435049
#define CBMEM_ID_ACPI_GNVS 0x474e5653
+#define CBMEM_ID_ACPI_UCSI 0x55435349
#define CBMEM_ID_AFTER_CAR 0xc4787a93
#define CBMEM_ID_AGESA_RUNTIME 0x41474553
#define CBMEM_ID_AMDMCT_MEMINFO 0x494D454E
@@ -81,6 +82,7 @@
#define CBMEM_ID_TO_NAME_TABLE \
{ CBMEM_ID_ACPI, "ACPI " }, \
{ CBMEM_ID_ACPI_GNVS, "ACPI GNVS " }, \
+ { CBMEM_ID_ACPI_UCSI, "ACPI UCSI " }, \
{ CBMEM_ID_AGESA_RUNTIME, "AGESA RSVD " }, \
{ CBMEM_ID_AFTER_CAR, "AFTER CAR " }, \
{ CBMEM_ID_AMDMCT_MEMINFO, "AMDMEM INFO" }, \
diff --git a/src/drivers/usb/ucsi/Kconfig b/src/drivers/usb/ucsi/Kconfig
new file mode 100644
index 0000000..22e751d
--- /dev/null
+++ b/src/drivers/usb/ucsi/Kconfig
@@ -0,0 +1,12 @@
+config DRIVERS_USB_UCSI
+ bool
+ default n
+ depends on HAVE_ACPI_TABLES
+ help
+ This driver allocates a fixed memory region in cbmem for the EC
+ implementation of the USB Type-C System Software Interface.
+ The shared memory region is used for the OS driver to pass
+ data to the _DSM method, which must be implemented by the EC.
+ The ACPI path of the EC device is provided in devicetree so the
+ ACPI operation region can be added to the specific UCSI device
+ that the EC implements.
diff --git a/src/drivers/usb/ucsi/Makefile.inc b/src/drivers/usb/ucsi/Makefile.inc
new file mode 100644
index 0000000..a62d58c
--- /dev/null
+++ b/src/drivers/usb/ucsi/Makefile.inc
@@ -0,0 +1 @@
+ramstage-$(CONFIG_DRIVERS_USB_UCSI) += ucsi.c
diff --git a/src/drivers/usb/ucsi/chip.h b/src/drivers/usb/ucsi/chip.h
new file mode 100644
index 0000000..860d6c5
--- /dev/null
+++ b/src/drivers/usb/ucsi/chip.h
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __USB_UCSI_CHIP_H__
+#define __USB_UCSI_CHIP_H__
+
+struct drivers_usb_ucsi_config {
+ /* Location of the UCSI device defined by the EC */
+ const char *path;
+};
+
+#endif /* __USB_UCSI_CHIP_H__ */
diff --git a/src/drivers/usb/ucsi/ucsi.c b/src/drivers/usb/ucsi/ucsi.c
new file mode 100644
index 0000000..a697e4f
--- /dev/null
+++ b/src/drivers/usb/ucsi/ucsi.c
@@ -0,0 +1,149 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi_device.h>
+#include <arch/acpigen.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/path.h>
+#include <device/pnp.h>
+#include <stdint.h>
+#include "chip.h"
+
+/*
+ * The UCSI fields are defined in the UCSI specification at
+ * https://www.intel.com/content/www/us/en/io/universal-serial-bus/usb-type-c-…
+ * https://www.intel.com/content/www/us/en/io/universal-serial-bus/bios-implem…
+ */
+
+static struct fieldlist ucsi_region_fields[] = {
+ FIELDLIST_NAMESTR("VER0", 8),
+ FIELDLIST_NAMESTR("VER1", 8),
+ FIELDLIST_NAMESTR("RSV0", 8),
+ FIELDLIST_NAMESTR("RSV1", 8),
+ FIELDLIST_NAMESTR("CCI0", 8),
+ FIELDLIST_NAMESTR("CCI1", 8),
+ FIELDLIST_NAMESTR("CCI2", 8),
+ FIELDLIST_NAMESTR("CCI3", 8),
+ FIELDLIST_NAMESTR("CTL0", 8),
+ FIELDLIST_NAMESTR("CTL1", 8),
+ FIELDLIST_NAMESTR("CTL2", 8),
+ FIELDLIST_NAMESTR("CTL3", 8),
+ FIELDLIST_NAMESTR("CTL4", 8),
+ FIELDLIST_NAMESTR("CTL5", 8),
+ FIELDLIST_NAMESTR("CTL6", 8),
+ FIELDLIST_NAMESTR("CTL7", 8),
+ FIELDLIST_NAMESTR("MGI0", 8),
+ FIELDLIST_NAMESTR("MGI1", 8),
+ FIELDLIST_NAMESTR("MGI2", 8),
+ FIELDLIST_NAMESTR("MGI3", 8),
+ FIELDLIST_NAMESTR("MGI4", 8),
+ FIELDLIST_NAMESTR("MGI5", 8),
+ FIELDLIST_NAMESTR("MGI6", 8),
+ FIELDLIST_NAMESTR("MGI7", 8),
+ FIELDLIST_NAMESTR("MGI8", 8),
+ FIELDLIST_NAMESTR("MGI9", 8),
+ FIELDLIST_NAMESTR("MGIA", 8),
+ FIELDLIST_NAMESTR("MGIB", 8),
+ FIELDLIST_NAMESTR("MGIC", 8),
+ FIELDLIST_NAMESTR("MGID", 8),
+ FIELDLIST_NAMESTR("MGIE", 8),
+ FIELDLIST_NAMESTR("MGIF", 8),
+ FIELDLIST_NAMESTR("MGO0", 8),
+ FIELDLIST_NAMESTR("MGO1", 8),
+ FIELDLIST_NAMESTR("MGO2", 8),
+ FIELDLIST_NAMESTR("MGO3", 8),
+ FIELDLIST_NAMESTR("MGO4", 8),
+ FIELDLIST_NAMESTR("MGO5", 8),
+ FIELDLIST_NAMESTR("MGO6", 8),
+ FIELDLIST_NAMESTR("MGO7", 8),
+ FIELDLIST_NAMESTR("MGO8", 8),
+ FIELDLIST_NAMESTR("MGO9", 8),
+ FIELDLIST_NAMESTR("MGOA", 8),
+ FIELDLIST_NAMESTR("MGOB", 8),
+ FIELDLIST_NAMESTR("MGOC", 8),
+ FIELDLIST_NAMESTR("MGOD", 8),
+ FIELDLIST_NAMESTR("MGOE", 8),
+ FIELDLIST_NAMESTR("MGOF", 8),
+};
+static const size_t ucsi_region_len = ARRAY_SIZE(ucsi_region_fields);
+
+/* Allocate cbmem region for EC UCSI device to use for OS shared memory */
+static void ucsi_fill_ssdt_generator(struct device *dev)
+{
+ struct drivers_usb_ucsi_config *config = dev->chip_info;
+ struct opregion opreg;
+ void *region_ptr;
+
+ if (!dev->enabled || !config)
+ return;
+ if (!config->path) {
+ printk(BIOS_ERR, "%s: ACPI path for UCSI device required\n",
+ dev_path(dev));
+ return;
+ }
+
+ region_ptr = cbmem_add(CBMEM_ID_ACPI_UCSI, ucsi_region_len);
+ if (!region_ptr)
+ return;
+ memset(region_ptr, 0, ucsi_region_len);
+
+ opreg.name = "UCSM";
+ opreg.regionspace = SYSTEMMEMORY;
+ opreg.regionoffset = (uintptr_t)region_ptr;
+ opreg.regionlen = ucsi_region_len;
+
+ acpigen_write_scope(config->path);
+ acpigen_write_name("_CRS");
+ acpigen_write_resourcetemplate_header();
+ acpigen_write_mem32fixed(1, (uintptr_t)region_ptr, ucsi_region_len);
+ acpigen_write_resourcetemplate_footer();
+ acpigen_write_opregion(&opreg);
+ acpigen_write_field(opreg.name, ucsi_region_fields, ucsi_region_len,
+ FIELD_ANYACC | FIELD_LOCK | FIELD_PRESERVE);
+ acpigen_pop_len(); /* Scope */
+
+ printk(BIOS_INFO, "%s: %s at %s\n", config->path,
+ dev->chip_ops->name, dev_path(dev));
+}
+
+static const char *ucsi_acpi_name(const struct device *dev)
+{
+ return "UCSI";
+}
+
+static struct device_operations ops = {
+ .read_resources = DEVICE_NOOP,
+ .set_resources = DEVICE_NOOP,
+ .enable_resources = DEVICE_NOOP,
+ .acpi_name = ucsi_acpi_name,
+ .scan_bus = scan_generic_bus,
+ .acpi_fill_ssdt_generator = ucsi_fill_ssdt_generator,
+};
+
+static struct pnp_info info[] = {
+ { NULL, 0, 0, 0, }
+};
+
+static void ucsi_enable(struct device *dev)
+{
+ pnp_enable_devices(dev, &ops, ARRAY_SIZE(info), info);
+}
+
+struct chip_operations drivers_usb_ucsi_ops = {
+ CHIP_NAME("USB Type-C Connector System Software Interface (UCSI)")
+ .enable_dev = ucsi_enable
+};
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Id5b7fa19436443bc11a6ebe3ce89cd552cee4d85
Gerrit-Change-Number: 32356
Gerrit-PatchSet: 1
Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org>
Gerrit-MessageType: newchange
Hello V Sowmya,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/33233
to review the following change.
Change subject: soc/intel/cannonlake: Add _DSM method for SD controller
......................................................................
soc/intel/cannonlake: Add _DSM method for SD controller
Change-Id: I15090ed9f9bc90b35dfcba47c913e3d37b799d0b
Signed-off-by: V Sowmya <v.sowmya(a)intel.com>
---
M src/soc/intel/cannonlake/acpi/scs.asl
1 file changed, 61 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/33233/1
diff --git a/src/soc/intel/cannonlake/acpi/scs.asl b/src/soc/intel/cannonlake/acpi/scs.asl
index cdfff91..924228e 100644
--- a/src/soc/intel/cannonlake/acpi/scs.asl
+++ b/src/soc/intel/cannonlake/acpi/scs.asl
@@ -95,6 +95,67 @@
PGEN, 1, /* PG_ENABLE */
}
+ /* _DSM x86 Device Specific Method
+ * Arg0: UUID Unique function identifier
+ * Arg1: Integer Revision Level
+ * Arg2: Integer Function Index (0 = Return Supported Functions)
+ * Arg3: Package Parameters
+ */
+ Method (_DSM, 4)
+ {
+ If(LEqual(Arg0, ToUUID("f6c13ea5-65cd-461f-ab7a-29f7e8d5bd61"))) {
+ /* Check the revision */
+ If(LGreaterEqual(Arg1, Zero)) {
+ /* Switch statement based on the function index. */
+ Switch(ToInteger(Arg2)) {
+ /*
+ * Function Index 0 the return value is a buffer containing
+ * one bit for each function index, starting with zero.
+ * Bit 0 - Indicates whether there is support for any functions other than function 0.
+ * Bit 1 - Indicates support to clear power control register
+ * Bit 2 - Indicates support to set power control register
+ * Bit 3 - Indicates support to set 1.8V signalling
+ * Bit 4 - Indicates support to set 3.3V signalling
+ * Bit 5 - Indicates support for HS200 mode
+ * Bit 6 - Indicates support for HS400 mode
+ * Bit 9 - Indicates eMMC I/O Driver Strength
+ */
+ /*
+ * For SD we have to support functions to
+ * set 1.8V signalling and 3.3V signalling [BIT4, BIT3]
+ */
+ Case(0) {
+ Return (Buffer() {0x19})
+ }
+
+ /*
+ * Function Index 3: Set 1.8v signalling.
+ * We put a sleep of 100ms in this method to
+ * work around a known issue with detecting
+ * UHS SD card on PCH. This is to compensate
+ * for the SD VR slowness.
+ */
+ Case(3) {
+ Sleep (100) // Sleep 100ms
+ Return(Buffer(){0x00})
+ }
+ /*
+ * Function Index 4: Set 3.3v signalling.
+ * We put a sleep of 100ms in this method to
+ * work around a known issue with detecting
+ * UHS SD card on PCH. This is to compensate
+ * for the SD VR slowness.
+ */
+ Case(4) {
+ Sleep (100) // Sleep 100ms
+ Return(Buffer(){0x00})
+ }
+ } // End - Switch(Arg2)
+ }
+ } // End - UUID check
+ Return(Buffer() {0x0})
+ } // End _DSM
+
Method(_INI)
{
/* Clear register 0x1C20/0x4820 */
--
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Gerrit-Change-Number: 33233
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Gerrit-Owner: Evan Green <evgreen(a)chromium.org>
Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com>
Gerrit-MessageType: newchange
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33189
Change subject: soc/intel/common: Skip SoC GT programming based on CONFIG_SKIP_GRAPHICS_ENABLING
......................................................................
soc/intel/common: Skip SoC GT programming based on CONFIG_SKIP_GRAPHICS_ENABLING
Skip GT specific programming in coreboot to support early
parts without GT enable.
Change-Id: I231e13367cbfbafbfb0cb4235487dbcbcae76820
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
---
M src/soc/intel/common/block/graphics/Kconfig
M src/soc/intel/icelake/graphics.c
2 files changed, 12 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/33189/1
diff --git a/src/soc/intel/common/block/graphics/Kconfig b/src/soc/intel/common/block/graphics/Kconfig
index 4ab9200..36cac22 100644
--- a/src/soc/intel/common/block/graphics/Kconfig
+++ b/src/soc/intel/common/block/graphics/Kconfig
@@ -2,3 +2,11 @@
bool
help
Intel Processor common Graphics support
+
+config SKIP_GRAPHICS_ENABLING
+ bool
+ depends on SOC_INTEL_COMMON_BLOCK_GRAPHICS
+ default n
+ help
+ Skip GT specific programming in coreboot to support
+ early parts without GT enable.
diff --git a/src/soc/intel/icelake/graphics.c b/src/soc/intel/icelake/graphics.c
index 0fbddf0..0709033 100644
--- a/src/soc/intel/icelake/graphics.c
+++ b/src/soc/intel/icelake/graphics.c
@@ -34,6 +34,10 @@
{
uint32_t ddi_buf_ctl;
+ /* Skip IGD GT programming */
+ if (CONFIG(SKIP_GRAPHICS_ENABLING))
+ return;
+
/*
* Enable DDI-A (eDP) 4-lane operation if the link is not up yet.
* This will allow the kernel to use 4-lane eDP links properly
--
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