Change in ...coreboot[master]: soc/intel/icelake: Pass FSP-M/S UPD as per ICL requirement - coreboot-gerrit

18 Mar 2019

Hello Aamir Bohra,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/31955
to review the following change.
Change subject: soc/intel/icelake: Pass FSP-M/S UPD as per ICL requirement
......................................................................
soc/intel/icelake: Pass FSP-M/S UPD as per ICL requirement
1. Gfx stolen memory requirement for ICL GFX
2. Enable PeiGraphicsPeim support
Change-Id: I22dd14249b7402873f1ac07bee164ee7bee36414
Signed-off-by: Aamir Bohra aamir.bohra@intel.com
Signed-off-by: Subrata Banik subrata.banik@intel.com
---
M src/soc/intel/icelake/fsp_params.c
M src/soc/intel/icelake/romstage/fsp_params.c
2 files changed, 243 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/31955/1

diff --git a/src/soc/intel/icelake/fsp_params.c b/src/soc/intel/icelake/fsp_params.c
index 513ef00..533555d 100644
--- a/src/soc/intel/icelake/fsp_params.c
+++ b/src/soc/intel/icelake/fsp_params.c
@@ -13,14 +13,199 @@
  * GNU General Public License for more details.
  */
+#include <chip.h>
 #include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
 #include <fsp/api.h>
+#include <fsp/util.h>
+#include <intelblocks/xdci.h>
+#include <soc/intel/common/vbt.h>
+#include <soc/pci_devs.h>
 #include <soc/ramstage.h>
+#include <string.h>
+
+static void parse_devicetree(FSP_S_CONFIG *params)
+{
+	struct device *dev = SA_DEV_ROOT;
+	if (!dev) {
+		printk(BIOS_ERR, "Could not find root device\n");
+		return;
+	}
+
+	const config_t *config = dev->chip_info;
+
+	for (int i = 0; i < CONFIG_SOC_INTEL_I2C_DEV_MAX; i++) {
+		params->SerialIoI2cMode[i] = config->SerialIoI2cMode[i];
+	}
+
+	for (int i = 0; i < CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX; i++) {
+		params->SerialIoSpiMode[i] = config->SerialIoGSpiMode[i];
+		params->SerialIoSpiCsMode[i] = config->SerialIoGSpiCsMode[i];
+		params->SerialIoSpiCsState[i] = config->SerialIoGSpiCsState[i];
+	}
+
+	for (int i = 0; i < CONFIG_SOC_INTEL_UART_DEV_MAX; i++) {
+		params->SerialIoUartMode[i] = config->SerialIoUartMode[i];
+	}
+}
/* UPD parameters to be initialized before SiliconInit */
 void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 {
-	/* ToDo: update with UPD override as FSP matures */
+	int i;
+	FSP_S_CONFIG *params = &supd->FspsConfig;
+	struct device *dev = SA_DEV_ROOT;
+	config_t *config = dev->chip_info;
+
+	/* Parse device tree and enable/disable devices */
+	parse_devicetree(params);
+
+	/* Load VBT before devicetree-specific config. */
+	params->GraphicsConfigPtr = (uintptr_t)vbt_get();
+
+	/* Set USB OC pin to 0 first */
+	for (i = 0; i < ARRAY_SIZE(params->Usb2OverCurrentPin); i++) {
+		params->Usb2OverCurrentPin[i] = 0;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(params->Usb3OverCurrentPin); i++) {
+		params->Usb3OverCurrentPin[i] = 0;
+	}
+
+	mainboard_silicon_init_params(params);
+
+	params->PeiGraphicsPeimInit = 1;
+	params->GtFreqMax = 2;
+	params->CdClock = 3;
+	/* Unlock upper 8 bytes of RTC RAM */
+	params->PchLockDownRtcMemoryLock = 0;
+
+	params->CnviBtAudioOffload = config->CnviBtAudioOffload;
+	/* SATA */
+	dev = dev_find_slot(0, PCH_DEVFN_SATA);
+	if (!dev)
+		params->SataEnable = 0;
+	else {
+		params->SataEnable = dev->enabled;
+		params->SataMode = config->SataMode;
+		params->SataSalpSupport = config->SataSalpSupport;
+		memcpy(params->SataPortsEnable, config->SataPortsEnable,
+				sizeof(params->SataPortsEnable));
+		memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp,
+				sizeof(params->SataPortsDevSlp));
+	}
+
+	/* Lan */
+	dev = dev_find_slot(0, PCH_DEVFN_GBE);
+	if (!dev)
+		params->PchLanEnable = 0;
+	else
+		params->PchLanEnable = dev->enabled;
+
+	/* Audio */
+	params->PchHdaDspEnable = config->PchHdaDspEnable;
+	params->PchHdaAudioLinkHda = config->PchHdaAudioLinkHda;
+	params->PchHdaAudioLinkDmic0 = config->PchHdaAudioLinkDmic0;
+	params->PchHdaAudioLinkDmic1 = config->PchHdaAudioLinkDmic1;
+	params->PchHdaAudioLinkSsp0 = config->PchHdaAudioLinkSsp0;
+	params->PchHdaAudioLinkSsp1 = config->PchHdaAudioLinkSsp1;
+	params->PchHdaAudioLinkSsp2 = config->PchHdaAudioLinkSsp2;
+	params->PchHdaAudioLinkSndw1 = config->PchHdaAudioLinkSndw1;
+	params->PchHdaAudioLinkSndw2 = config->PchHdaAudioLinkSndw2;
+	params->PchHdaAudioLinkSndw3 = config->PchHdaAudioLinkSndw3;
+	params->PchHdaAudioLinkSndw4 = config->PchHdaAudioLinkSndw4;
+
+	/* disable Legacy PME */
+	memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));
+
+	/* S0ix */
+	params->PchPmSlpS0Enable = config->s0ix_enable;
+
+	/* USB */
+	for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
+		params->PortUsb20Enable[i] =
+			config->usb2_ports[i].enable;
+		params->Usb2OverCurrentPin[i] =
+			config->usb2_ports[i].ocpin;
+		params->Usb2PhyPetxiset[i] =
+			config->usb2_ports[i].pre_emp_bias;
+		params->Usb2PhyTxiset[i] =
+			config->usb2_ports[i].tx_bias;
+		params->Usb2PhyPredeemp[i] =
+			config->usb2_ports[i].tx_emp_enable;
+		params->Usb2PhyPehalfbit[i] =
+			config->usb2_ports[i].pre_emp_bit;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) {
+		params->PortUsb30Enable[i] = config->usb3_ports[i].enable;
+		params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;
+		if (config->usb3_ports[i].tx_de_emp) {
+			params->Usb3HsioTxDeEmphEnable[i] = 1;
+			params->Usb3HsioTxDeEmph[i] =
+				config->usb3_ports[i].tx_de_emp;
+		}
+		if (config->usb3_ports[i].tx_downscale_amp) {
+			params->Usb3HsioTxDownscaleAmpEnable[i] = 1;
+			params->Usb3HsioTxDownscaleAmp[i] =
+				config->usb3_ports[i].tx_downscale_amp;
+		}
+	}
+
+	/* Enable xDCI controller if enabled in devicetree and allowed */
+	dev = dev_find_slot(0, PCH_DEVFN_USBOTG);
+	if (!xdci_can_enable())
+		dev->enabled = 0;
+	params->XdciEnable = dev->enabled;
+
+	/* PCI Express */
+	for (i = 0; i < ARRAY_SIZE(config->PcieClkSrcUsage); i++) {
+		if (config->PcieClkSrcUsage[i] == 0)
+			config->PcieClkSrcUsage[i] = PCIE_CLK_NOTUSED;
+	}
+	memcpy(params->PcieClkSrcUsage, config->PcieClkSrcUsage,
+	       sizeof(config->PcieClkSrcUsage));
+	memcpy(params->PcieClkSrcClkReq, config->PcieClkSrcClkReq,
+	       sizeof(config->PcieClkSrcClkReq));
+
+	/* eMMC */
+	dev = dev_find_slot(0, PCH_DEVFN_EMMC);
+	if (!dev)
+		params->ScsEmmcEnabled = 0;
+	else {
+		params->ScsEmmcEnabled = dev->enabled;
+		params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled;
+		params->EmmcUseCustomDlls = config->EmmcUseCustomDlls;
+		if (config->EmmcUseCustomDlls == 1) {
+			params->EmmcTxCmdDelayRegValue =
+					config->EmmcTxCmdDelayRegValue;
+			params->EmmcTxDataDelay1RegValue =
+					config->EmmcTxDataDelay1RegValue;
+			params->EmmcTxDataDelay2RegValue =
+					config->EmmcTxDataDelay2RegValue;
+			params->EmmcRxCmdDataDelay1RegValue =
+					config->EmmcRxCmdDataDelay1RegValue;
+			params->EmmcRxCmdDataDelay2RegValue =
+					config->EmmcRxCmdDataDelay2RegValue;
+			params->EmmcRxStrobeDelayRegValue =
+					config->EmmcRxStrobeDelayRegValue;
+		}
+	}
+
+	/* SD */
+	dev = dev_find_slot(0, PCH_DEVFN_SDCARD);
+	if (!dev)
+		params->ScsSdCardEnabled = 0;
+	else {
+		params->ScsSdCardEnabled = dev->enabled;
+		params->SdCardPowerEnableActiveHigh =
+				config->SdCardPowerEnableActiveHigh;
+	}
+
+	params->Heci3Enabled = config->Heci3Enabled;
+	params->Device4Enable = config->Device4Enable;
+	params->SkipMpInit = !chip_get_fsp_mp_init();
 }
/* Mainboard GPIO Configuration */
diff --git a/src/soc/intel/icelake/romstage/fsp_params.c b/src/soc/intel/icelake/romstage/fsp_params.c
index 69b5b7a..7c7a26d 100644
--- a/src/soc/intel/icelake/romstage/fsp_params.c
+++ b/src/soc/intel/icelake/romstage/fsp_params.c
@@ -13,13 +13,69 @@
  * GNU General Public License for more details.
  */
+#include <assert.h>
+#include <chip.h>
 #include <console/console.h>
 #include <fsp/util.h>
+#include <soc/iomap.h>
+#include <soc/pci_devs.h>
 #include <soc/romstage.h>
+static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config)
+{
+	unsigned int i;
+	const struct device *dev = dev_find_slot(0, PCH_DEVFN_HDA);
+	uint32_t mask = 0;
+
+	/* Set IGD stolen size to 60MB. */
+	m_cfg->IgdDvmt50PreAlloc = 0xFE;
+	/* Vt-D config */
+	m_cfg->VtdDisable = config->VtdDisable;
+	m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;
+	m_cfg->IedSize = CONFIG_IED_REGION_SIZE;
+	m_cfg->SaGv = config->SaGv;
+	m_cfg->UserBd = BOARD_TYPE_ULT_ULX;
+	m_cfg->RMT = config->RMT;
+	/* If Audio Codec is enabled, enable FSP UPD */
+	if (!dev)
+		m_cfg->PchHdaEnable = 0;
+	else
+		m_cfg->PchHdaEnable = dev->enabled;
+
+	for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {
+		if (config->PcieRpEnable[i])
+			mask |= (1 << i);
+	}
+	m_cfg->PcieRpEnableMask = mask;
+	m_cfg->PrmrrSize = config->PrmrrSize;
+	m_cfg->EnableC6Dram = config->enable_c6dram;
+	/* Disable BIOS Guard */
+	m_cfg->BiosGuard = 0;
+	/* Disable Cpu Ratio Override temporary. */
+	m_cfg->CpuRatio = 0;
+	m_cfg->PcdSerialIoUartNumber = CONFIG_UART_FOR_CONSOLE;
+	/* Disable Vmx if Vt-d is already disabled */
+	if (config->VtdDisable)
+		m_cfg->VmxEnable = 0;
+	else
+		m_cfg->VmxEnable = config->VmxEnable;
+}
+
 void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 {
-	/* ToDo: update with UPD override as FSP matures */
+	const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);
+	assert(dev != NULL);
+	const config_t *config = dev->chip_info;
+	FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
+
+	soc_memory_init_params(m_cfg, config);
+
+	/* Enable SMBus controller based on config */
+	m_cfg->SmbusEnable = config->SmbusEnable;
+	/* Set debug probe type */
+	m_cfg->PlatformDebugConsent = config->DebugConsent;
+
+	mainboard_memory_init_params(mupd);
 }
__weak void mainboard_memory_init_params(FSPM_UPD *mupd)
-- 
To view, visit https://review.coreboot.org/c/coreboot/+/31955
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I22dd14249b7402873f1ac07bee164ee7bee36414
Gerrit-Change-Number: 31955
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik subrata.banik@intel.com
Gerrit-Reviewer: Aamir Bohra aamir.bohra@intel.com
Gerrit-MessageType: newchange



    