coreboot-gerrit June 2019

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Change in ...coreboot[master]: qcs405: Enable VBOOT_MIGRATE_WORKING_DATA
by Nitheesh Sekar (Code Review) 06 Jun '19

06 Jun '19

Nitheesh Sekar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33158 Change subject: qcs405: Enable VBOOT_MIGRATE_WORKING_DATA ...................................................................... qcs405: Enable VBOOT_MIGRATE_WORKING_DATA Enable VBOOT MIGRATE_WORKING_DATA so that the data required by depthcharge is copied into the coreboot tables and made available to depthcharge after BOOT_IMEM is cleansed. Change-Id: I0317b73d24b07553672695998589f86677e0be64 Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/soc/qualcomm/qcs405/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/33158/1 diff --git a/src/soc/qualcomm/qcs405/Kconfig b/src/soc/qualcomm/qcs405/Kconfig index 1c8a30a..696abd4 100644 --- a/src/soc/qualcomm/qcs405/Kconfig +++ b/src/soc/qualcomm/qcs405/Kconfig @@ -20,6 +20,7 @@ select VBOOT_SEPARATE_VERSTAGE select VBOOT_RETURN_FROM_VERSTAGE select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_MIGRATE_WORKING_DATA config QCS405_BLSP_SPI bool -- To view, visit https://review.coreboot.org/c/coreboot/+/33158 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0317b73d24b07553672695998589f86677e0be64 Gerrit-Change-Number: 33158 Gerrit-PatchSet: 1 Gerrit-Owner: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: qcs405: Add PRESERVE flag for RO_VPD
by Nitheesh Sekar (Code Review) 06 Jun '19

06 Jun '19

Nitheesh Sekar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33020 Change subject: qcs405: Add PRESERVE flag for RO_VPD ...................................................................... qcs405: Add PRESERVE flag for RO_VPD Add PRESERVE flag to preserve the VPD data. Change-Id: I78ab4de31030465345c5ae58813bfed5e27494fb Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/mainboard/google/mistral/chromeos.fmd 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/33020/1 diff --git a/src/mainboard/google/mistral/chromeos.fmd b/src/mainboard/google/mistral/chromeos.fmd index 633df2e..76cdd50 100644 --- a/src/mainboard/google/mistral/chromeos.fmd +++ b/src/mainboard/google/mistral/chromeos.fmd @@ -22,7 +22,7 @@ GBB 0x2f00 RO_FRID 0x100 } - RO_VPD 128K + RO_VPD(PRESERVE) 128K RO_DDR_TRAINING(PRESERVE) 8K } -- To view, visit https://review.coreboot.org/c/coreboot/+/33020 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78ab4de31030465345c5ae58813bfed5e27494fb Gerrit-Change-Number: 33020 Gerrit-PatchSet: 1 Gerrit-Owner: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/amd/common: Make biosram functions more readable
by Richard Spiegel (Code Review) 06 Jun '19

06 Jun '19

Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32932 ) Change subject: soc/amd/common: Make biosram functions more readable ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/32932 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b491da6f263cbab2b549301e16a7e19896f2428 Gerrit-Change-Number: 32932 Gerrit-PatchSet: 3 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 06 Jun 2019 19:30:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/amd/common: Fix consistency in AcpiMmio arguments
by Marshall Dawson (Code Review) 06 Jun '19

06 Jun '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32930 Change subject: soc/amd/common: Fix consistency in AcpiMmio arguments ...................................................................... soc/amd/common: Fix consistency in AcpiMmio arguments Change all arguments named "offset" to "reg" to match the others. These should have gone into change 69486cac7: Create AcpiMmio functionality from stoneyridge Change-Id: Ifdd00d0a5d1e03bfa68a13eeece2d2cfd56aa39d Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/block/acpimmio/mmio_util.c M src/soc/amd/common/block/include/amdblocks/acpimmio.h 2 files changed, 37 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/32930/1 diff --git a/src/soc/amd/common/block/acpimmio/mmio_util.c b/src/soc/amd/common/block/acpimmio/mmio_util.c index 7d4c4c5..281880c 100644 --- a/src/soc/amd/common/block/acpimmio/mmio_util.c +++ b/src/soc/amd/common/block/acpimmio/mmio_util.c @@ -69,34 +69,34 @@ /* smi read/write - access registers at 0xfed80200 */ -uint8_t smi_read8(uint8_t offset) +uint8_t smi_read8(uint8_t reg) { - return read8((void *)(ACPIMMIO_SMI_BASE + offset)); + return read8((void *)(ACPIMMIO_SMI_BASE + reg)); } -uint16_t smi_read16(uint8_t offset) +uint16_t smi_read16(uint8_t reg) { - return read16((void *)(ACPIMMIO_SMI_BASE + offset)); + return read16((void *)(ACPIMMIO_SMI_BASE + reg)); } -uint32_t smi_read32(uint8_t offset) +uint32_t smi_read32(uint8_t reg) { - return read32((void *)(ACPIMMIO_SMI_BASE + offset)); + return read32((void *)(ACPIMMIO_SMI_BASE + reg)); } -void smi_write8(uint8_t offset, uint8_t value) +void smi_write8(uint8_t reg, uint8_t value) { - write8((void *)(ACPIMMIO_SMI_BASE + offset), value); + write8((void *)(ACPIMMIO_SMI_BASE + reg), value); } -void smi_write16(uint8_t offset, uint16_t value) +void smi_write16(uint8_t reg, uint16_t value) { - write16((void *)(ACPIMMIO_SMI_BASE + offset), value); + write16((void *)(ACPIMMIO_SMI_BASE + reg), value); } -void smi_write32(uint8_t offset, uint32_t value) +void smi_write32(uint8_t reg, uint32_t value) { - write32((void *)(ACPIMMIO_SMI_BASE + offset), value); + write32((void *)(ACPIMMIO_SMI_BASE + reg), value); } /* pm read/write - access registers at 0xfed80300 */ @@ -135,45 +135,45 @@ /* biosram read/write - access registers at 0xfed80500 */ -uint8_t biosram_read8(uint8_t offset) +uint8_t biosram_read8(uint8_t reg) { - return read8((void *)(ACPIMMIO_BIOSRAM_BASE + offset)); + return read8((void *)(ACPIMMIO_BIOSRAM_BASE + reg)); } -uint16_t biosram_read16(uint8_t offset) /* Must be 1 byte at a time */ +uint16_t biosram_read16(uint8_t reg) /* Must be 1 byte at a time */ { int i; uint16_t value = 0; for (i = sizeof(value) - 1 ; i >= 0 ; i--) - value = (value << 8) | biosram_read8(offset + i); + value = (value << 8) | biosram_read8(reg + i); return value; } -uint32_t biosram_read32(uint8_t offset) +uint32_t biosram_read32(uint8_t reg) { - uint32_t value = biosram_read16(offset + sizeof(uint16_t)) << 16; - return value | biosram_read16(offset); + uint32_t value = biosram_read16(reg + sizeof(uint16_t)) << 16; + return value | biosram_read16(reg); } -void biosram_write8(uint8_t offset, uint8_t value) +void biosram_write8(uint8_t reg, uint8_t value) { - write8((void *)(ACPIMMIO_BIOSRAM_BASE + offset), value); + write8((void *)(ACPIMMIO_BIOSRAM_BASE + reg), value); } -void biosram_write16(uint8_t offset, uint16_t value) +void biosram_write16(uint8_t reg, uint16_t value) { int i; for (i = 0 ; i < sizeof(value) ; i++) { - biosram_write8(offset + i, value & 0xff); + biosram_write8(reg + i, value & 0xff); value >>= 8; } } -void biosram_write32(uint8_t offset, uint32_t value) +void biosram_write32(uint8_t reg, uint32_t value) { int i; for (i = 0 ; i < sizeof(value) ; i++) { - biosram_write8(offset + i, value & 0xff); + biosram_write8(reg + i, value & 0xff); value >>= 8; } } diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h index 34e9ce9..c90c0c8 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -25,12 +25,12 @@ void pm_io_write8(uint8_t reg, uint8_t value); void pm_io_write16(uint8_t reg, uint16_t value); void pm_io_write32(uint8_t reg, uint32_t value); -uint8_t smi_read8(uint8_t offset); -uint16_t smi_read16(uint8_t offset); -uint32_t smi_read32(uint8_t offset); -void smi_write8(uint8_t offset, uint8_t value); -void smi_write16(uint8_t offset, uint16_t value); -void smi_write32(uint8_t offset, uint32_t value); +uint8_t smi_read8(uint8_t reg); +uint16_t smi_read16(uint8_t reg); +uint32_t smi_read32(uint8_t reg); +void smi_write8(uint8_t reg, uint8_t value); +void smi_write16(uint8_t reg, uint16_t value); +void smi_write32(uint8_t reg, uint32_t value); uint8_t pm_read8(uint8_t reg); uint16_t pm_read16(uint8_t reg); uint32_t pm_read32(uint8_t reg); @@ -43,12 +43,12 @@ void pm2_write8(uint8_t reg, uint8_t value); void pm2_write16(uint8_t reg, uint16_t value); void pm2_write32(uint8_t reg, uint32_t value); -uint8_t biosram_read8(uint8_t offset); -uint16_t biosram_read16(uint8_t offset); -uint32_t biosram_read32(uint8_t offset); -void biosram_write8(uint8_t offset, uint8_t value); -void biosram_write16(uint8_t offset, uint16_t value); -void biosram_write32(uint8_t offset, uint32_t value); +uint8_t biosram_read8(uint8_t reg); +uint16_t biosram_read16(uint8_t reg); +uint32_t biosram_read32(uint8_t reg); +void biosram_write8(uint8_t reg, uint8_t value); +void biosram_write16(uint8_t reg, uint16_t value); +void biosram_write32(uint8_t reg, uint32_t value); uint8_t acpi_read8(uint8_t reg); uint16_t acpi_read16(uint8_t reg); uint32_t acpi_read32(uint8_t reg); -- To view, visit https://review.coreboot.org/c/coreboot/+/32930 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifdd00d0a5d1e03bfa68a13eeece2d2cfd56aa39d Gerrit-Change-Number: 32930 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/amd/common: Clean up prototypes for AcpiMmio
by Marshall Dawson (Code Review) 06 Jun '19

06 Jun '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32929 Change subject: soc/amd/common: Clean up prototypes for AcpiMmio ...................................................................... soc/amd/common: Clean up prototypes for AcpiMmio Reorder the biosram prototypes to match the rest of the file. Remove prototypes for asf 32-bit functions that have not been implemented. Change-Id: Ic2663158d8a71952c26eb37f34342a6ea5e58a42 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/block/include/amdblocks/acpimmio.h 1 file changed, 1 insertion(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/32929/1 diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h index e1cf7cb..34e9ce9 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -44,9 +44,9 @@ void pm2_write16(uint8_t reg, uint16_t value); void pm2_write32(uint8_t reg, uint32_t value); uint8_t biosram_read8(uint8_t offset); -void biosram_write8(uint8_t offset, uint8_t value); uint16_t biosram_read16(uint8_t offset); uint32_t biosram_read32(uint8_t offset); +void biosram_write8(uint8_t offset, uint8_t value); void biosram_write16(uint8_t offset, uint16_t value); void biosram_write32(uint8_t offset, uint32_t value); uint8_t acpi_read8(uint8_t reg); @@ -57,10 +57,8 @@ void acpi_write32(uint8_t reg, uint32_t value); uint8_t asf_read8(uint8_t reg); uint16_t asf_read16(uint8_t reg); -uint32_t asf_read32(uint8_t reg); void asf_write8(uint8_t reg, uint8_t value); void asf_write16(uint8_t reg, uint16_t value); -void asf_write32(uint8_t reg, uint32_t value); uint8_t smbus_read8(uint8_t reg); uint16_t smbus_read16(uint8_t reg); void smbus_write8(uint8_t reg, uint8_t value); -- To view, visit https://review.coreboot.org/c/coreboot/+/32929 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2663158d8a71952c26eb37f34342a6ea5e58a42 Gerrit-Change-Number: 32929 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/amd/stoneyridge: Move alink source to common
by Marshall Dawson (Code Review) 06 Jun '19

06 Jun '19

Hello Richard Spiegel, Martin Roth, Furquan Shaikh, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32663 to review the following change. Change subject: src/amd/stoneyridge: Move alink source to common ...................................................................... src/amd/stoneyridge: Move alink source to common Relocate the alink access functions out of stoneyridge where they were dead code. This source maintains the ability to access all register spaces, however more modern APUs define only ABCFG in the BKDGs. Change-Id: I5c558ccc64bd04a66399c678d43beb0a97e72f63 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- A src/soc/amd/common/block/alink/Kconfig A src/soc/amd/common/block/alink/Makefile.inc A src/soc/amd/common/block/alink/alink.c A src/soc/amd/common/block/include/amdblocks/alink.h M src/soc/amd/stoneyridge/include/soc/smbus.h M src/soc/amd/stoneyridge/smbus.c 6 files changed, 154 insertions(+), 99 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/32663/1 diff --git a/src/soc/amd/common/block/alink/Kconfig b/src/soc/amd/common/block/alink/Kconfig new file mode 100644 index 0000000..75cf66f --- /dev/null +++ b/src/soc/amd/common/block/alink/Kconfig @@ -0,0 +1,5 @@ +config SOC_AMD_COMMON_BLOCK_ALINK + bool + default n + help + Select this option to access the FCH A-link configuration registers. diff --git a/src/soc/amd/common/block/alink/Makefile.inc b/src/soc/amd/common/block/alink/Makefile.inc new file mode 100644 index 0000000..720a7cb --- /dev/null +++ b/src/soc/amd/common/block/alink/Makefile.inc @@ -0,0 +1,6 @@ +bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_ALINK) += alink.c +verstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ALINK) += alink.c +romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ALINK) += alink.c +postcar-$(CONFIG_SOC_AMD_COMMON_BLOCK_ALINK) += alink.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ALINK) += alink.c +smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_ALINK) += alink.c diff --git a/src/soc/amd/common/block/alink/alink.c b/src/soc/amd/common/block/alink/alink.c new file mode 100644 index 0000000..f481f6b --- /dev/null +++ b/src/soc/amd/common/block/alink/alink.c @@ -0,0 +1,95 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <stdint.h> +#include <console/console.h> +#include <amdblocks/alink.h> + +void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val) +{ + u32 tmp; + + outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); + tmp = inl(AB_DATA); + /* rpr 4.2 + * For certain revisions of the chip, the ABCFG registers, + * with an address of 0x100NN (where 'N' is any hexadecimal + * number), require an extra programming step.*/ + outl(0, AB_INDX); + + tmp &= ~mask; + tmp |= val; + + // printk(BIOS_DEBUG, "about write %x, index=%x", tmp, + // (reg_space&0x3)<<29 | reg_addr); + + /* probably we dont have to do it again. */ + outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); + outl(tmp, AB_DATA); + outl(0, AB_INDX); +} + +void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val) +{ + u32 tmp; + + outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); + tmp = inl(AB_DATA); + /* rpr 4.2 + * For certain revisions of the chip, the ABCFG registers, + * with an address of 0x100NN (where 'N' is any hexadecimal + * number), require an extra programming step.*/ + outl(0, AB_INDX); + + tmp &= ~mask; + tmp |= val; + + //printk(BIOS_DEBUG, "about write %x, index=%x", tmp, + // (reg_space&0x3)<<29 | (port&3) << 24 | reg_addr); + + /* probably we dont have to do it again. */ + outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); + outl(tmp, AB_DATA); + outl(0, AB_INDX); +} + +/* + * space = 0: AX_INDXC, AX_DATAC + * space = 1: AX_INDXP, AX_DATAP + */ +void alink_ax_indx(u32 space /*c or p? */, u32 axindc, u32 mask, u32 val) +{ + u32 tmp; + + /* read axindc to tmp */ + outl(space << 29 | space << 3 | 0x30, AB_INDX); + outl(axindc, AB_DATA); + outl(0, AB_INDX); + outl(space << 29 | space << 3 | 0x34, AB_INDX); + tmp = inl(AB_DATA); + outl(0, AB_INDX); + + tmp &= ~mask; + tmp |= val; + + /* write tmp */ + outl(space << 29 | space << 3 | 0x30, AB_INDX); + outl(axindc, AB_DATA); + outl(0, AB_INDX); + outl(space << 29 | space << 3 | 0x34, AB_INDX); + outl(tmp, AB_DATA); + outl(0, AB_INDX); +} diff --git a/src/soc/amd/common/block/include/amdblocks/alink.h b/src/soc/amd/common/block/include/amdblocks/alink.h new file mode 100644 index 0000000..d14df04 --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/alink.h @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AMDBLOCKS_ALINK_H__ +#define __AMDBLOCKS_ALINK_H__ + +#include <stdint.h> + +#define AB_INDX 0xcd8 +#define AB_DATA (AB_INDX+4) + +#define AX_INDXC 0 +#define AX_INDXP 2 +#define AXCFG 4 +#define ABCFG 6 +#define RC_INDXC 1 +#define RC_INDXP 3 + +#define abcfg_reg(reg, mask, val) \ + alink_ab_indx((ABCFG), (reg), (mask), (val)) +#define axcfg_reg(reg, mask, val) \ + alink_ab_indx((AXCFG), (reg), (mask), (val)) +#define axindxc_reg(reg, mask, val) \ + alink_ax_indx((AX_INDXC), (reg), (mask), (val)) +#define axindxp_reg(reg, mask, val) \ + alink_ax_indx((AX_INDXP), (reg), (mask), (val)) +#define rcindxc_reg(reg, port, mask, val) \ + alink_rc_indx((RC_INDXC), (reg), (port), (mask), (val)) +#define rcindxp_reg(reg, port, mask, val) \ + alink_rc_indx((RC_INDXP), (reg), (port), (mask), (val)) + +void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val); +void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val); +void alink_ax_indx(u32 space /*c or p? */, u32 axindc, u32 mask, u32 val); + +#endif /* __AMDBLOCKS_ALINK_H__ */ diff --git a/src/soc/amd/stoneyridge/include/soc/smbus.h b/src/soc/amd/stoneyridge/include/soc/smbus.h index 71f7faf..391084d 100644 --- a/src/soc/amd/stoneyridge/include/soc/smbus.h +++ b/src/soc/amd/stoneyridge/include/soc/smbus.h @@ -21,38 +21,15 @@ #define SMB_SPEED_400KHZ (66000000 / (400000 * 4)) -#define AX_INDXC 0 -#define AX_INDXP 2 -#define AXCFG 4 -#define ABCFG 6 -#define RC_INDXC 1 -#define RC_INDXP 3 - /* * Between 1-10 seconds, We should never timeout normally * Longer than this is just painful when a timeout condition occurs. */ #define SMBUS_TIMEOUT (100 * 1000 * 10) -#define abcfg_reg(reg, mask, val) \ - alink_ab_indx((ABCFG), (reg), (mask), (val)) -#define axcfg_reg(reg, mask, val) \ - alink_ab_indx((AXCFG), (reg), (mask), (val)) -#define axindxc_reg(reg, mask, val) \ - alink_ax_indx((AX_INDXC), (reg), (mask), (val)) -#define axindxp_reg(reg, mask, val) \ - alink_ax_indx((AX_INDXP), (reg), (mask), (val)) -#define rcindxc_reg(reg, port, mask, val) \ - alink_rc_indx((RC_INDXC), (reg), (port), (mask), (val)) -#define rcindxp_reg(reg, port, mask, val) \ - alink_rc_indx((RC_INDXP), (reg), (port), (mask), (val)) - int do_smbus_read_byte(u32 mmio, u8 device, u8 address); int do_smbus_write_byte(u32 mmio, u8 device, u8 address, u8 val); int do_smbus_recv_byte(u32 mmio, u8 device); int do_smbus_send_byte(u32 mmio, u8 device, u8 val); -void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val); -void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val); -void alink_ax_indx(u32 space /*c or p? */, u32 axindc, u32 mask, u32 val); #endif /* __STONEYRIDGE_SMBUS_H__ */ diff --git a/src/soc/amd/stoneyridge/smbus.c b/src/soc/amd/stoneyridge/smbus.c index df7a86e..31457f9 100644 --- a/src/soc/amd/stoneyridge/smbus.c +++ b/src/soc/amd/stoneyridge/smbus.c @@ -189,79 +189,3 @@ return 0; } - -void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val) -{ - u32 tmp; - - outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); - tmp = inl(AB_DATA); - /* rpr 4.2 - * For certain revisions of the chip, the ABCFG registers, - * with an address of 0x100NN (where 'N' is any hexadecimal - * number), require an extra programming step.*/ - outl(0, AB_INDX); - - tmp &= ~mask; - tmp |= val; - - // printk(BIOS_DEBUG, "about write %x, index=%x", tmp, - // (reg_space&0x3)<<29 | reg_addr); - - /* probably we dont have to do it again. */ - outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); - outl(tmp, AB_DATA); - outl(0, AB_INDX); -} - -void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val) -{ - u32 tmp; - - outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); - tmp = inl(AB_DATA); - /* rpr 4.2 - * For certain revisions of the chip, the ABCFG registers, - * with an address of 0x100NN (where 'N' is any hexadecimal - * number), require an extra programming step.*/ - outl(0, AB_INDX); - - tmp &= ~mask; - tmp |= val; - - //printk(BIOS_DEBUG, "about write %x, index=%x", tmp, - // (reg_space&0x3)<<29 | (port&3) << 24 | reg_addr); - - /* probably we dont have to do it again. */ - outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); - outl(tmp, AB_DATA); - outl(0, AB_INDX); -} - -/* - * space = 0: AX_INDXC, AX_DATAC - * space = 1: AX_INDXP, AX_DATAP - */ -void alink_ax_indx(u32 space /*c or p? */, u32 axindc, u32 mask, u32 val) -{ - u32 tmp; - - /* read axindc to tmp */ - outl(space << 29 | space << 3 | 0x30, AB_INDX); - outl(axindc, AB_DATA); - outl(0, AB_INDX); - outl(space << 29 | space << 3 | 0x34, AB_INDX); - tmp = inl(AB_DATA); - outl(0, AB_INDX); - - tmp &= ~mask; - tmp |= val; - - /* write tmp */ - outl(space << 29 | space << 3 | 0x30, AB_INDX); - outl(axindc, AB_DATA); - outl(0, AB_INDX); - outl(space << 29 | space << 3 | 0x34, AB_INDX); - outl(tmp, AB_DATA); - outl(0, AB_INDX); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/32663 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c558ccc64bd04a66399c678d43beb0a97e72f63 Gerrit-Change-Number: 32663 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-MessageType: newchange

4 11

Change in ...coreboot[master]: soc/amd/stoneyrige: Add ALink-AHB Bridge to iomap.h
by Marshall Dawson (Code Review) 06 Jun '19

06 Jun '19

Hello Richard Spiegel, Martin Roth, Furquan Shaikh, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32662 to review the following change. Change subject: soc/amd/stoneyrige: Add ALink-AHB Bridge to iomap.h ...................................................................... soc/amd/stoneyrige: Add ALink-AHB Bridge to iomap.h Add the address and replace the hardcoded value in the ASL code. Change-Id: If0b99de78d8c5948e2e5f2aa50dfc2efc1bd1ba1 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/acpi/sb_fch.asl M src/soc/amd/stoneyridge/include/soc/iomap.h 2 files changed, 6 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/32662/1 diff --git a/src/soc/amd/stoneyridge/acpi/sb_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_fch.asl index 4c1196d..e7975f8 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_fch.asl @@ -22,7 +22,7 @@ Name (_UID, 0x0) Name (_CRS, ResourceTemplate() { - Memory32Fixed (ReadWrite, 0xFEDC0000, 0x2000) + Memory32Fixed (ReadWrite, ALINK_AHB_ADDRESS, 0x2000) }) Method (_STA, 0x0, NotSerialized) diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h index 7762043..3856a22 100644 --- a/src/soc/amd/stoneyridge/include/soc/iomap.h +++ b/src/soc/amd/stoneyridge/include/soc/iomap.h @@ -25,10 +25,12 @@ /* AcpiMmio blocks are at fixed offsets from FED8_0000h, enabled in PMx04[1] */ #include <amdblocks/acpimmio_map.h> +#define ALINK_AHB_ADDRESS 0xfedc0000 + /* I2C fixed address */ -#define I2C_BASE_ADDRESS 0xfedc2000 -#define I2C_DEVICE_SIZE 0x00001000 -#define I2C_DEVICE_COUNT 4 +#define I2C_BASE_ADDRESS 0xfedc2000 +#define I2C_DEVICE_SIZE 0x00001000 +#define I2C_DEVICE_COUNT 4 #if CONFIG(HPET_ADDRESS_OVERRIDE) #error HPET address override is not allowed and must be fixed at 0xfed00000 -- To view, visit https://review.coreboot.org/c/coreboot/+/32662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0b99de78d8c5948e2e5f2aa50dfc2efc1bd1ba1 Gerrit-Change-Number: 32662 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-MessageType: newchange

4 8

Change in ...coreboot[master]: soc/amd/stoneyridge: Move sata to common
by Marshall Dawson (Code Review) 06 Jun '19

06 Jun '19

Hello Richard Spiegel, Martin Roth, Furquan Shaikh, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32661 to review the following change. Change subject: soc/amd/stoneyridge: Move sata to common ...................................................................... soc/amd/stoneyridge: Move sata to common Relocate generic sata support from stoneyridge to common/block. Change-Id: I4e9eddaa291e5e03f4f8d88826973c5b8ee9a1c5 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- A src/soc/amd/common/block/include/amdblocks/sata.h A src/soc/amd/common/block/sata/Kconfig A src/soc/amd/common/block/sata/Makefile.inc A src/soc/amd/common/block/sata/sata.c M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/sata.c 6 files changed, 83 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/32661/1 diff --git a/src/soc/amd/common/block/include/amdblocks/sata.h b/src/soc/amd/common/block/include/amdblocks/sata.h new file mode 100644 index 0000000..0469e7b --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/sata.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AMDBLOCKS_SATA_H__ +#define __STON__AMDBLOCKS_SATA_H__EYRIDGE_CPU_H__ + +#include <device/device.h> + +void soc_enable_sata_features(struct device *dev); + +#endif /* __AMDBLOCKS_SATA_H__ */ diff --git a/src/soc/amd/common/block/sata/Kconfig b/src/soc/amd/common/block/sata/Kconfig new file mode 100644 index 0000000..0c3d5bc --- /dev/null +++ b/src/soc/amd/common/block/sata/Kconfig @@ -0,0 +1,5 @@ +config SOC_AMD_COMMON_BLOCK_SATA + bool + default n + help + Select this option to use AMD common SATA driver support. diff --git a/src/soc/amd/common/block/sata/Makefile.inc b/src/soc/amd/common/block/sata/Makefile.inc new file mode 100644 index 0000000..59b99eb --- /dev/null +++ b/src/soc/amd/common/block/sata/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_HDA) += sata.c diff --git a/src/soc/amd/common/block/sata/sata.c b/src/soc/amd/common/block/sata/sata.c new file mode 100644 index 0000000..905c145 --- /dev/null +++ b/src/soc/amd/common/block/sata/sata.c @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <amdblocks/sata.h> + +void __weak soc_enable_sata_features(struct device *dev) { } + +static void sata_init(struct device *dev) +{ + soc_enable_sata_features(dev); +} + +static struct pci_operations lops_pci = { + /* .set_subsystem = pci_dev_set_subsystem, */ +}; + +static struct device_operations sata_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = sata_init, + .ops_pci = &lops_pci, +}; + +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_AMD_CZ_SATA, + PCI_DEVICE_ID_AMD_CZ_SATA_AHCI, + 0 +}; + +static const struct pci_driver sata0_driver __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_AMD, + .devices = pci_device_ids, +}; diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index cbb8ba0..a307f66 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -52,6 +52,7 @@ select SOC_AMD_COMMON_BLOCK_ACPI select SOC_AMD_COMMON_BLOCK_LPC select SOC_AMD_COMMON_BLOCK_PCI + select SOC_AMD_COMMON_BLOCK_SATA select SOC_AMD_COMMON_BLOCK_PI select SOC_AMD_COMMON_BLOCK_PSP select SOC_AMD_COMMON_BLOCK_CAR diff --git a/src/soc/amd/stoneyridge/sata.c b/src/soc/amd/stoneyridge/sata.c index f0dabe0..6740698 100644 --- a/src/soc/amd/stoneyridge/sata.c +++ b/src/soc/amd/stoneyridge/sata.c @@ -18,9 +18,10 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <device/pci_def.h> +#include <amdblocks/sata.h> #include <soc/southbridge.h> -static void soc_enable_sata_features(struct device *dev) +void soc_enable_sata_features(struct device *dev) { u8 *ahci_ptr; u32 misc_ctl, cap_cfg; @@ -45,32 +46,3 @@ temp &= ~SATA_MISC_SUBCLASS_WREN; pci_write_config32(dev, SATA_MISC_CONTROL_REG, temp); }; - -static void sata_init(struct device *dev) -{ - soc_enable_sata_features(dev); -} - -static struct pci_operations lops_pci = { - /* .set_subsystem = pci_dev_set_subsystem, */ -}; - -static struct device_operations sata_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = sata_init, - .ops_pci = &lops_pci, -}; - -static const unsigned short pci_device_ids[] = { - PCI_DEVICE_ID_AMD_CZ_SATA, - PCI_DEVICE_ID_AMD_CZ_SATA_AHCI, - 0 -}; - -static const struct pci_driver sata0_driver __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_AMD, - .devices = pci_device_ids, -}; -- To view, visit https://review.coreboot.org/c/coreboot/+/32661 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e9eddaa291e5e03f4f8d88826973c5b8ee9a1c5 Gerrit-Change-Number: 32661 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-MessageType: newchange

4 9

Change in ...coreboot[master]: soc/amd/stoneyridge: Split sata functionality
by Marshall Dawson (Code Review) 06 Jun '19

06 Jun '19

Hello Richard Spiegel, Martin Roth, Furquan Shaikh, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32660 to review the following change. Change subject: soc/amd/stoneyridge: Split sata functionality ...................................................................... soc/amd/stoneyridge: Split sata functionality Separate chipset-specific source from sata_init(), and modify it to better match coreboot conventions. A subsequent patch will move the generic portion to soc/amd/common. The support for enabling port multipliers appears to have been first added for Kabini. Although missing from the documentation, the ability to affect the HBA Capabilities Register seems to remain for Stoney Ridge. Change-Id: I5dd9f613d36badc3e4d185a22b4475cb82ce187e Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/sata.c 2 files changed, 28 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/32660/1 diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 99e5eef..334d281 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -250,6 +250,13 @@ /* ISA Bridge SPI BASE at D14F3xA0 */ #define SPI_BASE_ALIGNMENT 32 +/* SATA Controller D11F0 */ +#define SATA_MISC_CONTROL_REG 0x40 +#define SATA_MISC_SUBCLASS_WREN BIT(0) +/* Register in AHCIBaseAddress (BAR5 at D11F0x24) */ +#define SATA_CAPABILITIES_REG 0xfc +#define SATA_CAPABILITY_SPM BIT(12) + /* SPI Controller (base address in D14F3xA0) */ #define SPI_CNTRL0 0x00 #define SPI_BUSY BIT(31) diff --git a/src/soc/amd/stoneyridge/sata.c b/src/soc/amd/stoneyridge/sata.c index 52932e2..f0dabe0 100644 --- a/src/soc/amd/stoneyridge/sata.c +++ b/src/soc/amd/stoneyridge/sata.c @@ -17,40 +17,40 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> +#include <device/pci_def.h> #include <soc/southbridge.h> - -static void sata_init(struct device *dev) +static void soc_enable_sata_features(struct device *dev) { - /************************************** - * Configure the SATA port multiplier * - **************************************/ - #define BYTE_TO_DWORD_OFFSET(x) (x/4) - #define AHCI_BASE_ADDRESS_REG 0x24 - #define MISC_CONTROL_REG 0x40 - #define UNLOCK_BIT (1<<0) - #define SATA_CAPABILITIES_REG 0xfc - #define CFG_CAP_SPM (1<<12) + u8 *ahci_ptr; + u32 misc_ctl, cap_cfg; - u32 *ahci_ptr = (void *)(uintptr_t)ALIGN_DOWN( - pci_read_config32(dev, AHCI_BASE_ADDRESS_REG), 256); u32 temp; /* unlock the write-protect */ - temp = pci_read_config32(dev, MISC_CONTROL_REG); - temp |= UNLOCK_BIT; - pci_write_config32(dev, MISC_CONTROL_REG, temp); + misc_ctl = pci_read_config32(dev, SATA_MISC_CONTROL_REG); + misc_ctl |= SATA_MISC_SUBCLASS_WREN; + pci_write_config32(dev, SATA_MISC_CONTROL_REG, misc_ctl); /* set the SATA AHCI mode to allow port expanders */ - *(ahci_ptr + BYTE_TO_DWORD_OFFSET(SATA_CAPABILITIES_REG)) - |= CFG_CAP_SPM; + ahci_ptr = (u8 *)(uintptr_t)ALIGN_DOWN( + pci_read_config32(dev, PCI_BASE_ADDRESS_5), 256); + + cap_cfg = read32(ahci_ptr + SATA_CAPABILITIES_REG); + cap_cfg |= SATA_CAPABILITY_SPM; + write32(ahci_ptr + SATA_CAPABILITIES_REG, cap_cfg); /* lock the write-protect */ - temp = pci_read_config32(dev, MISC_CONTROL_REG); - temp &= ~UNLOCK_BIT; - pci_write_config32(dev, MISC_CONTROL_REG, temp); + temp = pci_read_config32(dev, SATA_MISC_CONTROL_REG); + temp &= ~SATA_MISC_SUBCLASS_WREN; + pci_write_config32(dev, SATA_MISC_CONTROL_REG, temp); }; +static void sata_init(struct device *dev) +{ + soc_enable_sata_features(dev); +} + static struct pci_operations lops_pci = { /* .set_subsystem = pci_dev_set_subsystem, */ }; -- To view, visit https://review.coreboot.org/c/coreboot/+/32660 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5dd9f613d36badc3e4d185a22b4475cb82ce187e Gerrit-Change-Number: 32660 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-MessageType: newchange

4 5

Change in ...coreboot[master]: soc/amd/stoneyridge: Remove sb_util.c
by Marshall Dawson (Code Review) 06 Jun '19

06 Jun '19

Hello Richard Spiegel, Martin Roth, Furquan Shaikh, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32659 to review the following change. Change subject: soc/amd/stoneyridge: Remove sb_util.c ...................................................................... soc/amd/stoneyridge: Remove sb_util.c pm_acpi_pm_cnt_blk() is only used in the SMI handler when reissuing the SLP_TYP cycle to send the device into S3/S5. This must be an I/O cycle, not MMIO. Make this a static in smihandler.c. Remove unused pm_acpi_pm_evt_blk(). Relocate the reamining functions to get/save UMA information to southbridge.c. Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: I90c4394e3cf26f4ad60a078948a84303bda693d0 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/Makefile.inc M src/soc/amd/stoneyridge/include/soc/southbridge.h D src/soc/amd/stoneyridge/sb_util.c M src/soc/amd/stoneyridge/smihandler.c M src/soc/amd/stoneyridge/southbridge.c 5 files changed, 29 insertions(+), 62 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/32659/1 diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 57c886d..babd878 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -46,7 +46,6 @@ bootblock-y += monotonic_timer.c bootblock-y += pmutil.c bootblock-y += reset.c -bootblock-y += sb_util.c bootblock-y += tsc_freq.c bootblock-y += southbridge.c bootblock-y += nb_util.c @@ -61,7 +60,6 @@ romstage-y += monotonic_timer.c romstage-y += pmutil.c romstage-y += reset.c -romstage-y += sb_util.c romstage-y += smbus.c romstage-y += smbus_spd.c romstage-y += ramtop.c @@ -75,7 +73,6 @@ verstage-y += gpio.c verstage-y += i2c.c verstage-y += monotonic_timer.c -verstage-y += sb_util.c verstage-y += pmutil.c verstage-y += reset.c verstage-$(CONFIG_STONEYRIDGE_UART) += uart.c @@ -86,7 +83,6 @@ postcar-y += monotonic_timer.c postcar-$(CONFIG_STONEYRIDGE_UART) += uart.c postcar-y += ramtop.c -postcar-y += sb_util.c postcar-y += nb_util.c postcar-$(CONFIG_VBOOT_MEASURED_BOOT) += i2c.c postcar-y += tsc_freq.c @@ -101,7 +97,6 @@ ramstage-y += gpio.c ramstage-y += monotonic_timer.c ramstage-y += southbridge.c -ramstage-y += sb_util.c ramstage-y += northbridge.c ramstage-y += pmutil.c ramstage-y += reset.c @@ -121,7 +116,6 @@ smm-y += monotonic_timer.c smm-y += smihandler.c smm-y += smi_util.c -smm-y += sb_util.c smm-y += tsc_freq.c smm-$(CONFIG_DEBUG_SMI) += uart.c smm-$(CONFIG_SPI_FLASH) += spi.c diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 40d6ec7..99e5eef 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -357,8 +357,6 @@ void southbridge_init(void *chip_info); void sb_read_mode(u32 mode); void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm); -uint16_t pm_acpi_pm_cnt_blk(void); -uint16_t pm_acpi_pm_evt_blk(void); void bootblock_fch_early_init(void); void bootblock_fch_init(void); /** diff --git a/src/soc/amd/stoneyridge/sb_util.c b/src/soc/amd/stoneyridge/sb_util.c deleted file mode 100644 index 7869065..0000000 --- a/src/soc/amd/stoneyridge/sb_util.c +++ /dev/null @@ -1,54 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2017 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <device/mmio.h> -#include <arch/acpi.h> -#include <amdblocks/acpimmio.h> -#include <soc/southbridge.h> - -uint16_t pm_acpi_pm_cnt_blk(void) -{ - return pm_read16(PM1_CNT_BLK); -} - -uint16_t pm_acpi_pm_evt_blk(void) -{ - return pm_read16(PM_EVT_BLK); -} - -void save_uma_size(uint32_t size) -{ - biosram_write32(BIOSRAM_UMA_SIZE, size); -} - -void save_uma_base(uint64_t base) -{ - biosram_write32(BIOSRAM_UMA_BASE, (uint32_t) base); - biosram_write32(BIOSRAM_UMA_BASE + 4, (uint32_t) (base >> 32)); -} - -uint32_t get_uma_size(void) -{ - return biosram_read32(BIOSRAM_UMA_SIZE); -} - -uint64_t get_uma_base(void) -{ - uint64_t base; - base = biosram_read32(BIOSRAM_UMA_BASE); - base |= ((uint64_t)(biosram_read32(BIOSRAM_UMA_BASE + 4)) << 32); - return base; -} diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c index e08aee4..55367ea 100644 --- a/src/soc/amd/stoneyridge/smihandler.c +++ b/src/soc/amd/stoneyridge/smihandler.c @@ -118,6 +118,11 @@ smi_write32(SMI_REG_SMISTS4, smi_read32(SMI_REG_SMISTS4)); } +static uint16_t pm_acpi_pm_cnt_blk(void) +{ + return pm_read16(PM1_CNT_BLK); +} + static void sb_slp_typ_handler(void) { uint32_t pci_ctrl, reg32; diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index a08d6b5..b3b9e36 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -649,3 +649,27 @@ * on entry into BS_DEV_ENABLE. */ BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL); + +void save_uma_size(uint32_t size) +{ + biosram_write32(BIOSRAM_UMA_SIZE, size); +} + +void save_uma_base(uint64_t base) +{ + biosram_write32(BIOSRAM_UMA_BASE, (uint32_t) base); + biosram_write32(BIOSRAM_UMA_BASE + 4, (uint32_t) (base >> 32)); +} + +uint32_t get_uma_size(void) +{ + return biosram_read32(BIOSRAM_UMA_SIZE); +} + +uint64_t get_uma_base(void) +{ + uint64_t base; + base = biosram_read32(BIOSRAM_UMA_BASE); + base |= ((uint64_t)(biosram_read32(BIOSRAM_UMA_BASE + 4)) << 32); + return base; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/32659 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I90c4394e3cf26f4ad60a078948a84303bda693d0 Gerrit-Change-Number: 32659 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-MessageType: newchange

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coreboot-gerrit June 2019