coreboot-gerrit June 2019

coreboot-gerrit@coreboot.org

1 participants
1454 discussions

Change in ...coreboot[master]: mainboard/portwell/m107: Do initial mainboard commit
by build bot (Jenkins) (Code Review) 06 Jun '19

06 Jun '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29470 ) Change subject: mainboard/portwell/m107: Do initial mainboard commit ...................................................................... Patch Set 15: (2 comments) https://review.coreboot.org/#/c/29470/15/src/mainboard/portwell/m107/irqrou… File src/mainboard/portwell/m107/irqroute.h: https://review.coreboot.org/#/c/29470/15/src/mainboard/portwell/m107/irqrou… PS15, Line 40: #define PCI_DEV_PIRQ_ROUTES \ Macros with complex values should be enclosed in parentheses https://review.coreboot.org/#/c/29470/15/src/mainboard/portwell/m107/irqrou… PS15, Line 62: #define PIRQ_PIC_ROUTES \ Macros with complex values should be enclosed in parentheses -- To view, visit https://review.coreboot.org/c/coreboot/+/29470 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d3173fdcf881f894a75cd9798ba173b425d4e62 Gerrit-Change-Number: 29470 Gerrit-PatchSet: 15 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 06 Jun 2019 14:09:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: mainboard/portwell/m107: Do initial mainboard commit
by Frans Hendriks (Code Review) 06 Jun '19

06 Jun '19

Hello Patrick Rudolph, Piotr Król, David Hendricks, Paul Menzel, build bot (Jenkins), Michał Żygowski, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29470 to look at the new patch set (#15). Change subject: mainboard/portwell/m107: Do initial mainboard commit ...................................................................... mainboard/portwell/m107: Do initial mainboard commit Initial support for Portwell PQ7-M107 (Q7) module. Code based on Intel Strago mainboard. BUG=N/A TEST=booting SeaBIOS and Linux 4.15 kernel on PQ7-M107 Change-Id: I7d3173fdcf881f894a75cd9798ba173b425d4e62 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M Documentation/mainboard/index.md A Documentation/mainboard/portwell/pq7-m107.md A src/mainboard/portwell/Kconfig A src/mainboard/portwell/Kconfig.name A src/mainboard/portwell/m107/Kconfig A src/mainboard/portwell/m107/Kconfig.name A src/mainboard/portwell/m107/Makefile.inc A src/mainboard/portwell/m107/acpi/ec.asl A src/mainboard/portwell/m107/acpi/mainboard.asl A src/mainboard/portwell/m107/acpi/sleepstates.asl A src/mainboard/portwell/m107/acpi/superio.asl A src/mainboard/portwell/m107/acpi_tables.c A src/mainboard/portwell/m107/board_info.txt A src/mainboard/portwell/m107/cmos.layout A src/mainboard/portwell/m107/com_init.c A src/mainboard/portwell/m107/devicetree.cb A src/mainboard/portwell/m107/dsdt.asl A src/mainboard/portwell/m107/fadt.c A src/mainboard/portwell/m107/gpio.c A src/mainboard/portwell/m107/hda_verb.c A src/mainboard/portwell/m107/irqroute.c A src/mainboard/portwell/m107/irqroute.h A src/mainboard/portwell/m107/mainboard.c A src/mainboard/portwell/m107/onboard.h A src/mainboard/portwell/m107/romstage.c A src/mainboard/portwell/m107/spd/MICRON_MT41K512M16HA-125A.spd.hex A src/mainboard/portwell/m107/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex A src/mainboard/portwell/m107/w25q64.c 28 files changed, 1,830 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/29470/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/29470 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d3173fdcf881f894a75cd9798ba173b425d4e62 Gerrit-Change-Number: 29470 Gerrit-PatchSet: 15 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: mainboard/portwell/m107: Do initial mainboard commit
by build bot (Jenkins) (Code Review) 06 Jun '19

06 Jun '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29470 ) Change subject: mainboard/portwell/m107: Do initial mainboard commit ...................................................................... Patch Set 14: (2 comments) https://review.coreboot.org/#/c/29470/14/src/mainboard/portwell/m107/irqrou… File src/mainboard/portwell/m107/irqroute.h: https://review.coreboot.org/#/c/29470/14/src/mainboard/portwell/m107/irqrou… PS14, Line 40: #define PCI_DEV_PIRQ_ROUTES \ Macros with complex values should be enclosed in parentheses https://review.coreboot.org/#/c/29470/14/src/mainboard/portwell/m107/irqrou… PS14, Line 62: #define PIRQ_PIC_ROUTES \ Macros with complex values should be enclosed in parentheses -- To view, visit https://review.coreboot.org/c/coreboot/+/29470 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d3173fdcf881f894a75cd9798ba173b425d4e62 Gerrit-Change-Number: 29470 Gerrit-PatchSet: 14 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 06 Jun 2019 13:56:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: mainboard/portwell/m107: Do initial mainboard commit
by Frans Hendriks (Code Review) 06 Jun '19

06 Jun '19

Hello Patrick Rudolph, Piotr Król, David Hendricks, Paul Menzel, build bot (Jenkins), Michał Żygowski, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29470 to look at the new patch set (#14). Change subject: mainboard/portwell/m107: Do initial mainboard commit ...................................................................... mainboard/portwell/m107: Do initial mainboard commit Initial support for Portwell PQ7-M107 (Q7) module. Code based on Intel Strago mainboard. BUG=N/A TEST=booting SeaBIOS and Linux 4.15 kernel on PQ7-M107 Change-Id: I7d3173fdcf881f894a75cd9798ba173b425d4e62 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M Documentation/mainboard/index.md A Documentation/mainboard/portwell/pq7-m107.md A src/mainboard/portwell/Kconfig A src/mainboard/portwell/Kconfig.name A src/mainboard/portwell/m107/Kconfig A src/mainboard/portwell/m107/Kconfig.name A src/mainboard/portwell/m107/Makefile.inc A src/mainboard/portwell/m107/acpi/ec.asl A src/mainboard/portwell/m107/acpi/mainboard.asl A src/mainboard/portwell/m107/acpi/sleepstates.asl A src/mainboard/portwell/m107/acpi/superio.asl A src/mainboard/portwell/m107/acpi_tables.c A src/mainboard/portwell/m107/board_info.txt A src/mainboard/portwell/m107/cmos.layout A src/mainboard/portwell/m107/com_init.c A src/mainboard/portwell/m107/devicetree.cb A src/mainboard/portwell/m107/dsdt.asl A src/mainboard/portwell/m107/fadt.c A src/mainboard/portwell/m107/gpio.c A src/mainboard/portwell/m107/hda_verb.c A src/mainboard/portwell/m107/irqroute.c A src/mainboard/portwell/m107/irqroute.h A src/mainboard/portwell/m107/mainboard.c A src/mainboard/portwell/m107/onboard.h A src/mainboard/portwell/m107/romstage.c A src/mainboard/portwell/m107/spd/MICRON_MT41K512M16HA-125A.spd.hex A src/mainboard/portwell/m107/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex A src/mainboard/portwell/m107/w25q64.c 28 files changed, 1,831 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/29470/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/29470 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d3173fdcf881f894a75cd9798ba173b425d4e62 Gerrit-Change-Number: 29470 Gerrit-PatchSet: 14 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: mb/dell: Add Dell Optiplex 790
by Christoph Pomaska (Code Review) 06 Jun '19

06 Jun '19

Hello Kyösti Mälkki, Patrick Rudolph, Felix Held, Angel Pons, Johanna Schander, Arthur Heymans, Jonathan Neuschäfer, Paul Menzel, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/21774 to look at the new patch set (#57). Change subject: mb/dell: Add Dell Optiplex 790 ...................................................................... mb/dell: Add Dell Optiplex 790 This port was generated by autoport and has been tweaked (see below) There are (at least) three different mainboards: - DT: 4 RAM slots, PEG, PCIe x1, PCI, PCIe x16 - MT: 4 RAM slots, PEG, PCIe x1, PCI, PCIe x16 - SFF: 4 RAM slots, PEG, PCIe x16 - USFF: 2 RAM slots, mPCIe The variants have different PCI/PCIe configurations and are not exactly compatible towards each other. This port has been tested with: USFF What works: - Booting Arch Linux with kernel 5.0.0-arch1-1-ARCH - PCIe (Hotplug on PCIe X1 only!) - Onboard graphics with libgfxinit (via VGA) - Turning on and off (S5) - Harddrive activity LED - Onboard sound - Onboard ethernet - SATA (hotplug) - IOMMU - Suspend/resume (S3) - EHCI debug (rear side, bottom port on the block with ethernet) What does not work: - SuperI/O (Chip is a SCH5544-NS) - Serial port - PS/2 - Fan control (fans go to full speed) - VBT is missing Further notes: - Default IFD settings block reads/writes to some regions. This can be bypassed by plugging the SERVICE_MODE jumper. BIOS version A05 does not set any protected ranges, so internal flashing is possible (use a layout if the SERVICE_MODE jumper is not plugged). - Setting the jumper slows down the boot process of coreboot significantly, as coreboot waits 900ms for the ME to report an OK DRAM (which doesn't happen with the jumper set) - The controller that controls the POST code LEDs on the front of the case (likely the SuperIO) stays on slow blinking POST 234, corrupt or defect BIOS according to [1]. - The mainboard has one SOIC16 8192KiB and one SOIC8 2048KiB BIOS chip that are recognized as one "Opaque flash chip" of 10240K in size. - Without the VGA_BIOS_FILE the make process starts behaving weird, so I will keep it in until further notice (Is this still true?) [1] http://www.dell.com/support/article/us/en/04/sln284978/a-reference-guide-to… Change-Id: If3d3a13163d5da1368259a7498019d42fb3ed57f Signed-off-by: Christoph Pomaska <github(a)aufmachen.jetzt> Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- A src/mainboard/dell/Kconfig A src/mainboard/dell/Kconfig.name A src/mainboard/dell/optiplex_790/Kconfig A src/mainboard/dell/optiplex_790/Kconfig.name A src/mainboard/dell/optiplex_790/Makefile.inc A src/mainboard/dell/optiplex_790/acpi/ec.asl A src/mainboard/dell/optiplex_790/acpi/platform.asl A src/mainboard/dell/optiplex_790/acpi/superio.asl A src/mainboard/dell/optiplex_790/acpi_tables.c A src/mainboard/dell/optiplex_790/board_info.txt A src/mainboard/dell/optiplex_790/dsdt.asl A src/mainboard/dell/optiplex_790/gma-mainboard.ads A src/mainboard/dell/optiplex_790/hda_verb.c A src/mainboard/dell/optiplex_790/mainboard.c A src/mainboard/dell/optiplex_790/romstage.c A src/mainboard/dell/optiplex_790/variants/optiplex_790_mt-sff/devicetree.cb A src/mainboard/dell/optiplex_790/variants/optiplex_790_mt-sff/gpio.c A src/mainboard/dell/optiplex_790/variants/optiplex_790_mt-sff/hda_verb.c A src/mainboard/dell/optiplex_790/variants/optiplex_790_usff/devicetree.cb A src/mainboard/dell/optiplex_790/variants/optiplex_790_usff/gpio.c A src/mainboard/dell/optiplex_790/variants/optiplex_790_usff/hda_verb.c 21 files changed, 1,151 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/21774/57 -- To view, visit https://review.coreboot.org/c/coreboot/+/21774 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3d3a13163d5da1368259a7498019d42fb3ed57f Gerrit-Change-Number: 21774 Gerrit-PatchSet: 57 Gerrit-Owner: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Johanna Schander <coreboot(a)mimoja.de> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: sb/intel/ibexpeak: Copy the sandybridge bootblock.c file
by Arthur Heymans (Code Review) 06 Jun '19

06 Jun '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33188 Change subject: sb/intel/ibexpeak: Copy the sandybridge bootblock.c file ...................................................................... sb/intel/ibexpeak: Copy the sandybridge bootblock.c file This allows to port C_ENVIRONMENT_BOOTBLOCK to sandybridge separately from nehalem. Change-Id: If3c6619cf22d1e2995eb19823b0f3f969d252b3b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/ibexpeak/Kconfig A src/southbridge/intel/ibexpeak/bootblock.c 2 files changed, 78 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/33188/1 diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index 85c8979..00eb413 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -53,7 +53,7 @@ config BOOTBLOCK_SOUTHBRIDGE_INIT string - default "southbridge/intel/bd82x6x/bootblock.c" + default "southbridge/intel/ibexpeak/bootblock.c" config SERIRQ_CONTINUOUS_MODE bool diff --git a/src/southbridge/intel/ibexpeak/bootblock.c b/src/southbridge/intel/ibexpeak/bootblock.c new file mode 100644 index 0000000..0086fe3 --- /dev/null +++ b/src/southbridge/intel/ibexpeak/bootblock.c @@ -0,0 +1,77 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/pci_ops.h> +#include "pch.h" + +/* + * Enable Prefetching and Caching. + */ +static void enable_spi_prefetch(void) +{ + u8 reg8; + pci_devfn_t dev = PCH_LPC_DEV; + + reg8 = pci_read_config8(dev, BIOS_CNTL); + reg8 &= ~(3 << 2); + reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ + pci_write_config8(dev, BIOS_CNTL, reg8); +} + +static void enable_port80_on_lpc(void) +{ + pci_devfn_t dev = PCH_LPC_DEV; + + /* Enable port 80 POST on LPC */ + pci_write_config32(dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1); +#if 0 + RCBA32(GCS) &= (~0x04); +#else + volatile u32 *gcs = (volatile u32 *)(DEFAULT_RCBA + GCS); + u32 reg32 = *gcs; + reg32 = reg32 & ~0x04; + *gcs = reg32; +#endif +} + +static void set_spi_speed(void) +{ + u32 fdod; + u8 ssfc; + + /* Observe SPI Descriptor Component Section 0 */ + RCBA32(0x38b0) = 0x1000; + + /* Extract the Write/Erase SPI Frequency from descriptor */ + fdod = RCBA32(0x38b4); + fdod >>= 24; + fdod &= 7; + + /* Set Software Sequence frequency to match */ + ssfc = RCBA8(0x3893); + ssfc &= ~7; + ssfc |= fdod; + RCBA8(0x3893) = ssfc; +} + +static void bootblock_southbridge_init(void) +{ + enable_spi_prefetch(); + enable_port80_on_lpc(); + set_spi_speed(); + + /* Enable upper 128bytes of CMOS */ + RCBA32(RC) = (1 << 2); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/33188 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3c6619cf22d1e2995eb19823b0f3f969d252b3b Gerrit-Change-Number: 33188 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 3

Change in ...coreboot[master]: QCS405: Added RPM support
by Patrick Georgi (Code Review) 06 Jun '19

06 Jun '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29970 ) Change subject: QCS405: Added RPM support ...................................................................... Patch Set 28: -Code-Review oops, missed half of the commit during review -- To view, visit https://review.coreboot.org/c/coreboot/+/29970 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I17f491f0a4bd0dce7522b7e80e1bac97ec18b945 Gerrit-Change-Number: 29970 Gerrit-PatchSet: 28 Gerrit-Owner: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sricharan Ramabadhran <srichara(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Thu, 06 Jun 2019 12:01:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: QCS405: Added RPM support
by Patrick Georgi (Code Review) 06 Jun '19

06 Jun '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29970 ) Change subject: QCS405: Added RPM support ...................................................................... Patch Set 28: Code-Review+1 (1 comment) too much debug printing, otherwise this looks okay https://review.coreboot.org/#/c/29970/28/src/soc/qualcomm/qcs405/rpm_load_r… File src/soc/qualcomm/qcs405/rpm_load_reset.c: https://review.coreboot.org/#/c/29970/28/src/soc/qualcomm/qcs405/rpm_load_r… PS28, Line 42: printk(BIOS_DEBUG, "\nNIT:PROG_INIT for /rpm has happened.\n"); These lowlevel debugging messages can probably be removed? -- To view, visit https://review.coreboot.org/c/coreboot/+/29970 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I17f491f0a4bd0dce7522b7e80e1bac97ec18b945 Gerrit-Change-Number: 29970 Gerrit-PatchSet: 28 Gerrit-Owner: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sricharan Ramabadhran <srichara(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Thu, 06 Jun 2019 12:00:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: src/soc/intel/common/smbios: Add addtional infos to dimm_info
by Christian Walter (Code Review) 06 Jun '19

06 Jun '19

Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33031 Change subject: src/soc/intel/common/smbios: Add addtional infos to dimm_info ...................................................................... src/soc/intel/common/smbios: Add addtional infos to dimm_info Added ECC Support and VDD Voltage to dimm_info struct. Now Bus Width and ECCSupport will be propagated correctly in SMBIOS Type 17 Entry. Change-Id: Ic6f0d4b223f1490ec7aa71a6105603635b514021 Signed-off-by: Christian Walter <christian.walter(a)9elements.com> --- M src/arch/x86/smbios.c M src/include/memory_info.h M src/soc/intel/apollolake/meminit_util_apl.c M src/soc/intel/apollolake/meminit_util_glk.c M src/soc/intel/cannonlake/romstage/romstage.c M src/soc/intel/common/smbios.c M src/soc/intel/common/smbios.h M src/soc/intel/icelake/romstage/romstage.c M src/soc/intel/skylake/romstage/romstage_fsp20.c 9 files changed, 42 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/33031/1 diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index bf627f2..54c2b09 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -372,6 +372,11 @@ dimm->module_part_number[DIMM_INFO_PART_NUMBER_SIZE - 1] = '\0'; smbios_fill_dimm_part_number((char *)dimm->module_part_number, t); + /* Voltage Levels */ + t->configured_voltage = dimm->vdd_voltage; + t->minimum_voltage = dimm->vdd_voltage; + t->maximum_voltage = dimm->vdd_voltage; + /* Synchronous = 1 */ t->type_detail = 0x0080; /* no handle for error information */ diff --git a/src/include/memory_info.h b/src/include/memory_info.h index 93c7b6b..c11e745 100644 --- a/src/include/memory_info.h +++ b/src/include/memory_info.h @@ -86,6 +86,10 @@ * See the smbios.h smbios_memory_bus_width enum. */ uint8_t bus_width; + /* + * Voltage Level + */ + uint32_t vdd_voltage; } __packed; struct memory_info { diff --git a/src/soc/intel/apollolake/meminit_util_apl.c b/src/soc/intel/apollolake/meminit_util_apl.c index b272a99..cda7be5 100644 --- a/src/soc/intel/apollolake/meminit_util_apl.c +++ b/src/soc/intel/apollolake/meminit_util_apl.c @@ -80,6 +80,8 @@ if (!src_dimm->SizeInMb) continue; + u8 memProfNum = memory_info_hob->MemoryProfile; + /* Populate the DIMM information */ dimm_info_fill(dest_dimm, src_dimm->SizeInMb, @@ -91,7 +93,9 @@ dram_part_num, strlen(dram_part_num), NULL, /* SPD not available */ - memory_info_hob->DataWidth); + memory_info_hob->DataWidth, + memory_info_hob->VddVoltage[memProfNum], + memory_info_hob->EccSupport); index++; } } diff --git a/src/soc/intel/apollolake/meminit_util_glk.c b/src/soc/intel/apollolake/meminit_util_glk.c index 29dcd56..6940da6 100644 --- a/src/soc/intel/apollolake/meminit_util_glk.c +++ b/src/soc/intel/apollolake/meminit_util_glk.c @@ -86,6 +86,8 @@ if (!src_dimm->DimmCapacity) continue; + u8 memProfNum = memory_info_hob->MemoryProfile; + /* Populate the DIMM information */ dimm_info_fill(dest_dimm, src_dimm->DimmCapacity, @@ -97,7 +99,9 @@ dram_part_num, strlen(dram_part_num), src_dimm->SpdSave + SPD_SAVE_OFFSET_SERIAL, - memory_info_hob->DataWidth); + memory_info_hob->DataWidth, + memory_info_hob->VddVoltage[memProfNum], + memory_info_hob->EccSupport); index++; } } diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index 98d4c00..fa530a2 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -101,6 +101,8 @@ mainboard_get_dram_part_num(&dram_part_num, &dram_part_num_len); + u8 memProfNum = memory_info_hob->MemoryProfile; + /* Populate the DIMM information */ dimm_info_fill(dest_dimm, src_dimm->DimmCapacity, @@ -112,7 +114,9 @@ dram_part_num, dram_part_num_len, src_dimm->SpdSave + SPD_SAVE_OFFSET_SERIAL, - memory_info_hob->DataWidth); + memory_info_hob->DataWidth, + memory_info_hob->VddVoltage[memProfNum], + memory_info_hob->EccSupport); index++; } } diff --git a/src/soc/intel/common/smbios.c b/src/soc/intel/common/smbios.c index d89e9d5..f96e7f3 100644 --- a/src/soc/intel/common/smbios.c +++ b/src/soc/intel/common/smbios.c @@ -22,7 +22,8 @@ void dimm_info_fill(struct dimm_info *dimm, u32 dimm_capacity, u8 ddr_type, u32 frequency, u8 rank_per_dimm, u8 channel_id, u8 dimm_id, const char *module_part_num, size_t module_part_number_size, - const u8 *module_serial_num, u16 data_width) + const u8 *module_serial_num, u16 data_width, u32 vdd_voltage, + bool ecc_support) { dimm->dimm_size = dimm_capacity; dimm->ddr_type = ddr_type; @@ -30,6 +31,8 @@ dimm->rank_per_dimm = rank_per_dimm; dimm->channel_num = channel_id; dimm->dimm_num = dimm_id; + dimm->vdd_voltage = vdd_voltage; + strncpy((char *)dimm->module_part_number, module_part_num, min(sizeof(dimm->module_part_number), @@ -57,4 +60,7 @@ printk(BIOS_NOTICE, "Incorrect DIMM Data width: %u\n", (unsigned int)data_width); } + + if (ecc_support) + dimm->bus_width |= 0x8; } diff --git a/src/soc/intel/common/smbios.h b/src/soc/intel/common/smbios.h index 5824f5d..12b8da0 100644 --- a/src/soc/intel/common/smbios.h +++ b/src/soc/intel/common/smbios.h @@ -26,6 +26,7 @@ void dimm_info_fill(struct dimm_info *dimm, u32 dimm_capacity, u8 ddr_type, u32 frequency, u8 rank_per_dimm, u8 channel_id, u8 dimm_id, const char *module_part_num, size_t module_part_number_size, - const u8 *module_serial_num, u16 data_width); + const u8 *module_serial_num, u16 data_width, u32 vdd_voltage, + bool ecc_support); #endif /* _COMMON_SMBIOS_H_ */ diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c index 179d99c..a09641c 100644 --- a/src/soc/intel/icelake/romstage/romstage.c +++ b/src/soc/intel/icelake/romstage/romstage.c @@ -86,6 +86,8 @@ if (src_dimm->Status != DIMM_PRESENT) continue; + u8 memProfNum = memory_info_hob->MemoryProfile; + /* Populate the DIMM information */ dimm_info_fill(dest_dimm, src_dimm->DimmCapacity, @@ -97,7 +99,9 @@ (const char *)src_dimm->ModulePartNum, sizeof(src_dimm->ModulePartNum), src_dimm->SpdSave + SPD_SAVE_OFFSET_SERIAL, - memory_info_hob->DataWidth); + memory_info_hob->DataWidth, + memory_info_hob->VddVoltage[memProfNum], + memory_info_hob->EccSupport); index++; } } diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 96937d6..12ad757 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -115,6 +115,7 @@ ddr_type = MEMORY_TYPE_UNKNOWN; break; } + u8 memProfNum = memory_info_hob->MemoryProfile; /* Populate the DIMM information */ dimm_info_fill(dest_dimm, @@ -127,7 +128,9 @@ (const char *)src_dimm->ModulePartNum, sizeof(src_dimm->ModulePartNum), src_dimm->SpdSave + SPD_SAVE_OFFSET_SERIAL, - memory_info_hob->DataWidth); + memory_info_hob->DataWidth, + memory_info_hob->VddVoltage[memProfNum], + memory_info_hob->EccSupport); index++; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/33031 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6f0d4b223f1490ec7aa71a6105603635b514021 Gerrit-Change-Number: 33031 Gerrit-PatchSet: 1 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: newchange

6 19

Change in ...coreboot[master]: qclib: Add qclib support with interface tables
by Patrick Georgi (Code Review) 06 Jun '19

06 Jun '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29967 ) Change subject: qclib: Add qclib support with interface tables ...................................................................... Patch Set 28: I pushed a minor update that gets rid of extra newlines in a Makefile.inc that the infra complained about. Julius' comments from patch set 25 aren't handled yet. -- To view, visit https://review.coreboot.org/c/coreboot/+/29967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I534af71163d034ea04420dda6a94ce31b08c8a07 Gerrit-Change-Number: 29967 Gerrit-PatchSet: 28 Gerrit-Owner: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sricharan Ramabadhran <srichara(a)qualcomm.corp-partner.google.com> Gerrit-CC: mturney mturney <mturney(a)codeaurora.org> Gerrit-Comment-Date: Thu, 06 Jun 2019 11:28:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit June 2019