coreboot-gerrit June 2019

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Change in ...coreboot[master]: {drivers,soc/intel/braswell}: Implement C_ENVIRONMENT_BOOTBLOCK support
by Frans Hendriks (Code Review) 05 Jun '19

05 Jun '19

Hello Patrick Rudolph, Huang Jin, Arthur Heymans, York Yang, Lee Leahy, Matt DeVillier, build bot (Jenkins), Hannah Williams, Michał Żygowski, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29662 to look at the new patch set (#44). Change subject: {drivers,soc/intel/braswell}: Implement C_ENVIRONMENT_BOOTBLOCK support ...................................................................... {drivers,soc/intel/braswell}: Implement C_ENVIRONMENT_BOOTBLOCK support No C_ENVIRONMENT_BOOTBLOCK support for Braswell is available. Enable support and add required files for the Braswell Bootblock in C. The next changes are made support C_ENVIRONMENT_BOOTBLOCK: - Add car_stage_entry() function bootblock-c_entry() functions. - Specify config DCACHE_BSP_STACK_SIZE and C_ENV_BOOTBLOCK_SIZE. - Add bootblock_c_entry(). - Move init from car_soc_XXX_console_init() to bootblock_soc_XXX_Init() Removed the unused cache_as_ram_main() and weak car_XXX_XXX_console_init() BUG=NA TEST=Booting Embedded Linux on Facebook FBG-1701 Building Google Banos Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/drivers/intel/fsp1_1/Makefile.inc D src/drivers/intel/fsp1_1/cache_as_ram.inc M src/drivers/intel/fsp1_1/car.c M src/drivers/intel/fsp1_1/include/fsp/car.h M src/mainboard/google/cyan/Makefile.inc M src/mainboard/google/cyan/com_init.c M src/mainboard/intel/strago/Makefile.inc M src/mainboard/intel/strago/com_init.c M src/soc/intel/braswell/Kconfig M src/soc/intel/braswell/Makefile.inc M src/soc/intel/braswell/bootblock/bootblock.c M src/soc/intel/braswell/include/soc/romstage.h M src/soc/intel/braswell/romstage/Makefile.inc D src/soc/intel/braswell/romstage/pmc.c M src/soc/intel/braswell/romstage/romstage.c 15 files changed, 123 insertions(+), 415 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/29662/44 -- To view, visit https://review.coreboot.org/c/coreboot/+/29662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c Gerrit-Change-Number: 29662 Gerrit-PatchSet: 44 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: York Yang <yyang024(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: libpayload/i8042/keyboard: Fix return value check for keyboard_cmd
by Furquan Shaikh (Code Review) 05 Jun '19

05 Jun '19

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33185 Change subject: libpayload/i8042/keyboard: Fix return value check for keyboard_cmd ...................................................................... libpayload/i8042/keyboard: Fix return value check for keyboard_cmd CB:32951 ("libpayload: Reset PS/2 keyboard") added a call to reset keyboard and check the return value of keyboard_cmd() to compare against I8042_KBCMD_ACK. However, keyboard_cmd() already checks for ACK and returns 1 or 0 based on whether ACK is received. This change fixes the check introduced by CB:32951 to compare against 0 just like the other checks for keyboard_cmd(). BUG=b:134366527 TEST=Verified that logs do not contain "ERROR: Keyboard reset failed" anymore. Change-Id: Idcadaae12e0a44e404a1d98c6deb633d97058203 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M payloads/libpayload/drivers/i8042/keyboard.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/33185/1 diff --git a/payloads/libpayload/drivers/i8042/keyboard.c b/payloads/libpayload/drivers/i8042/keyboard.c index 12255fb..1bc321d 100644 --- a/payloads/libpayload/drivers/i8042/keyboard.c +++ b/payloads/libpayload/drivers/i8042/keyboard.c @@ -319,8 +319,8 @@ /* Reset keyboard and self test (keyboard side) */ ret = keyboard_cmd(I8042_KBCMD_RESET); - if (ret != I8042_KBCMD_ACK) { - printf("ERROR: Keyboard reset failed ACK: 0x%x\n", ret); + if (!ret) { + printf("ERROR: Keyboard reset failed!\n", ret); return; } -- To view, visit https://review.coreboot.org/c/coreboot/+/33185 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idcadaae12e0a44e404a1d98c6deb633d97058203 Gerrit-Change-Number: 33185 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: southbridge/intel/fsp_rangeley: Fixing wrong parameters passed to outw
by Name of user not set (Code Review) 05 Jun '19

05 Jun '19

hannah.williams(a)dell.com has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32842 Change subject: southbridge/intel/fsp_rangeley: Fixing wrong parameters passed to outw ...................................................................... southbridge/intel/fsp_rangeley: Fixing wrong parameters passed to outw outw takes (value, addr) not (addr, value) Change-Id: I6c00413ce9b9b6a3d5691d71ade2b12b08538622 --- M src/southbridge/intel/fsp_rangeley/early_init.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/32842/1 diff --git a/src/southbridge/intel/fsp_rangeley/early_init.c b/src/southbridge/intel/fsp_rangeley/early_init.c index 32e3bb5..230f6e1 100644 --- a/src/southbridge/intel/fsp_rangeley/early_init.c +++ b/src/southbridge/intel/fsp_rangeley/early_init.c @@ -40,8 +40,8 @@ /* Disable the watchdog reboot and turn off the watchdog timer */ write8((void *)(DEFAULT_PBASE + PMC_CFG), read8((void *)(DEFAULT_PBASE + PMC_CFG)) | NO_REBOOT); // disable reboot on timer trigger - outw(DEFAULT_ABASE + TCO1_CNT, inw(DEFAULT_ABASE + TCO1_CNT) | - TCO_TMR_HALT); // disable watchdog timer + outw( inw(DEFAULT_ABASE + TCO1_CNT) | TCO_TMR_HALT, + DEFAULT_ABASE + TCO1_CNT); // disable watchdog timer printk(BIOS_DEBUG, " done.\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/32842 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c00413ce9b9b6a3d5691d71ade2b12b08538622 Gerrit-Change-Number: 32842 Gerrit-PatchSet: 1 Gerrit-Owner: hannah.williams(a)dell.com Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mainboard/portwell/m107: Do initial mainboard commit
by David Hendricks (Code Review) 05 Jun '19

05 Jun '19

David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29470 ) Change subject: mainboard/portwell/m107: Do initial mainboard commit ...................................................................... Patch Set 11: (26 comments) marking some comments as resolved... https://review.coreboot.org/#/c/29470/8/src/mainboard/portwell/m107/devicet… File src/mainboard/portwell/m107/devicetree.cb: https://review.coreboot.org/#/c/29470/8/src/mainboard/portwell/m107/devicet… PS8, Line 99: device pci 0b.0 on end # 8086 22DC - PUNIT/DPTF > PUNIT device is by code. Should be disabled here also. Done https://review.coreboot.org/#/c/29470/1/src/mainboard/portwell/m107/spd/SAM… File src/mainboard/portwell/m107/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex: https://review.coreboot.org/#/c/29470/1/src/mainboard/portwell/m107/spd/SAM… PS1, Line 35: # bit7 : 0 = CRC covers bytes 0 ~ 128 > trailing whitespace Done https://review.coreboot.org/#/c/29470/1/src/mainboard/portwell/m107/spd/SAM… PS1, Line 61: # bits[7:6]: 0 = reserved > trailing whitespace Done https://review.coreboot.org/#/c/29470/1/src/mainboard/portwell/m107/spd/SAM… PS1, Line 80: # bits[7:5]: reserved > trailing whitespace Done https://review.coreboot.org/#/c/29470/1/src/mainboard/portwell/m107/spd/SAM… PS1, Line 90: 01 > trailing whitespace Done https://review.coreboot.org/#/c/29470/1/src/mainboard/portwell/m107/spd/SAM… PS1, Line 117: 78 > trailing whitespace Done https://review.coreboot.org/#/c/29470/1/src/mainboard/portwell/m107/spd/SAM… PS1, Line 151: 3C > trailing whitespace Done https://review.coreboot.org/#/c/29470/1/src/mainboard/portwell/m107/spd/SAM… PS1, Line 154: 3C > trailing whitespace Done https://review.coreboot.org/#/c/29470/1/src/mainboard/portwell/m107/spd/SAM… PS1, Line 181: 41 > trailing whitespace Done https://review.coreboot.org/#/c/29470/1/src/mainboard/portwell/m107/spd/SAM… PS1, Line 187: 00 > trailing whitespace Done https://review.coreboot.org/#/c/29470/1/src/mainboard/portwell/m107/spd/SAM… PS1, Line 190: 00 > trailing whitespace Done https://review.coreboot.org/#/c/29470/1/src/mainboard/portwell/m107/spd/SAM… PS1, Line 193: 00 > trailing whitespace Done https://review.coreboot.org/#/c/29470/1/src/mainboard/portwell/m107/spd/SAM… PS1, Line 203: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > trailing whitespace Done https://review.coreboot.org/#/c/29470/1/src/mainboard/portwell/m107/spd/SAM… PS1, Line 204: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > trailing whitespace Done https://review.coreboot.org/#/c/29470/1/src/mainboard/portwell/m107/spd/SAM… PS1, Line 209: 80 CE > trailing whitespace Done https://review.coreboot.org/#/c/29470/1/src/mainboard/portwell/m107/spd/SAM… PS1, Line 212: 01 > trailing whitespace Done https://review.coreboot.org/#/c/29470/1/src/mainboard/portwell/m107/spd/SAM… PS1, Line 215: 12 1B > trailing whitespace Done https://review.coreboot.org/#/c/29470/1/src/mainboard/portwell/m107/spd/SAM… PS1, Line 218: 00 00 00 00 > trailing whitespace Done https://review.coreboot.org/#/c/29470/1/src/mainboard/portwell/m107/spd/SAM… PS1, Line 225: 20 20 > trailing whitespace Done https://review.coreboot.org/#/c/29470/1/src/mainboard/portwell/m107/spd/SAM… PS1, Line 234: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > trailing whitespace Done https://review.coreboot.org/#/c/29470/1/src/mainboard/portwell/m107/spd/SAM… PS1, Line 240: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > trailing whitespace Done https://review.coreboot.org/#/c/29470/1/src/mainboard/portwell/m107/spd/SAM… PS1, Line 241: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > trailing whitespace Done https://review.coreboot.org/#/c/29470/1/src/mainboard/portwell/m107/spd/SAM… PS1, Line 242: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > trailing whitespace Done https://review.coreboot.org/#/c/29470/1/src/mainboard/portwell/m107/spd/SAM… PS1, Line 243: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > trailing whitespace Done https://review.coreboot.org/#/c/29470/2/src/mainboard/portwell/m107/spd/SAM… File src/mainboard/portwell/m107/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex: https://review.coreboot.org/#/c/29470/2/src/mainboard/portwell/m107/spd/SAM… PS2, Line 187: 00 > trailing whitespace Done https://review.coreboot.org/#/c/29470/2/src/mainboard/portwell/m107/spd/SAM… PS2, Line 218: 00 00 00 00 > trailing whitespace Done -- To view, visit https://review.coreboot.org/c/coreboot/+/29470 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d3173fdcf881f894a75cd9798ba173b425d4e62 Gerrit-Change-Number: 29470 Gerrit-PatchSet: 11 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 05 Jun 2019 14:35:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Frans Hendriks <fhendriks(a)eltan.com> Comment-In-Reply-To: build bot (Jenkins) <no-reply(a)coreboot.org> Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: {drivers,soc/intel/braswell}: Implement C_ENVIRONMENT_BOOTBLOCK support
by Frans Hendriks (Code Review) 05 Jun '19

05 Jun '19

Hello Patrick Rudolph, Huang Jin, Arthur Heymans, York Yang, Lee Leahy, Matt DeVillier, build bot (Jenkins), Hannah Williams, Michał Żygowski, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29662 to look at the new patch set (#43). Change subject: {drivers,soc/intel/braswell}: Implement C_ENVIRONMENT_BOOTBLOCK support ...................................................................... {drivers,soc/intel/braswell}: Implement C_ENVIRONMENT_BOOTBLOCK support No C_ENVIRONMENT_BOOTBLOCK support for Braswell is available. Enable support and add required files for the Braswell Bootblock in C. The next changes are made support C_ENVIRONMENT_BOOTBLOCK: - Add car_stage_entry() function bootblock-c_entry() functions. - Specify config DCACHE_BSP_STACK_SIZE and C_ENV_BOOTBLOCK_SIZE. - Add bootblock_c_entry(). - Move init from car_soc_XXX_console_init() to bootblock_soc_XXX_Init() Removed the unused cache_as_ram_main() and weak car_XXX_XXX_console_init() BUG=NA TEST=Booting Embedded Linux on Facebook FBG-1701 Building Google Banos Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/drivers/intel/fsp1_1/Makefile.inc R src/drivers/intel/fsp1_1/cache_as_ram.S M src/drivers/intel/fsp1_1/car.c M src/drivers/intel/fsp1_1/include/fsp/car.h M src/mainboard/google/cyan/Makefile.inc M src/mainboard/google/cyan/com_init.c M src/mainboard/intel/strago/Makefile.inc M src/mainboard/intel/strago/com_init.c M src/soc/intel/braswell/Kconfig M src/soc/intel/braswell/Makefile.inc M src/soc/intel/braswell/bootblock/bootblock.c R src/soc/intel/braswell/include/soc/bootblock.h M src/soc/intel/braswell/include/soc/romstage.h M src/soc/intel/braswell/romstage/Makefile.inc M src/soc/intel/braswell/romstage/romstage.c 15 files changed, 140 insertions(+), 196 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/29662/43 -- To view, visit https://review.coreboot.org/c/coreboot/+/29662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c Gerrit-Change-Number: 29662 Gerrit-PatchSet: 43 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: York Yang <yyang024(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: mb/dell: Add Dell Optiplex 790
by Christoph Pomaska (Code Review) 05 Jun '19

05 Jun '19

Christoph Pomaska has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/21774 ) Change subject: mb/dell: Add Dell Optiplex 790 ...................................................................... Patch Set 54: (3 comments) https://review.coreboot.org/#/c/21774/54//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/21774/54//COMMIT_MSG@11 PS54, Line 11: There are (at least) three different mainboards: > say for which of these boards this patch adds support Ack https://review.coreboot.org/#/c/21774/54//COMMIT_MSG@21 PS54, Line 21: This port has been tested with: USFF > what is with the Minitower variant? I can test this later, but not right now. https://review.coreboot.org/#/c/21774/45/src/mainboard/dell/optiplex_790/ma… File src/mainboard/dell/optiplex_790/mainboard.c: https://review.coreboot.org/#/c/21774/45/src/mainboard/dell/optiplex_790/ma… PS45, Line 24: > Remove blank line Done -- To view, visit https://review.coreboot.org/c/coreboot/+/21774 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3d3a13163d5da1368259a7498019d42fb3ed57f Gerrit-Change-Number: 21774 Gerrit-PatchSet: 54 Gerrit-Owner: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Johanna Schander <coreboot(a)mimoja.de> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Thomas Heijligen <src(a)posteo.de> Gerrit-Comment-Date: Wed, 05 Jun 2019 14:16:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <siro(a)das-labor.org> Comment-In-Reply-To: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: comment

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Change in ...coreboot[master]: mainboard/portwell/m107: Do initial mainboard commit
by David Hendricks (Code Review) 05 Jun '19

05 Jun '19

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Change in ...coreboot[master]: [TOTEST]nb/intel/sandybridge/mrc.bin: Increase the CAR size
by Arthur Heymans (Code Review) 05 Jun '19

05 Jun '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33174 Change subject: [TOTEST]nb/intel/sandybridge/mrc.bin: Increase the CAR size ...................................................................... [TOTEST]nb/intel/sandybridge/mrc.bin: Increase the CAR size The mrc.bin places its stack at an awkward location, close to the bottom of the CAR location, which easily conflicts with other CAR linker symbols. To work around this issue, increase the CAR with 128k to a total of 256k, align the base and make sure the mrc.bin falls in the DCACHE_RAM_MRC_VAR_SIZE. Change-Id: Ida8ad9a54d29a9ee1301bdcff00d81f548d2b81e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/sandybridge/Kconfig 1 file changed, 3 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/33174/1 diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 4f9da00..47ef829 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -98,16 +98,15 @@ config DCACHE_RAM_BASE hex - default 0xff7e0000 + default 0xff7c0000 config DCACHE_RAM_SIZE hex - default 0x1c000 + default 0x21000 config DCACHE_RAM_MRC_VAR_SIZE hex - default 0x4000 - + default 0x1f000 config MRC_FILE string "Intel System Agent path and filename" default "3rdparty/blobs/northbridge/intel/sandybridge/systemagent-r6.bin" -- To view, visit https://review.coreboot.org/c/coreboot/+/33174 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida8ad9a54d29a9ee1301bdcff00d81f548d2b81e Gerrit-Change-Number: 33174 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/dell: Add Dell Optiplex 790
by Thomas Heijligen (Code Review) 05 Jun '19

05 Jun '19

Thomas Heijligen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/21774 ) Change subject: mb/dell: Add Dell Optiplex 790 ...................................................................... Patch Set 54: (2 comments) There are some FIXME tags. Are they solvable? https://review.coreboot.org/#/c/21774/54//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/21774/54//COMMIT_MSG@11 PS54, Line 11: There are (at least) three different mainboards: say for which of these boards this patch adds support https://review.coreboot.org/#/c/21774/54//COMMIT_MSG@21 PS54, Line 21: This port has been tested with: USFF what is with the Minitower variant? -- To view, visit https://review.coreboot.org/c/coreboot/+/21774 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3d3a13163d5da1368259a7498019d42fb3ed57f Gerrit-Change-Number: 21774 Gerrit-PatchSet: 54 Gerrit-Owner: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Johanna Schander <coreboot(a)mimoja.de> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Thomas Heijligen <src(a)posteo.de> Gerrit-Comment-Date: Wed, 05 Jun 2019 13:44:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/dell: Add Dell Optiplex 790
by Christoph Pomaska (Code Review) 05 Jun '19

05 Jun '19

Hello Kyösti Mälkki, Patrick Rudolph, Felix Held, Angel Pons, Johanna Schander, Arthur Heymans, Jonathan Neuschäfer, Paul Menzel, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/21774 to look at the new patch set (#54). Change subject: mb/dell: Add Dell Optiplex 790 ...................................................................... mb/dell: Add Dell Optiplex 790 This port was generated by autoport and has been tweaked (see below) There are (at least) three different mainboards: - DT: 4 RAM slots, PEG, PCIe x1, PCI, PCIe x16 - MT: 4 RAM slots, PEG, PCIe x1, PCI, PCIe x16 - SFF: 4 RAM slots, PEG, PCIe x16 - USFF: 2 RAM slots, mPCIe The variants have different PCI/PCIe configurations and are not exactly compatible towards each other. This port has been tested with: USFF What works: - Booting Arch Linux with kernel 5.0.0-arch1-1-ARCH - PCIe (Hotplug on PCIe X1 only!) - Onboard graphics with libgfxinit (via VGA) - Turning on and off (S5) - Harddrive activity LED - Onboard sound - Onboard ethernet - SATA (hotplug) - IOMMU - Suspend/resume (S3) - EHCI debug (rear side, bottom port on the block with ethernet) What does not work: - SuperI/O (Chip is a SCH5544-NS) - Serial port - PS/2 - Fan control (fans go to full speed) - VBT is missing Further notes: - Default IFD settings block reads/writes to some regions. This can be bypassed by plugging the SERVICE_MODE jumper. BIOS version A05 does not set any protected ranges, so internal flashing is possible (use a layout if the SERVICE_MODE jumper is not plugged). - Setting the jumper slows down the boot process of coreboot significantly, as coreboot waits 900ms for the ME to report an OK DRAM (which doesn't happen with the jumper set) - The controller that controls the POST code LEDs on the front of the case (likely the SuperIO) stays on slow blinking POST 234, corrupt or defect BIOS according to [1]. - The mainboard has one SOIC16 8192KiB and one SOIC8 2048KiB BIOS chip that are recognized as one "Opaque flash chip" of 10240K in size. - Without the VGA_BIOS_FILE the make process starts behaving weird, so I will keep it in until further notice (Is this still true?) [1] http://www.dell.com/support/article/us/en/04/sln284978/a-reference-guide-to… Change-Id: If3d3a13163d5da1368259a7498019d42fb3ed57f Signed-off-by: Christoph Pomaska <github(a)aufmachen.jetzt> Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- A src/mainboard/dell/Kconfig A src/mainboard/dell/Kconfig.name A src/mainboard/dell/optiplex_790/Kconfig A src/mainboard/dell/optiplex_790/Kconfig.name A src/mainboard/dell/optiplex_790/Makefile.inc A src/mainboard/dell/optiplex_790/acpi/ec.asl A src/mainboard/dell/optiplex_790/acpi/platform.asl A src/mainboard/dell/optiplex_790/acpi/superio.asl A src/mainboard/dell/optiplex_790/acpi_tables.c A src/mainboard/dell/optiplex_790/board_info.txt A src/mainboard/dell/optiplex_790/dsdt.asl A src/mainboard/dell/optiplex_790/gma-mainboard.ads A src/mainboard/dell/optiplex_790/hda_verb.c A src/mainboard/dell/optiplex_790/mainboard.c A src/mainboard/dell/optiplex_790/romstage.c A src/mainboard/dell/optiplex_790/variants/optiplex_790_mt/devicetree.cb A src/mainboard/dell/optiplex_790/variants/optiplex_790_mt/gpio.c A src/mainboard/dell/optiplex_790/variants/optiplex_790_mt/hda_verb.c A src/mainboard/dell/optiplex_790/variants/optiplex_790_usff/devicetree.cb A src/mainboard/dell/optiplex_790/variants/optiplex_790_usff/gpio.c A src/mainboard/dell/optiplex_790/variants/optiplex_790_usff/hda_verb.c 21 files changed, 1,150 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/21774/54 -- To view, visit https://review.coreboot.org/c/coreboot/+/21774 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3d3a13163d5da1368259a7498019d42fb3ed57f Gerrit-Change-Number: 21774 Gerrit-PatchSet: 54 Gerrit-Owner: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Johanna Schander <coreboot(a)mimoja.de> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit June 2019