coreboot-gerrit June 2019

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Change in ...coreboot[master]: mb/dell: Add Dell Optiplex 790
by Christoph Pomaska (Code Review) 06 Jun '19

06 Jun '19

Hello Kyösti Mälkki, Patrick Rudolph, Felix Held, Angel Pons, Johanna Schander, Arthur Heymans, Jonathan Neuschäfer, Paul Menzel, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/21774 to look at the new patch set (#56). Change subject: mb/dell: Add Dell Optiplex 790 ...................................................................... mb/dell: Add Dell Optiplex 790 This port was generated by autoport and has been tweaked (see below) There are (at least) three different mainboards: - DT: 4 RAM slots, PEG, PCIe x1, PCI, PCIe x16 - MT: 4 RAM slots, PEG, PCIe x1, PCI, PCIe x16 - SFF: 4 RAM slots, PEG, PCIe x16 - USFF: 2 RAM slots, mPCIe The variants have different PCI/PCIe configurations and are not exactly compatible towards each other. This port has been tested with: USFF What works: - Booting Arch Linux with kernel 5.0.0-arch1-1-ARCH - PCIe (Hotplug on PCIe X1 only!) - Onboard graphics with libgfxinit (via VGA) - Turning on and off (S5) - Harddrive activity LED - Onboard sound - Onboard ethernet - SATA (hotplug) - IOMMU - Suspend/resume (S3) - EHCI debug (rear side, bottom port on the block with ethernet) What does not work: - SuperI/O (Chip is a SCH5544-NS) - Serial port - PS/2 - Fan control (fans go to full speed) - VBT is missing Further notes: - Default IFD settings block reads/writes to some regions. This can be bypassed by plugging the SERVICE_MODE jumper. BIOS version A05 does not set any protected ranges, so internal flashing is possible (use a layout if the SERVICE_MODE jumper is not plugged). - Setting the jumper slows down the boot process of coreboot significantly, as coreboot waits 900ms for the ME to report an OK DRAM (which doesn't happen with the jumper set) - The controller that controls the POST code LEDs on the front of the case (likely the SuperIO) stays on slow blinking POST 234, corrupt or defect BIOS according to [1]. - The mainboard has one SOIC16 8192KiB and one SOIC8 2048KiB BIOS chip that are recognized as one "Opaque flash chip" of 10240K in size. - Without the VGA_BIOS_FILE the make process starts behaving weird, so I will keep it in until further notice (Is this still true?) [1] http://www.dell.com/support/article/us/en/04/sln284978/a-reference-guide-to… Change-Id: If3d3a13163d5da1368259a7498019d42fb3ed57f Signed-off-by: Christoph Pomaska <github(a)aufmachen.jetzt> Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- A src/mainboard/dell/Kconfig A src/mainboard/dell/Kconfig.name A src/mainboard/dell/optiplex_790/Kconfig A src/mainboard/dell/optiplex_790/Kconfig.name A src/mainboard/dell/optiplex_790/Makefile.inc A src/mainboard/dell/optiplex_790/acpi/ec.asl A src/mainboard/dell/optiplex_790/acpi/platform.asl A src/mainboard/dell/optiplex_790/acpi/superio.asl A src/mainboard/dell/optiplex_790/acpi_tables.c A src/mainboard/dell/optiplex_790/board_info.txt A src/mainboard/dell/optiplex_790/dsdt.asl A src/mainboard/dell/optiplex_790/gma-mainboard.ads A src/mainboard/dell/optiplex_790/hda_verb.c A src/mainboard/dell/optiplex_790/mainboard.c A src/mainboard/dell/optiplex_790/romstage.c A src/mainboard/dell/optiplex_790/variants/optiplex_790_mt-sff/devicetree.cb A src/mainboard/dell/optiplex_790/variants/optiplex_790_mt-sff/gpio.c A src/mainboard/dell/optiplex_790/variants/optiplex_790_mt-sff/hda_verb.c A src/mainboard/dell/optiplex_790/variants/optiplex_790_usff/devicetree.cb A src/mainboard/dell/optiplex_790/variants/optiplex_790_usff/gpio.c A src/mainboard/dell/optiplex_790/variants/optiplex_790_usff/hda_verb.c 21 files changed, 1,151 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/21774/56 -- To view, visit https://review.coreboot.org/c/coreboot/+/21774 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3d3a13163d5da1368259a7498019d42fb3ed57f Gerrit-Change-Number: 21774 Gerrit-PatchSet: 56 Gerrit-Owner: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Johanna Schander <coreboot(a)mimoja.de> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: Documentation: libgfxinit timing parameters
by Daniel Maslowski (Code Review) 06 Jun '19

06 Jun '19

Daniel Maslowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33246 Change subject: Documentation: libgfxinit timing parameters ...................................................................... Documentation: libgfxinit timing parameters Change-Id: I94c2784ffcc12f54c285e1f90d73ff3905c4fae7 Signed-off-by: Daniel Maslowski <daniel.maslowski(a)img.ly> --- M Documentation/gfx/libgfxinit.md 1 file changed, 29 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/33246/1 diff --git a/Documentation/gfx/libgfxinit.md b/Documentation/gfx/libgfxinit.md index c50761a..c19b10b 100644 --- a/Documentation/gfx/libgfxinit.md +++ b/Documentation/gfx/libgfxinit.md @@ -125,3 +125,32 @@ given order until all available pipes are taken. That's 1 pipe in VGA textmode, 2 pipes in high-resolution mode until Sandy Bridge, 3 pipes from Ivy Bridge on. + +GMA: Timing Parameters +---------------------- + +From the binary file `edid` in the sys filesystem on Linux, the panel can be +identified. The exact path may differ slightly. Here is an example: + +```sh +$ strings /sys/devices/pci0000:00/0000:00:02.0/drm/card0/card0-eDP-1/edid +@0 5 +LG Display +LP140WF3-SPD1 +``` + +To figure out the timing parameters, refer to the [Intel Programmer's Reference +Manuals](https://01.org/linuxgraphics/documentation/hardware-specification-prms) +and try to find the datasheet of the panel using the information from `edid`. +In the example above, you would search for `LP140WF3-SPD1`. Find a table listing +the power sequence timing parameters, which are usually named T[N] and also +referenced in Intel's respective registers listing. You need the values for +`PP_ON_DELAYS`, `PP_OFF_DELAYS` and `PP_DIVISOR` for your `devicetree.cb`: + +|Intel docs |devicetree.cb |Haswell | +|---------------------------|--------------------------------------|--------| +|Power up delay |`gpu_panel_power_up_delay` |T3 | +|Power on to backlight on |`gpu_panel_power_backlight_on_delay` |T7 | +|Power Down delay |`gpu_panel_power_down_delay` |T10 | +|Backlight off to power down|`gpu_panel_power_backlight_off_delay` |T7 | +|Power Cycle Delay |`gpu_panel_power_cycle_delay` |T12 | -- To view, visit https://review.coreboot.org/c/coreboot/+/33246 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94c2784ffcc12f54c285e1f90d73ff3905c4fae7 Gerrit-Change-Number: 33246 Gerrit-PatchSet: 1 Gerrit-Owner: Daniel Maslowski <info(a)orangecms.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/dell: Add Dell Optiplex 790
by Christoph Pomaska (Code Review) 06 Jun '19

06 Jun '19

Hello Kyösti Mälkki, Patrick Rudolph, Felix Held, Angel Pons, Johanna Schander, Arthur Heymans, Jonathan Neuschäfer, Paul Menzel, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/21774 to look at the new patch set (#55). Change subject: mb/dell: Add Dell Optiplex 790 ...................................................................... mb/dell: Add Dell Optiplex 790 This port was generated by autoport and has been tweaked (see below) There are (at least) three different mainboards: - DT: 4 RAM slots, PEG, PCIe x1, PCI, PCIe x16 - MT: 4 RAM slots, PEG, PCIe x1, PCI, PCIe x16 - SFF: 4 RAM slots, PEG, PCIe x16 - USFF: 2 RAM slots, mPCIe The variants have different PCI/PCIe configurations and are not exactly compatible towards each other. This port has been tested with: USFF What works: - Booting Arch Linux with kernel 5.0.0-arch1-1-ARCH - PCIe (Hotplug on PCIe X1 only!) - Onboard graphics with libgfxinit (via VGA) - Turning on and off (S5) - Harddrive activity LED - Onboard sound - Onboard ethernet - SATA (hotplug) - IOMMU - Suspend/resume (S3) - EHCI debug (rear side, bottom port on the block with ethernet) What does not work: - SuperI/O (Chip is a SCH5544-NS) - Serial port - PS/2 - Fan control (fans go to full speed) - VBT is missing Further notes: - Default IFD settings block reads/writes to some regions. This can be bypassed by plugging the SERVICE_MODE jumper. BIOS version A05 does not set any protected ranges, so internal flashing is possible (use a layout if the SERVICE_MODE jumper is not plugged). - Setting the jumper slows down the boot process of coreboot significantly, as coreboot waits 900ms for the ME to report an OK DRAM (which doesn't happen with the jumper set) - The controller that controls the POST code LEDs on the front of the case (likely the SuperIO) stays on slow blinking POST 234, corrupt or defect BIOS according to [1]. - The mainboard has one SOIC16 8192KiB and one SOIC8 2048KiB BIOS chip that are recognized as one "Opaque flash chip" of 10240K in size. - Without the VGA_BIOS_FILE the make process starts behaving weird, so I will keep it in until further notice (Is this still true?) [1] http://www.dell.com/support/article/us/en/04/sln284978/a-reference-guide-to… Change-Id: If3d3a13163d5da1368259a7498019d42fb3ed57f Signed-off-by: Christoph Pomaska <github(a)aufmachen.jetzt> Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- A src/mainboard/dell/Kconfig A src/mainboard/dell/Kconfig.name A src/mainboard/dell/optiplex_790/Kconfig A src/mainboard/dell/optiplex_790/Kconfig.name A src/mainboard/dell/optiplex_790/Makefile.inc A src/mainboard/dell/optiplex_790/acpi/ec.asl A src/mainboard/dell/optiplex_790/acpi/platform.asl A src/mainboard/dell/optiplex_790/acpi/superio.asl A src/mainboard/dell/optiplex_790/acpi_tables.c A src/mainboard/dell/optiplex_790/board_info.txt A src/mainboard/dell/optiplex_790/dsdt.asl A src/mainboard/dell/optiplex_790/gma-mainboard.ads A src/mainboard/dell/optiplex_790/hda_verb.c A src/mainboard/dell/optiplex_790/mainboard.c A src/mainboard/dell/optiplex_790/romstage.c A src/mainboard/dell/optiplex_790/variants/optiplex_790_mt-usff/devicetree.cb A src/mainboard/dell/optiplex_790/variants/optiplex_790_mt-usff/gpio.c A src/mainboard/dell/optiplex_790/variants/optiplex_790_mt-usff/hda_verb.c A src/mainboard/dell/optiplex_790/variants/optiplex_790_usff/devicetree.cb A src/mainboard/dell/optiplex_790/variants/optiplex_790_usff/gpio.c A src/mainboard/dell/optiplex_790/variants/optiplex_790_usff/hda_verb.c 21 files changed, 1,151 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/21774/55 -- To view, visit https://review.coreboot.org/c/coreboot/+/21774 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3d3a13163d5da1368259a7498019d42fb3ed57f Gerrit-Change-Number: 21774 Gerrit-PatchSet: 55 Gerrit-Owner: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Johanna Schander <coreboot(a)mimoja.de> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: siemens/mc_apl5: Add own GPIO file
by Mario Scheithauer (Code Review) 06 Jun '19

06 Jun '19

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33172 Change subject: siemens/mc_apl5: Add own GPIO file ...................................................................... siemens/mc_apl5: Add own GPIO file Because of some differences to the baseboard this board variant needs its own GPIO file. Change-Id: Ie3424cb0b867c5d43cd7db9e9ae654196cef5e90 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl5/Makefile.inc A src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c 2 files changed, 420 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/33172/1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Makefile.inc b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Makefile.inc index adf9aff..03759d2 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Makefile.inc +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Makefile.inc @@ -1,2 +1,5 @@ +romstage-y += gpio.c + +ramstage-y += gpio.c ramstage-y += mainboard.c ramstage-y += ptn3460.c diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c new file mode 100755 index 0000000..1dcd4f9 --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c @@ -0,0 +1,417 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * Copyright (C) 2017-2018 Siemens AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include <commonlib/helpers.h> +#include <baseboard/variants.h> + +/* + * Pad configuration in ramstage. The order largely follows the 'GPIO Muxing' + * table found in EDS vol 1, but some pins aren't grouped functionally in + * the table so those were moved for more logical grouping. + */ +static const struct pad_config gpio_table[] = { + + /* Southwest Community */ + + /* PCIE_WAKE[0:3]_N */ + PAD_CFG_NF(GPIO_205, NONE, DEEP, NF1), /* PCIE_WAKE0_N */ + PAD_CFG_NF(GPIO_206, NONE, DEEP, NF1), /* PCIE_WAKE1_N */ + PAD_CFG_NF(GPIO_207, NONE, DEEP, NF1), /* PCIE_WAKE2_N */ + PAD_CFG_NF(GPIO_208, NONE, DEEP, NF1), /* PCIE_WAKE3_N */ + + /* EMMC interface. */ + PAD_CFG_NF(GPIO_156, DN_20K, DEEP, NF1), /* EMMC_CLK */ + PAD_CFG_NF(GPIO_157, NONE, DEEP, NF1), /* EMMC_D0 */ + PAD_CFG_NF(GPIO_158, NONE, DEEP, NF1), /* EMMC_D1 */ + PAD_CFG_NF(GPIO_159, NONE, DEEP, NF1), /* EMMC_D2 */ + PAD_CFG_NF(GPIO_160, NONE, DEEP, NF1), /* EMMC_D3 */ + PAD_CFG_NF(GPIO_161, NONE, DEEP, NF1), /* EMMC_D4 */ + PAD_CFG_NF(GPIO_162, NONE, DEEP, NF1), /* EMMC_D5 */ + PAD_CFG_NF(GPIO_163, NONE, DEEP, NF1), /* EMMC_D6 */ + PAD_CFG_NF(GPIO_164, NONE, DEEP, NF1), /* EMMC_D7 */ + PAD_CFG_NF(GPIO_165, NONE, DEEP, NF1), /* EMMC_CMD */ + PAD_CFG_NF(GPIO_182, DN_20K, DEEP, NF1), /* EMMC_RCLK */ + + /* SDIO -- unused */ + PAD_CFG_GPI(GPIO_166, DN_20K, DEEP), /* SDIO_CLK */ + PAD_CFG_GPI(GPIO_167, NONE, DEEP), /* SDIO_D0 */ + /* Configure SDIO to enable power gating. */ + PAD_CFG_GPI(GPIO_168, NONE, DEEP), /* SDIO_D1 */ + PAD_CFG_GPI(GPIO_169, NONE, DEEP), /* SDIO_D2 */ + PAD_CFG_GPI(GPIO_170, NONE, DEEP), /* SDIO_D3 */ + PAD_CFG_GPI(GPIO_171, NONE, DEEP), /* SDIO_CMD */ + + /* SDCARD */ + /* Pull down clock by 20K. */ + PAD_CFG_NF(GPIO_172, DN_20K, DEEP, NF1), /* SDCARD_CLK */ + PAD_CFG_NF(GPIO_173, UP_20K, DEEP, NF1), /* SDCARD_D0 */ + PAD_CFG_NF(GPIO_174, UP_20K, DEEP, NF1), /* SDCARD_D1 */ + PAD_CFG_NF(GPIO_175, UP_20K, DEEP, NF1), /* SDCARD_D2 */ + PAD_CFG_NF(GPIO_176, UP_20K, DEEP, NF1), /* SDCARD_D3 */ + /* Card detect is active LOW with external pull up. */ + PAD_CFG_NF(GPIO_177, NONE, DEEP, NF1), /* SDCARD_CD_N */ + PAD_CFG_NF(GPIO_178, UP_20K, DEEP, NF1), /* SDCARD_CMD */ + /* CLK feedback, internal signal, needs 20K pull down. */ + PAD_CFG_NF(GPIO_179, DN_20K, DEEP, NF1), /* SDCARD_CLK_FB */ + PAD_CFG_GPI(GPIO_186, NONE, DEEP), /* SDCARD_LVL_WP */ + /* EN_SD_SOCKET_PWR_L for SD slot power control. Default on. */ + PAD_CFG_GPO(GPIO_183, 1, DEEP), /* SDIO_PWR_DOWN_N */ + + /* SMBus */ + PAD_CFG_GPI(SMB_ALERTB, NONE, DEEP), /* SMB_ALERT _N */ + PAD_CFG_NF(SMB_CLK, NONE, DEEP, NF1), /* SMB_CLK */ + PAD_CFG_NF(SMB_DATA, NONE, DEEP, NF1), /* SMB_DATA */ + + /* LPC */ + PAD_CFG_NF(LPC_ILB_SERIRQ, NONE, DEEP, NF1), /* LPC_SERIRQ */ + PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1), /* LPC_CLKOUT0 */ + PAD_CFG_GPI(LPC_CLKOUT1, UP_20K, DEEP), /* LPC_CLKOUT1 */ + PAD_CFG_NF(LPC_AD0, NONE, DEEP, NF1), /* LPC_AD0 */ + PAD_CFG_NF(LPC_AD1, NONE, DEEP, NF1), /* LPC_AD1 */ + PAD_CFG_NF(LPC_AD2, NONE, DEEP, NF1), /* LPC_AD2 */ + PAD_CFG_NF(LPC_AD3, NONE, DEEP, NF1), /* LPC_AD3 */ + PAD_CFG_NF(LPC_CLKRUNB, NONE, DEEP, NF1), /* LPC_CLKRUN_N */ + PAD_CFG_NF(LPC_FRAMEB, NONE, DEEP, NF1), /* LPC_FRAME_N */ + + /* West Community */ + + /* I2C0 - I2C Level Shifter */ + PAD_CFG_NF(GPIO_124, NONE, DEEP, NF1), /* LPSS_I2C0_SDA */ + PAD_CFG_NF(GPIO_125, NONE, DEEP, NF1), /* LPSS_I2C0_SCL */ + + /* I2C[1:7] -- unused */ + PAD_CFG_GPI(GPIO_126, UP_20K, DEEP), /* LPSS_I2C1_SDA */ + PAD_CFG_GPI(GPIO_127, UP_20K, DEEP), /* LPSS_I2C1_SCL */ + PAD_CFG_GPI(GPIO_128, UP_20K, DEEP), /* LPSS_I2C2_SDA */ + PAD_CFG_GPI(GPIO_129, UP_20K, DEEP), /* LPSS_I2C2_SCL */ + PAD_CFG_GPI(GPIO_130, UP_20K, DEEP), /* LPSS_I2C3_SDA */ + PAD_CFG_GPI(GPIO_131, UP_20K, DEEP), /* LPSS_I2C3_SCL */ + PAD_CFG_GPI(GPIO_132, UP_20K, DEEP), /* LPSS_I2C4_SDA */ + PAD_CFG_GPI(GPIO_133, UP_20K, DEEP), /* LPSS_I2C4_SCL */ + PAD_CFG_GPI(GPIO_134, UP_20K, DEEP), /* LPSS_I2C5_SDA */ + PAD_CFG_GPI(GPIO_135, UP_20K, DEEP), /* LPSS_I2C5_SCL */ + PAD_CFG_GPI(GPIO_136, UP_20K, DEEP), /* LPSS_I2C6_SDA */ + PAD_CFG_GPI(GPIO_137, UP_20K, DEEP), /* LPSS_I2C6_SCL */ + PAD_CFG_GPI(GPIO_138, UP_20K, DEEP), /* LPSS_I2C7_SDA */ + PAD_CFG_GPI(GPIO_139, UP_20K, DEEP), /* LPSS_I2C7_SCL */ + + /* ISH_GPIO_[0:9] -- unused */ + PAD_CFG_GPI(GPIO_146, DN_20K, DEEP), /* ISH_GPIO_0 */ + PAD_CFG_GPI(GPIO_147, DN_20K, DEEP), /* ISH_GPIO_1 */ + PAD_CFG_GPI(GPIO_148, DN_20K, DEEP), /* ISH_GPIO_2 */ + PAD_CFG_GPI(GPIO_149, DN_20K, DEEP), /* ISH_GPIO_3 */ + PAD_CFG_GPI(GPIO_150, DN_20K, DEEP), /* ISH_GPIO_4 */ + PAD_CFG_GPI(GPIO_151, DN_20K, DEEP), /* ISH_GPIO_5 */ + PAD_CFG_GPI(GPIO_152, DN_20K, DEEP), /* ISH_GPIO_6 */ + PAD_CFG_GPI(GPIO_153, DN_20K, DEEP), /* ISH_GPIO_7 */ + PAD_CFG_GPI(GPIO_154, DN_20K, DEEP), /* ISH_GPIO_8 */ + PAD_CFG_GPI(GPIO_155, DN_20K, DEEP), /* ISH_GPIO_9 */ + + /* PCIE_CLKREQ[0:3]_N */ + PAD_CFG_NF(GPIO_209, NONE, DEEP, NF1), + PAD_CFG_NF(GPIO_210, NONE, DEEP, NF1), + PAD_CFG_NF(GPIO_211, NONE, DEEP, NF1), + PAD_CFG_NF(GPIO_212, NONE, DEEP, NF1), + + /* OSC_CLK_OUT_0 - RES_CLK_CPU_FPGA */ + PAD_CFG_NF(OSC_CLK_OUT_0, DN_20K, DEEP, NF1), + /* OSC_CLK_OUT_[1:4] -- unused */ + PAD_CFG_GPI(OSC_CLK_OUT_1, DN_20K, DEEP), + PAD_CFG_GPI(OSC_CLK_OUT_2, DN_20K, DEEP), + PAD_CFG_GPI(OSC_CLK_OUT_3, DN_20K, DEEP), + PAD_CFG_GPI(OSC_CLK_OUT_4, DN_20K, DEEP), + + /* PMU Signals */ + PAD_CFG_GPI(PMU_AC_PRESENT, NONE, DEEP), /* PMU_AC_PRESENT */ + PAD_CFG_NF(PMU_BATLOW_B, UP_20K, DEEP, NF1), /* PMU_BATLOW_N */ + PAD_CFG_NF(PMU_PLTRST_B, NONE, DEEP, NF1), /* PMU_PLTRST_N */ + PAD_CFG_NF(PMU_PWRBTN_B, NONE, DEEP, NF1), /* PMU_PWRBTN_N */ + PAD_CFG_NF(PMU_RESETBUTTON_B, NONE, DEEP, NF1), /* PMU_RSTBTN_N */ + /* PMU_SLP_S0_N */ + PAD_CFG_NF_IOSSTATE(PMU_SLP_S0_B, NONE, DEEP, NF1, IGNORE), + PAD_CFG_NF(PMU_SLP_S3_B, NONE, DEEP, NF1), /* PMU_SLP_S3_N */ + PAD_CFG_NF(PMU_SLP_S4_B, NONE, DEEP, NF1), /* PMU_SLP_S4_N */ + PAD_CFG_NF(PMU_SUSCLK, NONE, DEEP, NF1), /* PMU_SUSCLK */ + PAD_CFG_GPO(PMU_WAKE_B, 1, DEEP), /* EN_PP3300_EMMC */ + PAD_CFG_NF(SUS_STAT_B, NONE, DEEP, NF1), /* SUS_STAT_N */ + PAD_CFG_NF(SUSPWRDNACK, NONE, DEEP, NF1), /* SUSPWRDNACK */ + + /* Northwest Community */ + + /* DDI0 SDA and SCL -- unused */ + PAD_CFG_GPI(GPIO_187, DN_20K, DEEP), /* HV_DDI0_DDC_SDA */ + PAD_CFG_GPI(GPIO_188, DN_20K, DEEP), /* HV_DDI0_DDC_SCL */ + /* DDI1 SDA and SCL - Display-Port */ + PAD_CFG_NF(GPIO_189, NONE, DEEP, NF1), /* HV_DDI1_DDC_SDA */ + PAD_CFG_NF(GPIO_190, NONE, DEEP, NF1), /* HV_DDI1_DDC_SCL */ + + /* MIPI I2C -- unused */ + PAD_CFG_GPI(GPIO_191, DN_20K, DEEP), /* MIPI_I2C_SDA */ + PAD_CFG_GPI(GPIO_192, DN_20K, DEEP), /* MIPI_I2C_SCL */ + + /* Panel 0 control -- unused */ + PAD_CFG_TERM_GPO(GPIO_193, 0, DN_20K, DEEP), /* PNL0_VDDEN */ + PAD_CFG_TERM_GPO(GPIO_194, 0, DN_20K, DEEP), /* PNL0_BKLTEN */ + PAD_CFG_TERM_GPO(GPIO_195, 0, DN_20K, DEEP), /* PNL0_BKLTCTL */ + + /* Panel 1 control -- unused */ + PAD_CFG_GPI(GPIO_196, DN_20K, DEEP), /* PNL1_VDDEN */ + PAD_CFG_GPI(GPIO_197, DN_20K, DEEP), /* PNL1_BKLTEN */ + PAD_CFG_GPI(GPIO_198, DN_20K, DEEP), /* PNL1_BKLTCTL */ + + /* DDI[0:1]_HPD -- unused */ + PAD_CFG_GPI(GPIO_199, NONE, DEEP), /* XHPD_DP */ + PAD_CFG_GPI(GPIO_200, DN_20K, DEEP), /* unused */ + + /* MDSI signals -- unused */ + PAD_CFG_GPI(GPIO_201, DN_20K, DEEP), /* MDSI_A_TE */ + PAD_CFG_GPI(GPIO_202, DN_20K, DEEP), /* MDSI_C_TE */ + + /* USB overcurrent pins. */ + PAD_CFG_NF(GPIO_203, NONE, DEEP, NF1), /* USB_OC0_N */ + PAD_CFG_NF(GPIO_204, NONE, DEEP, NF1), /* USB_OC1_N */ + + /* PMC SPI -- almost entirely unused. */ + PAD_CFG_GPI(PMC_SPI_FS0, UP_20K, DEEP), + PAD_CFG_NF(PMC_SPI_FS1, NONE, DEEP, NF2), /* XHPD_EDP_APL */ + PAD_CFG_GPI(PMC_SPI_FS2, UP_20K, DEEP), + PAD_CFG_GPI(PMC_SPI_RXD, DN_20K, DEEP), + PAD_CFG_GPI(PMC_SPI_TXD, DN_20K, DEEP), + PAD_CFG_GPI(PMC_SPI_CLK, DN_20K, DEEP), + + /* PMIC Signals unused signals related to an old PMIC interface. */ + PAD_CFG_GPO(PMIC_PWRGOOD, 1, DEEP), /* PMIC_PWRGOOD */ + PAD_CFG_GPI(PMIC_RESET_B, DN_20K, DEEP), /* PMIC_RESET_B */ + PAD_CFG_TERM_GPO(GPIO_213, 0, DN_20K, DEEP), /* NFC_OUT_RESERVE */ + PAD_CFG_TERM_GPO(GPIO_214, 0, DN_20K, DEEP), /* NFC_EN */ + PAD_CFG_GPI(GPIO_215, DN_20K, DEEP), /* NFC_IN_RESERVE */ + /* THERMTRIP_N */ + PAD_CFG_NF(PMIC_THERMTRIP_B, UP_20K, DEEP, NF1), + /* 1 - Remove the reset signal for the PCIe switch. */ + PAD_CFG_GPO(PMIC_STDBY, 1, DEEP), + PAD_CFG_NF(PROCHOT_B, NONE, DEEP, NF1), /* PROCHOT_N */ + PAD_CFG_NF(PMIC_I2C_SCL, NONE, DEEP, NF1), /* PMIC_I2C_SCL */ + PAD_CFG_NF(PMIC_I2C_SDA, NONE, DEEP, NF1), /* PMIC_I2C_SDA */ + + /* I2S1 -- unused */ + PAD_CFG_GPI(GPIO_74, DN_20K, DEEP), /* I2S1_MCLK */ + PAD_CFG_GPI(GPIO_75, DN_20K, DEEP), /* I2S1_BCLK */ + PAD_CFG_GPI(GPIO_76, DN_20K, DEEP), /* I2S1_WS_SYNC */ + PAD_CFG_GPI(GPIO_77, DN_20K, DEEP), /* I2S1_SDI */ + PAD_CFG_GPI(GPIO_78, DN_20K, DEEP), /* I2S1_SDO */ + + /* DMIC or I2S4 -- unused */ + PAD_CFG_GPI(GPIO_79, DN_20K, DEEP), /* AVS_M_CLK_A1 */ + PAD_CFG_GPI(GPIO_80, DN_20K, DEEP), /* AVS_M_CLK_B1 */ + PAD_CFG_GPI(GPIO_81, DN_20K, DEEP), /* AVS_M_DATA_1 */ + PAD_CFG_GPI(GPIO_82, DN_20K, DEEP), /* AVS_M_CLK_AB2 */ + PAD_CFG_GPI(GPIO_83, DN_20K, DEEP), /* AVS_M_DATA_2 */ + + /* I2S2 -- unused */ + PAD_CFG_GPI(GPIO_84, DN_20K, DEEP), /* AVS_I2S2_MCLK */ + PAD_CFG_GPI(GPIO_85, DN_20K, DEEP), /* AVS_I2S2_BCLK */ + PAD_CFG_GPI(GPIO_86, DN_20K, DEEP), /* AVS_I2S2_WS_SYNC */ + PAD_CFG_GPI(GPIO_87, DN_20K, DEEP), /* AVS_I2S2_SDI */ + PAD_CFG_GPI(GPIO_88, DN_20K, DEEP), /* AVS_I2S2_SDO */ + + /* I2S3 -- unused */ + PAD_CFG_GPI(GPIO_89, DN_20K, DEEP), /* AVS_I2S3_BCLK */ + PAD_CFG_GPI(GPIO_90, DN_20K, DEEP), /* AVS_I2S3_WS_SYNC */ + PAD_CFG_GPI(GPIO_91, DN_20K, DEEP), /* AVS_I2S3_SDI */ + PAD_CFG_GPI(GPIO_92, DN_20K, DEEP), /* AVS_I2S3_SDO */ + + /* Fast SPI */ + /* FST_SPI_CS0_B */ + PAD_CFG_NF_IOSSTATE(GPIO_97, NATIVE, DEEP, NF1, IGNORE), + /* FST_SPI_CS1_B -- unused */ + PAD_CFG_GPI(GPIO_98, DN_20K, DEEP), + /* FST_SPI_MOSI_IO0 */ + PAD_CFG_NF_IOSSTATE(GPIO_99, NATIVE, DEEP, NF1, IGNORE), + /* FST_SPI_MISO_IO1 */ + PAD_CFG_NF_IOSSTATE(GPIO_100, NATIVE, DEEP, NF1, IGNORE), + /* FST_IO2 -- MEM_CONFIG0 */ + PAD_CFG_NF(GPIO_101, NATIVE, DEEP, NF1), + /* FST_IO3 -- MEM_CONFIG1 */ + PAD_CFG_NF(GPIO_102, NATIVE, DEEP, NF1), + /* FST_SPI_CLK */ + PAD_CFG_NF_IOSSTATE(GPIO_103, NATIVE, DEEP, NF1, IGNORE), + /* FST_SPI_CLK_FB */ + PAD_CFG_NF_IOSSTATE(FST_SPI_CLK_FB, NATIVE, DEEP, NF1, IGNORE), + + /* SIO_SPI_0 -- unused */ + PAD_CFG_GPI(GPIO_104, DN_20K, DEEP), /* GP_SSP_0_CLK */ + PAD_CFG_GPI(GPIO_105, DN_20K, DEEP), /* GP_SSP_0_FS0 */ + PAD_CFG_GPI(GPIO_106, UP_20K, DEEP), /* GP_SSP_0_FS1 */ + PAD_CFG_GPI(GPIO_109, DN_20K, DEEP), /* GP_SSP_0_RXD */ + PAD_CFG_GPI(GPIO_110, DN_20K, DEEP), /* GP_SSP_0_TXD */ + + /* SIO_SPI_1 -- unused */ + PAD_CFG_GPI(GPIO_111, DN_20K, DEEP), /* GP_SSP_1_CLK */ + PAD_CFG_GPI(GPIO_112, DN_20K, DEEP), /* GP_SSP_1_FS0 */ + PAD_CFG_GPI(GPIO_113, DN_20K, DEEP), /* GP_SSP_1_FS1 */ + PAD_CFG_GPI(GPIO_116, DN_20K, DEEP), /* GP_SSP_1_RXD */ + PAD_CFG_GPI(GPIO_117, DN_20K, DEEP), /* GP_SSP_1_TXD */ + + /* SIO_SPI_2 -- unused */ + PAD_CFG_GPI(GPIO_118, DN_20K, DEEP), /* GP_SSP_2_CLK */ + PAD_CFG_GPI(GPIO_119, DN_20K, DEEP), /* GP_SSP_2_FS0 */ + PAD_CFG_GPI(GPIO_120, DN_20K, DEEP), /* GP_SSP_2_FS1 */ + PAD_CFG_GPI(GPIO_121, DN_20K, DEEP), /* GP_SSP_2_FS2 */ + PAD_CFG_GPI(GPIO_122, DN_20K, DEEP), /* GP_SSP_2_RXD */ + PAD_CFG_GPI(GPIO_123, NONE, DEEP), /* GP_SSP_2_TXD */ + + /* North Community */ + + /* Debug tracing. */ + PAD_CFG_GPI(GPIO_0, DN_20K, DEEP), /* TRACE_0_CLK_VNN */ + PAD_CFG_GPI(GPIO_1, DN_20K, DEEP), /* TRACE_0_DATA0_VNN */ + PAD_CFG_GPI(GPIO_2, DN_20K, DEEP), /* TRACE_0_DATA1_VNN */ + PAD_CFG_GPI(GPIO_3, DN_20K, DEEP), /* TRACE_0_DATA2_VNN */ + PAD_CFG_GPI(GPIO_4, DN_20K, DEEP), /* TRACE_0_DATA3_VNN */ + PAD_CFG_GPI(GPIO_5, DN_20K, DEEP), /* TRACE_0_DATA4_VNN */ + PAD_CFG_GPI(GPIO_6, DN_20K, DEEP), /* TRACE_0_DATA5_VNN */ + PAD_CFG_GPI(GPIO_7, DN_20K, DEEP), /* TRACE_0_DATA6_VNN */ + PAD_CFG_GPI(GPIO_8, DN_20K, DEEP), /* TRACE_0_DATA7_VNN */ + + PAD_CFG_GPI(GPIO_9, DN_20K, DEEP), /* TRACE_1_CLK_VNN */ + PAD_CFG_GPI(GPIO_10, DN_20K, DEEP), /* TRACE_1_DATA0_VNN */ + PAD_CFG_GPI(GPIO_11, DN_20K, DEEP), /* TRACE_1_DATA1_VNN */ + PAD_CFG_GPI(GPIO_12, DN_20K, DEEP), /* TRACE_1_DATA2_VNN */ + PAD_CFG_GPI(GPIO_13, DN_20K, DEEP), /* TRACE_1_DATA3_VNN */ + PAD_CFG_GPI(GPIO_14, DN_20K, DEEP), /* TRACE_1_DATA4_VNN */ + PAD_CFG_GPI(GPIO_15, DN_20K, DEEP), /* TRACE_1_DATA5_VNN */ + PAD_CFG_GPI(GPIO_16, DN_20K, DEEP), /* TRACE_1_DATA6_VNN */ + PAD_CFG_GPI(GPIO_17, DN_20K, DEEP), /* TRACE_1_DATA7_VNN */ + + PAD_CFG_GPI(GPIO_18, DN_20K, DEEP), /* TRACE_2_CLK_VNN */ + PAD_CFG_GPI(GPIO_19, DN_20K, DEEP), /* TRACE_2_DATA0_VNN */ + PAD_CFG_GPI(GPIO_20, DN_20K, DEEP), /* TRACE_2_DATA1_VNN */ + PAD_CFG_GPI(GPIO_21, DN_20K, DEEP), /* TRACE_2_DATA2_VNN */ + PAD_CFG_GPI(GPIO_22, DN_20K, DEEP), /* TRACE_2_DATA3_VNN */ + PAD_CFG_GPI(GPIO_23, DN_20K, DEEP), /* TRACE_2_DATA4_VNN */ + PAD_CFG_GPI(GPIO_24, DN_20K, DEEP), /* TRACE_2_DATA5_VNN */ + PAD_CFG_GPI(GPIO_25, DN_20K, DEEP), /* TRACE_2_DATA6_VNN */ + PAD_CFG_GPI(GPIO_26, DN_20K, DEEP), /* TRACE_2_DATA7_VNN */ + + PAD_CFG_GPI(GPIO_27, DN_20K, DEEP), /* TRIGOUT_0 */ + PAD_CFG_GPI(GPIO_28, DN_20K, DEEP), /* TRIGOUT_1 */ + PAD_CFG_GPI(GPIO_29, DN_20K, DEEP), /* TRIGIN_0 */ + + PAD_CFG_GPI(GPIO_30, DN_20K, DEEP), /* ISH_GPIO_12 */ + PAD_CFG_GPO(GPIO_31, 1, DEEP), /* ISH_GPIO_13 */ + PAD_CFG_GPI(GPIO_32, NONE, DEEP), /* ISH_GPIO_14 */ + PAD_CFG_GPI(GPIO_33, DN_20K, DEEP), /* ISH_GPIO_15 */ + + /* PWM[0:3] -- unused */ + PAD_CFG_GPI(GPIO_34, DN_20K, DEEP), + PAD_CFG_GPI(GPIO_35, DN_20K, DEEP), + PAD_CFG_GPI(GPIO_36, DN_20K, DEEP), + PAD_CFG_GPI(GPIO_37, DN_20K, DEEP), + + /* LPSS_UART[0:2] */ + PAD_CFG_GPI(GPIO_38, UP_20K, DEEP), /* LPSS_UART0_RXD - unused */ + PAD_CFG_GPI(GPIO_39, DN_20K, DEEP), /* LPSS_UART0_TXD - unused */ + PAD_CFG_GPI(GPIO_40, DN_20K, DEEP), /* LPSS_UART0_RTS - unused */ + PAD_CFG_GPI(GPIO_41, UP_20K, DEEP), /* LPSS_UART0_CTS - unused */ + PAD_CFG_GPI(GPIO_42, NONE, DEEP), /* LPSS_UART1_RXD - unused */ + PAD_CFG_GPI(GPIO_43, DN_20K, DEEP), /* LPSS_UART1_TXD - unused */ + PAD_CFG_GPI(GPIO_44, UP_20K, DEEP), /* LPSS_UART1_RTS - unused */ + PAD_CFG_GPI(GPIO_45, UP_20K, DEEP), /* LPSS_UART1_CTS - unused */ + PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* LPSS_UART2_RXD */ + /* LPSS_UART2_TXD */ + PAD_CFG_NF_IOSSTATE(GPIO_47, NATIVE, DEEP, NF1, Tx1RxDCRx0), + PAD_CFG_GPI(GPIO_48, DN_20K, DEEP), /* LPSS_UART2_RTS - unused */ + PAD_CFG_GPI(GPIO_49, UP_20K, DEEP), /* LPSS_UART2_CTS - unused */ + + /* Camera interface -- completely unused. */ + PAD_CFG_GPI(GPIO_62, DN_20K, DEEP), /* GP_CAMERASB00 */ + PAD_CFG_GPI(GPIO_63, DN_20K, DEEP), /* GP_CAMERASB01 */ + PAD_CFG_GPI(GPIO_64, DN_20K, DEEP), /* GP_CAMERASB02 */ + PAD_CFG_GPI(GPIO_65, DN_20K, DEEP), /* GP_CAMERASB03 */ + PAD_CFG_GPI(GPIO_66, DN_20K, DEEP), /* GP_CAMERASB04 */ + PAD_CFG_GPI(GPIO_67, DN_20K, DEEP), /* GP_CAMERASB05 */ + PAD_CFG_GPI(GPIO_68, DN_20K, DEEP), /* GP_CAMERASB06 */ + PAD_CFG_GPI(GPIO_69, DN_20K, DEEP), /* GP_CAMERASB07 */ + PAD_CFG_GPI(GPIO_70, DN_20K, DEEP), /* GP_CAMERASB08 */ + PAD_CFG_GPI(GPIO_71, DN_20K, DEEP), /* GP_CAMERASB09 */ + PAD_CFG_GPI(GPIO_72, DN_20K, DEEP), /* GP_CAMERASB10 */ + PAD_CFG_GPI(GPIO_73, DN_20K, DEEP), /* GP_CAMERASB11 */ + + /* CNV bridge described into IAFW Vol2. */ + /* GPIO_[216:219] described into EDS Vol1. */ + PAD_CFG_GPO(CNV_BRI_DT, 0, DEEP), /* Reserve of FPGA */ + PAD_CFG_GPO(CNV_BRI_RSP, 0, DEEP), /* Reserve of FPGA */ + PAD_CFG_GPO(CNV_RGI_DT, 0, DEEP), /* Reserve of FPGA */ + PAD_CFG_NF(CNV_RGI_RSP, UP_20K, DEEP, NF1), /* eMMC */ + + /* Serial VID */ + PAD_CFG_NF(SVID0_ALERT_B, NONE, DEEP, NF1), /* SVID0_ALERT_B */ + PAD_CFG_NF(SVID0_DATA, UP_20K, DEEP, NF1), /* SVID0_DATA */ + PAD_CFG_NF(SVID0_CLK, UP_20K, DEEP, NF1), /* SVID0_CLK */ +}; + +const struct pad_config *__weak variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +/* GPIOs needed prior to ramstage. */ +static const struct pad_config early_gpio_table[] = { + + /* Debug tracing. */ + PAD_CFG_GPI(GPIO_0, DN_20K, DEEP), /* TRACE_0_CLK_VNN */ + PAD_CFG_GPI(GPIO_1, DN_20K, DEEP), /* TRACE_0_DATA0_VNN */ + PAD_CFG_GPI(GPIO_2, DN_20K, DEEP), /* TRACE_0_DATA1_VNN */ + PAD_CFG_GPI(GPIO_3, DN_20K, DEEP), /* TRACE_0_DATA2_VNN */ + PAD_CFG_GPI(GPIO_4, DN_20K, DEEP), /* TRACE_0_DATA3_VNN */ + PAD_CFG_GPI(GPIO_5, DN_20K, DEEP), /* TRACE_0_DATA4_VNN */ + PAD_CFG_GPI(GPIO_6, DN_20K, DEEP), /* TRACE_0_DATA5_VNN */ + PAD_CFG_GPI(GPIO_7, DN_20K, DEEP), /* TRACE_0_DATA6_VNN */ + PAD_CFG_GPI(GPIO_8, DN_20K, DEEP), /* TRACE_0_DATA7_VNN */ + + PAD_CFG_GPO(GPIO_13, 0, DEEP), /* PERST# */ + PAD_CFG_GPO(GPIO_15, 0, DEEP), /* PERST# */ + PAD_CFG_GPO(GPIO_17, 1, DEEP), /* PFET */ + PAD_CFG_GPO(GPIO_19, 1, DEEP), /* PFET */ + PAD_CFG_GPO(GPIO_152, 0, DEEP), /* PERST# */ + + /* SMBus */ + PAD_CFG_NF(SMB_CLK, NONE, DEEP, NF1), /* SMB_CLK */ + PAD_CFG_NF(SMB_DATA, NONE, DEEP, NF1), /* SMB_DATA */ + + /* LPC */ + PAD_CFG_NF(LPC_ILB_SERIRQ, NONE, DEEP, NF1), /* LPC_SERIRQ */ + PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1), /* LPC_CLKOUT0 */ + /* LPC_CLKOUT1 - unused */ + PAD_CFG_GPI(LPC_CLKOUT1, DN_20K, DEEP), + PAD_CFG_NF(LPC_AD0, NONE, DEEP, NF1), /* LPC_AD0 */ + PAD_CFG_NF(LPC_AD1, NONE, DEEP, NF1), /* LPC_AD1 */ + PAD_CFG_NF(LPC_AD2, NONE, DEEP, NF1), /* LPC_AD2 */ + PAD_CFG_NF(LPC_AD3, NONE, DEEP, NF1), /* LPC_AD3 */ + PAD_CFG_NF(LPC_CLKRUNB, NONE, DEEP, NF1), /* LPC_CLKRUN_N */ + PAD_CFG_NF(LPC_FRAMEB, NONE, DEEP, NF1), /* LPC_FRAME_N */ + + /* 0 - Hold PCIe switch in reset. */ + PAD_CFG_GPO(PMIC_STDBY, 0, DEEP), +}; + +const struct pad_config *__weak +variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/33172 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3424cb0b867c5d43cd7db9e9ae654196cef5e90 Gerrit-Change-Number: 33172 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sb/intel/i82801gx: Detect if the southbridge supports AHCI
by Arthur Heymans (Code Review) 06 Jun '19

06 Jun '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30822 Change subject: sb/intel/i82801gx: Detect if the southbridge supports AHCI ...................................................................... sb/intel/i82801gx: Detect if the southbridge supports AHCI This automatically detects whether the southbridge supports AHCI. If AHCI support is selected it will be used unless "sata_no_ahci" is set in the devicetree to override the behavior. Change-Id: I8d9f4e63ae8b2862c422938f3103c44e761bcda4 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/apple/macbook21/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb M src/mainboard/asus/p5gc-mx/devicetree.cb M src/mainboard/asus/p5qpl-am/devicetree.cb M src/mainboard/foxconn/d41s/devicetree.cb M src/mainboard/foxconn/g41s-k/devicetree.cb M src/mainboard/getac/p470/devicetree.cb M src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb M src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb M src/mainboard/ibase/mb899/devicetree.cb M src/mainboard/intel/d510mo/devicetree.cb M src/mainboard/intel/d945gclf/devicetree.cb M src/mainboard/intel/dg41wv/devicetree.cb M src/mainboard/kontron/986lcd-m/devicetree.cb M src/mainboard/lenovo/t60/devicetree.cb M src/mainboard/lenovo/thinkcentre_a58/devicetree.cb M src/mainboard/lenovo/x60/devicetree.cb M src/mainboard/lenovo/z61t/devicetree.cb M src/mainboard/roda/rk886ex/devicetree.cb M src/southbridge/intel/i82801gx/chip.h M src/southbridge/intel/i82801gx/i82801gx.h M src/southbridge/intel/i82801gx/sata.c 25 files changed, 18 insertions(+), 35 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/30822/1 diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb index 898aae4..84c923b 100644 --- a/src/mainboard/apple/macbook21/devicetree.cb +++ b/src/mainboard/apple/macbook21/devicetree.cb @@ -64,7 +64,6 @@ register "gpi1_routing" = "2" register "gpi7_routing" = "2" - register "sata_ahci" = "0x1" register "sata_ports_implemented" = "0x04" register "gpe0_en" = "0x11000006" diff --git a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb index 156fe3f..acb8ac6 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb @@ -51,7 +51,6 @@ register "gpi13_routing" = "2" register "ide_enable_primary" = "0x1" - register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant register "sata_ports_implemented" = "0x3" register "gpe0_en" = "0x440" diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb index ba2f00d..f4d1dc4 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb @@ -46,7 +46,6 @@ register "pirqh_routing" = "0x0b" register "ide_enable_primary" = "0x1" - register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant register "sata_ports_implemented" = "0x3" register "gpe0_en" = "0x440" diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb index 2fa0fe4..2b74e7e 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb @@ -46,7 +46,6 @@ register "pirqh_routing" = "0x0b" register "ide_enable_primary" = "0x1" - register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant register "sata_ports_implemented" = "0x3" register "gpe0_en" = "0x440" diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb index b458115..5479faf 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb @@ -46,7 +46,6 @@ register "pirqh_routing" = "0x0b" register "ide_enable_primary" = "0x1" - register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant register "gpe0_en" = "0x440" device pci 1b.0 on # Audio diff --git a/src/mainboard/asus/p5gc-mx/devicetree.cb b/src/mainboard/asus/p5gc-mx/devicetree.cb index 2f7d278..de63da2 100644 --- a/src/mainboard/asus/p5gc-mx/devicetree.cb +++ b/src/mainboard/asus/p5gc-mx/devicetree.cb @@ -53,7 +53,6 @@ register "ide_legacy_combined" = "0x0" register "ide_enable_primary" = "0x1" register "ide_enable_secondary" = "0x0" - register "sata_ahci" = "0x0" register "p_cnt_throttling_supported" = "0" diff --git a/src/mainboard/asus/p5qpl-am/devicetree.cb b/src/mainboard/asus/p5qpl-am/devicetree.cb index 5bf582b..4e39ac5 100644 --- a/src/mainboard/asus/p5qpl-am/devicetree.cb +++ b/src/mainboard/asus/p5qpl-am/devicetree.cb @@ -43,7 +43,6 @@ # 2 SCI (if corresponding GPIO_EN bit is also set) register "ide_enable_primary" = "0x1" - register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant register "gpe0_en" = "0x04000440" device pci 1b.0 on end # Audio diff --git a/src/mainboard/foxconn/d41s/devicetree.cb b/src/mainboard/foxconn/d41s/devicetree.cb index 75df88e..a611ee3 100644 --- a/src/mainboard/foxconn/d41s/devicetree.cb +++ b/src/mainboard/foxconn/d41s/devicetree.cb @@ -40,7 +40,6 @@ register "pirqf_routing" = "0x0b" register "pirqg_routing" = "0x0b" register "pirqh_routing" = "0x0b" - register "sata_ahci" = "0x1" register "sata_ports_implemented" = "0x3" register "gpe0_en" = "0x441" diff --git a/src/mainboard/foxconn/g41s-k/devicetree.cb b/src/mainboard/foxconn/g41s-k/devicetree.cb index 237e22d..a00718f 100644 --- a/src/mainboard/foxconn/g41s-k/devicetree.cb +++ b/src/mainboard/foxconn/g41s-k/devicetree.cb @@ -48,7 +48,6 @@ register "ide_enable_primary" = "0x0" register "ide_enable_secondary" = "0x0" - register "sata_ahci" = "0x0" # AHCI does not work register "sata_ports_implemented" = "0x3" device pci 1b.0 on end # Audio diff --git a/src/mainboard/getac/p470/devicetree.cb b/src/mainboard/getac/p470/devicetree.cb index a81ef3a..f2a3912 100644 --- a/src/mainboard/getac/p470/devicetree.cb +++ b/src/mainboard/getac/p470/devicetree.cb @@ -57,7 +57,6 @@ register "ide_legacy_combined" = "0x1" register "ide_enable_primary" = "0x1" register "ide_enable_secondary" = "0x0" - register "sata_ahci" = "0x0" register "c3_latency" = "85" register "docking_supported" = "1" diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb index 7ed4d19..1c69613 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb @@ -76,7 +76,6 @@ register "ide_legacy_combined" = "0x0" register "ide_enable_primary" = "0x1" register "ide_enable_secondary" = "0x0" - register "sata_ahci" = "0x0" register "c3_latency" = "85" register "p_cnt_throttling_supported" = "0" diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb index 8b47c4f..d24eb5d 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb @@ -48,7 +48,6 @@ register "ide_legacy_combined" = "0x0" # Combined mode broken register "ide_enable_primary" = "0x1" register "ide_enable_secondary" = "0x0" - register "sata_ahci" = "0x0" # AHCI does not work register "sata_ports_implemented" = "0x3" register "gpe0_en" = "0x40" diff --git a/src/mainboard/ibase/mb899/devicetree.cb b/src/mainboard/ibase/mb899/devicetree.cb index 3544c96..8b170e1 100644 --- a/src/mainboard/ibase/mb899/devicetree.cb +++ b/src/mainboard/ibase/mb899/devicetree.cb @@ -36,7 +36,6 @@ register "ide_legacy_combined" = "0x0" register "ide_enable_primary" = "0x1" register "ide_enable_secondary" = "0x0" - register "sata_ahci" = "0x1" register "c3_latency" = "85" register "p_cnt_throttling_supported" = "0" diff --git a/src/mainboard/intel/d510mo/devicetree.cb b/src/mainboard/intel/d510mo/devicetree.cb index a008610..825611e 100644 --- a/src/mainboard/intel/d510mo/devicetree.cb +++ b/src/mainboard/intel/d510mo/devicetree.cb @@ -38,7 +38,6 @@ register "pirqf_routing" = "0x0b" register "pirqg_routing" = "0x0b" register "pirqh_routing" = "0x0b" - register "sata_ahci" = "0x1" register "sata_ports_implemented" = "0x3" register "gpe0_en" = "0x20000040" diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb index 716654c..573b9c8 100644 --- a/src/mainboard/intel/d945gclf/devicetree.cb +++ b/src/mainboard/intel/d945gclf/devicetree.cb @@ -50,7 +50,6 @@ register "ide_legacy_combined" = "0x0" register "ide_enable_primary" = "0x1" register "ide_enable_secondary" = "0x0" - register "sata_ahci" = "0x0" register "c3_latency" = "85" register "p_cnt_throttling_supported" = "0" diff --git a/src/mainboard/intel/dg41wv/devicetree.cb b/src/mainboard/intel/dg41wv/devicetree.cb index be28763..295fbc4 100644 --- a/src/mainboard/intel/dg41wv/devicetree.cb +++ b/src/mainboard/intel/dg41wv/devicetree.cb @@ -63,7 +63,6 @@ register "gpi15_routing" = "2" register "ide_enable_primary" = "0x1" - register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant register "gpe0_en" = "0x440" device pci 1b.0 on # Audio diff --git a/src/mainboard/kontron/986lcd-m/devicetree.cb b/src/mainboard/kontron/986lcd-m/devicetree.cb index 06f29e0..023c516 100644 --- a/src/mainboard/kontron/986lcd-m/devicetree.cb +++ b/src/mainboard/kontron/986lcd-m/devicetree.cb @@ -36,7 +36,6 @@ register "ide_legacy_combined" = "0x1" register "ide_enable_primary" = "0x1" register "ide_enable_secondary" = "0x1" - register "sata_ahci" = "0x0" register "c3_latency" = "85" register "p_cnt_throttling_supported" = "0" diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index 7b1721e..67b7794 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -72,7 +72,6 @@ register "gpi12_routing" = "2" register "gpi8_routing" = "2" - register "sata_ahci" = "0x1" register "sata_ports_implemented" = "0x01" register "gpe0_en" = "0x11000006" diff --git a/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb b/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb index cc3ef49..ace2bfb 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb +++ b/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb @@ -44,7 +44,6 @@ register "gpi13_routing" = "1" # ??vendor register "ide_enable_primary" = "0x1" - register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant register "gpe0_en" = "0x440" device pci 1b.0 on end # Audio diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index 2a60b87..ad31557 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -65,7 +65,6 @@ register "gpi12_routing" = "1" register "gpi8_routing" = "2" - register "sata_ahci" = "0x1" register "sata_ports_implemented" = "0x01" register "gpe0_en" = "0x11000006" diff --git a/src/mainboard/lenovo/z61t/devicetree.cb b/src/mainboard/lenovo/z61t/devicetree.cb index 92bf3ce..6e2450a 100644 --- a/src/mainboard/lenovo/z61t/devicetree.cb +++ b/src/mainboard/lenovo/z61t/devicetree.cb @@ -71,7 +71,6 @@ register "gpi12_routing" = "2" register "gpi8_routing" = "2" - register "sata_ahci" = "0x1" register "sata_ports_implemented" = "0x01" register "gpe0_en" = "0x11000006" diff --git a/src/mainboard/roda/rk886ex/devicetree.cb b/src/mainboard/roda/rk886ex/devicetree.cb index ec42766..efe8ce1 100644 --- a/src/mainboard/roda/rk886ex/devicetree.cb +++ b/src/mainboard/roda/rk886ex/devicetree.cb @@ -61,7 +61,6 @@ register "ide_legacy_combined" = "0x1" register "ide_enable_primary" = "0x1" register "ide_enable_secondary" = "0x0" - register "sata_ahci" = "0x0" device pci 1b.0 off end # High Definition Audio device pci 1c.0 on end # PCIe port 1 diff --git a/src/southbridge/intel/i82801gx/chip.h b/src/southbridge/intel/i82801gx/chip.h index db27ef7..019c65e 100644 --- a/src/southbridge/intel/i82801gx/chip.h +++ b/src/southbridge/intel/i82801gx/chip.h @@ -65,7 +65,7 @@ uint32_t ide_legacy_combined; uint32_t ide_enable_primary; uint32_t ide_enable_secondary; - uint32_t sata_ahci; + uint32_t sata_no_ahci; uint32_t sata_ports_implemented; /* Enable linear PCIe Root Port function numbers starting at zero */ diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index d37a822..521d372 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -90,6 +90,7 @@ #define FDVCT 0xe4 #define PCIE_4_PORTS_MAX (1 << 7) +#define AHCI_UNSUPPORTED (1 << 3) /* GEN_PMCON_3 bits */ #define RTC_BATTERY_DEAD (1 << 2) diff --git a/src/southbridge/intel/i82801gx/sata.c b/src/southbridge/intel/i82801gx/sata.c index 567c1e5..dcd9b80 100644 --- a/src/southbridge/intel/i82801gx/sata.c +++ b/src/southbridge/intel/i82801gx/sata.c @@ -71,6 +71,10 @@ u32 *ahci_bar; u8 ports; + + struct device *lpc_dev = pcidev_path_on_root(PCI_DEVFN(31, 0)); + bool ahci_supported = pci_read_config32(lpc_dev, FDVCT) & ACHI_UNSUPPORTED ? false : true; + /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -87,7 +91,18 @@ /* Enable BARs */ pci_write_config16(dev, PCI_COMMAND, 0x0007); - if (config->ide_legacy_combined) { + if (ahci_supported && !config->sata_no_ahci) { + printk(BIOS_DEBUG, "SATA controller in AHCI mode.\n"); + /* Allow both Legacy and Native mode */ + pci_write_config8(dev, 0x09, 0x8f); + + /* Set Interrupt Line */ + /* Interrupt Pin is set by D31IP.PIP */ + pci_write_config8(dev, INTR_LN, 0x0a); + + ahci_bar = (u32 *)(pci_read_config32(dev, 0x27) & ~0x3ff); + ahci_bar[3] = config->sata_ports_implemented; + } else if (config->ide_legacy_combined) { printk(BIOS_DEBUG, "SATA controller in combined mode.\n"); /* No AHCI: clear AHCI base */ pci_write_config32(dev, 0x24, 0x00000000); @@ -118,17 +133,6 @@ /* Restrict ports - 0 and 2 only available */ ports &= 0x5; - } else if (config->sata_ahci) { - printk(BIOS_DEBUG, "SATA controller in AHCI mode.\n"); - /* Allow both Legacy and Native mode */ - pci_write_config8(dev, 0x09, 0x8f); - - /* Set Interrupt Line */ - /* Interrupt Pin is set by D31IP.PIP */ - pci_write_config8(dev, INTR_LN, 0x0a); - - ahci_bar = (u32 *)(pci_read_config32(dev, 0x27) & ~0x3ff); - ahci_bar[3] = config->sata_ports_implemented; } else { printk(BIOS_DEBUG, "SATA controller in plain mode.\n"); /* Set Sata Controller Mode. No Mapping(?) */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30822 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d9f4e63ae8b2862c422938f3103c44e761bcda4 Gerrit-Change-Number: 30822 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

7 25

Change in ...coreboot[master]: qcs405: Add bl31 stage and elf
by build bot (Jenkins) (Code Review) 06 Jun '19

06 Jun '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29981 ) Change subject: qcs405: Add bl31 stage and elf ...................................................................... Patch Set 27: (1 comment) https://review.coreboot.org/#/c/29981/27/src/soc/qualcomm/qcs405/soc.c File src/soc/qualcomm/qcs405/soc.c: https://review.coreboot.org/#/c/29981/27/src/soc/qualcomm/qcs405/soc.c@26 PS27, Line 26: bootmem_add_range((uintptr_t)_dram_reserved, _dram_reserved_size, BM_MEM_BL31); line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/29981 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I967c0b78a3561574609bf8332a22838c85e43429 Gerrit-Change-Number: 29981 Gerrit-PatchSet: 27 Gerrit-Owner: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 06 Jun 2019 10:21:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: qclib: Add qclib support with interface tables
by Patrick Georgi (Code Review) 06 Jun '19

06 Jun '19

Patrick Georgi has uploaded a new patch set (#28) to the change originally created by Nitheesh Sekar. ( https://review.coreboot.org/c/coreboot/+/29967 ) Change subject: qclib: Add qclib support with interface tables ...................................................................... qclib: Add qclib support with interface tables Add to load and execute qclib blob to configure pmic, clocks and ddr.This also loads the qcsdi, cdt blob. Added support for interface tables to read ddr info from qclib and do ddr one time training based on it. Change-Id: I534af71163d034ea04420dda6a94ce31b08c8a07 Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> --- M src/mainboard/google/mistral/Makefile.inc M src/mainboard/google/mistral/romstage.c M src/soc/qualcomm/common/qclib.c M src/soc/qualcomm/qcs405/Makefile.inc M src/soc/qualcomm/qcs405/include/soc/memlayout.ld A src/soc/qualcomm/qcs405/include/soc/qclib.h M src/soc/qualcomm/qcs405/include/soc/symbols.h M src/soc/qualcomm/qcs405/mmu.c A src/soc/qualcomm/qcs405/soc_blob_load.c 9 files changed, 148 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/29967/28 -- To view, visit https://review.coreboot.org/c/coreboot/+/29967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I534af71163d034ea04420dda6a94ce31b08c8a07 Gerrit-Change-Number: 29967 Gerrit-PatchSet: 28 Gerrit-Owner: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sricharan Ramabadhran <srichara(a)qualcomm.corp-partner.google.com> Gerrit-CC: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: soc/intel/skylake: Use PCI func0 if enabled in device tree
by caveh jalali (Code Review) 06 Jun '19

06 Jun '19

caveh jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32846 ) Change subject: soc/intel/skylake: Use PCI func0 if enabled in device tree ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/32846/1/src/soc/intel/skylake/chip_fsp20.c File src/soc/intel/skylake/chip_fsp20.c: https://review.coreboot.org/#/c/32846/1/src/soc/intel/skylake/chip_fsp20.c@… PS1, Line 113: enabled > "... enabled in device tree, ... […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/32846 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c44ee5493eff1f9e04aa891030fde2a6f0c636f Gerrit-Change-Number: 32846 Gerrit-PatchSet: 2 Gerrit-Owner: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org> Gerrit-Comment-Date: Thu, 06 Jun 2019 08:45:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/skylake: Use PCI func0 if enabled in device tree
by Caveh Jalali (Code Review) 06 Jun '19

06 Jun '19

Hello Patrick Rudolph, caveh jalali, Duncan Laurie, Gaggery Tsai, build bot (Jenkins), Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/32846 to look at the new patch set (#2). Change subject: soc/intel/skylake: Use PCI func0 if enabled in device tree ...................................................................... soc/intel/skylake: Use PCI func0 if enabled in device tree Originally, if a devfn0 device was physically present, it would be swapped with the next enabled device from the device tree. This would result in the WiFi chip not showing up in ACPI SSDT. We should check to see if the original device is enabled in the device tree before looking for the next device to swap into its place. BUG=b:122327852 TEST=the WiFi chip ACPI wake resource is now present SSDT: Scope (\_SB.PCI0.RP01) { Device (WIFI) { Name (_UID, Zero) // _UID: Unique ID Name (_DDN, "Intel WiFi") // _DDN: DOS Device Name Name (_ADR, 0x00000000) // _ADR: Address Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake { 0x27, 0x03 }) } } localhost ~ # cat /proc/acpi/wakeup Device S-state Status Sysfs node ... WIFI S3 *disabled pci:0000:01:00.0 ... localhost ~ # Change-Id: I7c44ee5493eff1f9e04aa891030fde2a6f0c636f Signed-off-by: Caveh Jalali <caveh(a)chromium.org> --- M src/soc/intel/skylake/chip_fsp20.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/32846/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/32846 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c44ee5493eff1f9e04aa891030fde2a6f0c636f Gerrit-Change-Number: 32846 Gerrit-PatchSet: 2 Gerrit-Owner: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: mainboard/portwell/m107: Do initial mainboard commit
by Frans Hendriks (Code Review) 06 Jun '19

06 Jun '19

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29470 ) Change subject: mainboard/portwell/m107: Do initial mainboard commit ...................................................................... Patch Set 13: (6 comments) https://review.coreboot.org/#/c/29470/11/Documentation/mainboard/portwell/p… File Documentation/mainboard/portwell/pq7-m107.md: https://review.coreboot.org/#/c/29470/11/Documentation/mainboard/portwell/p… PS11, Line 94: | Super I/O | None | > Should this be "Super I/O, EC", like https://review.coreboot. […] Done https://review.coreboot.org/#/c/29470/11/src/mainboard/portwell/m107/Kconfig File src/mainboard/portwell/m107/Kconfig: https://review.coreboot.org/#/c/29470/11/src/mainboard/portwell/m107/Kconfi… PS11, Line 30: choice > This line https://review.coreboot.org/c/coreboot/+/29470/11/src/mainboard/portwell/m1… […] Done https://review.coreboot.org/#/c/29470/11/src/mainboard/portwell/m107/board_… File src/mainboard/portwell/m107/board_info.txt: https://review.coreboot.org/#/c/29470/11/src/mainboard/portwell/m107/board_… PS11, Line 3: Category: misc > sbc? Done https://review.coreboot.org/#/c/29470/11/src/mainboard/portwell/m107/com_in… File src/mainboard/portwell/m107/com_init.c: https://review.coreboot.org/#/c/29470/11/src/mainboard/portwell/m107/com_in… PS11, Line 24: void car_mainboard_pre_console_init(void) > It can be also used to disable the onboard UART and enable the SuperIO UART in one sway. […] Done https://review.coreboot.org/#/c/29470/11/src/mainboard/portwell/m107/fadt.c File src/mainboard/portwell/m107/fadt.c: https://review.coreboot.org/#/c/29470/11/src/mainboard/portwell/m107/fadt.c… PS11, Line 31: header->asl_compiler_revision = 1; > Is there a reason for setting this to 1? Usually it is set to asl_revision. Done https://review.coreboot.org/#/c/29470/11/src/mainboard/portwell/m107/smihan… File src/mainboard/portwell/m107/smihandler.c: https://review.coreboot.org/#/c/29470/11/src/mainboard/portwell/m107/smihan… PS11, Line 25: case 0x99: > Perhaps we can get rid of this file, same as https://review.coreboot. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/29470 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d3173fdcf881f894a75cd9798ba173b425d4e62 Gerrit-Change-Number: 29470 Gerrit-PatchSet: 13 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 06 Jun 2019 08:40:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Frans Hendriks <fhendriks(a)eltan.com> Comment-In-Reply-To: David Hendricks <david.hendricks(a)gmail.com> Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: comment

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coreboot-gerrit June 2019