coreboot-gerrit June 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: nb/intel/sandybridge: Drop iommu.c and rename functions
by Felix Held (Code Review) 07 Jun '19

07 Jun '19

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32068 ) Change subject: nb/intel/sandybridge: Drop iommu.c and rename functions ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/32068 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ec395bf6722bceb84316e92733dcfcd7a093639 Gerrit-Change-Number: 32068 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 07 Jun 2019 13:56:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: [WIP] Nvidia Optimus support for ThinkPads
by Patrik Tesarik (Code Review) 07 Jun '19

07 Jun '19

Patrik Tesarik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28380 ) Change subject: [WIP] Nvidia Optimus support for ThinkPads ...................................................................... Patch Set 13: > Patch Set 13: > > The latest build does not work anymore for my T430, internal and external displays don't activate at all. Yesterday with the build dated 04-06 or 06-06-19 it worked. I'll try to reproduce later today. > > Though I really appreciate the progress. Thanks! Edit: Works now. I most probably missed to flag "Load proprietary blob repos" after a 'make distclean'. -- To view, visit https://review.coreboot.org/c/coreboot/+/28380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I277808d6c1d8bd6e0a267a53f25471597698f8d5 Gerrit-Change-Number: 28380 Gerrit-PatchSet: 13 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt Parnell Gerrit-CC: Name of user not set #1002090 Gerrit-CC: Patrik Tesarik Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 07 Jun 2019 12:51:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/dell: Add Dell Optiplex 790
by Angel Pons (Code Review) 07 Jun '19

07 Jun '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/21774 ) Change subject: mb/dell: Add Dell Optiplex 790 ...................................................................... Patch Set 57: (1 comment) I found this document about the Optiplex 790, which may be helpful as a reference: https://clascsg.uconn.edu/download/specs/O790.pdf https://review.coreboot.org/#/c/21774/57//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/21774/57//COMMIT_MSG@12 PS57, Line 12: : - DT: 4 RAM slots, PEG, PCIe x1, PCI, PCIe x16 : - MT: 4 RAM slots, PEG, PCIe x1, PCI, PCIe x16 Both of these use the exact same PCB, but the MT version has an extra SATA connector installed on the mainboard. DT has the footprint for the connector, but it is not installed. -- To view, visit https://review.coreboot.org/c/coreboot/+/21774 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3d3a13163d5da1368259a7498019d42fb3ed57f Gerrit-Change-Number: 21774 Gerrit-PatchSet: 57 Gerrit-Owner: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Johanna Schander <coreboot(a)mimoja.de> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Thomas Heijligen <src(a)posteo.de> Gerrit-Comment-Date: Fri, 07 Jun 2019 12:14:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: [WIP] Nvidia Optimus support for ThinkPads
by Patrik Tesarik (Code Review) 07 Jun '19

07 Jun '19

Patrik Tesarik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28380 ) Change subject: [WIP] Nvidia Optimus support for ThinkPads ...................................................................... Patch Set 13: The latest build does not work anymore for my T430, internal and external displays don't activate at all. Yesterday with the build dated 04-06 or 06-06-19 it worked. I'll try to reproduce later today. Though I really appreciate the progress. Thanks! -- To view, visit https://review.coreboot.org/c/coreboot/+/28380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I277808d6c1d8bd6e0a267a53f25471597698f8d5 Gerrit-Change-Number: 28380 Gerrit-PatchSet: 13 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt Parnell Gerrit-CC: Name of user not set #1002090 Gerrit-CC: Patrik Tesarik Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 07 Jun 2019 11:14:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel: Add some missing MCH PCIe IDs
by Keno Fischer (Code Review) 07 Jun '19

07 Jun '19

Keno Fischer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33286 Change subject: soc/intel: Add some missing MCH PCIe IDs ...................................................................... soc/intel: Add some missing MCH PCIe IDs These are documented in the Intel Datasheet entitled "6th Generation Intel® Processor Datasheet for S-Platforms" "6th Generation Intel® Processor Datasheet for H-Platforms" (Volume 2) Without them, coreboot fails to properly inform the payload of the amount of available memory. Signed-off-by: Keno Fischer <keno(a)juliacomputing.com> Change-Id: I5b810c6415c4aa0404e5fa318d2c8db292566b8a --- M src/include/device/pci_ids.h M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/skylake/bootblock/report_platform.c 3 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/33286/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index a35e134..fd90396 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3076,7 +3076,10 @@ #define PCI_DEVICE_ID_INTEL_SKL_ID_U 0x1904 #define PCI_DEVICE_ID_INTEL_SKL_ID_Y 0x190c #define PCI_DEVICE_ID_INTEL_SKL_ID_ULX 0x1924 +#define PCI_DEVICE_ID_INTEL_SKL_ID_H_2 0x1900 #define PCI_DEVICE_ID_INTEL_SKL_ID_H 0x1910 +#define PCI_DEVICE_ID_INTEL_SKL_ID_S_2 0x190f +#define PCI_DEVICE_ID_INTEL_SKL_ID_S_4 0x191f #define PCI_DEVICE_ID_INTEL_KBL_ID_S 0x590f #define PCI_DEVICE_ID_INTEL_SKL_ID_H_EM 0x1918 #define PCI_DEVICE_ID_INTEL_SKL_ID_DT 0x191f diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 281a7f7..a93db65 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -341,6 +341,9 @@ PCI_DEVICE_ID_INTEL_SKL_ID_Y, PCI_DEVICE_ID_INTEL_SKL_ID_ULX, PCI_DEVICE_ID_INTEL_SKL_ID_H, + PCI_DEVICE_ID_INTEL_SKL_ID_H_2, + PCI_DEVICE_ID_INTEL_SKL_ID_S_2, + PCI_DEVICE_ID_INTEL_SKL_ID_S_4, PCI_DEVICE_ID_INTEL_WHL_ID_Wx2, PCI_DEVICE_ID_INTEL_WHL_ID_Wx4, PCI_DEVICE_ID_INTEL_KBL_ID_S, diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c index 1e81809..e201a0a 100644 --- a/src/soc/intel/skylake/bootblock/report_platform.c +++ b/src/soc/intel/skylake/bootblock/report_platform.c @@ -53,6 +53,9 @@ { PCI_DEVICE_ID_INTEL_SKL_ID_H, "Skylake-H" }, { PCI_DEVICE_ID_INTEL_SKL_ID_H_EM, "Skylake-H Embedded" }, { PCI_DEVICE_ID_INTEL_SKL_ID_DT, "Skylake-DT" }, + { PCI_DEVICE_ID_INTEL_SKL_ID_H_2, "Skylake-H (2 Core)" }, + { PCI_DEVICE_ID_INTEL_SKL_ID_S_2, "Skylake-S (2 Core)" }, + { PCI_DEVICE_ID_INTEL_SKL_ID_S_4, "Skylake-S (4 Core)" }, { PCI_DEVICE_ID_INTEL_KBL_ID_U, "Kabylake-U" }, { PCI_DEVICE_ID_INTEL_KBL_U_R, "Kabylake-R ULT"}, { PCI_DEVICE_ID_INTEL_KBL_ID_Y, "Kabylake-Y" }, -- To view, visit https://review.coreboot.org/c/coreboot/+/33286 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b810c6415c4aa0404e5fa318d2c8db292566b8a Gerrit-Change-Number: 33286 Gerrit-PatchSet: 1 Gerrit-Owner: Keno Fischer <keno(a)alumni.harvard.edu> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Remove a newline.
by Asami Doi (Code Review) 07 Jun '19

07 Jun '19

Asami Doi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33291 Change subject: Remove a newline. ...................................................................... Remove a newline. Change-Id: Ia70d34f8ddc414b5dfc238251bd36201a606fa87 Signed-off-by: Asami Doi <doiasami1219(a)gmail.com> --- M payloads/libpayload/configs/config.emulation-qemu-arm M payloads/libpayload/include/arm/arch/io.h 2 files changed, 6 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/33291/1 diff --git a/payloads/libpayload/configs/config.emulation-qemu-arm b/payloads/libpayload/configs/config.emulation-qemu-arm index e498126..191aa7a 100644 --- a/payloads/libpayload/configs/config.emulation-qemu-arm +++ b/payloads/libpayload/configs/config.emulation-qemu-arm @@ -7,4 +7,3 @@ CONFIG_LP_USB_OHCI=y CONFIG_LP_USB_EHCI=y CONFIG_LP_USB_XHCI=y - diff --git a/payloads/libpayload/include/arm/arch/io.h b/payloads/libpayload/include/arm/arch/io.h index 58b8a22..f0180a3 100644 --- a/payloads/libpayload/include/arm/arch/io.h +++ b/payloads/libpayload/include/arm/arch/io.h @@ -34,13 +34,13 @@ #include <stdint.h> #include <arch/cache.h> -#define inb(a) read8((const void *) (a)) -#define inw(a) read16((const void *) (a)) -#define inl(a) read32((const void *) (a)) +#define inb(a) read8((const void *)(a)) +#define inw(a) read16((const void *)(a)) +#define inl(a) read32((const void *)(a)) -#define outb(v, a) write8((void *) (&v), a) -#define outw(v, a) write16((void *) (&v), a) -#define outl(v, a) write32((void *) (&v), a) +#define outb(v, a) write8((void *)(&v), a) +#define outw(v, a) write16((void *)(&v), a) +#define outl(v, a) write32((void *)(&v), a) /* * readb/w/l writeb/w/l are deprecated. use read8/16/32 and write8/16/32 -- To view, visit https://review.coreboot.org/c/coreboot/+/33291 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia70d34f8ddc414b5dfc238251bd36201a606fa87 Gerrit-Change-Number: 33291 Gerrit-PatchSet: 1 Gerrit-Owner: Asami Doi <d0iasm.pub(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...libgfxinit[master]: gma: Add Kaby Lake support
by Thomas Heijligen (Code Review) 07 Jun '19

07 Jun '19

Thomas Heijligen has posted comments on this change. ( https://review.coreboot.org/c/libgfxinit/+/28763 ) Change subject: gma: Add Kaby Lake support ...................................................................... Patch Set 7: Code-Review+1 still working on tested device -- To view, visit https://review.coreboot.org/c/libgfxinit/+/28763 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: Ice05e07b016cebc7258a9790e38e079e63227a4b Gerrit-Change-Number: 28763 Gerrit-PatchSet: 7 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 07 Jun 2019 08:51:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/intel/icelake_rvp: Update FSP-M UPDs to support iclrvp memory init
by Subrata Banik (Code Review) 07 Jun '19

07 Jun '19

Hello Aaron Durbin, Aamir Bohra, Aamir Bohra, Wonkyu Kim, Ravishankar Sarawadi, Rizwan Qureshi, Shelley Chen, build bot (Jenkins), Patrick Georgi, Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/32522 to look at the new patch set (#4). Change subject: mb/intel/icelake_rvp: Update FSP-M UPDs to support iclrvp memory init ...................................................................... mb/intel/icelake_rvp: Update FSP-M UPDs to support iclrvp memory init Change-Id: Ib55fdfae6e9320c44761682fc134be0731de0fcf Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/mainboard/intel/icelake_rvp/romstage_fsp_params.c 1 file changed, 44 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/32522/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/32522 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib55fdfae6e9320c44761682fc134be0731de0fcf Gerrit-Change-Number: 32522 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamirbohra(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: Remove a newline and apply for a patch of lint errors.
by Asami Doi (Code Review) 07 Jun '19

07 Jun '19

Asami Doi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33290 Change subject: Remove a newline and apply for a patch of lint errors. ...................................................................... Remove a newline and apply for a patch of lint errors. Change-Id: I2efcc74038e73c8193ae9d6177c7b44c59ec8d61 Signed-off-by: Asami Doi <doiasami1219(a)gmail.com> --- M payloads/libpayload/configs/config.emulation-qemu-arm M payloads/libpayload/include/arm/arch/io.h 2 files changed, 6 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/33290/1 diff --git a/payloads/libpayload/configs/config.emulation-qemu-arm b/payloads/libpayload/configs/config.emulation-qemu-arm index e498126..191aa7a 100644 --- a/payloads/libpayload/configs/config.emulation-qemu-arm +++ b/payloads/libpayload/configs/config.emulation-qemu-arm @@ -7,4 +7,3 @@ CONFIG_LP_USB_OHCI=y CONFIG_LP_USB_EHCI=y CONFIG_LP_USB_XHCI=y - diff --git a/payloads/libpayload/include/arm/arch/io.h b/payloads/libpayload/include/arm/arch/io.h index 58b8a22..f0180a3 100644 --- a/payloads/libpayload/include/arm/arch/io.h +++ b/payloads/libpayload/include/arm/arch/io.h @@ -34,13 +34,13 @@ #include <stdint.h> #include <arch/cache.h> -#define inb(a) read8((const void *) (a)) -#define inw(a) read16((const void *) (a)) -#define inl(a) read32((const void *) (a)) +#define inb(a) read8((const void *)(a)) +#define inw(a) read16((const void *)(a)) +#define inl(a) read32((const void *)(a)) -#define outb(v, a) write8((void *) (&v), a) -#define outw(v, a) write16((void *) (&v), a) -#define outl(v, a) write32((void *) (&v), a) +#define outb(v, a) write8((void *)(&v), a) +#define outw(v, a) write16((void *)(&v), a) +#define outl(v, a) write32((void *)(&v), a) /* * readb/w/l writeb/w/l are deprecated. use read8/16/32 and write8/16/32 -- To view, visit https://review.coreboot.org/c/coreboot/+/33290 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2efcc74038e73c8193ae9d6177c7b44c59ec8d61 Gerrit-Change-Number: 33290 Gerrit-PatchSet: 1 Gerrit-Owner: Asami Doi <d0iasm.pub(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Remove a newline and fix lint errrors.
by Asami Doi (Code Review) 07 Jun '19

07 Jun '19

Asami Doi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33289 Change subject: Remove a newline and fix lint errrors. ...................................................................... Remove a newline and fix lint errrors. Change-Id: I3a669af772cc349ac3e16b9038d88ae664023720 Signed-off-by: Asami Doi <doiasami1219(a)gmail.com> --- M payloads/libpayload/configs/config.emulation-qemu-arm M payloads/libpayload/include/arm/arch/io.h 2 files changed, 6 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/33289/1 diff --git a/payloads/libpayload/configs/config.emulation-qemu-arm b/payloads/libpayload/configs/config.emulation-qemu-arm index e498126..191aa7a 100644 --- a/payloads/libpayload/configs/config.emulation-qemu-arm +++ b/payloads/libpayload/configs/config.emulation-qemu-arm @@ -7,4 +7,3 @@ CONFIG_LP_USB_OHCI=y CONFIG_LP_USB_EHCI=y CONFIG_LP_USB_XHCI=y - diff --git a/payloads/libpayload/include/arm/arch/io.h b/payloads/libpayload/include/arm/arch/io.h index 58b8a22..f0180a3 100644 --- a/payloads/libpayload/include/arm/arch/io.h +++ b/payloads/libpayload/include/arm/arch/io.h @@ -34,13 +34,13 @@ #include <stdint.h> #include <arch/cache.h> -#define inb(a) read8((const void *) (a)) -#define inw(a) read16((const void *) (a)) -#define inl(a) read32((const void *) (a)) +#define inb(a) read8((const void *)(a)) +#define inw(a) read16((const void *)(a)) +#define inl(a) read32((const void *)(a)) -#define outb(v, a) write8((void *) (&v), a) -#define outw(v, a) write16((void *) (&v), a) -#define outl(v, a) write32((void *) (&v), a) +#define outb(v, a) write8((void *)(&v), a) +#define outw(v, a) write16((void *)(&v), a) +#define outl(v, a) write32((void *)(&v), a) /* * readb/w/l writeb/w/l are deprecated. use read8/16/32 and write8/16/32 -- To view, visit https://review.coreboot.org/c/coreboot/+/33289 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a669af772cc349ac3e16b9038d88ae664023720 Gerrit-Change-Number: 33289 Gerrit-PatchSet: 1 Gerrit-Owner: Asami Doi <d0iasm.pub(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit June 2019