Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33293
Change subject: src/soc/intel/skylake/acpi: Remove Return for PS0/3 ......................................................................
src/soc/intel/skylake/acpi: Remove Return for PS0/3
Remove the Return statement within the PS0, PS3 methods. PS0/3 are not allowed to return anything. Even an empty return will be resolved to Return(Null). In order to be conform with the specification, the code has been refactored to remove the return statements.
Change-Id: I7b4820e8dd40a9169a7facce67282b8af5af67af Signed-off-by: Christian Walter christian.walter@9elements.com --- M src/soc/intel/skylake/acpi/xhci.asl 1 file changed, 74 insertions(+), 78 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/33293/1
diff --git a/src/soc/intel/skylake/acpi/xhci.asl b/src/soc/intel/skylake/acpi/xhci.asl index a23d78a..b5aa412 100644 --- a/src/soc/intel/skylake/acpi/xhci.asl +++ b/src/soc/intel/skylake/acpi/xhci.asl @@ -129,97 +129,93 @@
Method (_PS0, 0, Serialized) { - If (LEqual (^DVID, 0xFFFF)) { - Return - } - If (LOr (LEqual (^XMEM, 0xFFFF), LEqual (^XMEM, 0x0000))) { - Return - } + If (!LEqual (^DVID, 0xFFFF)) { + If (!LOr (LEqual (^XMEM, 0xFFFF), LEqual (^XMEM, 0x0000))) {
- /* Disable d3hot and SS link trunk clock gating */ - Store(Zero, ^D3HE) - Store(Zero, ^STGE) + /* Disable d3hot and SS link trunk clock gating */ + Store(Zero, ^D3HE) + Store(Zero, ^STGE)
- /* If device is in D3, set back to D0 */ - If (LEqual (^D0D3, 3)) { - Store (Zero, Local0) - Store (Local0, ^D0D3) - Store (^D0D3, Local0) - } - - /* Disable USB2 PHY SUS Well Power Gating */ - Store (Zero, ^UPSW) - - /* - * Apply USB2 PHPY Power Gating workaround if needed. - */ - If (^^PMC.UWAB) { - /* Write to MTPMC to have PMC disable power gating */ - Store (1, ^^PMC.MPMC) - - /* Wait for PCH_PM_STS.MSG_FULL_STS to be 0 */ - Store (10, Local0) - While (^^PMC.PMFS) { - If (LNot (Local0)) { - Break + /* If device is in D3, set back to D0 */ + If (LEqual (^D0D3, 3)) { + Store (Zero, Local0) + Store (Local0, ^D0D3) + Store (^D0D3, Local0) } - Decrement (Local0) - Sleep (10) + + /* Disable USB2 PHY SUS Well Power Gating */ + Store (Zero, ^UPSW) + + /* + * Apply USB2 PHPY Power Gating workaround if needed. + */ + If (^^PMC.UWAB) { + /* Write to MTPMC to have PMC disable power gating */ + Store (1, ^^PMC.MPMC) + + /* Wait for PCH_PM_STS.MSG_FULL_STS to be 0 */ + Store (10, Local0) + While (^^PMC.PMFS) { + If (LNot (Local0)) { + Break + } + Decrement (Local0) + Sleep (10) + } + } } } }
Method (_PS3, 0, Serialized) { - If (LEqual (^DVID, 0xFFFF)) { - Return - } - If (LOr (LEqual (^XMEM, 0xFFFF), LEqual (^XMEM, 0x0000))) { - Return - } + If (!LEqual (^DVID, 0xFFFF)) { + If (!LOr (LEqual (^XMEM, 0xFFFF), LEqual (^XMEM, 0x0000))) {
- /* Clear PME Status */ - Store (1, ^PMES) + /* Clear PME Status */ + Store (1, ^PMES)
- /* Enable PME */ - Store (1, ^PMEE) + /* Enable PME */ + Store (1, ^PMEE)
- /* If device is in D3, set back to D0 */ - If (LEqual (^D0D3, 3)) { - Store (Zero, Local0) - Store (Local0, ^D0D3) - Store (^D0D3, Local0) - } - - /* Enable USB2 PHY SUS Well Power Gating in D0/D0i2/D0i3/D3 */ - Store (3, ^UPSW) - - /* Enable d3hot and SS link trunk clock gating */ - Store(One, ^D3HE) - Store(One, ^STGE) - - /* Now put device in D3 */ - Store (3, Local0) - Store (Local0, ^D0D3) - Store (^D0D3, Local0) - - /* - * Apply USB2 PHPY Power Gating workaround if needed. - * This code assumes XDCI is disabled, if it is enabled - * then this must also check if it is in D3 state too. - */ - If (^^PMC.UWAB) { - /* Write to MTPMC to have PMC enable power gating */ - Store (3, ^^PMC.MPMC) - - /* Wait for PCH_PM_STS.MSG_FULL_STS to be 0 */ - Store (10, Local0) - While (^^PMC.PMFS) { - If (LNot (Local0)) { - Break + /* If device is in D3, set back to D0 */ + If (LEqual (^D0D3, 3)) { + Store (Zero, Local0) + Store (Local0, ^D0D3) + Store (^D0D3, Local0) } - Decrement (Local0) - Sleep (10) + + /* Enable USB2 PHY SUS Well Power Gating in D0/D0i2/D0i3/D3 */ + Store (3, ^UPSW) + + /* Enable d3hot and SS link trunk clock gating */ + Store(One, ^D3HE) + Store(One, ^STGE) + + /* Now put device in D3 */ + Store (3, Local0) + Store (Local0, ^D0D3) + Store (^D0D3, Local0) + + /* + * Apply USB2 PHPY Power Gating workaround if needed. + * This code assumes XDCI is disabled, if it is enabled + * then this must also check if it is in D3 state too. + */ + If (^^PMC.UWAB) { + /* Write to MTPMC to have PMC enable power gating */ + Store (3, ^^PMC.MPMC) + + /* Wait for PCH_PM_STS.MSG_FULL_STS to be 0 */ + Store (10, Local0) + While (^^PMC.PMFS) { + If (LNot (Local0)) { + Break + } + Decrement (Local0) + Sleep (10) + } + } } } }
Christian Walter has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/33293 )
Change subject: src/soc/intel/skylake/acpi: Remove Return for PS0/3 ......................................................................
src/soc/intel/skylake/acpi: Remove Return for PS0/3
Remove the Return statement within the PS0, PS3 methods. PS0/3 are not allowed to return anything. Even an empty return will be resolved to Return(0). In order to be conform with the specification, the code has been refactored to remove the return statements.
Change-Id: I7b4820e8dd40a9169a7facce67282b8af5af67af Signed-off-by: Christian Walter christian.walter@9elements.com --- M src/soc/intel/skylake/acpi/xhci.asl 1 file changed, 74 insertions(+), 78 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/33293/2
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33293
to look at the new patch set (#3).
Change subject: src/soc/intel/skylake/acpi: Remove Return for PS0/3 ......................................................................
src/soc/intel/skylake/acpi: Remove Return for PS0/3
Remove the Return statement within the PS0, PS3 methods. PS0/3 are not allowed to return anything. Even an empty return will be resolved to Return(Null). In order to be conform with the specification, the code has been refactored to remove the return statements.
Change-Id: I7b4820e8dd40a9169a7facce67282b8af5af67af Signed-off-by: Christian Walter christian.walter@9elements.com --- M src/soc/intel/skylake/acpi/xhci.asl 1 file changed, 74 insertions(+), 78 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/33293/3
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33293 )
Change subject: src/soc/intel/skylake/acpi: Remove Return for PS0/3 ......................................................................
Patch Set 4: Code-Review+2
Felix Held has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/33293 )
Change subject: src/soc/intel/skylake/acpi: Remove Return for PS0/3 ......................................................................
src/soc/intel/skylake/acpi: Remove Return for PS0/3
Remove the Return statement within the PS0, PS3 methods. PS0/3 are not allowed to return anything. Even an empty return will be resolved to Return(Null). In order to be conform with the specification, the code has been refactored to remove the return statements.
Change-Id: I7b4820e8dd40a9169a7facce67282b8af5af67af Signed-off-by: Christian Walter christian.walter@9elements.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/33293 Reviewed-by: Felix Held felix-coreboot@felixheld.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/skylake/acpi/xhci.asl 1 file changed, 74 insertions(+), 78 deletions(-)
Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved
diff --git a/src/soc/intel/skylake/acpi/xhci.asl b/src/soc/intel/skylake/acpi/xhci.asl index a23d78a..b5aa412 100644 --- a/src/soc/intel/skylake/acpi/xhci.asl +++ b/src/soc/intel/skylake/acpi/xhci.asl @@ -129,97 +129,93 @@
Method (_PS0, 0, Serialized) { - If (LEqual (^DVID, 0xFFFF)) { - Return - } - If (LOr (LEqual (^XMEM, 0xFFFF), LEqual (^XMEM, 0x0000))) { - Return - } + If (!LEqual (^DVID, 0xFFFF)) { + If (!LOr (LEqual (^XMEM, 0xFFFF), LEqual (^XMEM, 0x0000))) {
- /* Disable d3hot and SS link trunk clock gating */ - Store(Zero, ^D3HE) - Store(Zero, ^STGE) + /* Disable d3hot and SS link trunk clock gating */ + Store(Zero, ^D3HE) + Store(Zero, ^STGE)
- /* If device is in D3, set back to D0 */ - If (LEqual (^D0D3, 3)) { - Store (Zero, Local0) - Store (Local0, ^D0D3) - Store (^D0D3, Local0) - } - - /* Disable USB2 PHY SUS Well Power Gating */ - Store (Zero, ^UPSW) - - /* - * Apply USB2 PHPY Power Gating workaround if needed. - */ - If (^^PMC.UWAB) { - /* Write to MTPMC to have PMC disable power gating */ - Store (1, ^^PMC.MPMC) - - /* Wait for PCH_PM_STS.MSG_FULL_STS to be 0 */ - Store (10, Local0) - While (^^PMC.PMFS) { - If (LNot (Local0)) { - Break + /* If device is in D3, set back to D0 */ + If (LEqual (^D0D3, 3)) { + Store (Zero, Local0) + Store (Local0, ^D0D3) + Store (^D0D3, Local0) } - Decrement (Local0) - Sleep (10) + + /* Disable USB2 PHY SUS Well Power Gating */ + Store (Zero, ^UPSW) + + /* + * Apply USB2 PHPY Power Gating workaround if needed. + */ + If (^^PMC.UWAB) { + /* Write to MTPMC to have PMC disable power gating */ + Store (1, ^^PMC.MPMC) + + /* Wait for PCH_PM_STS.MSG_FULL_STS to be 0 */ + Store (10, Local0) + While (^^PMC.PMFS) { + If (LNot (Local0)) { + Break + } + Decrement (Local0) + Sleep (10) + } + } } } }
Method (_PS3, 0, Serialized) { - If (LEqual (^DVID, 0xFFFF)) { - Return - } - If (LOr (LEqual (^XMEM, 0xFFFF), LEqual (^XMEM, 0x0000))) { - Return - } + If (!LEqual (^DVID, 0xFFFF)) { + If (!LOr (LEqual (^XMEM, 0xFFFF), LEqual (^XMEM, 0x0000))) {
- /* Clear PME Status */ - Store (1, ^PMES) + /* Clear PME Status */ + Store (1, ^PMES)
- /* Enable PME */ - Store (1, ^PMEE) + /* Enable PME */ + Store (1, ^PMEE)
- /* If device is in D3, set back to D0 */ - If (LEqual (^D0D3, 3)) { - Store (Zero, Local0) - Store (Local0, ^D0D3) - Store (^D0D3, Local0) - } - - /* Enable USB2 PHY SUS Well Power Gating in D0/D0i2/D0i3/D3 */ - Store (3, ^UPSW) - - /* Enable d3hot and SS link trunk clock gating */ - Store(One, ^D3HE) - Store(One, ^STGE) - - /* Now put device in D3 */ - Store (3, Local0) - Store (Local0, ^D0D3) - Store (^D0D3, Local0) - - /* - * Apply USB2 PHPY Power Gating workaround if needed. - * This code assumes XDCI is disabled, if it is enabled - * then this must also check if it is in D3 state too. - */ - If (^^PMC.UWAB) { - /* Write to MTPMC to have PMC enable power gating */ - Store (3, ^^PMC.MPMC) - - /* Wait for PCH_PM_STS.MSG_FULL_STS to be 0 */ - Store (10, Local0) - While (^^PMC.PMFS) { - If (LNot (Local0)) { - Break + /* If device is in D3, set back to D0 */ + If (LEqual (^D0D3, 3)) { + Store (Zero, Local0) + Store (Local0, ^D0D3) + Store (^D0D3, Local0) } - Decrement (Local0) - Sleep (10) + + /* Enable USB2 PHY SUS Well Power Gating in D0/D0i2/D0i3/D3 */ + Store (3, ^UPSW) + + /* Enable d3hot and SS link trunk clock gating */ + Store(One, ^D3HE) + Store(One, ^STGE) + + /* Now put device in D3 */ + Store (3, Local0) + Store (Local0, ^D0D3) + Store (^D0D3, Local0) + + /* + * Apply USB2 PHPY Power Gating workaround if needed. + * This code assumes XDCI is disabled, if it is enabled + * then this must also check if it is in D3 state too. + */ + If (^^PMC.UWAB) { + /* Write to MTPMC to have PMC enable power gating */ + Store (3, ^^PMC.MPMC) + + /* Wait for PCH_PM_STS.MSG_FULL_STS to be 0 */ + Store (10, Local0) + While (^^PMC.PMFS) { + If (LNot (Local0)) { + Break + } + Decrement (Local0) + Sleep (10) + } + } } } }
-
Christian Walter (Code Review) -
Felix Held (Code Review)