coreboot-gerrit May 2019

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Change in ...coreboot[master]: [Test] Remaining unused variables
by HAOUAS Elyes (Code Review) 22 May '19

22 May '19

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29926 to look at the new patch set (#27). Change subject: [Test] Remaining unused variables ...................................................................... [Test] Remaining unused variables Test CFLAGS_common += -Wno-unused-function \ -Wno-tautological-compare -Wno-shift-overflow Change-Id: Ic3dde296ab4b84add8a8ab6a3bb5ecb65da2c158 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/29926/27 -- To view, visit https://review.coreboot.org/c/coreboot/+/29926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3dde296ab4b84add8a8ab6a3bb5ecb65da2c158 Gerrit-Change-Number: 29926 Gerrit-PatchSet: 27 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: soc/amd/common: Create AcpiMmio functionality from stoneyridge
by Marshall Dawson (Code Review) 22 May '19

22 May '19

Hello Richard Spiegel, Martin Roth, Furquan Shaikh, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32649 to review the following change. Change subject: soc/amd/common: Create AcpiMmio functionality from stoneyridge ...................................................................... soc/amd/common: Create AcpiMmio functionality from stoneyridge Move the stoneyridge AcpiMmio code into soc/amd/common. The SB800 southbridge introduced the MMIO hardware blocks at 0xfed80000 commonly known as AcpiMmio. Implementations beginning with Mullins enable decode in PMx04. Older designs use PMx24 and allow for configuring the base address. Future work may support the older version. Comparing the documentation for AMD's RRGs and BKDGs, it is evident that the block locations have not been reassigned across products. In some cases, address locations are deprecated and new ones consumed, e.g. the early GPIO blocks were simpler at offset 0x100 and the newer GPIO banks are now at 0x1500, 0x1600, and 0x1700. Note: Do not infer the definitions within the hardware blocks are consistent across family/model products. Change-Id: I083b6339cd29e72289e63c9331a815c46d71600d Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/mainboard/google/kahlee/mainboard.c M src/soc/amd/common/block/acpi/halt.c A src/soc/amd/common/block/acpimmio/Kconfig A src/soc/amd/common/block/acpimmio/Makefile.inc A src/soc/amd/common/block/acpimmio/mmio_util.c A src/soc/amd/common/block/include/amdblocks/acpimmio.h A src/soc/amd/common/block/include/amdblocks/acpimmio_map.h M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/acpi.c M src/soc/amd/stoneyridge/gpio.c M src/soc/amd/stoneyridge/include/soc/iomap.h M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/lpc.c M src/soc/amd/stoneyridge/pmutil.c M src/soc/amd/stoneyridge/ramtop.c M src/soc/amd/stoneyridge/reset.c M src/soc/amd/stoneyridge/sb_util.c M src/soc/amd/stoneyridge/smbus.c M src/soc/amd/stoneyridge/smi.c M src/soc/amd/stoneyridge/smi_util.c M src/soc/amd/stoneyridge/smihandler.c M src/soc/amd/stoneyridge/southbridge.c M src/soc/amd/stoneyridge/usb.c 23 files changed, 591 insertions(+), 458 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/32649/1 diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index ad979a5..cfd5637 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -27,6 +27,7 @@ #include <soc/nvs.h> #include <soc/pci_devs.h> #include <soc/southbridge.h> +#include <amdblocks/acpimmio.h> #include <variant/ec.h> #include <variant/thermal.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/soc/amd/common/block/acpi/halt.c b/src/soc/amd/common/block/acpi/halt.c index 8f36efb..200b3c1 100644 --- a/src/soc/amd/common/block/acpi/halt.c +++ b/src/soc/amd/common/block/acpi/halt.c @@ -15,6 +15,7 @@ #include <arch/acpi.h> #include <soc/southbridge.h> +#include <amdblocks/acpimmio.h> #include <halt.h> void poweroff(void) diff --git a/src/soc/amd/common/block/acpimmio/Kconfig b/src/soc/amd/common/block/acpimmio/Kconfig new file mode 100644 index 0000000..f14cc0c --- /dev/null +++ b/src/soc/amd/common/block/acpimmio/Kconfig @@ -0,0 +1,6 @@ +config SOC_AMD_COMMON_BLOCK_ACPIMMIO + bool + default n + help + Select this option to enable hardware blocks in the AcpiMmio + address space (0xfed8xxxx). diff --git a/src/soc/amd/common/block/acpimmio/Makefile.inc b/src/soc/amd/common/block/acpimmio/Makefile.inc new file mode 100644 index 0000000..9517b10 --- /dev/null +++ b/src/soc/amd/common/block/acpimmio/Makefile.inc @@ -0,0 +1,6 @@ +bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += mmio_util.c +verstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += mmio_util.c +romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += mmio_util.c +postcar-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += mmio_util.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += mmio_util.c +smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += mmio_util.c diff --git a/src/soc/amd/common/block/acpimmio/mmio_util.c b/src/soc/amd/common/block/acpimmio/mmio_util.c new file mode 100644 index 0000000..2eaaa74 --- /dev/null +++ b/src/soc/amd/common/block/acpimmio/mmio_util.c @@ -0,0 +1,388 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <arch/io.h> +#include <device/mmio.h> +#include <amdblocks/acpimmio_map.h> +#include <amdblocks/acpimmio.h> + +void enable_acpimmio_decode(void) +{ + uint32_t dw; + + dw = pm_io_read32(ACPIMMIO_DECODE_REGISTER); + dw |= ACPIMMIO_DECODE_EN; + pm_io_write32(ACPIMMIO_DECODE_REGISTER, dw); +} + +/* PM registers are accessed a byte at a time via CD6/CD7 */ +uint8_t pm_io_read8(uint8_t reg) +{ + outb(reg, PM_INDEX); + return inb(PM_DATA); +} + +uint16_t pm_io_read16(uint8_t reg) +{ + int i; + uint16_t value = 0; + for (i = sizeof(value) - 1 ; i >= 0 ; i--) + value = (value << 8) | pm_io_read8(reg + i); + return value; +} + +uint32_t pm_io_read32(uint8_t reg) +{ + uint32_t value = pm_io_read16(reg + sizeof(uint16_t)) << 16; + return value | pm_io_read16(reg); +} + +void pm_io_write8(uint8_t reg, uint8_t value) +{ + outb(reg, PM_INDEX); + outb(value, PM_DATA); +} + +void pm_io_write16(uint8_t reg, uint16_t value) +{ + int i; + for (i = 0 ; i < sizeof(value) ; i++) { + pm_io_write8(reg + i, value & 0xff); + value >>= 8; + } +} + +void pm_io_write32(uint8_t reg, uint32_t value) +{ + int i; + for (i = 0 ; i < sizeof(value) ; i++) { + pm_io_write8(reg + i, value & 0xff); + value >>= 8; + } +} + +/* smbus pci read/write - access registers at 0xfed80000 - currently unused */ + +/* smi read/write - access registers at 0xfed80200 */ + +uint8_t smi_read8(uint8_t offset) +{ + return read8((void *)(ACPIMMIO_SMI_BASE + offset)); +} + +uint16_t smi_read16(uint8_t offset) +{ + return read16((void *)(ACPIMMIO_SMI_BASE + offset)); +} + +uint32_t smi_read32(uint8_t offset) +{ + return read32((void *)(ACPIMMIO_SMI_BASE + offset)); +} + +void smi_write8(uint8_t offset, uint8_t value) +{ + write8((void *)(ACPIMMIO_SMI_BASE + offset), value); +} + +void smi_write16(uint8_t offset, uint16_t value) +{ + write16((void *)(ACPIMMIO_SMI_BASE + offset), value); +} + +void smi_write32(uint8_t offset, uint32_t value) +{ + write32((void *)(ACPIMMIO_SMI_BASE + offset), value); +} + +/* pm read/write - access registers at 0xfed80300 */ + +u8 pm_read8(u8 reg) +{ + return read8((void *)(ACPIMMIO_PMIO_BASE + reg)); +} + +u16 pm_read16(u8 reg) +{ + return read16((void *)(ACPIMMIO_PMIO_BASE + reg)); +} + +u32 pm_read32(u8 reg) +{ + return read32((void *)(ACPIMMIO_PMIO_BASE + reg)); +} + +void pm_write8(u8 reg, u8 value) +{ + write8((void *)(ACPIMMIO_PMIO_BASE + reg), value); +} + +void pm_write16(u8 reg, u16 value) +{ + write16((void *)(ACPIMMIO_PMIO_BASE + reg), value); +} + +void pm_write32(u8 reg, u32 value) +{ + write32((void *)(ACPIMMIO_PMIO_BASE + reg), value); +} + +/* pm2 read/write - access registers at 0xfed80400 - currently unused */ + +/* biosram read/write - access registers at 0xfed80500 */ + +uint8_t biosram_read8(uint8_t offset) +{ + return read8((void *)(ACPIMMIO_BIOSRAM_BASE + offset)); +} + +uint16_t biosram_read16(uint8_t offset) /* Must be 1 byte at a time */ +{ + int i; + uint16_t value = 0; + for (i = sizeof(value) - 1 ; i >= 0 ; i--) + value = (value << 8) | biosram_read8(offset + i); + return value; +} + +uint32_t biosram_read32(uint8_t offset) +{ + uint32_t value = biosram_read16(offset + sizeof(uint16_t)) << 16; + return value | biosram_read16(offset); +} + +void biosram_write8(uint8_t offset, uint8_t value) +{ + write8((void *)(ACPIMMIO_BIOSRAM_BASE + offset), value); +} + +void biosram_write16(uint8_t offset, uint16_t value) +{ + int i; + for (i = 0 ; i < sizeof(value) ; i++) { + biosram_write8(offset + i, value & 0xff); + value >>= 8; + } +} + +void biosram_write32(uint8_t offset, uint32_t value) +{ + int i; + for (i = 0 ; i < sizeof(value) ; i++) { + biosram_write8(offset + i, value & 0xff); + value >>= 8; + } +} + +/* cmosram read/write - access registers at 0xfed80600 - currently unused */ + +/* cmos read/write - access registers at 0xfed80700 - currently unused */ + +/* acpi read/write - access registers at 0xfed80800 */ + +u8 acpi_read8(u8 reg) +{ + return read8((void *)(ACPIMMIO_ACPI_BASE + reg)); +} + +u16 acpi_read16(u8 reg) +{ + return read16((void *)(ACPIMMIO_ACPI_BASE + reg)); +} + +u32 acpi_read32(u8 reg) +{ + return read32((void *)(ACPIMMIO_ACPI_BASE + reg)); +} + +void acpi_write8(u8 reg, u8 value) +{ + write8((void *)(ACPIMMIO_ACPI_BASE + reg), value); +} + +void acpi_write16(u8 reg, u16 value) +{ + write16((void *)(ACPIMMIO_ACPI_BASE + reg), value); +} + +void acpi_write32(u8 reg, u32 value) +{ + write32((void *)(ACPIMMIO_ACPI_BASE + reg), value); +} + +/* asf read/write - access registers at 0xfed80900 - not currently used */ + +u8 asf_read8(u8 reg) +{ + return read8((void *)(ACPIMMIO_ASF_BASE + reg)); +} + +u16 asf_read16(u8 reg) +{ + return read16((void *)(ACPIMMIO_ASF_BASE + reg)); +} + +void asf_write8(u8 reg, u8 value) +{ + write8((void *)(ACPIMMIO_ASF_BASE + reg), value); +} + +void asf_write16(u8 reg, u16 value) +{ + write16((void *)(ACPIMMIO_ASF_BASE + reg), value); +} + +/* smbus read/write - access registers at 0xfed80a00 and ASF at 0xfed80900 */ + +u8 smbus_read8(u8 reg) +{ + return read8((void *)(ACPIMMIO_SMBUS_BASE + reg)); +} + +u16 smbus_read16(u8 reg) +{ + return read16((void *)(ACPIMMIO_SMBUS_BASE + reg)); +} + +void smbus_write8(u8 reg, u8 value) +{ + write8((void *)(ACPIMMIO_SMBUS_BASE + reg), value); +} + +void smbus_write16(u8 reg, u16 value) +{ + write16((void *)(ACPIMMIO_SMBUS_BASE + reg), value); +} + +/* wdt read/write - access registers at 0xfed80b00 - not currently used */ + +/* hpet read/write - access registers at 0xfed80c00 - not currently used */ + +/* iomux read/write - access registers at 0xfed80d00 */ + +u8 iomux_read8(u8 reg) +{ + return read8((void *)(ACPIMMIO_IOMUX_BASE + reg)); +} + +u16 iomux_read16(u8 reg) +{ + return read16((void *)(ACPIMMIO_IOMUX_BASE + reg)); +} + +u32 iomux_read32(u8 reg) +{ + return read32((void *)(ACPIMMIO_IOMUX_BASE + reg)); +} + +void iomux_write8(u8 reg, u8 value) +{ + write8((void *)(ACPIMMIO_IOMUX_BASE + reg), value); +} + +void iomux_write16(u8 reg, u16 value) +{ + write16((void *)(ACPIMMIO_IOMUX_BASE + reg), value); +} + +void iomux_write32(u8 reg, u32 value) +{ + write32((void *)(ACPIMMIO_IOMUX_BASE + reg), value); +} + +/* misc read/write - access registers at 0xfed80e00 */ + +u8 misc_read8(u8 reg) +{ + return read8((void *)(ACPIMMIO_MISC_BASE + reg)); +} + +u16 misc_read16(u8 reg) +{ + return read16((void *)(ACPIMMIO_MISC_BASE + reg)); +} + +u32 misc_read32(u8 reg) +{ + return read32((void *)(ACPIMMIO_MISC_BASE + reg)); +} + +void misc_write8(u8 reg, u8 value) +{ + write8((void *)(ACPIMMIO_MISC_BASE + reg), value); +} + +void misc_write16(u8 reg, u16 value) +{ + write16((void *)(ACPIMMIO_MISC_BASE + reg), value); +} + +void misc_write32(u8 reg, u32 value) +{ + write32((void *)(ACPIMMIO_MISC_BASE + reg), value); +} + +/* dpvga read/write - access registers at 0xfed81400 - not currently used */ + +/* gpio bk 0 read/write - access registers at 0xfed81500 - not currently used */ +/* gpio bk 1 read/write - access registers at 0xfed81600 - not currently used */ +/* gpio bk 2 read/write - access registers at 0xfed81700 - not currently used */ + +/* xhci_pm read/write - access registers at 0xfed81c00 */ + +uint8_t xhci_pm_read8(uint8_t reg) +{ + return read8((void *)(ACPIMMIO_XHCIPM_BASE + reg)); +} + +uint16_t xhci_pm_read16(uint8_t reg) +{ + return read16((void *)(ACPIMMIO_XHCIPM_BASE + reg)); +} + +uint32_t xhci_pm_read32(uint8_t reg) +{ + return read32((void *)(ACPIMMIO_XHCIPM_BASE + reg)); +} + +void xhci_pm_write8(uint8_t reg, uint8_t value) +{ + write8((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); +} + +void xhci_pm_write16(uint8_t reg, uint16_t value) +{ + write16((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); +} + +void xhci_pm_write32(uint8_t reg, uint32_t value) +{ + write32((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); +} + +/* acdc_tmr read/write - access registers at 0xfed81d00 */ + +/* aoac read/write - access registers at 0xfed81e00 - not currently used */ + +u8 aoac_read8(u8 reg) +{ + return read8((void *)(ACPIMMIO_AOAC_BASE + reg)); +} + +void aoac_write8(u8 reg, u8 value) +{ + write8((void *)(ACPIMMIO_AOAC_BASE + reg), value); +} diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h new file mode 100644 index 0000000..e1cf7cb --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -0,0 +1,101 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AMDBLOCKS_ACPIMMIO_H__ +#define __AMDBLOCKS_ACPIMMIO_H__ + +void enable_acpimmio_decode(void); +uint8_t pm_io_read8(uint8_t reg); +uint16_t pm_io_read16(uint8_t reg); +uint32_t pm_io_read32(uint8_t reg); +void pm_io_write8(uint8_t reg, uint8_t value); +void pm_io_write16(uint8_t reg, uint16_t value); +void pm_io_write32(uint8_t reg, uint32_t value); +uint8_t smi_read8(uint8_t offset); +uint16_t smi_read16(uint8_t offset); +uint32_t smi_read32(uint8_t offset); +void smi_write8(uint8_t offset, uint8_t value); +void smi_write16(uint8_t offset, uint16_t value); +void smi_write32(uint8_t offset, uint32_t value); +uint8_t pm_read8(uint8_t reg); +uint16_t pm_read16(uint8_t reg); +uint32_t pm_read32(uint8_t reg); +void pm_write8(uint8_t reg, uint8_t value); +void pm_write16(uint8_t reg, uint16_t value); +void pm_write32(uint8_t reg, uint32_t value); +uint8_t pm2_read8(uint8_t reg); +uint16_t pm2_read16(uint8_t reg); +uint32_t pm2_read32(uint8_t reg); +void pm2_write8(uint8_t reg, uint8_t value); +void pm2_write16(uint8_t reg, uint16_t value); +void pm2_write32(uint8_t reg, uint32_t value); +uint8_t biosram_read8(uint8_t offset); +void biosram_write8(uint8_t offset, uint8_t value); +uint16_t biosram_read16(uint8_t offset); +uint32_t biosram_read32(uint8_t offset); +void biosram_write16(uint8_t offset, uint16_t value); +void biosram_write32(uint8_t offset, uint32_t value); +uint8_t acpi_read8(uint8_t reg); +uint16_t acpi_read16(uint8_t reg); +uint32_t acpi_read32(uint8_t reg); +void acpi_write8(uint8_t reg, uint8_t value); +void acpi_write16(uint8_t reg, uint16_t value); +void acpi_write32(uint8_t reg, uint32_t value); +uint8_t asf_read8(uint8_t reg); +uint16_t asf_read16(uint8_t reg); +uint32_t asf_read32(uint8_t reg); +void asf_write8(uint8_t reg, uint8_t value); +void asf_write16(uint8_t reg, uint16_t value); +void asf_write32(uint8_t reg, uint32_t value); +uint8_t smbus_read8(uint8_t reg); +uint16_t smbus_read16(uint8_t reg); +void smbus_write8(uint8_t reg, uint8_t value); +void smbus_write16(uint8_t reg, uint16_t value); +uint8_t wdt_read8(uint8_t reg); +uint16_t wdt_read16(uint8_t reg); +uint32_t wdt_read32(uint8_t reg); +void wdt_write8(uint8_t reg, uint8_t value); +void wdt_write16(uint8_t reg, uint16_t value); +void wdt_write32(uint8_t reg, uint32_t value); +uint8_t hpet_read8(uint8_t reg); +uint16_t hpet_read16(uint8_t reg); +uint32_t hpet_read32(uint8_t reg); +void hpet_write8(uint8_t reg, uint8_t value); +void hpet_write16(uint8_t reg, uint16_t value); +void hpet_write32(uint8_t reg, uint32_t value); +uint8_t iomux_read8(uint8_t reg); +uint16_t iomux_read16(uint8_t reg); +uint32_t iomux_read32(uint8_t reg); +void iomux_write8(uint8_t reg, uint8_t value); +void iomux_write16(uint8_t reg, uint16_t value); +void iomux_write32(uint8_t reg, uint32_t value); +uint8_t misc_read8(uint8_t reg); +uint16_t misc_read16(uint8_t reg); +uint32_t misc_read32(uint8_t reg); +void misc_write8(uint8_t reg, uint8_t value); +void misc_write16(uint8_t reg, uint16_t value); +void misc_write32(uint8_t reg, uint32_t value); +uint8_t xhci_pm_read8(uint8_t reg); +uint16_t xhci_pm_read16(uint8_t reg); +uint32_t xhci_pm_read32(uint8_t reg); +void xhci_pm_write8(uint8_t reg, uint8_t value); +void xhci_pm_write16(uint8_t reg, uint16_t value); +void xhci_pm_write32(uint8_t reg, uint32_t value); +uint8_t aoac_read8(uint8_t reg); +void aoac_write8(uint8_t reg, uint8_t value); + +#endif /* __AMDBLOCKS_ACPIMMIO_H__ */ diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h new file mode 100644 index 0000000..755af52 --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AMDBLOCKS_ACPIMMIO_MAP_H__ +#define __AMDBLOCKS_ACPIMMIO_MAP_H__ + +/* IO index/data for accessing PMIO prior to enabling MMIO decode */ +#define PM_INDEX 0xcd6 +#define PM_DATA 0xcd7 + +/* TODO: In the event this is ported backward far enough, earlier devices + * enable the decode in PMx24 instead. All discrete FCHs and the Kabini + * SoC fall into this category. Kabini's successor, Mullins, uses this + * newer method. + */ +#define ACPIMMIO_DECODE_REGISTER 0x4 +#define ACPIMMIO_DECODE_EN BIT(0) + +/* MMIO register blocks are at fixed offsets from 0xfed80000 and are enabled + * in PMx24[1] (older implementations) and PMx04[1] (newer implementations). + * PM registers are also accessible via IO CD6/CD7. + * + * All products do not support all blocks below, however AMD has avoided + * redefining addresses and consumes new ranges as necessary. + * + * Definitions within each block are not guaranteed to remain consistent + * across family/model products. + */ + +#define AMD_SB_ACPI_MMIO_ADDR 0xfed80000 +#define ACPIMMIO_SM_PCI_BASE 0xfed80000 +#define ACPIMMIO_SMI_BASE 0xfed80200 +#define ACPIMMIO_PMIO_BASE 0xfed80300 +#define ACPIMMIO_PMIO2_BASE 0xfed80400 +#define ACPIMMIO_BIOSRAM_BASE 0xfed80500 +#define ACPIMMIO_CMOSRAM_BASE 0xfed80600 +#define ACPIMMIO_CMOS_BASE 0xfed80700 +#define ACPIMMIO_ACPI_BASE 0xfed80800 +#define ACPIMMIO_ASF_BASE 0xfed80900 +#define ACPIMMIO_SMBUS_BASE 0xfed80a00 +#define ACPIMMIO_WDT_BASE 0xfed80b00 +#define ACPIMMIO_HPET_BASE 0xfed80c00 +#define ACPIMMIO_IOMUX_BASE 0xfed80d00 +#define ACPIMMIO_MISC_BASE 0xfed80e00 +#define ACPIMMIO_DPVGA_BASE 0xfed81400 +#define ACPIMMIO_GPIO0_BASE 0xfed81500 +#define ACPIMMIO_GPIO1_BASE 0xfed81600 +#define ACPIMMIO_GPIO2_BASE 0xfed81700 +#define ACPIMMIO_XHCIPM_BASE 0xfed81c00 +#define ACPIMMIO_ACDCTMR_BASE 0xfed81d00 +#define ACPIMMIO_AOAC_BASE 0xfed81e00 + +#endif /* __AMDBLOCKS_ACPIMMIO_MAP_H__ */ diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 29ab149..d4e1feb 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -46,6 +46,7 @@ select SOC_AMD_PI select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK + select SOC_AMD_COMMON_BLOCK_ACPIMMIO select SOC_AMD_COMMON_BLOCK_PCI select SOC_AMD_COMMON_BLOCK_PI select SOC_AMD_COMMON_BLOCK_PSP diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index 227fb70..4f11ea2 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -28,6 +28,7 @@ #include <cbmem.h> #include <device/device.h> #include <device/pci.h> +#include <amdblocks/acpimmio.h> #include <soc/acpi.h> #include <soc/pci_devs.h> #include <soc/southbridge.h> diff --git a/src/soc/amd/stoneyridge/gpio.c b/src/soc/amd/stoneyridge/gpio.c index 285fedd..01ced08 100644 --- a/src/soc/amd/stoneyridge/gpio.c +++ b/src/soc/amd/stoneyridge/gpio.c @@ -16,13 +16,15 @@ */ #include <device/mmio.h> +#include <device/device.h> #include <console/console.h> #include <delay.h> #include <gpio.h> +#include <amdblocks/acpimmio.h> #include <soc/gpio.h> #include <soc/pci_devs.h> -#include <soc/southbridge.h> #include <assert.h> +#include "chip.h" static const struct soc_amd_event gpio_event_table[] = { { GPIO_1, GEVENT_19 }, diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h index e6327dc..7762043 100644 --- a/src/soc/amd/stoneyridge/include/soc/iomap.h +++ b/src/soc/amd/stoneyridge/include/soc/iomap.h @@ -22,6 +22,9 @@ #define SPI_BASE_ADDRESS 0xfec10000 #define IO_APIC2_ADDR 0xfec20000 +/* AcpiMmio blocks are at fixed offsets from FED8_0000h, enabled in PMx04[1] */ +#include <amdblocks/acpimmio_map.h> + /* I2C fixed address */ #define I2C_BASE_ADDRESS 0xfedc2000 #define I2C_DEVICE_SIZE 0x00001000 @@ -32,30 +35,6 @@ #endif #define HPET_BASE_ADDRESS 0xfed00000 -/* AcpiMmio blocks are at fixed offsets from FED8_0000h, enabled in PMx04[1] */ -#define AMD_SB_ACPI_MMIO_ADDR 0xfed80000 -#define ACPIMMIO_SM_PCI_BASE 0xfed80000 -#define ACPIMMIO_SMI_BASE 0xfed80200 -#define ACPIMMIO_PMIO_BASE 0xfed80300 -#define ACPIMMIO_PMIO2_BASE 0xfed80400 -#define ACPIMMIO_BIOSRAM_BASE 0xfed80500 -#define ACPIMMIO_CMOSRAM_BASE 0xfed80600 -#define ACPIMMIO_CMOS_BASE 0xfed80700 -#define ACPIMMIO_ACPI_BASE 0xfed80800 -#define ACPIMMIO_ASF_BASE 0xfed80900 -#define ACPIMMIO_SMBUS_BASE 0xfed80a00 -#define ACPIMMIO_WDT_BASE 0xfed80b00 -#define ACPIMMIO_HPET_BASE 0xfed80c00 -#define ACPIMMIO_IOMUX_BASE 0xfed80d00 -#define ACPIMMIO_MISC_BASE 0xfed80e00 -#define ACPIMMIO_DPVGA_BASE 0xfed81400 -#define ACPIMMIO_GPIO0_BASE 0xfed81500 -#define ACPIMMIO_GPIO1_BASE 0xfed81600 -#define ACPIMMIO_GPIO2_BASE 0xfed81700 -#define ACPIMMIO_XHCIPM_BASE 0xfed81c00 -#define ACPIMMIO_ACDCTMR_BASE 0xfed81d00 -#define ACPIMMIO_AOAC_BASE 0xfed81e00 - #define APU_UART0_BASE 0xfedc6000 #define APU_UART1_BASE 0xfedc8000 @@ -78,8 +57,6 @@ #define PM2_DATA 0xcd1 #define BIOSRAM_INDEX 0xcd4 #define BIOSRAM_DATA 0xcd5 -#define PM_INDEX 0xcd6 -#define PM_DATA 0xcd7 #define AB_INDX 0xcd8 #define AB_DATA (AB_INDX+4) #define SYS_RESET 0xcf9 diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 618a5de..6734efb 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -483,7 +483,6 @@ void southbridge_init(void *chip_info); void sb_lpc_port80(void); void sb_lpc_decode(void); -void sb_acpi_mmio_decode(void); void sb_pci_port80(void); void sb_read_mode(u32 mode); void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm); @@ -491,66 +490,8 @@ void sb_tpm_decode_spi(void); void lpc_wideio_512_window(uint16_t base); void lpc_wideio_16_window(uint16_t base); -uint8_t pm_io_read8(uint8_t reg); -uint16_t pm_io_read16(uint8_t reg); -uint32_t pm_io_read32(uint8_t reg); -void pm_io_write8(uint8_t reg, uint8_t value); -void pm_io_write16(uint8_t reg, uint16_t value); -void pm_io_write32(uint8_t reg, uint32_t value); -u8 pm_read8(u8 reg); -u16 pm_read16(u8 reg); -u32 pm_read32(u8 reg); -void pm_write8(u8 reg, u8 value); -void pm_write16(u8 reg, u16 value); -void pm_write32(u8 reg, u32 value); -u8 acpi_read8(u8 reg); -u16 acpi_read16(u8 reg); -u32 acpi_read32(u8 reg); -void acpi_write8(u8 reg, u8 value); -void acpi_write16(u8 reg, u16 value); -void acpi_write32(u8 reg, u32 value); -u8 misc_read8(u8 reg); -u16 misc_read16(u8 reg); -u32 misc_read32(u8 reg); -void misc_write8(u8 reg, u8 value); -void misc_write16(u8 reg, u16 value); -void misc_write32(u8 reg, u32 value); -uint8_t smi_read8(uint8_t offset); -uint16_t smi_read16(uint8_t offset); -uint32_t smi_read32(uint8_t offset); -void smi_write8(uint8_t offset, uint8_t value); -void smi_write16(uint8_t offset, uint16_t value); -void smi_write32(uint8_t offset, uint32_t value); -uint8_t biosram_read8(uint8_t offset); -void biosram_write8(uint8_t offset, uint8_t value); -uint16_t biosram_read16(uint8_t offset); -void biosram_write16(uint8_t offset, uint16_t value); -uint32_t biosram_read32(uint8_t offset); -void biosram_write32(uint8_t offset, uint32_t value); uint16_t pm_acpi_pm_cnt_blk(void); uint16_t pm_acpi_pm_evt_blk(void); -void xhci_pm_write8(uint8_t reg, uint8_t value); -uint8_t xhci_pm_read8(uint8_t reg); -void xhci_pm_write16(uint8_t reg, uint16_t value); -uint16_t xhci_pm_read16(uint8_t reg); -void xhci_pm_write32(uint8_t reg, uint32_t value); -uint32_t xhci_pm_read32(uint8_t reg); -u8 iomux_read8(u8 reg); -u16 iomux_read16(u8 reg); -u32 iomux_read32(u8 reg); -void iomux_write8(u8 reg, u8 value); -void iomux_write16(u8 reg, u16 value); -void iomux_write32(u8 reg, u32 value); -uint8_t asf_read8(uint8_t offset); -uint16_t asf_read16(uint8_t offset); -void asf_write8(uint8_t offset, uint8_t value); -void asf_write16(uint8_t offset, uint16_t value); -uint8_t smbus_read8(uint8_t offset); -uint16_t smbus_read16(uint8_t offset); -void smbus_write8(uint8_t offset, uint8_t value); -void smbus_write16(uint8_t offset, uint16_t value); -uint8_t aoac_read8(uint8_t reg); -void aoac_write8(uint8_t reg, uint8_t value); void bootblock_fch_early_init(void); void bootblock_fch_init(void); /** diff --git a/src/soc/amd/stoneyridge/lpc.c b/src/soc/amd/stoneyridge/lpc.c index a838146..3ace1fd 100644 --- a/src/soc/amd/stoneyridge/lpc.c +++ b/src/soc/amd/stoneyridge/lpc.c @@ -27,6 +27,7 @@ #include <arch/ioapic.h> #include <pc80/i8254.h> #include <pc80/i8259.h> +#include <amdblocks/acpimmio.h> #include <soc/acpi.h> #include <soc/pci_devs.h> #include <soc/southbridge.h> diff --git a/src/soc/amd/stoneyridge/pmutil.c b/src/soc/amd/stoneyridge/pmutil.c index bfb5f42..7367251 100644 --- a/src/soc/amd/stoneyridge/pmutil.c +++ b/src/soc/amd/stoneyridge/pmutil.c @@ -15,6 +15,7 @@ #include <arch/acpi.h> #include <soc/southbridge.h> +#include <amdblocks/acpimmio.h> #include <security/vboot/vboot_common.h> #include <security/vboot/vbnv.h> #include <pc80/mc146818rtc.h> diff --git a/src/soc/amd/stoneyridge/ramtop.c b/src/soc/amd/stoneyridge/ramtop.c index f43fcf3..7c855bb 100644 --- a/src/soc/amd/stoneyridge/ramtop.c +++ b/src/soc/amd/stoneyridge/ramtop.c @@ -25,7 +25,8 @@ #include <stage_cache.h> #include <arch/bert_storage.h> #include <soc/northbridge.h> -#include <soc/southbridge.h> +#include <soc/iomap.h> +#include <amdblocks/acpimmio.h> void backup_top_of_low_cacheable(uintptr_t ramtop) { diff --git a/src/soc/amd/stoneyridge/reset.c b/src/soc/amd/stoneyridge/reset.c index 34aa576..ec5ee91 100644 --- a/src/soc/amd/stoneyridge/reset.c +++ b/src/soc/amd/stoneyridge/reset.c @@ -20,6 +20,7 @@ #include <soc/pci_devs.h> #include <device/pci_ops.h> #include <soc/southbridge.h> +#include <amdblocks/acpimmio.h> #include <amdblocks/reset.h> void set_warm_reset_flag(void) diff --git a/src/soc/amd/stoneyridge/sb_util.c b/src/soc/amd/stoneyridge/sb_util.c index 8781617..11bf73a 100644 --- a/src/soc/amd/stoneyridge/sb_util.c +++ b/src/soc/amd/stoneyridge/sb_util.c @@ -16,367 +16,9 @@ #include <arch/io.h> #include <device/mmio.h> #include <arch/acpi.h> +#include <amdblocks/acpimmio.h> #include <soc/southbridge.h> -/* PM registers are accessed a byte at a time via CD6/CD7 */ -uint8_t pm_io_read8(uint8_t reg) -{ - outb(reg, PM_INDEX); - return inb(PM_DATA); -} - -uint16_t pm_io_read16(uint8_t reg) -{ - int i; - uint16_t value = 0; - for (i = sizeof(value) - 1 ; i >= 0 ; i--) - value = (value << 8) | pm_io_read8(reg + i); - return value; -} - -uint32_t pm_io_read32(uint8_t reg) -{ - uint32_t value = pm_io_read16(reg + sizeof(uint16_t)) << 16; - return value | pm_io_read16(reg); -} - -void pm_io_write8(uint8_t reg, uint8_t value) -{ - outb(reg, PM_INDEX); - outb(value, PM_DATA); -} - -void pm_io_write16(uint8_t reg, uint16_t value) -{ - int i; - for (i = 0 ; i < sizeof(value) ; i++) { - pm_io_write8(reg + i, value & 0xff); - value >>= 8; - } -} - -void pm_io_write32(uint8_t reg, uint32_t value) -{ - int i; - for (i = 0 ; i < sizeof(value) ; i++) { - pm_io_write8(reg + i, value & 0xff); - value >>= 8; - } -} - -/* smbus pci read/write - access registers at 0xfed80000 - currently unused */ - -/* smi read/write - access registers at 0xfed80200 */ - -uint8_t smi_read8(uint8_t offset) -{ - return read8((void *)(ACPIMMIO_SMI_BASE + offset)); -} - -uint16_t smi_read16(uint8_t offset) -{ - return read16((void *)(ACPIMMIO_SMI_BASE + offset)); -} - -uint32_t smi_read32(uint8_t offset) -{ - return read32((void *)(ACPIMMIO_SMI_BASE + offset)); -} - -void smi_write8(uint8_t offset, uint8_t value) -{ - write8((void *)(ACPIMMIO_SMI_BASE + offset), value); -} - -void smi_write16(uint8_t offset, uint16_t value) -{ - write16((void *)(ACPIMMIO_SMI_BASE + offset), value); -} - -void smi_write32(uint8_t offset, uint32_t value) -{ - write32((void *)(ACPIMMIO_SMI_BASE + offset), value); -} - -/* pm read/write - access registers at 0xfed80300 */ - -u8 pm_read8(u8 reg) -{ - return read8((void *)(ACPIMMIO_PMIO_BASE + reg)); -} - -u16 pm_read16(u8 reg) -{ - return read16((void *)(ACPIMMIO_PMIO_BASE + reg)); -} - -u32 pm_read32(u8 reg) -{ - return read32((void *)(ACPIMMIO_PMIO_BASE + reg)); -} - -void pm_write8(u8 reg, u8 value) -{ - write8((void *)(ACPIMMIO_PMIO_BASE + reg), value); -} - -void pm_write16(u8 reg, u16 value) -{ - write16((void *)(ACPIMMIO_PMIO_BASE + reg), value); -} - -void pm_write32(u8 reg, u32 value) -{ - write32((void *)(ACPIMMIO_PMIO_BASE + reg), value); -} - -/* pm2 read/write - access registers at 0xfed80400 - currently unused */ - -/* biosram read/write - access registers at 0xfed80500 */ - -uint8_t biosram_read8(uint8_t offset) -{ - return read8((void *)(ACPIMMIO_BIOSRAM_BASE + offset)); -} - -uint16_t biosram_read16(uint8_t offset) /* Must be 1 byte at a time */ -{ - int i; - uint16_t value = 0; - for (i = sizeof(value) - 1 ; i >= 0 ; i--) - value = (value << 8) | biosram_read8(offset + i); - return value; -} - -uint32_t biosram_read32(uint8_t offset) -{ - uint32_t value = biosram_read16(offset + sizeof(uint16_t)) << 16; - return value | biosram_read16(offset); -} - -void biosram_write8(uint8_t offset, uint8_t value) -{ - write8((void *)(ACPIMMIO_BIOSRAM_BASE + offset), value); -} - -void biosram_write16(uint8_t offset, uint16_t value) -{ - int i; - for (i = 0 ; i < sizeof(value) ; i++) { - biosram_write8(offset + i, value & 0xff); - value >>= 8; - } -} - -void biosram_write32(uint8_t offset, uint32_t value) -{ - int i; - for (i = 0 ; i < sizeof(value) ; i++) { - biosram_write8(offset + i, value & 0xff); - value >>= 8; - } -} - -/* cmosram read/write - access registers at 0xfed80600 - currently unused */ - -/* cmos read/write - access registers at 0xfed80700 - currently unused */ - -/* acpi read/write - access registers at 0xfed80800 */ - -u8 acpi_read8(u8 reg) -{ - return read8((void *)(ACPIMMIO_ACPI_BASE + reg)); -} - -u16 acpi_read16(u8 reg) -{ - return read16((void *)(ACPIMMIO_ACPI_BASE + reg)); -} - -u32 acpi_read32(u8 reg) -{ - return read32((void *)(ACPIMMIO_ACPI_BASE + reg)); -} - -void acpi_write8(u8 reg, u8 value) -{ - write8((void *)(ACPIMMIO_ACPI_BASE + reg), value); -} - -void acpi_write16(u8 reg, u16 value) -{ - write16((void *)(ACPIMMIO_ACPI_BASE + reg), value); -} - -void acpi_write32(u8 reg, u32 value) -{ - write32((void *)(ACPIMMIO_ACPI_BASE + reg), value); -} - -/* asf read/write - access registers at 0xfed80900 - not currently used */ - -u8 asf_read8(u8 reg) -{ - return read8((void *)(ACPIMMIO_ASF_BASE + reg)); -} - -u16 asf_read16(u8 reg) -{ - return read16((void *)(ACPIMMIO_ASF_BASE + reg)); -} - -void asf_write8(u8 reg, u8 value) -{ - write8((void *)(ACPIMMIO_ASF_BASE + reg), value); -} - -void asf_write16(u8 reg, u16 value) -{ - write16((void *)(ACPIMMIO_ASF_BASE + reg), value); -} - -/* smbus read/write - access registers at 0xfed80a00 and ASF at 0xfed80900 */ - -u8 smbus_read8(u8 reg) -{ - return read8((void *)(ACPIMMIO_SMBUS_BASE + reg)); -} - -u16 smbus_read16(u8 reg) -{ - return read16((void *)(ACPIMMIO_SMBUS_BASE + reg)); -} - -void smbus_write8(u8 reg, u8 value) -{ - write8((void *)(ACPIMMIO_SMBUS_BASE + reg), value); -} - -void smbus_write16(u8 reg, u16 value) -{ - write16((void *)(ACPIMMIO_SMBUS_BASE + reg), value); -} - -/* wdt read/write - access registers at 0xfed80b00 - not currently used */ - -/* hpet read/write - access registers at 0xfed80c00 - not currently used */ - -/* iomux read/write - access registers at 0xfed80d00 */ - -u8 iomux_read8(u8 reg) -{ - return read8((void *)(ACPIMMIO_IOMUX_BASE + reg)); -} - -u16 iomux_read16(u8 reg) -{ - return read16((void *)(ACPIMMIO_IOMUX_BASE + reg)); -} - -u32 iomux_read32(u8 reg) -{ - return read32((void *)(ACPIMMIO_IOMUX_BASE + reg)); -} - -void iomux_write8(u8 reg, u8 value) -{ - write8((void *)(ACPIMMIO_IOMUX_BASE + reg), value); -} - -void iomux_write16(u8 reg, u16 value) -{ - write16((void *)(ACPIMMIO_IOMUX_BASE + reg), value); -} - -void iomux_write32(u8 reg, u32 value) -{ - write32((void *)(ACPIMMIO_IOMUX_BASE + reg), value); -} - -/* misc read/write - access registers at 0xfed80e00 */ - -u8 misc_read8(u8 reg) -{ - return read8((void *)(ACPIMMIO_MISC_BASE + reg)); -} - -u16 misc_read16(u8 reg) -{ - return read16((void *)(ACPIMMIO_MISC_BASE + reg)); -} - -u32 misc_read32(u8 reg) -{ - return read32((void *)(ACPIMMIO_MISC_BASE + reg)); -} - -void misc_write8(u8 reg, u8 value) -{ - write8((void *)(ACPIMMIO_MISC_BASE + reg), value); -} - -void misc_write16(u8 reg, u16 value) -{ - write16((void *)(ACPIMMIO_MISC_BASE + reg), value); -} - -void misc_write32(u8 reg, u32 value) -{ - write32((void *)(ACPIMMIO_MISC_BASE + reg), value); -} - -/* dpvga read/write - access registers at 0xfed81400 - not currently used */ - -/* gpio bk 0 read/write - access registers at 0xfed81500 - not currently used */ -/* gpio bk 1 read/write - access registers at 0xfed81600 - not currently used */ -/* gpio bk 2 read/write - access registers at 0xfed81700 - not currently used */ - -/* xhci_pm read/write - access registers at 0xfed81c00 */ - -uint8_t xhci_pm_read8(uint8_t reg) -{ - return read8((void *)(ACPIMMIO_XHCIPM_BASE + reg)); -} - -uint16_t xhci_pm_read16(uint8_t reg) -{ - return read16((void *)(ACPIMMIO_XHCIPM_BASE + reg)); -} - -uint32_t xhci_pm_read32(uint8_t reg) -{ - return read32((void *)(ACPIMMIO_XHCIPM_BASE + reg)); -} - -void xhci_pm_write8(uint8_t reg, uint8_t value) -{ - write8((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); -} - -void xhci_pm_write16(uint8_t reg, uint16_t value) -{ - write16((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); -} - -void xhci_pm_write32(uint8_t reg, uint32_t value) -{ - write32((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); -} - -/* acdc_tmr read/write - access registers at 0xfed81d00 */ - -/* aoac read/write - access registers at 0xfed81e00 - not currently used */ - -u8 aoac_read8(u8 reg) -{ - return read8((void *)(ACPIMMIO_AOAC_BASE + reg)); -} - -void aoac_write8(u8 reg, u8 value) -{ - write8((void *)(ACPIMMIO_AOAC_BASE + reg), value); -} - uint16_t pm_acpi_pm_cnt_blk(void) { return pm_read16(PM1_CNT_BLK); diff --git a/src/soc/amd/stoneyridge/smbus.c b/src/soc/amd/stoneyridge/smbus.c index 6285d79..df7a86e 100644 --- a/src/soc/amd/stoneyridge/smbus.c +++ b/src/soc/amd/stoneyridge/smbus.c @@ -16,6 +16,7 @@ #include <arch/io.h> #include <stdint.h> #include <console/console.h> +#include <amdblocks/acpimmio.h> #include <soc/smbus.h> #include <soc/southbridge.h> diff --git a/src/soc/amd/stoneyridge/smi.c b/src/soc/amd/stoneyridge/smi.c index 5ddc0dd..4a0d833 100644 --- a/src/soc/amd/stoneyridge/smi.c +++ b/src/soc/amd/stoneyridge/smi.c @@ -19,6 +19,7 @@ */ #include <console/console.h> +#include <amdblocks/acpimmio.h> #include <soc/southbridge.h> #include <soc/smi.h> diff --git a/src/soc/amd/stoneyridge/smi_util.c b/src/soc/amd/stoneyridge/smi_util.c index 91b86e2..8759e2a 100644 --- a/src/soc/amd/stoneyridge/smi_util.c +++ b/src/soc/amd/stoneyridge/smi_util.c @@ -21,6 +21,7 @@ #include <console/console.h> #include <soc/southbridge.h> #include <soc/smi.h> +#include <amdblocks/acpimmio.h> void configure_smi(uint8_t smi_num, uint8_t mode) { diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c index c3f4b67..c3aed57 100644 --- a/src/soc/amd/stoneyridge/smihandler.c +++ b/src/soc/amd/stoneyridge/smihandler.c @@ -24,6 +24,7 @@ #include <device/pci_def.h> #include <soc/smi.h> #include <soc/southbridge.h> +#include <amdblocks/acpimmio.h> #include <elog.h> /* bits in smm_io_trap */ diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 8dfef8b..440f889 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -28,6 +28,7 @@ #include <amdblocks/amd_pci_util.h> #include <amdblocks/agesawrapper.h> #include <amdblocks/reset.h> +#include <amdblocks/acpimmio.h> #include <soc/southbridge.h> #include <soc/smbus.h> #include <soc/smi.h> @@ -360,16 +361,6 @@ pci_write_config32(SOC_LPC_DEV, LPC_IO_PORT_DECODE_ENABLE, tmp); } -void sb_acpi_mmio_decode(void) -{ - uint8_t byte; - - /* Enable ACPI MMIO range 0xfed80000 - 0xfed81fff */ - byte = pm_io_read8(PM_ISA_CONTROL); - byte |= MMIO_EN; - pm_io_write8(PM_ISA_CONTROL, byte); -} - static void sb_enable_cf9_io(void) { uint32_t reg = pm_read32(PM_DECODE_EN); @@ -643,7 +634,7 @@ sb_lpc_early_setup(); sb_spibase(); sb_disable_4dw_burst(); /* Must be disabled on CZ(ST) */ - sb_acpi_mmio_decode(); + enable_acpimmio_decode(); fch_smbus_init(); sb_enable_cf9_io(); setup_spread_spectrum(&reboot); diff --git a/src/soc/amd/stoneyridge/usb.c b/src/soc/amd/stoneyridge/usb.c index f2fa3ba..00f8237 100644 --- a/src/soc/amd/stoneyridge/usb.c +++ b/src/soc/amd/stoneyridge/usb.c @@ -22,7 +22,7 @@ #include <soc/acpi.h> #include <soc/pci_devs.h> #include <soc/southbridge.h> - +#include <amdblocks/acpimmio.h> static void set_usb_over_current(struct device *dev) { -- To view, visit https://review.coreboot.org/c/coreboot/+/32649 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I083b6339cd29e72289e63c9331a815c46d71600d Gerrit-Change-Number: 32649 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-MessageType: newchange

5 19

Change in ...coreboot[master]: coreboot: add post code for memory error from FSP
by Keith Short (Code Review) 22 May '19

22 May '19

Keith Short has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32773 Change subject: coreboot: add post code for memory error from FSP ...................................................................... coreboot: add post code for memory error from FSP Add a new post code POST_RAM_FAILURE, used when the Intel FSP code fails to initialize RAM. BUG=b:124401932 BRANCH=sarien TEST=build coreboot for sarien and arcada platforms Change-Id: Ibafefa0fc0b1c525f923929cc91731fbcc1e7533 Signed-off-by: Keith Short <keithshort(a)chromium.org> --- M src/drivers/intel/fsp1_1/raminit.c M src/drivers/intel/fsp2_0/memory_init.c M src/include/console/post_codes.h 3 files changed, 19 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/32773/1 diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index 726cc26..e91e49e 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -129,8 +129,10 @@ timestamp_add_now(TS_FSP_MEMORY_INIT_END); printk(BIOS_DEBUG, "FspMemoryInit returned 0x%08x\n", status); - if (status != EFI_SUCCESS) + if (status != EFI_SUCCESS) { + post_code(POST_RAM_FAILURE); die("ERROR - FspMemoryInit failed to initialize memory!\n"); + } /* Locate the FSP reserved memory area */ fsp_reserved_bytes = 0; @@ -195,8 +197,10 @@ } #if CONFIG(DISPLAY_HOBS) - if (hob_list_ptr == NULL) + if (hob_list_ptr == NULL) { + post_code(POST_INVALID_FSP); die("ERROR - HOB pointer is NULL!\n"); + } /* * Verify that FSP is generating the required HOBs: @@ -274,14 +278,17 @@ printk(BIOS_DEBUG, "0x%08x: Chipset reserved bytes reported by FSP\n", (unsigned int)delta_bytes); + post_code(POST_INVALID_FSP); die("Please verify the chipset reserved size\n"); } #endif } /* Verify the FSP 1.1 HOB interface */ - if (fsp_verification_failure) + if (fsp_verification_failure) { + post_code(POST_INVALID_FSP); die("ERROR - coreboot's requirements not met by FSP binary!\n"); + } /* Display the memory configuration */ report_memory_config(); diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 879b477..bc0e538 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -317,6 +317,7 @@ /* Handle any errors returned by FspMemoryInit */ fsp_handle_reset(status); if (status != FSP_SUCCESS) { + post_code(POST_RAM_FAILURE); printk(BIOS_CRIT, "FspMemoryInit returned 0x%08x\n", status); die("FspMemoryInit returned an error!\n"); } diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h index ce26aac..4b4226e 100644 --- a/src/include/console/post_codes.h +++ b/src/include/console/post_codes.h @@ -341,6 +341,14 @@ #define POST_INVALID_FSP 0xE2 /** + * \brief RAM failure + * + * Set if RAM could not be initialized. This includes RAM is missing, + * unsupported RAM configuration, or RAM failure. + */ +#define POST_RAM_FAILURE 0xE3 + +/** * \brief TPM failure * * An error with the TPM, either unexepcted state or communications failure. -- To view, visit https://review.coreboot.org/c/coreboot/+/32773 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibafefa0fc0b1c525f923929cc91731fbcc1e7533 Gerrit-Change-Number: 32773 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Short <keithshort(a)chromium.org> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Keith Short <keithshort(a)chromium.org> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 7

Change in ...coreboot[master]: coreboot: add post code for invalid FSP
by Keith Short (Code Review) 22 May '19

22 May '19

Keith Short has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32772 Change subject: coreboot: add post code for invalid FSP ...................................................................... coreboot: add post code for invalid FSP Add a new post code POST_INVALID_FSP, used when coreboot fails to locate or validate Intel FSP. BUG=b:124401932 BRANCH=sarien TEST=build coreboot for sarien and arcada platforms Change-Id: Ib1e359d4e8772c37922b1b779135e58c73bff6b4 Signed-off-by: Keith Short <keithshort(a)chromium.org> --- M src/drivers/intel/fsp2_0/memory_init.c M src/drivers/intel/fsp2_0/silicon_init.c M src/include/console/post_codes.h M src/soc/intel/fsp_baytrail/romstage/romstage.c M src/soc/intel/fsp_broadwell_de/romstage/romstage.c 5 files changed, 19 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/32772/1 diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index b3afb98..879b477 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -276,8 +276,10 @@ upd = (FSPM_UPD *)(hdr->cfg_region_offset + hdr->image_base); - if (upd->FspUpdHeader.Signature != FSPM_UPD_SIGNATURE) + if (upd->FspUpdHeader.Signature != FSPM_UPD_SIGNATURE) { + post_code(POST_INVALID_FSP); die("Invalid FSPM signature!\n"); + } /* Copy the default values from the UPD area */ memcpy(&fspm_upd, upd, sizeof(fspm_upd)); @@ -289,8 +291,10 @@ /* Fill common settings on behalf of chipset. */ if (fsp_fill_common_arch_params(arch_upd, s3wake, fsp_version, - memmap) != CB_SUCCESS) + memmap) != CB_SUCCESS) { + post_code(POST_INVALID_FSP); die("FSPM_ARCH_UPD not found!\n"); + } /* Give SoC and mainboard a chance to update the UPD */ platform_fsp_memory_init_params_cb(&fspm_upd, fsp_version); diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index 402b05d..dd4d730 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -32,8 +32,10 @@ supd = (FSPS_UPD *) (hdr->cfg_region_offset + hdr->image_base); - if (supd->FspUpdHeader.Signature != FSPS_UPD_SIGNATURE) + if (supd->FspUpdHeader.Signature != FSPS_UPD_SIGNATURE) { + post_code(POST_INVALID_FSP); die("Invalid FSPS signature\n"); + } upd = xmalloc(sizeof(FSPS_UPD)); diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h index 637083a..ce26aac 100644 --- a/src/include/console/post_codes.h +++ b/src/include/console/post_codes.h @@ -333,6 +333,14 @@ #define POST_INVALID_CBFS 0xE1 /** + * \brief FSP error + * + * Set if firmware failed to find or validate a FSP resource, or another + * FSP error occurred. + */ +#define POST_INVALID_FSP 0xE2 + +/** * \brief TPM failure * * An error with the TPM, either unexepcted state or communications failure. diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c index c46b09e..93900ef 100644 --- a/src/soc/intel/fsp_baytrail/romstage/romstage.c +++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c @@ -208,6 +208,7 @@ post_code(0x48); printk(BIOS_DEBUG, "Starting the Intel FSP (early_init)\n"); fsp_early_init(fsp_info_header); + post_code(POST_INVALID_FSP); die("Uh Oh! fsp_early_init should not return here.\n"); } diff --git a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c index a75dabd..12a1702 100644 --- a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c +++ b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c @@ -84,6 +84,7 @@ post_code(0x48); printk(BIOS_DEBUG, "Starting the Intel FSP (early_init)\n"); fsp_early_init(fsp_info_header); + post_code(POST_FSP_FAILURE); die("Uh Oh! fsp_early_init should not return here.\n"); } -- To view, visit https://review.coreboot.org/c/coreboot/+/32772 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib1e359d4e8772c37922b1b779135e58c73bff6b4 Gerrit-Change-Number: 32772 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Short <keithshort(a)chromium.org> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Keith Short <keithshort(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-MessageType: newchange

5 14

Change in ...coreboot[master]: coreboot: add post code for critical CBFS failures
by Keith Short (Code Review) 22 May '19

22 May '19

Keith Short has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32771 Change subject: coreboot: add post code for critical CBFS failures ...................................................................... coreboot: add post code for critical CBFS failures Add a new post code POST_INVALID_CBS, used when coreboot fails to locate or validate a resource that is stored in CBFS. BUG=b:124401932 BRANCH=sarien TEST=build coreboot for sarien and arcada platforms Change-Id: If1c8b92889040f9acd6250f847db02626809a987 Signed-off-by: Keith Short <keithshort(a)chromium.org> --- M src/arch/x86/postcar_loader.c M src/include/console/post_codes.h M src/soc/intel/quark/romstage/fsp2_0.c 3 files changed, 13 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/32771/1 diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index 9975931..e2a01cd 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -141,17 +141,17 @@ }; if (prog_locate(prog)) { - post_code(POST_INVALID_ROM); + post_code(POST_INVALID_CBFS); die("Failed to locate after CAR program.\n"); } if (rmodule_stage_load(&rsl)) { - post_code(POST_INVALID_ROM); + post_code(POST_INVALID_CBFS); die("Failed to load after CAR program.\n"); } /* Set the stack pointer within parameters of the program loaded. */ if (rsl.params == NULL) { - post_code(POST_INVALID_ROM); + post_code(POST_INVALID_CBFS); die("No parameters found in after CAR program.\n"); } diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h index 89a65ca..637083a 100644 --- a/src/include/console/post_codes.h +++ b/src/include/console/post_codes.h @@ -326,6 +326,13 @@ #define POST_INVALID_ROM 0xE0 /** + * \brief Invalid or corrupt CBFS + * + * Set if firmware failed to find or validate a resource that is stored in CBFS. + */ +#define POST_INVALID_CBFS 0xE1 + +/** * \brief TPM failure * * An error with the TPM, either unexepcted state or communications failure. diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c index 31e130a..280ae37 100644 --- a/src/soc/intel/quark/romstage/fsp2_0.c +++ b/src/soc/intel/quark/romstage/fsp2_0.c @@ -116,8 +116,10 @@ /* Locate the RMU data file in flash */ rmu_data = locate_rmu_file(&rmu_data_len); - if (!rmu_data) + if (!rmu_data) { + post_code(POST_INVALID_CBFS); die("Microcode file (rmu.bin) not found."); + } /* Locate the configuration data from devicetree.cb */ dev = pcidev_path_on_root(LPC_DEV_FUNC); -- To view, visit https://review.coreboot.org/c/coreboot/+/32771 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1c8b92889040f9acd6250f847db02626809a987 Gerrit-Change-Number: 32771 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Short <keithshort(a)chromium.org> Gerrit-MessageType: newchange

5 20

Change in ...coreboot[master]: coreboot: add post code for failure to load next stage
by Keith Short (Code Review) 22 May '19

22 May '19

Keith Short has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32770 Change subject: coreboot: add post code for failure to load next stage ...................................................................... coreboot: add post code for failure to load next stage Add a new post code, POST_INVALID_ROM, used when coreboot fails to locate or validate a resource that is stored in ROM. BUG=b:124401932 BRANCH=sarien TEST=build coreboot for sarien and arcada platforms Change-Id: Ie6de6590595d8fcdc57ad156237fffa03d5ead38 Signed-off-by: Keith Short <keithshort(a)chromium.org> --- M src/arch/x86/postcar_loader.c M src/include/console/post_codes.h M src/lib/prog_loaders.c M src/security/vboot/vboot_logic.c 4 files changed, 25 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/32770/1 diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index d62487e..9975931 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -140,14 +140,20 @@ .prog = prog, }; - if (prog_locate(prog)) + if (prog_locate(prog)) { + post_code(POST_INVALID_ROM); die("Failed to locate after CAR program.\n"); - if (rmodule_stage_load(&rsl)) + } + if (rmodule_stage_load(&rsl)) { + post_code(POST_INVALID_ROM); die("Failed to load after CAR program.\n"); + } /* Set the stack pointer within parameters of the program loaded. */ - if (rsl.params == NULL) + if (rsl.params == NULL) { + post_code(POST_INVALID_ROM); die("No parameters found in after CAR program.\n"); + } finalize_load(rsl.params, pcf->stack); diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h index f482ae9..89a65ca 100644 --- a/src/include/console/post_codes.h +++ b/src/include/console/post_codes.h @@ -319,6 +319,13 @@ #define POST_JUMPING_TO_PAYLOAD 0xf3 /** + * \brief Invalid or corrupt ROM + * + * Set if firmware failed to find or validate a resource that is stored in ROM. + */ +#define POST_INVALID_ROM 0xE0 + +/** * \brief TPM failure * * An error with the TPM, either unexepcted state or communications failure. diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index 3b77712..16eb746 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -68,8 +68,10 @@ prog_run(&romstage); fail: - if (CONFIG(BOOTBLOCK_CONSOLE)) + if (CONFIG(BOOTBLOCK_CONSOLE)) { + post_code(POST_INVALID_ROM); die("Couldn't load romstage.\n"); + } halt(); } diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index df34490..c61dfa9 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -319,8 +319,10 @@ /* Enable measured boot mode */ if (CONFIG(VBOOT_MEASURED_BOOT) && !(ctx.flags & VB2_CONTEXT_S3_RESUME)) { - if (vboot_init_crtm() != VB2_SUCCESS) + if (vboot_init_crtm() != VB2_SUCCESS) { + post_code(POST_INVALID_ROM); die("Initializing measured boot mode failed!"); + } } if (get_recovery_mode_switch()) { @@ -391,8 +393,10 @@ printk(BIOS_INFO, "Phase 4\n"); rv = locate_firmware(&ctx, &fw_main); - if (rv) + if (rv) { + post_code(POST_INVALID_ROM); die("Failed to read FMAP to locate firmware"); + } rv = hash_body(&ctx, &fw_main); save_if_needed(&ctx); -- To view, visit https://review.coreboot.org/c/coreboot/+/32770 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6de6590595d8fcdc57ad156237fffa03d5ead38 Gerrit-Change-Number: 32770 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Short <keithshort(a)chromium.org> Gerrit-MessageType: newchange

7 17

Change in ...coreboot[master]: post: during post_code, only call elog when enabled
by Jett Rink (Code Review) 22 May '19

22 May '19

Jett Rink has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32914 Change subject: post: during post_code, only call elog when enabled ...................................................................... post: during post_code, only call elog when enabled Now that we call post_code in other stages other than RAMSTAGE, we need to guard the elog calls with the appropriate condition in order to compile correctly. Change-Id: I766c276f28d46492fb05e0e3be71853e21f4e8e0 Signed-off-by: Jett Rink <jettrink(a)chromium.org> --- M src/console/post.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/32914/1 diff --git a/src/console/post.c b/src/console/post.c index b17a819..28ebd0e 100644 --- a/src/console/post.c +++ b/src/console/post.c @@ -81,7 +81,7 @@ default: printk(BIOS_WARNING, "POST: Unexpected post code " "in previous boot: 0x%02x\n", code); -#if CONFIG(ELOG) +#if CONFIG(ELOG) && (CONFIG(ENV_RAMSTAGE) || CONFIG(ELOG_PRERAM)) elog_add_event_word(ELOG_TYPE_LAST_POST_CODE, code); #if CONFIG(CMOS_POST_EXTRA) if (extra) -- To view, visit https://review.coreboot.org/c/coreboot/+/32914 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I766c276f28d46492fb05e0e3be71853e21f4e8e0 Gerrit-Change-Number: 32914 Gerrit-PatchSet: 1 Gerrit-Owner: Jett Rink <jettrink(a)chromium.org> Gerrit-MessageType: newchange

4 16

Change in ...coreboot[master]: mb/google/sarien: Add delay for EC sync
by EricR Lai (Code Review) 22 May '19

22 May '19

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32763 Change subject: mb/google/sarien: Add delay for EC sync ...................................................................... mb/google/sarien: Add delay for EC sync Kernel will fail at async when go into s0ix. Add a delay to let EC has some time for sync. BUG=b:130644677 TEST= check event log only log s0ix once Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I7ba48068f44ab2558199277f8dbbbbe9bcf249ff --- M src/soc/intel/cannonlake/acpi/lpit.asl 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/32763/1 diff --git a/src/soc/intel/cannonlake/acpi/lpit.asl b/src/soc/intel/cannonlake/acpi/lpit.asl index 93bce26..9b27c83 100644 --- a/src/soc/intel/cannonlake/acpi/lpit.asl +++ b/src/soc/intel/cannonlake/acpi/lpit.asl @@ -64,6 +64,7 @@ */ If(Arg2 == 5) { \_SB.PCI0.LPCB.EC0.S0IX(1) + Sleep(50) /* provide board level s0ix hook */ If (CondRefOf (\_SB.MS0X)) { \_SB.MS0X(1) @@ -74,6 +75,7 @@ */ If(Arg2 == 6) { \_SB.PCI0.LPCB.EC0.S0IX(0) + Sleep(50) /* provide board level s0ix hook */ If (CondRefOf (\_SB.MS0X)) { \_SB.MS0X(0) -- To view, visit https://review.coreboot.org/c/coreboot/+/32763 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ba48068f44ab2558199277f8dbbbbe9bcf249ff Gerrit-Change-Number: 32763 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mainboard/facebook/fbg1701: Do initial mainboard commit
by Frans Hendriks (Code Review) 22 May '19

22 May '19

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30414 ) Change subject: mainboard/facebook/fbg1701: Do initial mainboard commit ...................................................................... Patch Set 24: > Patch Set 24: Code-Review+1 > > The whole superio configuration is missing. Only the serial port of the superio is used. -- To view, visit https://review.coreboot.org/c/coreboot/+/30414 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28ac78a630ee705b1e546031f024bfe7f952ab39 Gerrit-Change-Number: 30414 Gerrit-PatchSet: 24 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Alex Thiessen <alex.thiessen.de+coreboot(a)gmail.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: David Hendricks <david.hendricks(a)gmail.com> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Comment-Date: Wed, 22 May 2019 13:30:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: {drivers,soc/intel/braswell}: Add C_ENVIRONMENT_BOOTBLOCK support
by Frans Hendriks (Code Review) 22 May '19

22 May '19

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29662 ) Change subject: {drivers,soc/intel/braswell}: Add C_ENVIRONMENT_BOOTBLOCK support ...................................................................... Patch Set 27: (4 comments) Will perform some more testing and update a new patch set. https://review.coreboot.org/#/c/29662/27//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/29662/27//COMMIT_MSG@13 PS27, Line 13: romstage_c_entry > you have hooks to do this in the bootblock. Comment of PS13 was to add this functions. I realize that bootblock takes care of init, but was not 100% sure about non-bootblock implementation. https://review.coreboot.org/#/c/29662/27/src/drivers/intel/fsp1_1/car.c File src/drivers/intel/fsp1_1/car.c: https://review.coreboot.org/#/c/29662/27/src/drivers/intel/fsp1_1/car.c@105 PS27, Line 105: car_soc_pre_console_init(); : car_mainboard_pre_console_init(); > You generally want the console set up in the bootblock, not in the romstage with C_ENVIRONMENT_BOOTB […] Same here. Should this functions not be placed around the console_init() to be compatible with other location where console_init() is used? https://review.coreboot.org/#/c/29662/27/src/drivers/intel/fsp1_1/car.c@110 PS27, Line 110: car_soc_post_console_init(); : car_mainboard_post_console_init(); > Similarly you have bootblock_soc_init() and bootblock_mainboard_init(). Will not add these calls here. https://review.coreboot.org/#/c/29662/27/src/soc/intel/braswell/bootblock/b… File src/soc/intel/braswell/bootblock/bootblock.c: https://review.coreboot.org/#/c/29662/27/src/soc/intel/braswell/bootblock/b… PS27, Line 50: > Where is this done now? Adding bootblock_cpu_init function result into message that fucntion is not used. For this reason (and the fact that system is booting without problem) This function was removed. For test purposed I have added function bootblock_soc_early_init to call this function. Will perform some more testing and add this to the patch set. -- To view, visit https://review.coreboot.org/c/coreboot/+/29662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c Gerrit-Change-Number: 29662 Gerrit-PatchSet: 27 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: York Yang <yyang024(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 22 May 2019 12:50:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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coreboot-gerrit May 2019