coreboot-gerrit May 2019

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Change in ...coreboot[master]: endian.h: Add be32dec/be32enc family of functions
by Julius Werner (Code Review) 23 May '19

23 May '19

Hello Patrick Rudolph, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32856 to review the following change. Change subject: endian.h: Add be32dec/be32enc family of functions ...................................................................... endian.h: Add be32dec/be32enc family of functions Libpayload has a family of functions that can "encode" or "decode" an endian-specific integer onto a byte stream pointer. These allow writing more pretty code than a raw be32_to_cpu/cpu_to_be32 with pointer casts in many (de-)serialization scenarios, so let's add them to coreboot as well. Change-Id: I049c5665484da12b3cf977a529310b0bde177d2d Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M src/include/endian.h 1 file changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/32856/1 diff --git a/src/include/endian.h b/src/include/endian.h index 08636f3..4bd30f1 100644 --- a/src/include/endian.h +++ b/src/include/endian.h @@ -84,6 +84,30 @@ #define clrbits_8(addr, clear) clrsetbits_8(addr, clear, 0) #define setbits_8(addr, set) setbits_8(addr, 0, set) +/* be16dec/be32dec/be64dec/le16dec/le32dec/le64dec family of functions. */ +#define DEFINE_ENDIAN_DEC(endian, width) \ + static inline uint##width##_t endian##width##dec(const void *p) { \ + return endian##width##_to_cpu(*(uint##width##_t *)p); \ + } +DEFINE_ENDIAN_DEC(be, 16) +DEFINE_ENDIAN_DEC(be, 32) +DEFINE_ENDIAN_DEC(be, 64) +DEFINE_ENDIAN_DEC(le, 16) +DEFINE_ENDIAN_DEC(le, 32) +DEFINE_ENDIAN_DEC(le, 64) + +/* be16enc/be32enc/be64enc/le16enc/le32enc/le64enc family of functions. */ +#define DEFINE_ENDIAN_ENC(endian, width) \ + static inline void endian##width##enc(void *p, uint##width##_t u) { \ + *(uint##width##_t *)p = cpu_to_##endian##width(u); \ + } +DEFINE_ENDIAN_ENC(be, 16) +DEFINE_ENDIAN_ENC(be, 32) +DEFINE_ENDIAN_ENC(be, 64) +DEFINE_ENDIAN_ENC(le, 16) +DEFINE_ENDIAN_ENC(le, 32) +DEFINE_ENDIAN_ENC(le, 64) + #ifndef __ROMCC__ /* * Portable (API) endian support that can be used in code that is shared -- To view, visit https://review.coreboot.org/c/coreboot/+/32856 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I049c5665484da12b3cf977a529310b0bde177d2d Gerrit-Change-Number: 32856 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/mainboard/google: Adopt Mainboards to changed Type41 Func
by Christian Walter (Code Review) 23 May '19

23 May '19

Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32909 Change subject: src/mainboard/google: Adopt Mainboards to changed Type41 Func ...................................................................... src/mainboard/google: Adopt Mainboards to changed Type41 Func Required for automatic onboard device detection in the next patch. Change-Id: I3087de779faf8d006510c460b5372b22ae54b887 Signed-off-by: Christian Walter <christian.walter(a)9elements.com> --- M src/arch/x86/smbios.c M src/include/smbios.h M src/mainboard/google/auron/variants/auron_paine/variant.c M src/mainboard/google/auron/variants/auron_yuna/variant.c M src/mainboard/google/auron/variants/buddy/variant.c M src/mainboard/google/auron/variants/gandof/variant.c M src/mainboard/google/auron/variants/lulu/variant.c M src/mainboard/google/butterfly/mainboard.c M src/mainboard/google/link/mainboard.c M src/mainboard/google/parrot/mainboard.c M src/mainboard/google/rambi/mainboard.c M src/mainboard/google/slippy/mainboard.c 12 files changed, 37 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/32909/1 diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 589f4f0..d389314 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -962,7 +962,7 @@ int smbios_write_type41(unsigned long *current, int *handle, const char *name, u8 instance, u16 segment, - u8 bus, u8 device, u8 function) + u8 bus, u8 device, u8 function, u8 device_type) { struct smbios_type41 *t = (struct smbios_type41 *)*current; int len = sizeof(struct smbios_type41); @@ -972,7 +972,7 @@ t->handle = *handle; t->length = len - 2; t->reference_designation = smbios_add_string(t->eos, name); - t->device_type = SMBIOS_DEVICE_TYPE_OTHER; + t->device_type = device_type; t->device_status = 1; t->device_type_instance = instance; t->segment_group_number = segment; diff --git a/src/include/smbios.h b/src/include/smbios.h index afe77d6..017e90e 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -44,7 +44,7 @@ const u8 irq); int smbios_write_type41(unsigned long *current, int *handle, const char *name, u8 instance, u16 segment, - u8 bus, u8 device, u8 function); + u8 bus, u8 device, u8 function, u8 device_type); const char *smbios_system_manufacturer(void); const char *smbios_system_product_name(void); diff --git a/src/mainboard/google/auron/variants/auron_paine/variant.c b/src/mainboard/google/auron/variants/auron_paine/variant.c index 62d4f52..84e26db 100644 --- a/src/mainboard/google/auron/variants/auron_paine/variant.c +++ b/src/mainboard/google/auron/variants/auron_paine/variant.c @@ -26,7 +26,8 @@ BOARD_TRACKPAD_I2C_BUS, /* segment */ BOARD_TRACKPAD_I2C_ADDR, /* bus */ 0, /* device */ - 0); /* function */ + 0, /* function */ + SMBIOS_DEVICE_TYPE_OTHER); /* device type */ return len; } diff --git a/src/mainboard/google/auron/variants/auron_yuna/variant.c b/src/mainboard/google/auron/variants/auron_yuna/variant.c index 62d4f52..84e26db 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/variant.c +++ b/src/mainboard/google/auron/variants/auron_yuna/variant.c @@ -26,7 +26,8 @@ BOARD_TRACKPAD_I2C_BUS, /* segment */ BOARD_TRACKPAD_I2C_ADDR, /* bus */ 0, /* device */ - 0); /* function */ + 0, /* function */ + SMBIOS_DEVICE_TYPE_OTHER); /* device type */ return len; } diff --git a/src/mainboard/google/auron/variants/buddy/variant.c b/src/mainboard/google/auron/variants/buddy/variant.c index 9f8188f..dcda04d 100644 --- a/src/mainboard/google/auron/variants/buddy/variant.c +++ b/src/mainboard/google/auron/variants/buddy/variant.c @@ -35,7 +35,8 @@ BOARD_TOUCHSCREEN_I2C_BUS, /* segment */ BOARD_TOUCHSCREEN_I2C_ADDR, /* bus */ 0, /* device */ - 0); /* function */ + 0, /* function */ + SMBIOS_DEVICE_TYPE_OTHER); /* device type */ return len; } diff --git a/src/mainboard/google/auron/variants/gandof/variant.c b/src/mainboard/google/auron/variants/gandof/variant.c index cd7a663..29b2988 100644 --- a/src/mainboard/google/auron/variants/gandof/variant.c +++ b/src/mainboard/google/auron/variants/gandof/variant.c @@ -29,7 +29,8 @@ BOARD_TRACKPAD_I2C_BUS, /* segment */ BOARD_TRACKPAD_I2C_ADDR, /* bus */ 0, /* device */ - 0); /* function */ + 0, /* function */ + SMBIOS_DEVICE_TYPE_OTHER); /* device type */ return len; } diff --git a/src/mainboard/google/auron/variants/lulu/variant.c b/src/mainboard/google/auron/variants/lulu/variant.c index 97302b8..a76cc85 100644 --- a/src/mainboard/google/auron/variants/lulu/variant.c +++ b/src/mainboard/google/auron/variants/lulu/variant.c @@ -29,7 +29,8 @@ BOARD_TRACKPAD_I2C_BUS, /* segment */ BOARD_TRACKPAD_I2C_ADDR, /* bus */ 0, /* device */ - 0); /* function */ + 0, /* function */ + SMBIOS_DEVICE_TYPE_OTHER); /* device type */ len += smbios_write_type41( current, handle, @@ -38,7 +39,8 @@ BOARD_TOUCHSCREEN_I2C_BUS, /* segment */ BOARD_TOUCHSCREEN_I2C_ADDR, /* bus */ 0, /* device */ - 0); /* function */ + 0, /* function */ + SMBIOS_DEVICE_TYPE_OTHER); /* device type */ return len; } diff --git a/src/mainboard/google/butterfly/mainboard.c b/src/mainboard/google/butterfly/mainboard.c index 9cc13c9..c298689 100644 --- a/src/mainboard/google/butterfly/mainboard.c +++ b/src/mainboard/google/butterfly/mainboard.c @@ -264,7 +264,8 @@ 0, /* segment */ BOARD_TRACKPAD_I2C_ADDR, /* bus */ 0, /* device */ - 0); /* function */ + 0, /* function */ + SMBIOS_DEVICE_TYPE_OTHER); /* device type */ return len; } diff --git a/src/mainboard/google/link/mainboard.c b/src/mainboard/google/link/mainboard.c index 410866d..37d1a67 100644 --- a/src/mainboard/google/link/mainboard.c +++ b/src/mainboard/google/link/mainboard.c @@ -170,7 +170,8 @@ 0, /* segment */ BOARD_LIGHTSENSOR_I2C_ADDR, /* bus */ 0, /* device */ - 0); /* function */ + 0, /* function */ + SMBIOS_DEVICE_TYPE_OTHER); /* device type */ len += smbios_write_type41( current, handle, @@ -179,7 +180,8 @@ 0, /* segment */ BOARD_TRACKPAD_I2C_ADDR, /* bus */ 0, /* device */ - 0); /* function */ + 0, /* function */ + SMBIOS_DEVICE_TYPE_OTHER); /* device type */ len += smbios_write_type41( current, handle, @@ -188,7 +190,8 @@ 0, /* segment */ BOARD_TOUCHSCREEN_I2C_ADDR, /* bus */ 0, /* device */ - 0); /* function */ + 0, /* function */ + SMBIOS_DEVICE_TYPE_OTHER); /* device type */ return len; } diff --git a/src/mainboard/google/parrot/mainboard.c b/src/mainboard/google/parrot/mainboard.c index 52e4af3..8c3ad63 100644 --- a/src/mainboard/google/parrot/mainboard.c +++ b/src/mainboard/google/parrot/mainboard.c @@ -57,7 +57,8 @@ 0, /* segment */ BOARD_TRACKPAD_I2C_ADDR, /* bus */ 0, /* device */ - 0); /* function */ + 0, /* function */ + SMBIOS_DEVICE_TYPE_OTHER); /* device type */ } else { len += smbios_write_type41( current, handle, @@ -66,7 +67,8 @@ 0, /* segment */ BOARD_TRACKPAD_I2C_ADDR, /* bus */ 0, /* device */ - 0); /* function */ + 0, /* function */ + SMBIOS_DEVICE_TYPE_OTHER); /* device type */ } return len; diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c index 15faac9..d3f6164 100644 --- a/src/mainboard/google/rambi/mainboard.c +++ b/src/mainboard/google/rambi/mainboard.c @@ -142,7 +142,8 @@ BOARD_TRACKPAD_I2C_BUS, /* segment */ BOARD_TRACKPAD_I2C_ADDR, /* bus */ 0, /* device */ - 0); /* function */ + 0, /* function */ + SMBIOS_DEVICE_TYPE_OTHER); /* device type */ #endif #ifdef BOARD_TOUCHSCREEN_NAME len += smbios_write_type41( @@ -152,7 +153,8 @@ BOARD_TOUCHSCREEN_I2C_BUS, /* segment */ BOARD_TOUCHSCREEN_I2C_ADDR, /* bus */ 0, /* device */ - 0); /* function */ + 0, /* function */ + SMBIOS_DEVICE_TYPE_OTHER); /* device type */ #endif return len; } diff --git a/src/mainboard/google/slippy/mainboard.c b/src/mainboard/google/slippy/mainboard.c index 4bbc1d6..b98fc8a 100644 --- a/src/mainboard/google/slippy/mainboard.c +++ b/src/mainboard/google/slippy/mainboard.c @@ -54,7 +54,8 @@ BOARD_LIGHTSENSOR_I2C_BUS, /* segment */ BOARD_LIGHTSENSOR_I2C_ADDR, /* bus */ 0, /* device */ - 0); /* function */ + 0, /* function */ + SMBIOS_DEVICE_TYPE_OTHER); /* device type */ len += smbios_write_type41( current, handle, @@ -63,7 +64,8 @@ BOARD_TRACKPAD_I2C_BUS, /* segment */ BOARD_TRACKPAD_I2C_ADDR, /* bus */ 0, /* device */ - 0); /* function */ + 0, /* function */ + SMBIOS_DEVICE_TYPE_OTHER); /* device type */ len += smbios_write_type41( current, handle, @@ -72,7 +74,8 @@ BOARD_TOUCHSCREEN_I2C_BUS, /* segment */ BOARD_TOUCHSCREEN_I2C_ADDR, /* bus */ 0, /* device */ - 0); /* function */ + 0, /* function */ + SMBIOS_DEVICE_TYPE_OTHER); /* device type */ return len; } -- To view, visit https://review.coreboot.org/c/coreboot/+/32909 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3087de779faf8d006510c460b5372b22ae54b887 Gerrit-Change-Number: 32909 Gerrit-PatchSet: 1 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/asus/p8h61-m_pro: Small fixes
by Patrick Rudolph (Code Review) 23 May '19

23 May '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32890 Change subject: mb/asus/p8h61-m_pro: Small fixes ...................................................................... mb/asus/p8h61-m_pro: Small fixes * Add VBT * Configure OnBoard NIC * Add documentation Change-Id: Iad739b4e1dacb41f5f63247150951df7013bbf0c Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- A Documentation/mainboard/asus/p8h61-m_pro.jpg A Documentation/mainboard/asus/p8h61-m_pro.md M Documentation/mainboard/index.md M src/mainboard/asus/p8h61-m_pro/Kconfig M src/mainboard/asus/p8h61-m_pro/devicetree.cb 5 files changed, 113 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/32890/1 diff --git a/Documentation/mainboard/asus/p8h61-m_pro.jpg b/Documentation/mainboard/asus/p8h61-m_pro.jpg new file mode 100644 index 0000000..5023966 --- /dev/null +++ b/Documentation/mainboard/asus/p8h61-m_pro.jpg Binary files differ diff --git a/Documentation/mainboard/asus/p8h61-m_pro.md b/Documentation/mainboard/asus/p8h61-m_pro.md new file mode 100644 index 0000000..cc53af6 --- /dev/null +++ b/Documentation/mainboard/asus/p8h61-m_pro.md @@ -0,0 +1,102 @@ +# ASUS P8H61-M Pro + +This page describes how to run coreboot on the [ASUS P8H61-M Pro]. + +## Flashing coreboot + +```eval_rst ++---------------------+------------+ +| Type | Value | ++=====================+============+ +| Socketed flash | yes | ++---------------------+------------+ +| Model | W25Q32BV | ++---------------------+------------+ +| Size | 4 MiB | ++---------------------+------------+ +| Package | DIP-8 | ++---------------------+------------+ +| Write protection | no | ++---------------------+------------+ +| Dual BIOS feature | no | ++---------------------+------------+ +| Internal flashing | yes | ++---------------------+------------+ +``` + +The flash IC is located right next to one of the SATA ports: +![](p8h61-m_pro.jpg) + +### Internal programming + +The main SPI flash can be accessed using [flashrom]. By default, only +the BIOS region of the flash is writable. If you wish to change any +other region (Management Engine or flash descriptor), then an external +programmer is required. + +The following command may be used to flash coreboot: + +``` +$ sudo flashrom --noverify-all --ifd -i bios -p internal -w coreboot.rom +``` + +The use of `--noverify-all` is required since the Management Engine +region is not readable even by the host. + +## Known issues + +- There is no automatic, OS-independent fan control. This is because + the super I/O hardware monitor can only obtain valid CPU temperature + readings from the PECI agent, whose complete initialisation is not + publicly documented. The `coretemp` driver can still be used for + accurate CPU temperature readings. + +- me_cleaner breaks LPC bus and attached components! + +## Untested + +- PCIe graphics +- parallel port +- PS/2 keyboard +- EHCI debug +- S/PDIF audio + +## Working + +- USB +- Gigabit Ethernet +- Integrated graphics +- SATA +- Serial port +- hardware monitor (see [Known issues](#known-issues) for caveats) +- front panel audio +- Native raminit (2 x 2GB, DDR3-1333) +- Native graphics init (libgfxinit) +- Wake-on-LAN +- TPM on TPM-header + +## Technology + +```eval_rst ++------------------+--------------------------------------------------+ +| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` | ++------------------+--------------------------------------------------+ +| Southbridge | bd82x6x | ++------------------+--------------------------------------------------+ +| CPU | model_206ax | ++------------------+--------------------------------------------------+ +| Super I/O | Nuvoton NCT6776 | ++------------------+--------------------------------------------------+ +| EC | None | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel Management Engine | ++------------------+--------------------------------------------------+ +``` + +## Extra resources + +- [Flash chip datasheet][W25Q32BV] + +[ASUS P8H61-M Pro]: https://www.asus.com/Motherboards/P8H61M_Pro/ +[W25Q32BV]: https://www.winbond.com/resource-files/w25q32bv_revi_100413_wo_automotive.p… +[flashrom]: https://flashrom.org/Flashrom diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 9af5c80..20578729 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -6,6 +6,7 @@ - [F2A85-M](asus/f2a85-m.md) - [P8H61-M LX](asus/p8h61-m_lx.md) +- [P8H61-M Pro](asus/p8h61-m_pro.md) ## ASRock diff --git a/src/mainboard/asus/p8h61-m_pro/Kconfig b/src/mainboard/asus/p8h61-m_pro/Kconfig index 14f841e..e8a6f64 100644 --- a/src/mainboard/asus/p8h61-m_pro/Kconfig +++ b/src/mainboard/asus/p8h61-m_pro/Kconfig @@ -31,6 +31,9 @@ select HAVE_CMOS_DEFAULT select DRIVERS_ASMEDIA_ASPM_BLACKLIST select MAINBOARD_HAS_LPC_TPM + select REALTEK_8168_RESET + select RT8168_SET_LED_MODE + select INTEL_GMA_HAVE_VBT config MAINBOARD_DIR string diff --git a/src/mainboard/asus/p8h61-m_pro/devicetree.cb b/src/mainboard/asus/p8h61-m_pro/devicetree.cb index f853452..d3f1795 100644 --- a/src/mainboard/asus/p8h61-m_pro/devicetree.cb +++ b/src/mainboard/asus/p8h61-m_pro/devicetree.cb @@ -49,7 +49,13 @@ device pci 1b.0 on end # High Definition Audio Audio controller device pci 1c.0 on end # PCIe x1 Port (PCIEX1_1) device pci 1c.1 on end # PCIe x1 Port (PCIEX1_2) - device pci 1c.2 on end # Realtek RTL8111E Ethernet Controller + device pci 1c.2 on # Realtek RTL8111E Ethernet Controller + chip drivers/net + register "customized_leds" = "0x00f6" + register "wake" = "9" + device pci 00.0 on end + end + end device pci 1c.3 on end # ASMedia ASM1042 USB3 Controller device pci 1c.4 on end # PCIe x1 Port, x16 size (PCIEX16_2) device pci 1c.5 on end # ASMedia ASM1062 SATA Controller -- To view, visit https://review.coreboot.org/c/coreboot/+/32890 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad739b4e1dacb41f5f63247150951df7013bbf0c Gerrit-Change-Number: 32890 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [Test] Remaining unused variables
by HAOUAS Elyes (Code Review) 22 May '19

22 May '19

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29926 to look at the new patch set (#30). Change subject: [Test] Remaining unused variables ...................................................................... [Test] Remaining unused variables Test CFLAGS_common += -Wno-unused-function \ -Wno-tautological-compare -Wno-shift-overflow Change-Id: Ic3dde296ab4b84add8a8ab6a3bb5ecb65da2c158 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M Makefile.inc 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/29926/30 -- To view, visit https://review.coreboot.org/c/coreboot/+/29926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3dde296ab4b84add8a8ab6a3bb5ecb65da2c158 Gerrit-Change-Number: 29926 Gerrit-PatchSet: 30 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: nb/intel/e7505: Remove unused function
by HAOUAS Elyes (Code Review) 22 May '19

22 May '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32927 Change subject: nb/intel/e7505: Remove unused function ...................................................................... nb/intel/e7505: Remove unused function Change-Id: I4b170a4607f3960a85162369668fa8214a61c463 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/e7505/northbridge.c 1 file changed, 0 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/32927/1 diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c index 7cb0b5b..9454218 100644 --- a/src/northbridge/intel/e7505/northbridge.c +++ b/src/northbridge/intel/e7505/northbridge.c @@ -22,12 +22,6 @@ #include "e7505.h" -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - static void mch_domain_read_resources(struct device *dev) { int idx; -- To view, visit https://review.coreboot.org/c/coreboot/+/32927 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b170a4607f3960a85162369668fa8214a61c463 Gerrit-Change-Number: 32927 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 1

Change in ...coreboot[master]: [Test] Remaining unused variables
by HAOUAS Elyes (Code Review) 22 May '19

22 May '19

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29926 to look at the new patch set (#29). Change subject: [Test] Remaining unused variables ...................................................................... [Test] Remaining unused variables Test CFLAGS_common += -Wno-unused-function \ -Wno-tautological-compare -Wno-shift-overflow Change-Id: Ic3dde296ab4b84add8a8ab6a3bb5ecb65da2c158 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M Makefile.inc 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/29926/29 -- To view, visit https://review.coreboot.org/c/coreboot/+/29926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3dde296ab4b84add8a8ab6a3bb5ecb65da2c158 Gerrit-Change-Number: 29926 Gerrit-PatchSet: 29 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: mb/google/sarien: Send post code to the EC
by Duncan Laurie (Code Review) 22 May '19

22 May '19

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32937 Change subject: mb/google/sarien: Send post code to the EC ...................................................................... mb/google/sarien: Send post code to the EC Use the mainboard post code hook to inform the wilco EC driver of the latest boot stage. BUG=b:124401932 BRANCH=sarien TEST=build coreboot for sarien and arcada platforms TEST=Remove DIMM module, confirm diagnostic LED pattern for memory failure (2 amber, 4 white). Change-Id: If5bf69365d8be3bdbd433f305c85848206ded7b0 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/mainboard/google/sarien/chromeos.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/32937/1 diff --git a/src/mainboard/google/sarien/chromeos.c b/src/mainboard/google/sarien/chromeos.c index fafc469..622a9fa 100644 --- a/src/mainboard/google/sarien/chromeos.c +++ b/src/mainboard/google/sarien/chromeos.c @@ -21,6 +21,7 @@ #include <vendorcode/google/chromeos/chromeos.h> #include <security/tpm/tss.h> #include <device/device.h> +#include <ec/google/wilco/commands.h> #include <intelblocks/pmclib.h> #include <soc/pmc.h> #include <soc/pci_devs.h> @@ -125,3 +126,8 @@ pmc_set_afterg3(PCH_DEV_PMC, MAINBOARD_POWER_STATE_ON); #endif } + +void mainboard_post(uint8_t value) +{ + wilco_ec_save_post_code(value); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/32937 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If5bf69365d8be3bdbd433f305c85848206ded7b0 Gerrit-Change-Number: 32937 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mainboard/google/sarien: set diagnostic LEDs on boot failure
by Keith Short (Code Review) 22 May '19

22 May '19

Keith Short has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32777 Change subject: mainboard/google/sarien: set diagnostic LEDs on boot failure ...................................................................... mainboard/google/sarien: set diagnostic LEDs on boot failure On Wilco devices, if any of the coreboot stages fails with a fatal error, set the diagnostic LEDs with the Wilco EC. BUG=b:124401932 BRANCH=sarien TEST=build coreboot for sarien and arcada platforms TEST=Remove DIMM module, confirm diagnostic LED pattern for memory failure (2 amber, 4 white). TEST=Forced a fatal error in both bootblock and verstage to confirm diagnostic LEDs during these stages. This works on cold-boots only. Bug b:132622888 tracks the mailbox failures on warm boots. Change-Id: If865ab8203f89e499130f4677fec166b40d80174 Signed-off-by: Keith Short <keithshort(a)chromium.org> --- M src/mainboard/google/sarien/chromeos.c 1 file changed, 42 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/32777/1 diff --git a/src/mainboard/google/sarien/chromeos.c b/src/mainboard/google/sarien/chromeos.c index fafc469..d6b34f9 100644 --- a/src/mainboard/google/sarien/chromeos.c +++ b/src/mainboard/google/sarien/chromeos.c @@ -15,22 +15,41 @@ #include <arch/acpi.h> #include <boot/coreboot_tables.h> +#include <console/console.h> #include <gpio.h> #include <soc/gpio.h> #include <variant/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> #include <security/tpm/tss.h> #include <device/device.h> +#include <ec/google/wilco/commands.h> #include <intelblocks/pmclib.h> #include <soc/pmc.h> #include <soc/pci_devs.h> +struct err_code_entry { + uint8_t post_code; + enum ec_err_code ec_err; +}; + enum rec_mode_state { REC_MODE_UNINITIALIZED, REC_MODE_NOT_REQUESTED, REC_MODE_REQUESTED, }; +static uint8_t sarien_post_code; + +/* + * Any post codes not listed in the sarien_err_codes[] use this default. + */ +static const enum ec_err_code sarien_default_ec_err = DLED_ROM; +static const struct err_code_entry sarien_err_codes[] = { + { .post_code = POST_RAM_FAILURE, .ec_err = DLED_MEMORY, }, + { .post_code = POST_VIDEO_FAILURE, .ec_err = DLED_PANEL, }, +}; + + void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -125,3 +144,26 @@ pmc_set_afterg3(PCH_DEV_PMC, MAINBOARD_POWER_STATE_ON); #endif } + +void mainboard_post(uint8_t value) +{ + sarien_post_code = value; +} + +void die_notify(void) +{ + size_t i; + enum ec_err_code ec_err = sarien_default_ec_err; + + for (i = 0; i < ARRAY_SIZE(sarien_err_codes); i++) { + if (sarien_err_codes[i].post_code == sarien_post_code) { + ec_err = sarien_err_codes[i].ec_err; + break; + } + } + + printk(BIOS_EMERG, "Fatal error: post_code 0x%02x, EC err 0x%02x\n", + sarien_post_code, ec_err); + + wilco_ec_err_code(ec_err); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/32777 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If865ab8203f89e499130f4677fec166b40d80174 Gerrit-Change-Number: 32777 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Short <keithshort(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: post_code: add post code for video initialization failure
by Duncan Laurie (Code Review) 22 May '19

22 May '19

Duncan Laurie has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32775 ) Change subject: post_code: add post code for video initialization failure ...................................................................... post_code: add post code for video initialization failure Add a new post code POST_VIDEO_FAILURE used when the Intel FSP silicon initialization returns an error when graphics was also initialized. BUG=b:124401932 BRANCH=sarien TEST=build coreboot for sarien and arcada platforms Change-Id: Ibc7f7defbed34038f445949010a37c8e368aae20 Signed-off-by: Keith Short <keithshort(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32775 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> --- M Documentation/POSTCODES M src/drivers/intel/fsp2_0/silicon_init.c M src/include/console/post_codes.h 3 files changed, 21 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/Documentation/POSTCODES b/Documentation/POSTCODES index a9d392a..0e67dd1 100644 --- a/Documentation/POSTCODES +++ b/Documentation/POSTCODES @@ -21,6 +21,7 @@ 0xe2 Vendor binary (e.g. FSP) generated a fatal error 0xe3 RAM could not be initialized 0xe4 Critical hardware component could not initialize +0xe5 Video subsystem failed to initialize 0xf8 Entry into elf boot 0xf3 Jumping to payload diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index b0a697d..e9c29db 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -18,6 +18,7 @@ #include <fsp/api.h> #include <fsp/util.h> #include <program_loading.h> +#include <soc/intel/common/vbt.h> #include <stage_cache.h> #include <string.h> #include <timestamp.h> @@ -29,6 +30,7 @@ FSPS_UPD *upd, *supd; fsp_silicon_init_fn silicon_init; uint32_t status; + uint8_t postcode; supd = (FSPS_UPD *) (hdr->cfg_region_offset + hdr->image_base); @@ -59,8 +61,18 @@ /* Handle any errors returned by FspSiliconInit */ fsp_handle_reset(status); if (status != FSP_SUCCESS) { + if (vbt_get()) { + /* Attempted to initialize graphics. Assume failure + * is related to a video failure. + */ + postcode = POST_VIDEO_FAILURE; + } else { + /* Other silicon initialization failed */ + postcode = POST_HW_INIT_FAILURE; + } printk(BIOS_SPEW, "FspSiliconInit returned 0x%08x\n", status); - die("FspSiliconINit returned an error!\n"); + die_with_post_code(postcode, + "FspSiliconINit returned an error!\n"); } } diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h index ae277d8..c1917ad 100644 --- a/src/include/console/post_codes.h +++ b/src/include/console/post_codes.h @@ -356,6 +356,13 @@ #define POST_HW_INIT_FAILURE 0xe4 /** + * \brief Video failure + * + * Video subsystem failed to initialize. + */ +#define POST_VIDEO_FAILURE 0xe5 + +/** * \brief TPM failure * * An error with the TPM, either unexepcted state or communications failure. -- To view, visit https://review.coreboot.org/c/coreboot/+/32775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc7f7defbed34038f445949010a37c8e368aae20 Gerrit-Change-Number: 32775 Gerrit-PatchSet: 14 Gerrit-Owner: Keith Short <keithshort(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Jett Rink <jettrink(a)chromium.org> Gerrit-Reviewer: Keith Short <keithshort(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in ...coreboot[master]: post_code: add post code for hardware initialization failure
by Duncan Laurie (Code Review) 22 May '19

22 May '19

Duncan Laurie has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32774 ) Change subject: post_code: add post code for hardware initialization failure ...................................................................... post_code: add post code for hardware initialization failure Add a new post code POST_HW_INIT_FAILURE, used when coreboot fails to detect or initialize a required hardware component. BUG=b:124401932 BRANCH=sarien TEST=build coreboot for sarien and arcada platforms Change-Id: I73820d24b3e1c269d9d446a78ef4f97e167e3552 Signed-off-by: Keith Short <keithshort(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32774 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> --- M Documentation/POSTCODES M src/console/Makefile.inc M src/include/console/post_codes.h M src/soc/intel/apollolake/memmap.c M src/soc/intel/cannonlake/bootblock/pch.c M src/soc/intel/cannonlake/memmap.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/p2sb/p2sb.c M src/soc/intel/common/block/pmc/pmc.c M src/soc/intel/fsp_baytrail/southcluster.c M src/soc/intel/icelake/memmap.c M src/soc/intel/quark/i2c.c 12 files changed, 34 insertions(+), 13 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/Documentation/POSTCODES b/Documentation/POSTCODES index 2a8285b..a9d392a 100644 --- a/Documentation/POSTCODES +++ b/Documentation/POSTCODES @@ -20,6 +20,7 @@ 0xe1 Resource stored within CBFS is corrupt 0xe2 Vendor binary (e.g. FSP) generated a fatal error 0xe3 RAM could not be initialized +0xe4 Critical hardware component could not initialize 0xf8 Entry into elf boot 0xf3 Jumping to payload diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index d5795d7..4f0c2ef 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -9,6 +9,7 @@ smm-$(CONFIG_DEBUG_SMI) += init.c console.c vtxprintf.c printk.c smm-$(CONFIG_SMM_TSEG) += die.c +smm-$(CONFIG_SMM_TSEG) += post.c verstage-y += init.c verstage-y += printk.c diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h index 07927ec..ae277d8 100644 --- a/src/include/console/post_codes.h +++ b/src/include/console/post_codes.h @@ -349,6 +349,13 @@ #define POST_RAM_FAILURE 0xe3 /** + * \brief Hardware initialization failure + * + * Set when a required hardware component was not found or is unsupported. + */ +#define POST_HW_INIT_FAILURE 0xe4 + +/** * \brief TPM failure * * An error with the TPM, either unexepcted state or communications failure. diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c index 4f91b8a..6058e34 100644 --- a/src/soc/intel/apollolake/memmap.c +++ b/src/soc/intel/apollolake/memmap.c @@ -40,7 +40,8 @@ config = dev->chip_info; if (!config) - die("Failed to get chip_info\n"); + die_with_post_code(POST_HW_INIT_FAILURE, + "Failed to get chip_info\n"); /* FSP allocates 2x PRMRR Size Memory for alignment */ if (config->sgx_enable) diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index 1c7fd7f..c43d6d8 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -120,7 +120,8 @@ pmc_base_reg = get_pmc_reg_base(); if (!pmc_base_reg) - die("Invalid PMC base address\n"); + die_with_post_code(POST_HW_INIT_FAILURE, + "Invalid PMC base address\n"); pmc_reg_value = pcr_read32(PID_PSF3, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4); diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c index 3512e2c..3cae54f 100644 --- a/src/soc/intel/cannonlake/memmap.c +++ b/src/soc/intel/cannonlake/memmap.c @@ -221,7 +221,8 @@ dev = dev_find_slot(0, PCI_DEVFN(SA_DEV_SLOT_IGD, 0)); if (!dev) - die("ERROR - IGD device not found!"); + die_with_post_code(POST_HW_INIT_FAILURE, + "ERROR - IGD device not found!"); /* Read TOLUD from Host Bridge offset */ dram_base = sa_get_tolud_base(); diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 5d3b4a1..4cea21b 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -58,7 +58,8 @@ */ uintptr_t memory_base = graphics_get_bar(PCI_BASE_ADDRESS_2); if (!memory_base) - die("GMADR is not programmed!"); + die_with_post_code(POST_HW_INIT_FAILURE, + "GMADR is not programmed!"); return memory_base; } @@ -74,7 +75,8 @@ if (!gtt_base) { gtt_base = graphics_get_bar(PCI_BASE_ADDRESS_0); if (!gtt_base) - die("GTTMMADR is not programmed!"); + die_with_post_code(POST_HW_INIT_FAILURE, + "GTTMMADR is not programmed!"); } return gtt_base; } diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index 1d7c091..24cde1b 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -36,7 +36,8 @@ pci_devfn_t dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); if (dev == PCI_DEV_INVALID) - die("PCH_DEV_P2SB not found!\n"); + die_with_post_code(POST_HW_INIT_FAILURE, + "PCH_DEV_P2SB not found!\n"); return dev; } @@ -45,7 +46,8 @@ { struct device *dev = PCH_DEV_P2SB; if (!dev) - die("PCH_DEV_P2SB not found!\n"); + die_with_post_code(POST_HW_INIT_FAILURE, + "PCH_DEV_P2SB not found!\n"); return dev; } @@ -99,7 +101,8 @@ if (pci_read_config16(P2SB_GET_DEV, PCI_VENDOR_ID) != PCI_VENDOR_ID_INTEL) - die("Unable to unhide PCH_DEV_P2SB device !\n"); + die_with_post_code(POST_HW_INIT_FAILURE, + "Unable to unhide PCH_DEV_P2SB device !\n"); } void p2sb_hide(void) @@ -108,7 +111,8 @@ if (pci_read_config16(P2SB_GET_DEV, PCI_VENDOR_ID) != 0xFFFF) - die("Unable to hide PCH_DEV_P2SB device !\n"); + die_with_post_code(POST_HW_INIT_FAILURE, + "Unable to hide PCH_DEV_P2SB device !\n"); } static void p2sb_configure_endpoints(int epmask_id, uint32_t mask) diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c index 43543a1..eaaf125 100644 --- a/src/soc/intel/common/block/pmc/pmc.c +++ b/src/soc/intel/common/block/pmc/pmc.c @@ -91,7 +91,8 @@ struct pmc_resource_config *config = &pmc_cfg; if (pmc_soc_get_resources(config) < 0) - die("Unable to get PMC controller resource information!"); + die_with_post_code(POST_HW_INIT_FAILURE, + "Unable to get PMC controller resource information!"); /* Get the normal PCI resources of this device. */ pci_dev_read_resources(dev); diff --git a/src/soc/intel/fsp_baytrail/southcluster.c b/src/soc/intel/fsp_baytrail/southcluster.c index c84f408..356b855 100644 --- a/src/soc/intel/fsp_baytrail/southcluster.c +++ b/src/soc/intel/fsp_baytrail/southcluster.c @@ -98,7 +98,7 @@ reg32 = *ioapic_data; printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); if (reg32 != (1 << 25)) - die("APIC Error\n"); + die_with_post_code(POST_HW_INIT_FAILURE, "APIC Error\n"); printk(BIOS_SPEW, "Dumping IOAPIC registers\n"); for (i=0; i<3; i++) { diff --git a/src/soc/intel/icelake/memmap.c b/src/soc/intel/icelake/memmap.c index 7d6e4e6..f446708 100644 --- a/src/soc/intel/icelake/memmap.c +++ b/src/soc/intel/icelake/memmap.c @@ -220,7 +220,8 @@ dev = dev_find_slot(0, PCI_DEVFN(SA_DEV_SLOT_IGD, 0)); if (!dev) - die("ERROR - IGD device not found!"); + die_with_post_code(POST_HW_INIT_FAILURE, + "ERROR - IGD device not found!"); /* Read TOLUD from Host Bridge offset */ dram_base = sa_get_tolud_base(); diff --git a/src/soc/intel/quark/i2c.c b/src/soc/intel/quark/i2c.c index 595c818..bb1a264 100644 --- a/src/soc/intel/quark/i2c.c +++ b/src/soc/intel/quark/i2c.c @@ -38,7 +38,8 @@ while (status & IC_ENABLE_CONTROLLER) { udelay(1); if (--timeout == 0) - die("ERROR - I2C failed to disable!\n"); + die_with_post_code(POST_HW_INIT_FAILURE, + "ERROR - I2C failed to disable!\n"); status = regs->ic_enable_status; } -- To view, visit https://review.coreboot.org/c/coreboot/+/32774 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73820d24b3e1c269d9d446a78ef4f97e167e3552 Gerrit-Change-Number: 32774 Gerrit-PatchSet: 13 Gerrit-Owner: Keith Short <keithshort(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Jett Rink <jettrink(a)chromium.org> Gerrit-Reviewer: Keith Short <keithshort(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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