coreboot-gerrit May 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: mb/google/hatch/variants: Fix DPTF sensor IDs
by Evan Green (Code Review) 23 May '19

23 May '19

Evan Green has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32920 Change subject: mb/google/hatch/variants: Fix DPTF sensor IDs ...................................................................... mb/google/hatch/variants: Fix DPTF sensor IDs There are indeed two temperature sensors hooked up to the EC, but they are indexed as 0 and 1, not 1 and 2. BUG=b:132999028 TEST=Boot hatch with hardened EC, observe no more index overflows Change-Id: Ia7f503bc1dc941635db52fce40f217bf34da6d2b Signed-off-by: Evan Green <evgreen(a)chromium.org> --- M src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/32920/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl index 1384ccf..ff7db49 100644 --- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl @@ -21,7 +21,7 @@ #define DPTF_CPU_ACTIVE_AC3 80 #define DPTF_CPU_ACTIVE_AC4 75 -#define DPTF_TSR0_SENSOR_ID 1 +#define DPTF_TSR0_SENSOR_ID 0 #define DPTF_TSR0_SENSOR_NAME "Thermal Sensor 1" #define DPTF_TSR0_PASSIVE 65 #define DPTF_TSR0_CRITICAL 75 @@ -31,7 +31,7 @@ #define DPTF_TSR0_ACTIVE_AC3 42 #define DPTF_TSR0_ACTIVE_AC4 39 -#define DPTF_TSR1_SENSOR_ID 2 +#define DPTF_TSR1_SENSOR_ID 1 #define DPTF_TSR1_SENSOR_NAME "Thermal Sensor 2" #define DPTF_TSR1_PASSIVE 65 #define DPTF_TSR1_CRITICAL 75 -- To view, visit https://review.coreboot.org/c/coreboot/+/32920 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7f503bc1dc941635db52fce40f217bf34da6d2b Gerrit-Change-Number: 32920 Gerrit-PatchSet: 1 Gerrit-Owner: Evan Green <evgreen(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/romcc: Add extra null pointer check
by Jacob Garber (Code Review) 23 May '19

23 May '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32917 Change subject: util/romcc: Add extra null pointer check ...................................................................... util/romcc: Add extra null pointer check It is possible that 'lnode->val' is set to 0 on a previous iteration of the loop, so check that it is non-null here before dereferencing it. Change-Id: I9827dd5623eaf11240df605a8b50ff9e27a5fce0 Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> Found-by: Coverity CID 1129149 --- M util/romcc/romcc.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/32917/1 diff --git a/util/romcc/romcc.c b/util/romcc/romcc.c index b9ec835..f8f8374 100644 --- a/util/romcc/romcc.c +++ b/util/romcc/romcc.c @@ -20935,7 +20935,8 @@ } } /* meet(const, const) = const or lattice low */ - else if (!constants_equal(state, lnode->val, tmp->val)) { + else if (lnode->val != 0 && + !constants_equal(state, lnode->val, tmp->val)) { lnode->val = 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/32917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9827dd5623eaf11240df605a8b50ff9e27a5fce0 Gerrit-Change-Number: 32917 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/romcc: Fix memory leak
by Jacob Garber (Code Review) 23 May '19

23 May '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32921 Change subject: util/romcc: Fix memory leak ...................................................................... util/romcc: Fix memory leak The 'new_type' function already allocates memory, so it is only necessary to clone the existing type if this function is not called. Change-Id: I47065204c5f4b6bab022bd7ccf19838c3ce1f86e Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> Found-by: Coverity Scan CID 1129106 --- M util/romcc/romcc.c 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/32921/1 diff --git a/util/romcc/romcc.c b/util/romcc/romcc.c index b9ec835..96f3812 100644 --- a/util/romcc/romcc.c +++ b/util/romcc/romcc.c @@ -12593,7 +12593,9 @@ } type = new_type(TYPE_BITFIELD, type, 0); type->elements = value->u.cval; - } + } else + type = clone_type(0, type); + return type; } @@ -12648,7 +12650,6 @@ done = 0; eat(state, TOK_COMMA); } - type = clone_type(0, type); type->field_ident = fident; if (*next) { *next = new_type(type_join, *next, type); -- To view, visit https://review.coreboot.org/c/coreboot/+/32921 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47065204c5f4b6bab022bd7ccf19838c3ce1f86e Gerrit-Change-Number: 32921 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/romcc: Add null check for filename
by Jacob Garber (Code Review) 23 May '19

23 May '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32922 Change subject: util/romcc: Add null check for filename ...................................................................... util/romcc: Add null check for filename It is possible that 'filename' is still null in this if statement, so we add an extra check to prevent a null dereference in strcmp. Change-Id: Iaba95b63a4d552051e0c56445522de7274dfd0b3 Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> Found-by: Coverity CID 1395330 --- M util/romcc/romcc.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/32922/1 diff --git a/util/romcc/romcc.c b/util/romcc/romcc.c index b9ec835..1011ed4 100644 --- a/util/romcc/romcc.c +++ b/util/romcc/romcc.c @@ -1989,7 +1989,7 @@ (last->line == line) && (last->function == function) && ((last->filename == filename) || - (strcmp(last->filename, filename) == 0))) + (filename != NULL && strcmp(last->filename, filename) == 0))) { get_occurrence(last); return last; -- To view, visit https://review.coreboot.org/c/coreboot/+/32922 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaba95b63a4d552051e0c56445522de7274dfd0b3 Gerrit-Change-Number: 32922 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/romcc: Add extra NULL checks for member
by Jacob Garber (Code Review) 23 May '19

23 May '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32916 Change subject: util/romcc: Add extra NULL checks for member ...................................................................... util/romcc: Add extra NULL checks for member In each of these cases it is possible that 'member' is NULL at the beginning, which will skip the earlier while loops entirely and cause a NULL dereference later on. Add extra error checks to prevent this. Change-Id: Ib5873c0830b71397ef661976d387fc6ce33c5cd1 Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> Found-by: Coverity CID 1129147, 1129152, 1129153, 1129154 --- M util/romcc/romcc.c 1 file changed, 9 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/32916/1 diff --git a/util/romcc/romcc.c b/util/romcc/romcc.c index b9ec835..3f1e040 100644 --- a/util/romcc/romcc.c +++ b/util/romcc/romcc.c @@ -6228,6 +6228,8 @@ size += size_of(state, member->left); member = member->right; } + if (member == NULL) + internal_error(state, 0, "Member is NULL"); size += needed_padding(state, member, size); } else if ((type->type & TYPE_MASK) == TYPE_UNION) { @@ -6350,10 +6352,12 @@ i++; member = member->right; } - size += needed_padding(state, member, size); + if (member == NULL) + internal_error(state, 0, "Member is NULL"); if (i != index) { internal_error(state, 0, "Missing member index: %u", index); } + size += needed_padding(state, member, size); } else if ((type->type & TYPE_MASK) == TYPE_JOIN) { ulong_t i; @@ -6402,6 +6406,8 @@ i++; member = member->right; } + if (member == NULL) + internal_error(state, 0, "Member is NULL"); if (i != index) { internal_error(state, 0, "Missing member index: %u", index); } @@ -6640,6 +6646,8 @@ offset += size; member = member->right; } + if (member == NULL) + internal_error(state, 0, "Member is NULL"); offset += reg_needed_padding(state, member, offset); member = reg_type(state, member, reg_offset - offset); break; -- To view, visit https://review.coreboot.org/c/coreboot/+/32916 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib5873c0830b71397ef661976d387fc6ce33c5cd1 Gerrit-Change-Number: 32916 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: AGESA binaryPI: Sync STRUCT_NAME definitions
by Kyösti Mälkki (Code Review) 23 May '19

23 May '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31510 Change subject: AGESA binaryPI: Sync STRUCT_NAME definitions ...................................................................... AGESA binaryPI: Sync STRUCT_NAME definitions While not implemented, copying the definitions from later AGESA/AMD.h to older helps us avoid lots of Change-Id: I34edc1ca23e9c063c4286273c53249ff0a953798 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/drivers/amd/agesa/eventlog.c M src/vendorcode/amd/agesa/f12/AMD.h M src/vendorcode/amd/agesa/f14/AMD.h M src/vendorcode/amd/agesa/f15tn/AMD.h M src/vendorcode/amd/agesa/f16kb/AMD.h M src/vendorcode/amd/pi/00630F01/AMD.h M src/vendorcode/amd/pi/00660F01/AMD.h M src/vendorcode/amd/pi/00730F01/AMD.h 8 files changed, 31 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/31510/1 diff --git a/src/drivers/amd/agesa/eventlog.c b/src/drivers/amd/agesa/eventlog.c index cc65652..3231d4f 100644 --- a/src/drivers/amd/agesa/eventlog.c +++ b/src/drivers/amd/agesa/eventlog.c @@ -29,8 +29,9 @@ static const char *AgesaFunctionNameStr[] = { "AmdInitRecovery", "AmdCreateStruct", "AmdInitEarly", "AmdInitEnv", "AmdInitLate", "AmdInitMid", "AmdInitPost", "AmdInitReset", "AmdInitResume", "AmdReleaseStruct", - "AmdS3LateRestore","AmdS3Save", "AmdGetApicId", "AmdGetPciAddress", "AmdIdentifyCore", + "AmdS3LateRestore", "AmdS3Save", "AmdGetApicId", "AmdGetPciAddress", "AmdIdentifyCore", "AmdReadEventLog", "AmdGetAvailableExeCacheSize", "AmdLateRunApTask", "AmdIdentifyDimm", + "Amd2dDataEye", "AmdS3FinalRestore", "AmdInitRtb" }; /* heapManager.h */ diff --git a/src/vendorcode/amd/agesa/f12/AMD.h b/src/vendorcode/amd/agesa/f12/AMD.h index 179c3f5..31c0b34 100644 --- a/src/vendorcode/amd/agesa/f12/AMD.h +++ b/src/vendorcode/amd/agesa/f12/AMD.h @@ -148,7 +148,10 @@ AMD_READ_EVENT_LOG, ///< AmdReadEventLog general service handle AMD_GET_EXECACHE_SIZE, ///< AmdGetAvailableExeCacheSize general service handle AMD_LATE_RUN_AP_TASK, ///< AmdLateRunApTask entry point handle - AMD_IDENTIFY_DIMMS ///< AmdIdentifyDimm general service handle + AMD_IDENTIFY_DIMMS, ///< AmdIdentifyDimm general service handle + AMD_GET_2D_DATA_EYE, ///< AmdGet2DDataEye general service handle + AMD_S3FINAL_RESTORE, ///< AmdS3FinalRestore entry point handle + AMD_INIT_RTB ///< AmdInitRtb entry point handle } AGESA_STRUCT_NAME; /* ResetType constant values */ diff --git a/src/vendorcode/amd/agesa/f14/AMD.h b/src/vendorcode/amd/agesa/f14/AMD.h index 9d443be..c1cfaa1 100644 --- a/src/vendorcode/amd/agesa/f14/AMD.h +++ b/src/vendorcode/amd/agesa/f14/AMD.h @@ -147,7 +147,10 @@ AMD_READ_EVENT_LOG, ///< AmdReadEventLog general service handle AMD_GET_EXECACHE_SIZE, ///< AmdGetAvailableExeCacheSize general service handle AMD_LATE_RUN_AP_TASK, ///< AmdLateRunApTask entry point handle - AMD_IDENTIFY_DIMMS ///< AmdIdentifyDimm general service handle + AMD_IDENTIFY_DIMMS, ///< AmdIdentifyDimm general service handle + AMD_GET_2D_DATA_EYE, ///< AmdGet2DDataEye general service handle + AMD_S3FINAL_RESTORE, ///< AmdS3FinalRestore entry point handle + AMD_INIT_RTB ///< AmdInitRtb entry point handle } AGESA_STRUCT_NAME; /* ResetType constant values */ diff --git a/src/vendorcode/amd/agesa/f15tn/AMD.h b/src/vendorcode/amd/agesa/f15tn/AMD.h index 31d38db..27326ec 100644 --- a/src/vendorcode/amd/agesa/f15tn/AMD.h +++ b/src/vendorcode/amd/agesa/f15tn/AMD.h @@ -144,7 +144,10 @@ AMD_READ_EVENT_LOG, ///< AmdReadEventLog general service handle AMD_GET_EXECACHE_SIZE, ///< AmdGetAvailableExeCacheSize general service handle AMD_LATE_RUN_AP_TASK, ///< AmdLateRunApTask entry point handle - AMD_IDENTIFY_DIMMS ///< AmdIdentifyDimm general service handle + AMD_IDENTIFY_DIMMS, ///< AmdIdentifyDimm general service handle + AMD_GET_2D_DATA_EYE, ///< AmdGet2DDataEye general service handle + AMD_S3FINAL_RESTORE, ///< AmdS3FinalRestore entry point handle + AMD_INIT_RTB ///< AmdInitRtb entry point handle } AGESA_STRUCT_NAME; /* ResetType constant values */ diff --git a/src/vendorcode/amd/agesa/f16kb/AMD.h b/src/vendorcode/amd/agesa/f16kb/AMD.h index bfce993..83d538f 100644 --- a/src/vendorcode/amd/agesa/f16kb/AMD.h +++ b/src/vendorcode/amd/agesa/f16kb/AMD.h @@ -143,7 +143,9 @@ AMD_GET_EXECACHE_SIZE, ///< AmdGetAvailableExeCacheSize general service handle AMD_LATE_RUN_AP_TASK, ///< AmdLateRunApTask entry point handle AMD_IDENTIFY_DIMMS, ///< AmdIdentifyDimm general service handle - AMD_GET_2D_DATA_EYE ///< AmdGet2DDataEye general service handle + AMD_GET_2D_DATA_EYE, ///< AmdGet2DDataEye general service handle + AMD_S3FINAL_RESTORE, ///< AmdS3FinalRestore entry point handle + AMD_INIT_RTB ///< AmdInitRtb entry point handle } AGESA_STRUCT_NAME; /* ResetType constant values */ diff --git a/src/vendorcode/amd/pi/00630F01/AMD.h b/src/vendorcode/amd/pi/00630F01/AMD.h index 68f7c32..f70b128 100644 --- a/src/vendorcode/amd/pi/00630F01/AMD.h +++ b/src/vendorcode/amd/pi/00630F01/AMD.h @@ -149,6 +149,8 @@ AMD_IDENTIFY_DIMMS = 0x00033000, ///< AmdIdentifyDimm general service handle AMD_GET_2D_DATA_EYE = 0x00034000, ///< AmdGet2DDataEye general service handle AMD_S3FINAL_RESTORE = 0x00035000, ///< AmdS3FinalRestore entry point handle + AMD_INIT_RTB = 0x00036000, /* reserved */ + AMD_HEAP_ALLOCATE_BUFFER = 0x00038000, AMD_HEAP_DEALLOCATE_BUFFER = 0x00039000, FCH_INIT_RESET = 0x00040000, diff --git a/src/vendorcode/amd/pi/00660F01/AMD.h b/src/vendorcode/amd/pi/00660F01/AMD.h index aa68204..54abf80 100644 --- a/src/vendorcode/amd/pi/00660F01/AMD.h +++ b/src/vendorcode/amd/pi/00660F01/AMD.h @@ -126,6 +126,11 @@ AccessS3SaveWidth64, ///< Save 64 bits data. } ACCESS_WIDTH; +/* When AMD rolled out CarrizoPI, they made a bad choice of removing + * an entry from the middle of the enumeration list. + */ +#define AMD_S3_SAVE_REMOVED + /// AGESA struct name typedef enum { // AGESA BASIC FUNCTIONS @@ -140,6 +145,10 @@ AMD_INIT_RESUME = 0x00029000, ///< AmdInitResume entry point handle AMD_RELEASE_STRUCT = 0x0002A000, ///< AmdReleaseStruct handle AMD_S3LATE_RESTORE = 0x0002B000, ///< AmdS3LateRestore entry point handle +#if 0 + /* This was removed, shifting everything else up.*/ + AMD_S3_SAVE = 0x0002C000, +#endif AMD_GET_APIC_ID = 0x0002C000, ///< AmdGetApicId entry point handle AMD_GET_PCI_ADDRESS = 0x0002D000, ///< AmdGetPciAddress entry point handle AMD_IDENTIFY_CORE = 0x0002E000, ///< AmdIdentifyCore general service handle diff --git a/src/vendorcode/amd/pi/00730F01/AMD.h b/src/vendorcode/amd/pi/00730F01/AMD.h index 1b6fdb2..13fc29a 100644 --- a/src/vendorcode/amd/pi/00730F01/AMD.h +++ b/src/vendorcode/amd/pi/00730F01/AMD.h @@ -148,6 +148,9 @@ AMD_LATE_RUN_AP_TASK = 0x00032000, ///< AmdLateRunApTask entry point handle AMD_IDENTIFY_DIMMS = 0x00033000, ///< AmdIdentifyDimm general service handle AMD_GET_2D_DATA_EYE = 0x00034000, ///< AmdGet2DDataEye general service handle + AMD_S3FINAL_RESTORE = 0x00035000, /* reserved */ + AMD_INIT_RTB = 0x00036000, /* reserved */ + AMD_HEAP_ALLOCATE_BUFFER = 0x00038000, AMD_HEAP_DEALLOCATE_BUFFER = 0x00039000, FCH_INIT_RESET = 0x00040000, -- To view, visit https://review.coreboot.org/c/coreboot/+/31510 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34edc1ca23e9c063c4286273c53249ff0a953798 Gerrit-Change-Number: 31510 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/autoport: Mention i2c-i801 module in readme.md
by Evgeny Zinoviev (Code Review) 23 May '19

23 May '19

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32681 Change subject: util/autoport: Mention i2c-i801 module in readme.md ...................................................................... util/autoport: Mention i2c-i801 module in readme.md SMBus adapter will not appear if i2c-i801 module is not loaded. Added it to the readme. Change-Id: I3de0e02f13178d78b8cc02a74a745ad66e929070 Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- M util/autoport/readme.md 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/32681/1 diff --git a/util/autoport/readme.md b/util/autoport/readme.md index 4683d8d..cfa8c36 100644 --- a/util/autoport/readme.md +++ b/util/autoport/readme.md @@ -120,6 +120,7 @@ the EEPROM has. Under Linux, you can use these commands to see what is on SMBus: $ sudo modprobe i2c-dev + $ sudo modprobe i2c-i801 $ sudo i2cdetect -l i2c-0 i2c i915 gmbus ssc I2C adapter i2c-1 i2c i915 gmbus vga I2C adapter -- To view, visit https://review.coreboot.org/c/coreboot/+/32681 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3de0e02f13178d78b8cc02a74a745ad66e929070 Gerrit-Change-Number: 32681 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/fsp_baytrail/romstage: Remove variable set but not used
by HAOUAS Elyes (Code Review) 23 May '19

23 May '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32899 Change subject: soc/intel/fsp_baytrail/romstage: Remove variable set but not used ...................................................................... soc/intel/fsp_baytrail/romstage: Remove variable set but not used Change-Id: Ic04cb7c51862bea4d01f853ee2c88cc03c414e35 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/fsp_baytrail/romstage/romstage.c 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/32899/1 diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c index c46b09e..b26e696 100644 --- a/src/soc/intel/fsp_baytrail/romstage/romstage.c +++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c @@ -217,7 +217,6 @@ */ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { - int cbmem_was_initted; void *cbmem_hob_ptr; uint32_t prev_sleep_state; @@ -244,7 +243,7 @@ late_mainboard_romstage_entry(); post_code(0x4c); - cbmem_was_initted = !cbmem_recovery(prev_sleep_state == ACPI_S3); + cbmem_recovery(prev_sleep_state == ACPI_S3); /* Save the HOB pointer in CBMEM to be used in ramstage*/ cbmem_hob_ptr = cbmem_add(CBMEM_ID_HOB_POINTER, sizeof(*hob_list_ptr)); -- To view, visit https://review.coreboot.org/c/coreboot/+/32899 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic04cb7c51862bea4d01f853ee2c88cc03c414e35 Gerrit-Change-Number: 32899 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/fsp_broadwell_de/romstage: Remove variable set but not used
by HAOUAS Elyes (Code Review) 23 May '19

23 May '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32898 Change subject: soc/intel/fsp_broadwell_de/romstage: Remove variable set but not used ...................................................................... soc/intel/fsp_broadwell_de/romstage: Remove variable set but not used Change-Id: I3e304b9b19978c4100ef3486088d809c2a7fe1d7 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/fsp_broadwell_de/romstage/romstage.c 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/32898/1 diff --git a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c index a75dabd..e929fa4 100644 --- a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c +++ b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c @@ -93,7 +93,6 @@ */ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { - int cbmem_was_initted; void *cbmem_hob_ptr; post_code(0x4a); @@ -112,7 +111,7 @@ late_mainboard_romstage_entry(); post_code(0x4d); - cbmem_was_initted = !cbmem_recovery(0); + cbmem_recovery(0); /* Save the HOB pointer in CBMEM to be used in ramstage*/ cbmem_hob_ptr = cbmem_add(CBMEM_ID_HOB_POINTER, sizeof(*hob_list_ptr)); -- To view, visit https://review.coreboot.org/c/coreboot/+/32898 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e304b9b19978c4100ef3486088d809c2a7fe1d7 Gerrit-Change-Number: 32898 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/intel/pineview/early_init.c: Remove variable set but not used
by HAOUAS Elyes (Code Review) 23 May '19

23 May '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32897 Change subject: nb/intel/pineview/early_init.c: Remove variable set but not used ...................................................................... nb/intel/pineview/early_init.c: Remove variable set but not used Change-Id: If9ca551794a52e47a3649b126c3f061a68c494e4 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/pineview/early_init.c 1 file changed, 3 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/32897/1 diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c index a0d5305..509ab4e 100644 --- a/src/northbridge/intel/pineview/early_init.c +++ b/src/northbridge/intel/pineview/early_init.c @@ -119,9 +119,7 @@ static void early_misc_setup(void) { - u32 reg32; - - reg32 = MCHBAR32(0x30); + MCHBAR32(0x30); MCHBAR32(0x30) = 0x21800; DMIBAR32(0x2c) = 0x86000040; pci_write_config32(PCI_DEV(0, 0x1e, 0), 0x18, 0x00020200); @@ -129,9 +127,9 @@ early_graphics_setup(); - reg32 = MCHBAR32(0x40); + MCHBAR32(0x40); MCHBAR32(0x40) = 0x0; - reg32 = MCHBAR32(0x40); + MCHBAR32(0x40); MCHBAR32(0x40) = 0x8; pci_write_config8(LPC, 0x8, 0x1d); -- To view, visit https://review.coreboot.org/c/coreboot/+/32897 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If9ca551794a52e47a3649b126c3f061a68c494e4 Gerrit-Change-Number: 32897 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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coreboot-gerrit May 2019