coreboot-gerrit May 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: nb/amd/amdmct/mct/mctecc_d.c: Remove variable set but not used
by HAOUAS Elyes (Code Review) 24 May '19

24 May '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32947 Change subject: nb/amd/amdmct/mct/mctecc_d.c: Remove variable set but not used ...................................................................... nb/amd/amdmct/mct/mctecc_d.c: Remove variable set but not used Change-Id: I309cf83a1fec16b796c72c1803d27e1b7932940f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/amd/amdmct/mct/mctecc_d.c 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/32947/1 diff --git a/src/northbridge/amd/amdmct/mct/mctecc_d.c b/src/northbridge/amd/amdmct/mct/mctecc_d.c index 7be6353..8eb7bf5 100644 --- a/src/northbridge/amd/amdmct/mct/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct/mctecc_d.c @@ -80,7 +80,6 @@ u16 OB_ECCRedir; u32 LDramECC; u32 OF_ScrubCTL; - u16 OB_ChipKill; u8 MemClrECC; u32 dev; @@ -96,7 +95,7 @@ OB_ECCRedir = mctGet_NVbits(NV_ECCRedir); /* ECC Redirection */ - OB_ChipKill = mctGet_NVbits(NV_ChipKill); /* ECC Chip-kill mode */ + mctGet_NVbits(NV_ChipKill); /* ECC Chip-kill mode */ OF_ScrubCTL = 0; /* Scrub CTL for Dcache, L2, and dram */ nvbits = mctGet_NVbits(NV_DCBKScrub); -- To view, visit https://review.coreboot.org/c/coreboot/+/32947 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I309cf83a1fec16b796c72c1803d27e1b7932940f Gerrit-Change-Number: 32947 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/amd/pi/00660F01: Remove variable set but not used
by HAOUAS Elyes (Code Review) 24 May '19

24 May '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32946 Change subject: nb/amd/pi/00660F01: Remove variable set but not used ...................................................................... nb/amd/pi/00660F01: Remove variable set but not used Change-Id: I14c69b324de795ba6dead7932b3267887130a6df Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/amd/pi/00660F01/northbridge.c 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/32946/1 diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index 43df725..41641ee 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -678,7 +678,6 @@ struct bus *link; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 struct hw_mem_hole_info mem_hole; - u32 reset_memhole = 1; #endif pci_tolm = 0xffffffffUL; @@ -708,7 +707,6 @@ /* Use hole_basek as mmio_basek, and we don't need to reset hole anymore */ if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { mmio_basek = mem_hole.hole_startk; - reset_memhole = 0; } #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/32946 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14c69b324de795ba6dead7932b3267887130a6df Gerrit-Change-Number: 32946 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: {drivers,soc/intel/braswell}: Implement C_ENVIRONMENT_BOOTBLOCK support
by Frans Hendriks (Code Review) 24 May '19

24 May '19

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29662 ) Change subject: {drivers,soc/intel/braswell}: Implement C_ENVIRONMENT_BOOTBLOCK support ...................................................................... Patch Set 30: (1 comment) https://review.coreboot.org/#/c/29662/30/src/soc/intel/braswell/bootblock/c… File src/soc/intel/braswell/bootblock/cache_as_ram.S: https://review.coreboot.org/#/c/29662/30/src/soc/intel/braswell/bootblock/c… PS30, Line 140: movd %mm2, %eax : push %eax /* BIST */ > this is not used by the function you call. My mistake. Checked against incorrect function define in cpu/intel/car/bootblock.c -- To view, visit https://review.coreboot.org/c/coreboot/+/29662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c Gerrit-Change-Number: 29662 Gerrit-PatchSet: 30 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: York Yang <yyang024(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 24 May 2019 09:33:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in ...coreboot[master]: {drivers,soc/intel/braswell}: Implement C_ENVIRONMENT_BOOTBLOCK support
by Frans Hendriks (Code Review) 24 May '19

24 May '19

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29662 ) Change subject: {drivers,soc/intel/braswell}: Implement C_ENVIRONMENT_BOOTBLOCK support ...................................................................... Patch Set 30: > Patch Set 30: > > (3 comments) > > You might want to rebase on top of https://review.coreboot.org/q/topic:%22fsp1.1+cleanup . It cleans up a few things and should make the transition and the bootflow in general cleaner. It gets rid of the many functions that do nothing but calling the next one, like the one in car_stage_entry.S I was wondering how to combine your cleanup and this patch. I tested a few of your patches, not all of them yet. Will rebase on top of your patch next week. -- To view, visit https://review.coreboot.org/c/coreboot/+/29662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c Gerrit-Change-Number: 29662 Gerrit-PatchSet: 30 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: York Yang <yyang024(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 24 May 2019 09:29:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: {drivers,soc/intel/braswell}: Implement C_ENVIRONMENT_BOOTBLOCK support
by Arthur Heymans (Code Review) 24 May '19

24 May '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29662 ) Change subject: {drivers,soc/intel/braswell}: Implement C_ENVIRONMENT_BOOTBLOCK support ...................................................................... Patch Set 30: (3 comments) You might want to rebase on top of https://review.coreboot.org/q/topic:%22fsp1.1+cleanup . It cleans up a few things and should make the transition and the bootflow in general cleaner. It gets rid of the many functions that do nothing but calling the next one, like the one in car_stage_entry.S https://review.coreboot.org/#/c/29662/30/src/soc/intel/braswell/bootblock/c… File src/soc/intel/braswell/bootblock/cache_as_ram.S: https://review.coreboot.org/#/c/29662/30/src/soc/intel/braswell/bootblock/c… PS30, Line 112: : movd %edi, %mm2 /* BIST value */ why do you do this? https://review.coreboot.org/#/c/29662/30/src/soc/intel/braswell/bootblock/c… PS30, Line 140: movd %mm2, %eax : push %eax /* BIST */ this is not used by the function you call. https://review.coreboot.org/#/c/29662/30/src/soc/intel/braswell/bootblock/c… PS30, Line 148: call bootblock_c_entry It seems a good idea to align the stack 16 bytes. -- To view, visit https://review.coreboot.org/c/coreboot/+/29662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c Gerrit-Change-Number: 29662 Gerrit-PatchSet: 30 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: York Yang <yyang024(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 24 May 2019 09:26:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: {drivers,soc/intel/braswell}: Implement C_ENVIRONMENT_BOOTBLOCK support
by Frans Hendriks (Code Review) 24 May '19

24 May '19

Hello Patrick Rudolph, Huang Jin, Arthur Heymans, York Yang, Lee Leahy, Matt DeVillier, build bot (Jenkins), Hannah Williams, Michał Żygowski, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29662 to look at the new patch set (#30). Change subject: {drivers,soc/intel/braswell}: Implement C_ENVIRONMENT_BOOTBLOCK support ...................................................................... {drivers,soc/intel/braswell}: Implement C_ENVIRONMENT_BOOTBLOCK support No C_ENVIRONMENT_BOOTBLOCK support for Braswell is available. Enable support and add required files for the Braswell Bootblock in C. The next changes are made support C_ENVIRONMENT_BOOTBLOCK: - Add car_stage_entry() function bootblock-c_entry() functions. - Specify config DCACHE_BSP_STACK_SIZE and C_ENV_BOOTBLOCK_SIZE. - Add bootblock_c_entry(). - Move init from car_soc_XXX_console_init() to bootblock_soc_XXX_Init() Removed the unused cache_as_ram_main() and weak car_XXX_XXX_console_init() BUG=NA TEST=Booting Embedded Linux on Facebook FBG-1701 Building Google Banos Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/drivers/intel/fsp1_1/Makefile.inc M src/drivers/intel/fsp1_1/car.c M src/drivers/intel/fsp1_1/include/fsp/car.h M src/soc/intel/braswell/Kconfig M src/soc/intel/braswell/Makefile.inc M src/soc/intel/braswell/bootblock/bootblock.c R src/soc/intel/braswell/bootblock/cache_as_ram.S R src/soc/intel/braswell/include/soc/bootblock.h M src/soc/intel/braswell/include/soc/romstage.h M src/soc/intel/braswell/romstage/Makefile.inc A src/soc/intel/braswell/romstage/car_stage_entry.S M src/soc/intel/braswell/romstage/romstage.c 12 files changed, 180 insertions(+), 266 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/29662/30 -- To view, visit https://review.coreboot.org/c/coreboot/+/29662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c Gerrit-Change-Number: 29662 Gerrit-PatchSet: 30 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: York Yang <yyang024(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: superio: Add ASpeed AST2400
by Patrick Rudolph (Code Review) 24 May '19

24 May '19

Patrick Rudolph has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/23135 ) Change subject: superio: Add ASpeed AST2400 ...................................................................... superio: Add ASpeed AST2400 Add support for ASpeed AST2400. This device uses write twice 0xA5 to enter config mode. BUG = N/A TEST = ASRock D1521D4U Change-Id: I58fce31f0a2483e61e9d31f38ab5a059b8cf4f83 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/23135 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/include/superio/conf_mode.h M src/superio/Makefile.inc A src/superio/aspeed/Makefile.inc A src/superio/aspeed/ast2400/Kconfig A src/superio/aspeed/ast2400/Makefile.inc A src/superio/aspeed/ast2400/ast2400.h A src/superio/aspeed/ast2400/superio.c A src/superio/aspeed/common/Kconfig A src/superio/aspeed/common/aspeed.h A src/superio/aspeed/common/early_serial.c M src/superio/common/conf_mode.c 11 files changed, 307 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/include/superio/conf_mode.h b/src/include/superio/conf_mode.h index ecc365d..8e753ea 100644 --- a/src/include/superio/conf_mode.h +++ b/src/include/superio/conf_mode.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Nico Huber <nico.h(a)gmx.de> + * Copyright (C) 2017-2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -25,6 +26,7 @@ void pnp_enter_conf_mode_7777(struct device *dev); void pnp_enter_conf_mode_8787(struct device *dev); void pnp_enter_conf_mode_a0a0(struct device *dev); +void pnp_enter_conf_mode_a5a5(struct device *dev); void pnp_exit_conf_mode_aa(struct device *dev); void pnp_enter_conf_mode_870155aa(struct device *dev); void pnp_exit_conf_mode_0202(struct device *dev); @@ -34,6 +36,7 @@ extern const struct pnp_mode_ops pnp_conf_mode_7777_aa; extern const struct pnp_mode_ops pnp_conf_mode_8787_aa; extern const struct pnp_mode_ops pnp_conf_mode_a0a0_aa; +extern const struct pnp_mode_ops pnp_conf_mode_a5a5_aa; extern const struct pnp_mode_ops pnp_conf_mode_870155_aa; #endif /* DEVICE_PNP_CONF_MODE_H */ diff --git a/src/superio/Makefile.inc b/src/superio/Makefile.inc index 5fc0ecd..ca96343 100644 --- a/src/superio/Makefile.inc +++ b/src/superio/Makefile.inc @@ -2,6 +2,7 @@ ## This file is part of the coreboot project. ## ## Copyright (C) 2009 Ronald G. Minnich +## Copyright (C) 2018 Eltan B.V. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -13,6 +14,7 @@ ## GNU General Public License for more details. ## +subdirs-y += aspeed subdirs-y += fintek subdirs-y += intel subdirs-y += ite diff --git a/src/superio/aspeed/Makefile.inc b/src/superio/aspeed/Makefile.inc new file mode 100644 index 0000000..6d0cc26 --- /dev/null +++ b/src/superio/aspeed/Makefile.inc @@ -0,0 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Ronald G. Minnich +## Copyright (C) 2018 Eltan B.V. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +## include generic fintek pre-ram stage driver +romstage-$(CONFIG_SUPERIO_ASPEED_COMMON_PRE_RAM) += common/early_serial.c +bootblock-$(CONFIG_SUPERIO_ASPEED_COMMON_PRE_RAM) += common/early_serial.c + +subdirs-y += ast2400 +subdirs-y += common + +CPPFLAGS_common += -Isrc/superio/aspeed diff --git a/src/superio/aspeed/ast2400/Kconfig b/src/superio/aspeed/ast2400/Kconfig new file mode 100644 index 0000000..1ced5af --- /dev/null +++ b/src/superio/aspeed/ast2400/Kconfig @@ -0,0 +1,21 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Ronald G. Minnich +## Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> +## Copyright (C) 2018 Eltan B.V. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config SUPERIO_ASPEED_AST2400 + bool + default n + select SUPERIO_ASPEED_COMMON_PRE_RAM diff --git a/src/superio/aspeed/ast2400/Makefile.inc b/src/superio/aspeed/ast2400/Makefile.inc new file mode 100644 index 0000000..a6f8b20 --- /dev/null +++ b/src/superio/aspeed/ast2400/Makefile.inc @@ -0,0 +1,18 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 Corey Osgood <corey.osgood(a)gmail.com> +## Copyright (C) 2018 Eltan B.V. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-$(CONFIG_SUPERIO_ASPEED_AST2400) += superio.c diff --git a/src/superio/aspeed/ast2400/ast2400.h b/src/superio/aspeed/ast2400/ast2400.h new file mode 100644 index 0000000..aa9b0a9 --- /dev/null +++ b/src/superio/aspeed/ast2400/ast2400.h @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_ASPEED_AST2400_H +#define SUPERIO_ASPEED_AST2400_H + +#define AST2400_SUART1 0x2 /* Com1 */ +#define AST2400_SUART2 0x3 /* Com2 */ +#define AST2400_SWAK 0x4 /* System Wake-Up control */ +#define AST2400_KBC 0x5 /* Keyboard controller */ +#define AST2400_GPIO 0x7 /* GPIO */ +#define AST2400_SUART3 0xB /* Com3 */ +#define AST2400_SUART4 0xC /* Com4 */ +#define AST2400_ILPC2AHB 0xD /* LPC 2 AHB */ +#define AST2400_MAILBOX 0xE /* Mailbox */ + +#endif /* SUPERIO_ASPEED_AST2400_H */ diff --git a/src/superio/aspeed/ast2400/superio.c b/src/superio/aspeed/ast2400/superio.c new file mode 100644 index 0000000..dcb14fa --- /dev/null +++ b/src/superio/aspeed/ast2400/superio.c @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Corey Osgood <corey.osgood(a)gmail.com> + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pnp.h> +#include <superio/conf_mode.h> +#include <console/console.h> +#include <string.h> +#include <pc80/keyboard.h> +#include "ast2400.h" + +static void ast2400_init(struct device *dev) +{ + if (!dev->enabled) + return; + + switch (dev->path.pnp.device) { + case AST2400_KBC: + pc_keyboard_init(NO_AUX_DEVICE); + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_enable, + .init = ast2400_init, + .ops_pnp_mode = &pnp_conf_mode_a5a5_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + { NULL, AST2400_SUART1, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0xfff8, }, + { NULL, AST2400_SUART2, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0xfff8, }, + { NULL, AST2400_SWAK, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IO3 + | PNP_IRQ0, 0xfff8, 0xfff8, 0xfff8, 0xfff8, }, + { NULL, AST2400_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1 + | PNP_MSC0, 0xffff, 0xffff, }, + { NULL, AST2400_GPIO, PNP_IRQ0, }, // GPIO LDN has no IO Region + { NULL, AST2400_SUART3, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0xfff8, }, + { NULL, AST2400_SUART4, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0xfff8, }, + { NULL, AST2400_ILPC2AHB, PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 | PNP_MSC2 + | PNP_MSC3 | PNP_MSC4 | PNP_MSC5 | PNP_MSC6 | PNP_MSC7 + | PNP_MSC8 | PNP_MSC9 | PNP_MSCA | PNP_MSCB | PNP_MSCC + | PNP_MSCD | PNP_MSCE, }, + { NULL, AST2400_MAILBOX, PNP_IO0 | PNP_IRQ0, 0xfffe, }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), + pnp_dev_info); +} + +struct chip_operations superio_aspeed_ast2400_ops = { + CHIP_NAME("ASpeed AST2400 Super I/O") + .enable_dev = enable_dev, +}; diff --git a/src/superio/aspeed/common/Kconfig b/src/superio/aspeed/common/Kconfig new file mode 100644 index 0000000..3f0dabb --- /dev/null +++ b/src/superio/aspeed/common/Kconfig @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Ronald G. Minnich +## Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> +## Copyright (C) 2018 Eltan B.V. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# Generic Aspeed preram driver - Just enough UART initialisation code for +# preram phase. +config SUPERIO_ASPEED_COMMON_PRE_RAM + bool + default n diff --git a/src/superio/aspeed/common/aspeed.h b/src/superio/aspeed/common/aspeed.h new file mode 100644 index 0000000..d3774ea --- /dev/null +++ b/src/superio/aspeed/common/aspeed.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_ASPEED_COMMON_ROMSTAGE_H +#define SUPERIO_ASPEED_COMMON_ROMSTAGE_H + +#include <arch/io.h> +#include <device/pnp_type.h> +#include <stdint.h> + +void aspeed_enable_serial(pnp_devfn_t dev, uint16_t iobase); + +void pnp_enter_conf_state(pnp_devfn_t dev); +void pnp_exit_conf_state(pnp_devfn_t dev); + +#endif /* SUPERIO_ASPEED_COMMON_ROMSTAGE_H */ diff --git a/src/superio/aspeed/common/early_serial.c b/src/superio/aspeed/common/early_serial.c new file mode 100644 index 0000000..7ac9474 --- /dev/null +++ b/src/superio/aspeed/common/early_serial.c @@ -0,0 +1,70 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * A generic pre-ram driver for Aspeed variant Super I/O chips. + * + * The following is derived directly from the vendor Aspeed's data-sheets: + * + * To toggle between `configuration mode` and `normal operation mode` as to + * manipulation the various LDN's in Aspeed Super I/O's we are required to + * pass magic numbers `passwords keys`. + * + * ASPEED_ENTRY_KEY := enable configuration : 0xA5 (twice!) + * ASPEED_EXIT_KEY := disable configuration : 0xAA + * + * To modify a LDN's configuration register, we use the index port to select + * the index of the LDN and then writing to the data port to alter the + * parameters. A default index, data port pair is 0x4E, 0x4F respectively, a + * user modified pair is 0x2E, 0x2F respectively. + * + */ + +#include <arch/io.h> +#include <device/pnp_def.h> +#include <device/pnp_ops.h> +#include <stdint.h> +#include "aspeed.h" + +#define ASPEED_ENTRY_KEY 0xA5 +#define ASPEED_EXIT_KEY 0xAA + +/* Enable configuration: pass entry key '0xA5' into index port dev. */ +void pnp_enter_conf_state(pnp_devfn_t dev) +{ + u16 port = dev >> 8; + outb(ASPEED_ENTRY_KEY, port); + outb(ASPEED_ENTRY_KEY, port); +} + +/* Disable configuration: pass exit key '0xAA' into index port dev. */ +void pnp_exit_conf_state(pnp_devfn_t dev) +{ + u16 port = dev >> 8; + outb(ASPEED_EXIT_KEY, port); +} + +/* Bring up early serial debugging output before the RAM is initialized. */ +void aspeed_enable_serial(pnp_devfn_t dev, u16 iobase) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + pnp_exit_conf_state(dev); +} diff --git a/src/superio/common/conf_mode.c b/src/superio/common/conf_mode.c index dec630b..8ba1cdd 100644 --- a/src/superio/common/conf_mode.c +++ b/src/superio/common/conf_mode.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Nico Huber <nico.h(a)gmx.de> + * Copyright (C) 2017-2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -48,6 +49,12 @@ outb(0xa0, dev->path.pnp.port); } +void pnp_enter_conf_mode_a5a5(struct device *dev) +{ + outb(0xa5, dev->path.pnp.port); + outb(0xa5, dev->path.pnp.port); +} + void pnp_exit_conf_mode_aa(struct device *dev) { outb(0xaa, dev->path.pnp.port); @@ -96,6 +103,11 @@ .exit_conf_mode = pnp_exit_conf_mode_aa, }; +const struct pnp_mode_ops pnp_conf_mode_a5a5_aa = { + .enter_conf_mode = pnp_enter_conf_mode_a5a5, + .exit_conf_mode = pnp_exit_conf_mode_aa, +}; + const struct pnp_mode_ops pnp_conf_mode_870155_aa = { .enter_conf_mode = pnp_enter_conf_mode_870155aa, .exit_conf_mode = pnp_exit_conf_mode_0202, -- To view, visit https://review.coreboot.org/c/coreboot/+/23135 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58fce31f0a2483e61e9d31f38ab5a059b8cf4f83 Gerrit-Change-Number: 23135 Gerrit-PatchSet: 31 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-MessageType: merged

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Change in ...coreboot[master]: mb/google/sarien: Modify ELAN Touchpad i2c bus clk
by EricR Lai (Code Review) 24 May '19

24 May '19

EricR Lai has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/30587 ) Change subject: mb/google/sarien: Modify ELAN Touchpad i2c bus clk ...................................................................... Abandoned no need -- To view, visit https://review.coreboot.org/c/coreboot/+/30587 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If98563ceadc4c17a2b66907f09d184d25ecbc96b Gerrit-Change-Number: 30587 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: abandon

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Change in ...coreboot[master]: mainboard/google/mistral: Add support for Mistral
by SANTHOSH JANARDHANA HASSAN (Code Review) 23 May '19

23 May '19

SANTHOSH JANARDHANA HASSAN has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29949 ) Change subject: mainboard/google/mistral: Add support for Mistral ...................................................................... Patch Set 14: (1 comment) https://review.coreboot.org/#/c/29949/14/src/mainboard/google/mistral/chrom… File src/mainboard/google/mistral/chromeos.fmd: https://review.coreboot.org/#/c/29949/14/src/mainboard/google/mistral/chrom… PS14, Line 25: RO_VPD 128K Add PRESERVE flag.Without this VPD data is lost if firmware is updated with this CL. Raise CL to fix this ASAP. -- To view, visit https://review.coreboot.org/c/coreboot/+/29949 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ecfad68bb50f42acf36f51bc3433add56597c3d Gerrit-Change-Number: 29949 Gerrit-PatchSet: 14 Gerrit-Owner: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: SANTHOSH JANARDHANA HASSAN <sahassan(a)google.com> Gerrit-CC: Sricharan Ramabadhran <srichara(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Thu, 23 May 2019 16:03:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: superio: Add ASpeed AST2400
by Felix Held (Code Review) 23 May '19

23 May '19

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/23135 ) Change subject: superio: Add ASpeed AST2400 ...................................................................... Patch Set 30: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/23135 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58fce31f0a2483e61e9d31f38ab5a059b8cf4f83 Gerrit-Change-Number: 23135 Gerrit-PatchSet: 30 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Comment-Date: Thu, 23 May 2019 14:57:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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