coreboot-gerrit May 2019

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Change in ...coreboot[master]: mb/lenovo: Unify thermal threshold handling
by Philipp Deppenwiese (Code Review) 25 May '19

25 May '19

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29659 ) Change subject: mb/lenovo: Unify thermal threshold handling ...................................................................... mb/lenovo: Unify thermal threshold handling Unify thermal handling across Lenovo boards (except g505, which is different). Namely, do the following: * Move thermal levels from acpi_tables to thermal.h (and create if necessary). * Don't use board-specific ifdef guards. * Set thermal levels using dedicated acpi_update_thermal_table function as almost all Lenovo boards do. * Update list of authors in comments. Merge all author's entries. * Minor whitespace and formatting. This makes diff -ruw between the Lenovo boards smaller. Change-Id: If569f67c932b7fbf14893b890a5588df4994daeb Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29659 Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/lenovo/l520/acpi_tables.c M src/mainboard/lenovo/l520/thermal.h M src/mainboard/lenovo/s230u/acpi_tables.c A src/mainboard/lenovo/s230u/thermal.h M src/mainboard/lenovo/t400/acpi_tables.c A src/mainboard/lenovo/t400/thermal.h M src/mainboard/lenovo/t420/thermal.h M src/mainboard/lenovo/t420s/thermal.h M src/mainboard/lenovo/t430/thermal.h M src/mainboard/lenovo/t430s/thermal.h M src/mainboard/lenovo/t520/acpi_tables.c M src/mainboard/lenovo/t520/thermal.h M src/mainboard/lenovo/t530/acpi_tables.c M src/mainboard/lenovo/t530/thermal.h M src/mainboard/lenovo/t60/acpi_tables.c A src/mainboard/lenovo/t60/thermal.h M src/mainboard/lenovo/x131e/thermal.h M src/mainboard/lenovo/x1_carbon_gen1/thermal.h M src/mainboard/lenovo/x200/acpi_tables.c A src/mainboard/lenovo/x200/thermal.h M src/mainboard/lenovo/x201/acpi_tables.c A src/mainboard/lenovo/x201/thermal.h M src/mainboard/lenovo/x220/thermal.h M src/mainboard/lenovo/x230/thermal.h M src/mainboard/lenovo/x60/acpi_tables.c A src/mainboard/lenovo/x60/thermal.h M src/mainboard/lenovo/z61t/acpi_tables.c A src/mainboard/lenovo/z61t/thermal.h 28 files changed, 402 insertions(+), 115 deletions(-) Approvals: build bot (Jenkins): Verified Philipp Deppenwiese: Looks good to me, approved Patrick Rudolph: Looks good to me, but someone else must approve diff --git a/src/mainboard/lenovo/l520/acpi_tables.c b/src/mainboard/lenovo/l520/acpi_tables.c index b861864..31f41e7 100644 --- a/src/mainboard/lenovo/l520/acpi_tables.c +++ b/src/mainboard/lenovo/l520/acpi_tables.c @@ -35,7 +35,6 @@ gnvs->s5u0 = 0; gnvs->s5u1 = 0; - // the lid is open by default. gnvs->lids = 1; diff --git a/src/mainboard/lenovo/l520/thermal.h b/src/mainboard/lenovo/l520/thermal.h index a2007ff..72953fd 100644 --- a/src/mainboard/lenovo/l520/thermal.h +++ b/src/mainboard/lenovo/l520/thermal.h @@ -2,7 +2,10 @@ * This file is part of the coreboot project. * * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> + * Copyright (C) 2017 James Ye <jye836(a)gmail.com> * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -15,13 +18,13 @@ * GNU General Public License for more details. */ -#ifndef L520_THERMAL_H -#define L520_THERMAL_H +#ifndef MAINBOARD_THERMAL_H +#define MAINBOARD_THERMAL_H - /* Temperature which OS will shutdown at */ - #define CRITICAL_TEMPERATURE 100 +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 - /* Temperature which OS will throttle CPU */ - #define PASSIVE_TEMPERATURE 90 +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 90 -#endif /* L520_THERMAL_H */ +#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/s230u/acpi_tables.c b/src/mainboard/lenovo/s230u/acpi_tables.c index 21fce85..8d6d93f 100644 --- a/src/mainboard/lenovo/s230u/acpi_tables.c +++ b/src/mainboard/lenovo/s230u/acpi_tables.c @@ -14,6 +14,13 @@ */ #include <southbridge/intel/bd82x6x/nvs.h> +#include "thermal.h" + +static void acpi_update_thermal_table(global_nvs_t *gnvs) +{ + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; +} void acpi_create_gnvs(global_nvs_t *gnvs) { @@ -28,6 +35,5 @@ /* The LID is open by default */ gnvs->lids = 1; - gnvs->tcrt = 100; - gnvs->tpsv = 90; + acpi_update_thermal_table(gnvs); } diff --git a/src/mainboard/lenovo/s230u/thermal.h b/src/mainboard/lenovo/s230u/thermal.h new file mode 100644 index 0000000..72953fd --- /dev/null +++ b/src/mainboard/lenovo/s230u/thermal.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> + * Copyright (C) 2017 James Ye <jye836(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_THERMAL_H +#define MAINBOARD_THERMAL_H + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 90 + +#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/t400/acpi_tables.c b/src/mainboard/lenovo/t400/acpi_tables.c index 301ca50..8fb9056 100644 --- a/src/mainboard/lenovo/t400/acpi_tables.c +++ b/src/mainboard/lenovo/t400/acpi_tables.c @@ -21,6 +21,13 @@ #include <device/device.h> #include <device/pci.h> #include <southbridge/intel/i82801ix/nvs.h> +#include "thermal.h" + +static void acpi_update_thermal_table(global_nvs_t *gnvs) +{ + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; +} void acpi_create_gnvs(global_nvs_t *gnvs) { @@ -32,9 +39,7 @@ gnvs->cmap = 0x01; gnvs->cmbp = 0x01; - /* Set thermal levels */ - gnvs->tcrt = 100; - gnvs->tpsv = 90; + acpi_update_thermal_table(gnvs); } unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/lenovo/t400/thermal.h b/src/mainboard/lenovo/t400/thermal.h new file mode 100644 index 0000000..72953fd --- /dev/null +++ b/src/mainboard/lenovo/t400/thermal.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> + * Copyright (C) 2017 James Ye <jye836(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_THERMAL_H +#define MAINBOARD_THERMAL_H + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 90 + +#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/t420/thermal.h b/src/mainboard/lenovo/t420/thermal.h index 6ca5b2a..72953fd 100644 --- a/src/mainboard/lenovo/t420/thermal.h +++ b/src/mainboard/lenovo/t420/thermal.h @@ -1,12 +1,16 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2008-2009 coresystems GmbH * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> + * Copyright (C) 2017 James Ye <jye836(a)gmail.com> * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -14,8 +18,8 @@ * GNU General Public License for more details. */ -#ifndef T420_THERMAL_H -#define T420_THERMAL_H +#ifndef MAINBOARD_THERMAL_H +#define MAINBOARD_THERMAL_H /* Temperature which OS will shutdown at */ #define CRITICAL_TEMPERATURE 100 @@ -23,4 +27,4 @@ /* Temperature which OS will throttle CPU */ #define PASSIVE_TEMPERATURE 90 -#endif +#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/t420s/thermal.h b/src/mainboard/lenovo/t420s/thermal.h index c7803e5..72953fd 100644 --- a/src/mainboard/lenovo/t420s/thermal.h +++ b/src/mainboard/lenovo/t420s/thermal.h @@ -1,12 +1,16 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2008-2009 coresystems GmbH * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> + * Copyright (C) 2017 James Ye <jye836(a)gmail.com> * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -14,13 +18,13 @@ * GNU General Public License for more details. */ -#ifndef T420S_THERMAL_H -#define T420S_THERMAL_H +#ifndef MAINBOARD_THERMAL_H +#define MAINBOARD_THERMAL_H - /* Temperature which OS will shutdown at */ - #define CRITICAL_TEMPERATURE 100 +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 - /* Temperature which OS will throttle CPU */ - #define PASSIVE_TEMPERATURE 90 +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 90 -#endif +#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/t430/thermal.h b/src/mainboard/lenovo/t430/thermal.h index e3e49f5..edfe3bc 100644 --- a/src/mainboard/lenovo/t430/thermal.h +++ b/src/mainboard/lenovo/t430/thermal.h @@ -1,12 +1,16 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2008-2009 coresystems GmbH * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> + * Copyright (C) 2017 James Ye <jye836(a)gmail.com> * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -14,8 +18,8 @@ * GNU General Public License for more details. */ -#ifndef _LENOVO_T430_THERMAL_H -#define _LENOVO_T430_THERMAL_H +#ifndef MAINBOARD_THERMAL_H +#define MAINBOARD_THERMAL_H /* Config TDP Sensor ID */ #define CTDP_SENSOR_ID 0 /* PECI */ @@ -37,4 +41,4 @@ /* Tj_max value for calculating PECI CPU temperature */ #define MAX_TEMPERATURE 105 -#endif +#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/t430s/thermal.h b/src/mainboard/lenovo/t430s/thermal.h index 1d55584..72953fd 100644 --- a/src/mainboard/lenovo/t430s/thermal.h +++ b/src/mainboard/lenovo/t430s/thermal.h @@ -1,12 +1,16 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2008-2009 coresystems GmbH * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> + * Copyright (C) 2017 James Ye <jye836(a)gmail.com> * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -14,8 +18,8 @@ * GNU General Public License for more details. */ -#ifndef T430S_THERMAL_H -#define T430S_THERMAL_H +#ifndef MAINBOARD_THERMAL_H +#define MAINBOARD_THERMAL_H /* Temperature which OS will shutdown at */ #define CRITICAL_TEMPERATURE 100 @@ -23,4 +27,4 @@ /* Temperature which OS will throttle CPU */ #define PASSIVE_TEMPERATURE 90 -#endif /* T430S_THERMAL_H */ +#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/t520/acpi_tables.c b/src/mainboard/lenovo/t520/acpi_tables.c index a3b0894..279674d 100644 --- a/src/mainboard/lenovo/t520/acpi_tables.c +++ b/src/mainboard/lenovo/t520/acpi_tables.c @@ -32,7 +32,6 @@ gnvs->s5u0 = 0; gnvs->s5u1 = 0; - // the lid is open by default. gnvs->lids = 1; diff --git a/src/mainboard/lenovo/t520/thermal.h b/src/mainboard/lenovo/t520/thermal.h index 60721bf..72953fd 100644 --- a/src/mainboard/lenovo/t520/thermal.h +++ b/src/mainboard/lenovo/t520/thermal.h @@ -1,12 +1,16 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2008-2009 coresystems GmbH * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> + * Copyright (C) 2017 James Ye <jye836(a)gmail.com> * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -14,13 +18,13 @@ * GNU General Public License for more details. */ -#ifndef T520_THERMAL_H -#define T520_THERMAL_H +#ifndef MAINBOARD_THERMAL_H +#define MAINBOARD_THERMAL_H - /* Temperature which OS will shutdown at */ - #define CRITICAL_TEMPERATURE 100 +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 - /* Temperature which OS will throttle CPU */ - #define PASSIVE_TEMPERATURE 90 +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 90 -#endif /* T520_THERMAL_H */ +#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/t530/acpi_tables.c b/src/mainboard/lenovo/t530/acpi_tables.c index a3b0894..279674d 100644 --- a/src/mainboard/lenovo/t530/acpi_tables.c +++ b/src/mainboard/lenovo/t530/acpi_tables.c @@ -32,7 +32,6 @@ gnvs->s5u0 = 0; gnvs->s5u1 = 0; - // the lid is open by default. gnvs->lids = 1; diff --git a/src/mainboard/lenovo/t530/thermal.h b/src/mainboard/lenovo/t530/thermal.h index 0b24ea8..72953fd 100644 --- a/src/mainboard/lenovo/t530/thermal.h +++ b/src/mainboard/lenovo/t530/thermal.h @@ -1,12 +1,16 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2008-2009 coresystems GmbH * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> + * Copyright (C) 2017 James Ye <jye836(a)gmail.com> * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -14,13 +18,13 @@ * GNU General Public License for more details. */ -#ifndef T530_THERMAL_H -#define T530_THERMAL_H +#ifndef MAINBOARD_THERMAL_H +#define MAINBOARD_THERMAL_H - /* Temperature which OS will shutdown at */ - #define CRITICAL_TEMPERATURE 100 +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 - /* Temperature which OS will throttle CPU */ - #define PASSIVE_TEMPERATURE 90 +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 90 -#endif /* T530_THERMAL_H */ +#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/t60/acpi_tables.c b/src/mainboard/lenovo/t60/acpi_tables.c index 183b7fe..bd10a0e 100644 --- a/src/mainboard/lenovo/t60/acpi_tables.c +++ b/src/mainboard/lenovo/t60/acpi_tables.c @@ -16,6 +16,13 @@ #include <stdint.h> #include <southbridge/intel/i82801gx/nvs.h> +#include "thermal.h" + +static void acpi_update_thermal_table(global_nvs_t *gnvs) +{ + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; +} void acpi_create_gnvs(global_nvs_t *gnvs) { @@ -23,7 +30,5 @@ gnvs->cmap = 0x01; gnvs->cmbp = 0x01; - /* Set thermal levels */ - gnvs->tcrt = 100; - gnvs->tpsv = 90; + acpi_update_thermal_table(gnvs); } diff --git a/src/mainboard/lenovo/t60/thermal.h b/src/mainboard/lenovo/t60/thermal.h new file mode 100644 index 0000000..72953fd --- /dev/null +++ b/src/mainboard/lenovo/t60/thermal.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> + * Copyright (C) 2017 James Ye <jye836(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_THERMAL_H +#define MAINBOARD_THERMAL_H + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 90 + +#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/x131e/thermal.h b/src/mainboard/lenovo/x131e/thermal.h index ff92869..72953fd 100644 --- a/src/mainboard/lenovo/x131e/thermal.h +++ b/src/mainboard/lenovo/x131e/thermal.h @@ -1,12 +1,16 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2008-2009 coresystems GmbH * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> * Copyright (C) 2017 James Ye <jye836(a)gmail.com> * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -14,15 +18,13 @@ * GNU General Public License for more details. */ -#ifndef X131E_THERMAL_H -#define X131E_THERMAL_H - -/* Active Thermal and fans are controlled by the EC. */ +#ifndef MAINBOARD_THERMAL_H +#define MAINBOARD_THERMAL_H /* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 100 +#define CRITICAL_TEMPERATURE 100 /* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 90 +#define PASSIVE_TEMPERATURE 90 -#endif /* X131E_THERMAL_H */ +#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/x1_carbon_gen1/thermal.h b/src/mainboard/lenovo/x1_carbon_gen1/thermal.h index 199c27e..72953fd 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/thermal.h +++ b/src/mainboard/lenovo/x1_carbon_gen1/thermal.h @@ -1,12 +1,16 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2008-2009 coresystems GmbH * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> + * Copyright (C) 2017 James Ye <jye836(a)gmail.com> * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -14,13 +18,13 @@ * GNU General Public License for more details. */ -#ifndef X230_THERMAL_H -#define X230_THERMAL_H +#ifndef MAINBOARD_THERMAL_H +#define MAINBOARD_THERMAL_H - /* Temperature which OS will shutdown at */ - #define CRITICAL_TEMPERATURE 100 +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 - /* Temperature which OS will throttle CPU */ - #define PASSIVE_TEMPERATURE 90 +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 90 -#endif +#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/x200/acpi_tables.c b/src/mainboard/lenovo/x200/acpi_tables.c index 301ca50..8fb9056 100644 --- a/src/mainboard/lenovo/x200/acpi_tables.c +++ b/src/mainboard/lenovo/x200/acpi_tables.c @@ -21,6 +21,13 @@ #include <device/device.h> #include <device/pci.h> #include <southbridge/intel/i82801ix/nvs.h> +#include "thermal.h" + +static void acpi_update_thermal_table(global_nvs_t *gnvs) +{ + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; +} void acpi_create_gnvs(global_nvs_t *gnvs) { @@ -32,9 +39,7 @@ gnvs->cmap = 0x01; gnvs->cmbp = 0x01; - /* Set thermal levels */ - gnvs->tcrt = 100; - gnvs->tpsv = 90; + acpi_update_thermal_table(gnvs); } unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/lenovo/x200/thermal.h b/src/mainboard/lenovo/x200/thermal.h new file mode 100644 index 0000000..72953fd --- /dev/null +++ b/src/mainboard/lenovo/x200/thermal.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> + * Copyright (C) 2017 James Ye <jye836(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_THERMAL_H +#define MAINBOARD_THERMAL_H + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 90 + +#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/x201/acpi_tables.c b/src/mainboard/lenovo/x201/acpi_tables.c index e412503..82991b2 100644 --- a/src/mainboard/lenovo/x201/acpi_tables.c +++ b/src/mainboard/lenovo/x201/acpi_tables.c @@ -17,10 +17,15 @@ #include <stdint.h> #include <southbridge/intel/ibexpeak/nvs.h> +#include "thermal.h" + +static void acpi_update_thermal_table(global_nvs_t *gnvs) +{ + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; +} void acpi_create_gnvs(global_nvs_t * gnvs) { - /* Set thermal levels */ - gnvs->tcrt = 100; - gnvs->tpsv = 90; + acpi_update_thermal_table(gnvs); } diff --git a/src/mainboard/lenovo/x201/thermal.h b/src/mainboard/lenovo/x201/thermal.h new file mode 100644 index 0000000..72953fd --- /dev/null +++ b/src/mainboard/lenovo/x201/thermal.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> + * Copyright (C) 2017 James Ye <jye836(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_THERMAL_H +#define MAINBOARD_THERMAL_H + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 90 + +#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/x220/thermal.h b/src/mainboard/lenovo/x220/thermal.h index 82df303..72953fd 100644 --- a/src/mainboard/lenovo/x220/thermal.h +++ b/src/mainboard/lenovo/x220/thermal.h @@ -1,12 +1,16 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2008-2009 coresystems GmbH * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> + * Copyright (C) 2017 James Ye <jye836(a)gmail.com> * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -14,13 +18,13 @@ * GNU General Public License for more details. */ -#ifndef X220_THERMAL_H -#define X220_THERMAL_H +#ifndef MAINBOARD_THERMAL_H +#define MAINBOARD_THERMAL_H - /* Temperature which OS will shutdown at */ - #define CRITICAL_TEMPERATURE 100 +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 - /* Temperature which OS will throttle CPU */ - #define PASSIVE_TEMPERATURE 90 +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 90 -#endif +#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/x230/thermal.h b/src/mainboard/lenovo/x230/thermal.h index 199c27e..72953fd 100644 --- a/src/mainboard/lenovo/x230/thermal.h +++ b/src/mainboard/lenovo/x230/thermal.h @@ -1,12 +1,16 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2008-2009 coresystems GmbH * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> + * Copyright (C) 2017 James Ye <jye836(a)gmail.com> * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -14,13 +18,13 @@ * GNU General Public License for more details. */ -#ifndef X230_THERMAL_H -#define X230_THERMAL_H +#ifndef MAINBOARD_THERMAL_H +#define MAINBOARD_THERMAL_H - /* Temperature which OS will shutdown at */ - #define CRITICAL_TEMPERATURE 100 +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 - /* Temperature which OS will throttle CPU */ - #define PASSIVE_TEMPERATURE 90 +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 90 -#endif +#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/x60/acpi_tables.c b/src/mainboard/lenovo/x60/acpi_tables.c index 183b7fe..bd10a0e 100644 --- a/src/mainboard/lenovo/x60/acpi_tables.c +++ b/src/mainboard/lenovo/x60/acpi_tables.c @@ -16,6 +16,13 @@ #include <stdint.h> #include <southbridge/intel/i82801gx/nvs.h> +#include "thermal.h" + +static void acpi_update_thermal_table(global_nvs_t *gnvs) +{ + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; +} void acpi_create_gnvs(global_nvs_t *gnvs) { @@ -23,7 +30,5 @@ gnvs->cmap = 0x01; gnvs->cmbp = 0x01; - /* Set thermal levels */ - gnvs->tcrt = 100; - gnvs->tpsv = 90; + acpi_update_thermal_table(gnvs); } diff --git a/src/mainboard/lenovo/x60/thermal.h b/src/mainboard/lenovo/x60/thermal.h new file mode 100644 index 0000000..72953fd --- /dev/null +++ b/src/mainboard/lenovo/x60/thermal.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> + * Copyright (C) 2017 James Ye <jye836(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_THERMAL_H +#define MAINBOARD_THERMAL_H + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 90 + +#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/z61t/acpi_tables.c b/src/mainboard/lenovo/z61t/acpi_tables.c index 3e9a810..bd10a0e 100644 --- a/src/mainboard/lenovo/z61t/acpi_tables.c +++ b/src/mainboard/lenovo/z61t/acpi_tables.c @@ -16,6 +16,13 @@ #include <stdint.h> #include <southbridge/intel/i82801gx/nvs.h> +#include "thermal.h" + +static void acpi_update_thermal_table(global_nvs_t *gnvs) +{ + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; +} void acpi_create_gnvs(global_nvs_t *gnvs) { @@ -23,4 +30,5 @@ gnvs->cmap = 0x01; gnvs->cmbp = 0x01; + acpi_update_thermal_table(gnvs); } diff --git a/src/mainboard/lenovo/z61t/thermal.h b/src/mainboard/lenovo/z61t/thermal.h new file mode 100644 index 0000000..72953fd --- /dev/null +++ b/src/mainboard/lenovo/z61t/thermal.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> + * Copyright (C) 2017 James Ye <jye836(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_THERMAL_H +#define MAINBOARD_THERMAL_H + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 90 + +#endif /* MAINBOARD_THERMAL_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/29659 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If569f67c932b7fbf14893b890a5588df4994daeb Gerrit-Change-Number: 29659 Gerrit-PatchSet: 6 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in ...coreboot[master]: console/post.c: Fix variable 'extra' set but not used
by HAOUAS Elyes (Code Review) 25 May '19

25 May '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32995 Change subject: console/post.c: Fix variable 'extra' set but not used ...................................................................... console/post.c: Fix variable 'extra' set but not used Change-Id: I678d62e78184a4bf99876df0bb96d6e05eacaf50 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/console/post.c 1 file changed, 4 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/32995/1 diff --git a/src/console/post.c b/src/console/post.c index 0719e5e..c7dada2 100644 --- a/src/console/post.c +++ b/src/console/post.c @@ -47,9 +47,7 @@ void cmos_post_log(void) { u8 code = 0; -#if CONFIG(CMOS_POST_EXTRA) u32 extra = 0; -#endif spin_lock(&cmos_post_lock); @@ -57,15 +55,13 @@ switch (cmos_read(CMOS_POST_BANK_OFFSET)) { case CMOS_POST_BANK_0_MAGIC: code = cmos_read(CMOS_POST_BANK_1_OFFSET); -#if CONFIG(CMOS_POST_EXTRA) - extra = cmos_read32(CMOS_POST_BANK_1_EXTRA); -#endif + if CONFIG(CMOS_POST_EXTRA) + extra = cmos_read32(CMOS_POST_BANK_1_EXTRA); break; case CMOS_POST_BANK_1_MAGIC: code = cmos_read(CMOS_POST_BANK_0_OFFSET); -#if CONFIG(CMOS_POST_EXTRA) - extra = cmos_read32(CMOS_POST_BANK_0_EXTRA); -#endif + if CONFIG(CMOS_POST_EXTRA) + extra = cmos_read32(CMOS_POST_BANK_0_EXTRA); break; } @@ -83,11 +79,9 @@ "in previous boot: 0x%02x\n", code); #if CONFIG(ELOG) && (ENV_RAMSTAGE || CONFIG(ELOG_PRERAM)) elog_add_event_word(ELOG_TYPE_LAST_POST_CODE, code); -#if CONFIG(CMOS_POST_EXTRA) if (extra) elog_add_event_dword(ELOG_TYPE_POST_EXTRA, extra); #endif -#endif } } -- To view, visit https://review.coreboot.org/c/coreboot/+/32995 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I678d62e78184a4bf99876df0bb96d6e05eacaf50 Gerrit-Change-Number: 32995 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 1

Change in ...coreboot[master]: src/cpu/amd/pi/00730F01: Add microcode update infrastructure for fam1...
by Kyösti Mälkki (Code Review) 25 May '19

25 May '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29272 ) Change subject: src/cpu/amd/pi/00730F01: Add microcode update infrastructure for fam16h PI ...................................................................... Patch Set 2: (2 comments) https://review.coreboot.org/#/c/29272/2/src/cpu/amd/pi/00730F01/microcode_f… File src/cpu/amd/pi/00730F01/microcode_fam16h.c: https://review.coreboot.org/#/c/29272/2/src/cpu/amd/pi/00730F01/microcode_f… PS2, Line 130: #if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK) #if CONFIG(...) https://review.coreboot.org/#/c/29272/2/src/cpu/amd/pi/00730F01/microcode_f… PS2, Line 150: "updates.\n"); Missing spin_unlock() and return here? Check for ucode_len > F16H_MPB_DATA_OFFSET to make sure there is at least some data, otherwise parsing the header is invalid access. -- To view, visit https://review.coreboot.org/c/coreboot/+/29272 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic15cba06f3cd9cfbc538b6764b158fa699f0ecf6 Gerrit-Change-Number: 29272 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Comment-Date: Sat, 25 May 2019 08:44:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: AGESA binaryPI: Add AGESA entry timestamps
by Kyösti Mälkki (Code Review) 25 May '19

25 May '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31515 Change subject: AGESA binaryPI: Add AGESA entry timestamps ...................................................................... AGESA binaryPI: Add AGESA entry timestamps Change-Id: I71e09d3bc4c8657979d447b90fb6ac7cae959479 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/drivers/amd/agesa/eventlog.c M src/drivers/amd/agesa/state_machine.c M src/northbridge/amd/agesa/state_machine.h 3 files changed, 37 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/31515/1 diff --git a/src/drivers/amd/agesa/eventlog.c b/src/drivers/amd/agesa/eventlog.c index 152011e..887da30 100644 --- a/src/drivers/amd/agesa/eventlog.c +++ b/src/drivers/amd/agesa/eventlog.c @@ -16,6 +16,7 @@ #include <console/console.h> #include <stdint.h> #include <string.h> +#include <timestamp.h> #include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/BiosCallOuts.h> @@ -30,54 +31,78 @@ { AGESA_STRUCT_NAME func; const char *name; + uint32_t entry_id; + uint32_t exit_id; }; static const struct agesa_mapping entrypoint[] = { { .func = AMD_INIT_RESET, .name = "AmdInitReset", + .entry_id = TS_AGESA_INIT_RESET_START, + .exit_id = TS_AGESA_INIT_RESET_DONE, }, { .func = AMD_INIT_EARLY, .name = "AmdInitEarly", + .entry_id = TS_AGESA_INIT_EARLY_START, + .exit_id = TS_AGESA_INIT_EARLY_DONE, }, { .func = AMD_INIT_POST, .name = "AmdInitPost", + .entry_id = TS_AGESA_INIT_POST_START, + .exit_id = TS_AGESA_INIT_POST_DONE, }, { .func = AMD_INIT_RESUME, .name = "AmdInitResume", + .entry_id = TS_AGESA_INIT_RESUME_START, + .exit_id = TS_AGESA_INIT_RESUME_DONE, }, { .func = AMD_INIT_ENV, .name = "AmdInitEnv", + .entry_id = TS_AGESA_INIT_ENV_START, + .exit_id = TS_AGESA_INIT_ENV_DONE, }, { .func = AMD_INIT_MID, .name = "AmdInitMid", + .entry_id = TS_AGESA_INIT_MID_START, + .exit_id = TS_AGESA_INIT_MID_DONE, }, { .func = AMD_INIT_LATE, .name = "AmdInitLate", + .entry_id = TS_AGESA_INIT_LATE_START, + .exit_id = TS_AGESA_INIT_LATE_DONE, }, { .func = AMD_S3LATE_RESTORE, .name = "AmdS3LateRestore", + .entry_id = TS_AGESA_S3_LATE_START, + .exit_id = TS_AGESA_S3_LATE_DONE, }, #if !defined(AMD_S3_SAVE_REMOVED) { .func = AMD_S3_SAVE, .name = "AmdS3Save", + .entry_id = TS_AGESA_INIT_RTB_START, + .exit_id = TS_AGESA_INIT_RTB_DONE, }, #endif { .func = AMD_S3FINAL_RESTORE, .name = "AmdS3FinalRestore", + .entry_id = TS_AGESA_S3_FINAL_START, + .exit_id = TS_AGESA_S3_FINAL_DONE, }, { .func = AMD_INIT_RTB, .name = "AmdInitRtb", + .entry_id = TS_AGESA_INIT_RTB_START, + .exit_id = TS_AGESA_INIT_RTB_DONE, }, }; @@ -92,6 +117,8 @@ for (i = 0; i < ARRAY_SIZE(entrypoint); i++) { if (task->func == entrypoint[i].func) { task->function_name = entrypoint[i].name; + task->ts_entry_id = entrypoint[i].entry_id; + task->ts_exit_id = entrypoint[i].exit_id; break; } } diff --git a/src/drivers/amd/agesa/state_machine.c b/src/drivers/amd/agesa/state_machine.c index f676192..4d56218 100644 --- a/src/drivers/amd/agesa/state_machine.c +++ b/src/drivers/amd/agesa/state_machine.c @@ -21,6 +21,8 @@ #include <arch/cpu.h> #include <bootstate.h> #include <cbfs.h> +#include <cbmem.h> +#include <timestamp.h> #include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/agesa_helper.h> @@ -263,12 +265,18 @@ AMD_CONFIG_PARAMS *StdHeader = aip.NewStructPtr; ASSERT(StdHeader->Func == func); + if (task.ts_entry_id) + timestamp_add_now(task.ts_entry_id); + if (ENV_ROMSTAGE) final = romstage_dispatch(cb, func, StdHeader); if (ENV_RAMSTAGE) final = ramstage_dispatch(cb, func, StdHeader); + if (task.ts_exit_id) + timestamp_add_now(task.ts_exit_id); + agesawrapper_trace(final, StdHeader, task.function_name); ASSERT(final < AGESA_FATAL); diff --git a/src/northbridge/amd/agesa/state_machine.h b/src/northbridge/amd/agesa/state_machine.h index 45d57c2..f1dd139 100644 --- a/src/northbridge/amd/agesa/state_machine.h +++ b/src/northbridge/amd/agesa/state_machine.h @@ -60,6 +60,8 @@ AGESA_STRUCT_NAME func; const char *function_name; + uint32_t ts_entry_id; + uint32_t ts_exit_id; }; void agesa_state_on_entry(struct agesa_state *task, AGESA_STRUCT_NAME func); -- To view, visit https://review.coreboot.org/c/coreboot/+/31515 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71e09d3bc4c8657979d447b90fb6ac7cae959479 Gerrit-Change-Number: 31515 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 5

Change in ...coreboot[master]: AGESA binaryPI: Redo entrypoints namelist
by Kyösti Mälkki (Code Review) 25 May '19

25 May '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31514 Change subject: AGESA binaryPI: Redo entrypoints namelist ...................................................................... AGESA binaryPI: Redo entrypoints namelist Stop assuming the list is complete with no gaps, and use a lookup-table to match AGESA_STRUCT_NAME types of the entrypoints we use with names. Change-Id: Ibef4690d8aa76ff5b47c879f5ceb9d8fc4c4c4cd Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/drivers/amd/agesa/eventlog.c 1 file changed, 62 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/31514/1 diff --git a/src/drivers/amd/agesa/eventlog.c b/src/drivers/amd/agesa/eventlog.c index 303af53..152011e 100644 --- a/src/drivers/amd/agesa/eventlog.c +++ b/src/drivers/amd/agesa/eventlog.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Kyösti Mälkki + * Copyright (C) 2016-2019 Kyösti Mälkki * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -26,45 +26,75 @@ static const char undefined[] = "undefined"; -/* Match order of enum AGESA_STRUCT_NAME. */ -static const char *AgesaFunctionNameStr[] = { - "AmdInitRecovery", "AmdCreateStruct", "AmdInitEarly", "AmdInitEnv", "AmdInitLate", - "AmdInitMid", "AmdInitPost", "AmdInitReset", "AmdInitResume", "AmdReleaseStruct", - "AmdS3LateRestore", "AmdS3Save", "AmdGetApicId", "AmdGetPciAddress", "AmdIdentifyCore", - "AmdReadEventLog", "AmdGetAvailableExeCacheSize", "AmdLateRunApTask", "AmdIdentifyDimm", - "Amd2dDataEye", "AmdS3FinalRestore", "AmdInitRtb" +struct agesa_mapping +{ + AGESA_STRUCT_NAME func; + const char *name; }; -/* This function has to match with enumeration of AGESA_STRUCT_NAME defined - * inside AMD.h header file. Unfortunately those are different across - * different vendorcode subtrees. - * - * TBD: Fix said header or move this function together with the strings above - * under vendorcode/ tree. - */ - -static const char *agesa_struct_name(AGESA_STRUCT_NAME state) -{ -#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_OPENSOURCE) - if ((state < AMD_INIT_RECOVERY) || (state > AMD_IDENTIFY_DIMMS)) - return undefined; - - int index = state - AMD_INIT_RECOVERY; -#else - state >>= 12; - if ((state < AMD_INIT_RECOVERY >> 12) || (state > AMD_IDENTIFY_DIMMS >> 12)) - return undefined; - - int index = state - (AMD_INIT_RECOVERY >> 12); +static const struct agesa_mapping entrypoint[] = { + { + .func = AMD_INIT_RESET, + .name = "AmdInitReset", + }, + { + .func = AMD_INIT_EARLY, + .name = "AmdInitEarly", + }, + { + .func = AMD_INIT_POST, + .name = "AmdInitPost", + }, + { + .func = AMD_INIT_RESUME, + .name = "AmdInitResume", + }, + { + .func = AMD_INIT_ENV, + .name = "AmdInitEnv", + }, + { + .func = AMD_INIT_MID, + .name = "AmdInitMid", + }, + { + .func = AMD_INIT_LATE, + .name = "AmdInitLate", + }, + { + .func = AMD_S3LATE_RESTORE, + .name = "AmdS3LateRestore", + }, +#if !defined(AMD_S3_SAVE_REMOVED) + { + .func = AMD_S3_SAVE, + .name = "AmdS3Save", + }, #endif - return AgesaFunctionNameStr[index]; -} + { + .func = AMD_S3FINAL_RESTORE, + .name = "AmdS3FinalRestore", + }, + { + .func = AMD_INIT_RTB, + .name = "AmdInitRtb", + }, +}; void agesa_state_on_entry(struct agesa_state *task, AGESA_STRUCT_NAME func) { + int i; + task->apic_id = (u8) (cpuid_ebx(1) >> 24); task->func = func; - task->function_name = agesa_struct_name(func); + task->function_name = undefined; + + for (i = 0; i < ARRAY_SIZE(entrypoint); i++) { + if (task->func == entrypoint[i].func) { + task->function_name = entrypoint[i].name; + break; + } + } printk(BIOS_DEBUG, "\nAPIC %02d: ** Enter %s [%08x]\n", task->apic_id, task->function_name, task->func); -- To view, visit https://review.coreboot.org/c/coreboot/+/31514 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibef4690d8aa76ff5b47c879f5ceb9d8fc4c4c4cd Gerrit-Change-Number: 31514 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 3

Change in ...coreboot[master]: AGESA: Move debug helper to eventlog file
by Kyösti Mälkki (Code Review) 25 May '19

25 May '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31513 Change subject: AGESA: Move debug helper to eventlog file ...................................................................... AGESA: Move debug helper to eventlog file Change-Id: I2d74f934936e250886526b9c8482f500628a1158 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/drivers/amd/agesa/eventlog.c M src/drivers/amd/agesa/state_machine.c M src/northbridge/amd/agesa/state_machine.h 3 files changed, 40 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/31513/1 diff --git a/src/drivers/amd/agesa/eventlog.c b/src/drivers/amd/agesa/eventlog.c index b80c220..303af53 100644 --- a/src/drivers/amd/agesa/eventlog.c +++ b/src/drivers/amd/agesa/eventlog.c @@ -1,6 +1,8 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2016 Kyösti Mälkki + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -18,6 +20,7 @@ #include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include <amdlib.h> +#include <debug_util.h> #include <AGESA.h> #include <AMD.h> @@ -40,7 +43,7 @@ * under vendorcode/ tree. */ -const char *agesa_struct_name(int state) +static const char *agesa_struct_name(AGESA_STRUCT_NAME state) { #if IS_ENABLED(CONFIG_CPU_AMD_AGESA_OPENSOURCE) if ((state < AMD_INIT_RECOVERY) || (state > AMD_IDENTIFY_DIMMS)) @@ -57,6 +60,27 @@ return AgesaFunctionNameStr[index]; } +void agesa_state_on_entry(struct agesa_state *task, AGESA_STRUCT_NAME func) +{ + task->apic_id = (u8) (cpuid_ebx(1) >> 24); + task->func = func; + task->function_name = agesa_struct_name(func); + + printk(BIOS_DEBUG, "\nAPIC %02d: ** Enter %s [%08x]\n", + task->apic_id, task->function_name, task->func); +} + +void agesa_state_on_exit(struct agesa_state *task, + AMD_CONFIG_PARAMS *StdHeader) +{ + printk(BIOS_DEBUG, "APIC %02d: Heap in %s (%d) at 0x%08x\n", + task->apic_id, heap_status_name(StdHeader->HeapStatus), + StdHeader->HeapStatus, (u32)StdHeader->HeapBasePtr); + + printk(BIOS_DEBUG, "APIC %02d: ** Exit %s [%08x]\n", + task->apic_id, task->function_name, task->func); +} + /* * Possible AGESA_STATUS values: * diff --git a/src/drivers/amd/agesa/state_machine.c b/src/drivers/amd/agesa/state_machine.c index 672bca1..f676192 100644 --- a/src/drivers/amd/agesa/state_machine.c +++ b/src/drivers/amd/agesa/state_machine.c @@ -27,7 +27,6 @@ #include <northbridge/amd/agesa/BiosCallOuts.h> #include <amdlib.h> -#include <debug_util.h> #include <AMD.h> #if IS_ENABLED(CONFIG_CPU_AMD_AGESA_OPENSOURCE) @@ -232,38 +231,6 @@ return status; } -/* DEBUG trace helper */ - -struct agesa_state -{ - u8 apic_id; - - AGESA_STRUCT_NAME func; - const char *function_name; -}; - -static void state_on_entry(struct agesa_state *task, AGESA_STRUCT_NAME func, - const char *struct_name) -{ - task->apic_id = (u8) (cpuid_ebx(1) >> 24); - task->func = func; - task->function_name = struct_name; - - printk(BIOS_DEBUG, "\nAPIC %02d: ** Enter %s [%08x]\n", - task->apic_id, task->function_name, task->func); -} - -static void state_on_exit(struct agesa_state *task, - AMD_CONFIG_PARAMS *StdHeader) -{ - printk(BIOS_DEBUG, "APIC %02d: Heap in %s (%d) at 0x%08x\n", - task->apic_id, heap_status_name(StdHeader->HeapStatus), - StdHeader->HeapStatus, (u32)StdHeader->HeapBasePtr); - - printk(BIOS_DEBUG, "APIC %02d: ** Exit %s [%08x]\n", - task->apic_id, task->function_name, task->func); -} - int agesa_execute_state(struct sysinfo *cb, AGESA_STRUCT_NAME func) { AMD_INTERFACE_PARAMS aip; @@ -273,13 +240,12 @@ } agesa_params; void *buf = NULL; size_t len = 0; - const char *state_name = agesa_struct_name(func); AGESA_STATUS status, final; struct agesa_state task; memset(&task, 0, sizeof(task)); - state_on_entry(&task, func, state_name); + agesa_state_on_entry(&task, func); aip.StdHeader = cb->StdHeader; @@ -303,13 +269,13 @@ if (ENV_RAMSTAGE) final = ramstage_dispatch(cb, func, StdHeader); - agesawrapper_trace(final, StdHeader, state_name); + agesawrapper_trace(final, StdHeader, task.function_name); ASSERT(final < AGESA_FATAL); status = amd_release_struct(&aip); ASSERT(status == AGESA_SUCCESS); - state_on_exit(&task, &aip.StdHeader); + agesa_state_on_exit(&task, &aip.StdHeader); return (final < AGESA_FATAL) ? 0 : -1; } diff --git a/src/northbridge/amd/agesa/state_machine.h b/src/northbridge/amd/agesa/state_machine.h index c7d654d..45d57c2 100644 --- a/src/northbridge/amd/agesa/state_machine.h +++ b/src/northbridge/amd/agesa/state_machine.h @@ -23,7 +23,6 @@ #define HAS_LEGACY_WRAPPER IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER) /* eventlog */ -const char *agesa_struct_name(int state); void agesawrapper_trace(AGESA_STATUS ret, AMD_CONFIG_PARAMS *StdHeader, const char *func); AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus); @@ -54,6 +53,18 @@ void platform_once(struct sysinfo *cb); void agesa_set_interface(struct sysinfo *cb); + +struct agesa_state +{ + u8 apic_id; + + AGESA_STRUCT_NAME func; + const char *function_name; +}; + +void agesa_state_on_entry(struct agesa_state *task, AGESA_STRUCT_NAME func); +void agesa_state_on_exit(struct agesa_state *task, + AMD_CONFIG_PARAMS *StdHeader); int agesa_execute_state(struct sysinfo *cb, AGESA_STRUCT_NAME func); /* AGESA dispatchers */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31513 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d74f934936e250886526b9c8482f500628a1158 Gerrit-Change-Number: 31513 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 3

Change in ...coreboot[master]: AGESA f12 f14 vendorcofe: Clean up extra CFLAGS
by Kyösti Mälkki (Code Review) 25 May '19

25 May '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31512 Change subject: AGESA f12 f14 vendorcofe: Clean up extra CFLAGS ...................................................................... AGESA f12 f14 vendorcofe: Clean up extra CFLAGS Extra variable is no longer required here. Change-Id: I2a6839ee0349e3019de3b2a91f9e7bb1c435603d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/vendorcode/amd/agesa/f12/Makefile.inc M src/vendorcode/amd/agesa/f14/Makefile.inc 2 files changed, 4 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/31512/1 diff --git a/src/vendorcode/amd/agesa/f12/Makefile.inc b/src/vendorcode/amd/agesa/f12/Makefile.inc index dbea9c3..9bc3c26 100644 --- a/src/vendorcode/amd/agesa/f12/Makefile.inc +++ b/src/vendorcode/amd/agesa/f12/Makefile.inc @@ -43,12 +43,8 @@ CFLAGS_x86_32 += -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing CFLAGS_x86_64 += -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing -# These are invalid, coreboot proper should not require -# use of AGESA internal header files. -CPPFLAGS_x86_ANY = - -CPPFLAGS_x86_32 += $(AGESA_INC) $(CPPFLAGS_x86_ANY) -CPPFLAGS_x86_64 += $(AGESA_INC) $(CPPFLAGS_x86_ANY) +CPPFLAGS_x86_32 += $(AGESA_INC) +CPPFLAGS_x86_64 += $(AGESA_INC) ####################################################################### diff --git a/src/vendorcode/amd/agesa/f14/Makefile.inc b/src/vendorcode/amd/agesa/f14/Makefile.inc index bf1051c..da79a39 100644 --- a/src/vendorcode/amd/agesa/f14/Makefile.inc +++ b/src/vendorcode/amd/agesa/f14/Makefile.inc @@ -43,12 +43,8 @@ CFLAGS_x86_32 += -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing CFLAGS_x86_64 += -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing -# These are invalid, coreboot proper should not require -# use of AGESA internal header files. -CPPFLAGS_x86_ANY = - -CPPFLAGS_x86_32 += $(AGESA_INC) $(CPPFLAGS_x86_ANY) -CPPFLAGS_x86_64 += $(AGESA_INC) $(CPPFLAGS_x86_ANY) +CPPFLAGS_x86_32 += $(AGESA_INC) +CPPFLAGS_x86_64 += $(AGESA_INC) ####################################################################### -- To view, visit https://review.coreboot.org/c/coreboot/+/31512 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a6839ee0349e3019de3b2a91f9e7bb1c435603d Gerrit-Change-Number: 31512 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

4 4

Change in ...coreboot[master]: AGESA: Move heap_status_name() implementation
by Kyösti Mälkki (Code Review) 25 May '19

25 May '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31511 Change subject: AGESA: Move heap_status_name() implementation ...................................................................... AGESA: Move heap_status_name() implementation Place it within class libagesa to avoid including AGESA internal header heapManager.h in coreboot proper build CPPFLAGS. Change-Id: Iae86d6631d7a6ba6ea2588a53b292b435dfd7861 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/drivers/amd/agesa/eventlog.c M src/drivers/amd/agesa/state_machine.c M src/northbridge/amd/agesa/state_machine.h M src/vendorcode/amd/agesa/common/Makefile.inc A src/vendorcode/amd/agesa/common/debug_util.c A src/vendorcode/amd/agesa/common/debug_util.h M src/vendorcode/amd/agesa/f12/Makefile.inc M src/vendorcode/amd/agesa/f14/Makefile.inc M src/vendorcode/amd/agesa/f15tn/Makefile.inc M src/vendorcode/amd/agesa/f16kb/Makefile.inc 10 files changed, 34 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/31511/1 diff --git a/src/drivers/amd/agesa/eventlog.c b/src/drivers/amd/agesa/eventlog.c index 3231d4f..b80c220 100644 --- a/src/drivers/amd/agesa/eventlog.c +++ b/src/drivers/amd/agesa/eventlog.c @@ -21,8 +21,6 @@ #include <AGESA.h> #include <AMD.h> -#include <heapManager.h> - static const char undefined[] = "undefined"; /* Match order of enum AGESA_STRUCT_NAME. */ @@ -34,11 +32,6 @@ "Amd2dDataEye", "AmdS3FinalRestore", "AmdInitRtb" }; -/* heapManager.h */ -static const char *HeapStatusStr[] = { - "DoNotExistYet", "LocalCache", "TempMem", "SystemMem", "DoNotExistAnymore","S3Resume" -}; - /* This function has to match with enumeration of AGESA_STRUCT_NAME defined * inside AMD.h header file. Unfortunately those are different across * different vendorcode subtrees. @@ -64,15 +57,6 @@ return AgesaFunctionNameStr[index]; } -const char *heap_status_name(int status) -{ - if ((status < HEAP_DO_NOT_EXIST_YET) || (status > HEAP_S3_RESUME)) - return undefined; - - int index = status - HEAP_DO_NOT_EXIST_YET; - return HeapStatusStr[index]; -} - /* * Possible AGESA_STATUS values: * diff --git a/src/drivers/amd/agesa/state_machine.c b/src/drivers/amd/agesa/state_machine.c index 15ea211..672bca1 100644 --- a/src/drivers/amd/agesa/state_machine.c +++ b/src/drivers/amd/agesa/state_machine.c @@ -27,6 +27,7 @@ #include <northbridge/amd/agesa/BiosCallOuts.h> #include <amdlib.h> +#include <debug_util.h> #include <AMD.h> #if IS_ENABLED(CONFIG_CPU_AMD_AGESA_OPENSOURCE) diff --git a/src/northbridge/amd/agesa/state_machine.h b/src/northbridge/amd/agesa/state_machine.h index 43b205a..c7d654d 100644 --- a/src/northbridge/amd/agesa/state_machine.h +++ b/src/northbridge/amd/agesa/state_machine.h @@ -24,7 +24,6 @@ /* eventlog */ const char *agesa_struct_name(int state); -const char *heap_status_name(int status); void agesawrapper_trace(AGESA_STATUS ret, AMD_CONFIG_PARAMS *StdHeader, const char *func); AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus); diff --git a/src/vendorcode/amd/agesa/common/Makefile.inc b/src/vendorcode/amd/agesa/common/Makefile.inc index 78dd4fc..2479694 100644 --- a/src/vendorcode/amd/agesa/common/Makefile.inc +++ b/src/vendorcode/amd/agesa/common/Makefile.inc @@ -30,6 +30,7 @@ romstage-y += agesa-entry.c ramstage-y += agesa-entry.c +libagesa-y += debug_util.c libagesa-y += amdlib.c # Do not optimise performance-critical low-level IO for size with -Os, diff --git a/src/vendorcode/amd/agesa/common/debug_util.c b/src/vendorcode/amd/agesa/common/debug_util.c new file mode 100644 index 0000000..29d0841 --- /dev/null +++ b/src/vendorcode/amd/agesa/common/debug_util.c @@ -0,0 +1,24 @@ + +#include <AGESA.h> +#include <AMD.h> +#include <heapManager.h> + +#include "debug_util.h" + +static const char undefined[] = "undefined"; + +static const char *HeapStatusStr[] = { + "DoNotExistYet", "LocalCache", "TempMem", "SystemMem", "DoNotExistAnymore","S3Resume" +}; + +/* This function has to match with enumeration of XXXX defined + * inside heapManager.h header file. + */ +const char *heap_status_name(UINT8 HeapStatus) +{ + if ((HeapStatus < HEAP_DO_NOT_EXIST_YET) || (HeapStatus > HEAP_S3_RESUME)) + return undefined; + + int index = HeapStatus - HEAP_DO_NOT_EXIST_YET; + return HeapStatusStr[index]; +} diff --git a/src/vendorcode/amd/agesa/common/debug_util.h b/src/vendorcode/amd/agesa/common/debug_util.h new file mode 100644 index 0000000..a8d9a33 --- /dev/null +++ b/src/vendorcode/amd/agesa/common/debug_util.h @@ -0,0 +1,8 @@ +#ifndef __AGESA_DEBUG_UTIL_H__ +#define __AGESA_DEBUG_UTIL_H__ + +#include "AMD.h" + +const char *heap_status_name(UINT8 HeapStatus); + +#endif diff --git a/src/vendorcode/amd/agesa/f12/Makefile.inc b/src/vendorcode/amd/agesa/f12/Makefile.inc index f925ccb..dbea9c3 100644 --- a/src/vendorcode/amd/agesa/f12/Makefile.inc +++ b/src/vendorcode/amd/agesa/f12/Makefile.inc @@ -46,7 +46,6 @@ # These are invalid, coreboot proper should not require # use of AGESA internal header files. CPPFLAGS_x86_ANY = -CPPFLAGS_x86_ANY += -I$(AGESA_ROOT)/Proc/CPU # heapManager.h CPPFLAGS_x86_32 += $(AGESA_INC) $(CPPFLAGS_x86_ANY) CPPFLAGS_x86_64 += $(AGESA_INC) $(CPPFLAGS_x86_ANY) diff --git a/src/vendorcode/amd/agesa/f14/Makefile.inc b/src/vendorcode/amd/agesa/f14/Makefile.inc index ad2d2dc..bf1051c 100644 --- a/src/vendorcode/amd/agesa/f14/Makefile.inc +++ b/src/vendorcode/amd/agesa/f14/Makefile.inc @@ -46,8 +46,6 @@ # These are invalid, coreboot proper should not require # use of AGESA internal header files. CPPFLAGS_x86_ANY = -CPPFLAGS_x86_ANY += -I$(AGESA_ROOT)/Proc/CPU # heapManager.h -CPPFLAGS_x86_ANY += -I$(AGESA_ROOT)/Proc/CPU/Family CPPFLAGS_x86_32 += $(AGESA_INC) $(CPPFLAGS_x86_ANY) CPPFLAGS_x86_64 += $(AGESA_INC) $(CPPFLAGS_x86_ANY) diff --git a/src/vendorcode/amd/agesa/f15tn/Makefile.inc b/src/vendorcode/amd/agesa/f15tn/Makefile.inc index 57350d9..1c5dc18 100644 --- a/src/vendorcode/amd/agesa/f15tn/Makefile.inc +++ b/src/vendorcode/amd/agesa/f15tn/Makefile.inc @@ -46,8 +46,6 @@ # These are invalid, coreboot proper should not require # use of AGESA internal header files. CPPFLAGS_x86_ANY = -CPPFLAGS_x86_ANY += -I$(AGESA_ROOT)/Proc/CPU # heapManager.h -CPPFLAGS_x86_ANY += -I$(AGESA_ROOT)/Proc/CPU/Family CPPFLAGS_x86_ANY += -I$(AGESA_ROOT)/Proc/Fch # FchPlatform.h CPPFLAGS_x86_ANY += -I$(AGESA_ROOT)/Proc/Fch/Common # FchCommonCfg.h diff --git a/src/vendorcode/amd/agesa/f16kb/Makefile.inc b/src/vendorcode/amd/agesa/f16kb/Makefile.inc index 3115c4d..c423cf2 100644 --- a/src/vendorcode/amd/agesa/f16kb/Makefile.inc +++ b/src/vendorcode/amd/agesa/f16kb/Makefile.inc @@ -46,8 +46,6 @@ # These are invalid, coreboot proper should not require # use of AGESA internal header files. CPPFLAGS_x86_ANY = -CPPFLAGS_x86_ANY += -I$(AGESA_ROOT)/Proc/CPU # heapManager.h -CPPFLAGS_x86_ANY += -I$(AGESA_ROOT)/Proc/CPU/Family CPPFLAGS_x86_ANY += -I$(AGESA_ROOT)/Proc/Fch # FchPlatform.h CPPFLAGS_x86_ANY += -I$(AGESA_ROOT)/Proc/Fch/Common # FchCommonCfg.h -- To view, visit https://review.coreboot.org/c/coreboot/+/31511 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae86d6631d7a6ba6ea2588a53b292b435dfd7861 Gerrit-Change-Number: 31511 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 9

Change in ...coreboot[master]: [Test] Remaining unused variables
by HAOUAS Elyes (Code Review) 25 May '19

25 May '19

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29926 to look at the new patch set (#32). Change subject: [Test] Remaining unused variables ...................................................................... [Test] Remaining unused variables Change-Id: Ic3dde296ab4b84add8a8ab6a3bb5ecb65da2c158 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M Makefile.inc 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/29926/32 -- To view, visit https://review.coreboot.org/c/coreboot/+/29926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3dde296ab4b84add8a8ab6a3bb5ecb65da2c158 Gerrit-Change-Number: 29926 Gerrit-PatchSet: 32 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: src/cpu/amd/pi/00730F01: Add microcode update infrastructure for fam1...
by mikeb mikeb (Code Review) 25 May '19

25 May '19

mikeb mikeb has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29272 ) Change subject: src/cpu/amd/pi/00730F01: Add microcode update infrastructure for fam16h PI ...................................................................... Patch Set 2: Michal, please read my comment here about the shortcomings of this "microcode update infrastructure" - https://review.coreboot.org/c/coreboot/+/28273/6#message-cbbdcce72362a39ad3… (and why I didn't want to port it for some other AMD boards). Is your implementation affected by these shortcomings as well? -- To view, visit https://review.coreboot.org/c/coreboot/+/29272 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic15cba06f3cd9cfbc538b6764b158fa699f0ecf6 Gerrit-Change-Number: 29272 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Comment-Date: Sat, 25 May 2019 07:35:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit May 2019