coreboot-gerrit May 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: cpu/intel/model_2065x: Put stage cache in TSEG
by Patrick Rudolph (Code Review) 26 May '19

26 May '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/26298 ) Change subject: cpu/intel/model_2065x: Put stage cache in TSEG ...................................................................... Patch Set 42: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/26298 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I89cbfb6ece62f554ac676fe686115e841d2c1e40 Gerrit-Change-Number: 26298 Gerrit-PatchSet: 42 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 26 May 2019 08:38:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: cpu/intel/model_2065x: Use parallel MP init
by Patrick Rudolph (Code Review) 26 May '19

26 May '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/26297 ) Change subject: cpu/intel/model_2065x: Use parallel MP init ...................................................................... Patch Set 38: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/26297 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I56b352f9d76ee58f5c82cd431a4e0fa206f848a0 Gerrit-Change-Number: 26297 Gerrit-PatchSet: 38 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matthias Gazzari <mail(a)qtux.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 26 May 2019 08:37:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: sb/intel/ibexpeak: Use common Intel SMM code
by Patrick Rudolph (Code Review) 26 May '19

26 May '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/26296 ) Change subject: sb/intel/ibexpeak: Use common Intel SMM code ...................................................................... Patch Set 38: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/26296 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc2d8f7755ace598e66b162d071d472093e4656e Gerrit-Change-Number: 26296 Gerrit-PatchSet: 38 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 26 May 2019 08:37:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: intel/sandybridge: Make timC training more robust.
by Arthur Heymans (Code Review) 26 May '19

26 May '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/22776 ) Change subject: intel/sandybridge: Make timC training more robust. ...................................................................... Patch Set 3: (3 comments) https://review.coreboot.org/#/c/22776/3/src/northbridge/intel/sandybridge/r… File src/northbridge/intel/sandybridge/raminit_common.c: https://review.coreboot.org/#/c/22776/3/src/northbridge/intel/sandybridge/r… PS3, Line 1577: rn.length < 8 Why? 0 errors is 0 errors... https://review.coreboot.org/#/c/22776/3/src/northbridge/intel/sandybridge/r… PS3, Line 1578: printk(BIOS_EMERG, "timC discovery failed: %d, %d, %d\n", : channel, slotrank, lane); I'd change the is message. https://review.coreboot.org/#/c/22776/3/src/northbridge/intel/sandybridge/r… PS3, Line 1581: avarage The average is a very high since most of the entries will have the max (4000) errors. Would a rather small (let's say 20-50) threshold above the min value not result in better statistics? -- To view, visit https://review.coreboot.org/c/coreboot/+/22776 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9986616e86560c4980ccd8e3e549af53caa15c71 Gerrit-Change-Number: 22776 Gerrit-PatchSet: 3 Gerrit-Owner: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 26 May 2019 07:46:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: intel/sandybridge: Make timC training more robust.
by Patrick Rudolph (Code Review) 26 May '19

26 May '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/22776 ) Change subject: intel/sandybridge: Make timC training more robust. ...................................................................... Patch Set 3: > Patch Set 2: > > I'd prefer this somewhat crude method to only be used in the case of 'failing' lanes instead of all the time. done. -- To view, visit https://review.coreboot.org/c/coreboot/+/22776 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9986616e86560c4980ccd8e3e549af53caa15c71 Gerrit-Change-Number: 22776 Gerrit-PatchSet: 3 Gerrit-Owner: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 26 May 2019 06:31:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: intel/sandybridge: Make timC training more robust.
by build bot (Jenkins) (Code Review) 26 May '19

26 May '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/22776 ) Change subject: intel/sandybridge: Make timC training more robust. ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/#/c/22776/3/src/northbridge/intel/sandybridge/r… File src/northbridge/intel/sandybridge/raminit_common.c: https://review.coreboot.org/#/c/22776/3/src/northbridge/intel/sandybridge/r… PS3, Line 1580: /* With command training not happend yet, the lane can 'happend' may be misspelled - perhaps 'happened'? -- To view, visit https://review.coreboot.org/c/coreboot/+/22776 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9986616e86560c4980ccd8e3e549af53caa15c71 Gerrit-Change-Number: 22776 Gerrit-PatchSet: 3 Gerrit-Owner: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 26 May 2019 06:31:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: intel/sandybridge: Make timC training more robust.
by Patrick Rudolph (Code Review) 26 May '19

26 May '19

Patrick Rudolph has uploaded a new patch set (#3) to the change originally created by Tobias Diedrich. ( https://review.coreboot.org/c/coreboot/+/22776 ) Change subject: intel/sandybridge: Make timC training more robust. ...................................................................... intel/sandybridge: Make timC training more robust. When using native raminit with https://review.coreboot.org/#/c/22683/ I've found that timC training usually fails unless the ram is overspecced (i.e. DDR3L-1600 rated for 1.35V works most of the time with native raminit as DDR3-1333 @1.5V). Looking at the training data I've found that during timC training it is reading register values in the 0-4000 range and checking for runs of 0, but with the failing training the values don't go all the way down to 0. The solution for me has been to do a thresholing pre-pass, after which both the DDR3-1333 @1.5V and the DDR3L-1600 @1.35V work fine for me. Tested: - Intel NUC DCP847SKE - RAM slots with 2x4GB Kingston KVR1333D3S9/4G (DDR3-1333 1.5V), boots fine with native raminit @1.5V - RAM slots with 2x4GB Kingston KVR16LS11/4G (DDR3L-1600 1.35V), boots fine with native raminit @1.35V - Casual use with these settings - Tested on Lenovo T520 with Crucial HyperX DDR3-1833. - Memtest86+ stable. Change-Id: I9986616e86560c4980ccd8e3e549af53caa15c71 Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 34 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/22776/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/22776 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9986616e86560c4980ccd8e3e549af53caa15c71 Gerrit-Change-Number: 22776 Gerrit-PatchSet: 3 Gerrit-Owner: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: nb/intel/sandybridge/raminit: Add workaround for timC
by Patrick Rudolph (Code Review) 26 May '19

26 May '19

Patrick Rudolph has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/23087 ) Change subject: nb/intel/sandybridge/raminit: Add workaround for timC ...................................................................... Abandoned Tested. Doesn't fix timC issues. -- To view, visit https://review.coreboot.org/c/coreboot/+/23087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I535ea4e320c4572bfae55ce1d0f2c1723e9c54d6 Gerrit-Change-Number: 23087 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in ...coreboot[master]: nb/intel/pineview: Use MTRR as a proxy for proper reset
by Arthur Heymans (Code Review) 25 May '19

25 May '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33010 Change subject: nb/intel/pineview: Use MTRR as a proxy for proper reset ...................................................................... nb/intel/pineview: Use MTRR as a proxy for proper reset On reset this platform can sometimes hang. This also fixes pineview mainboards not building due to the symbol 'check_mtrr' lacking. Change-Id: I61fe77113004ea664522bda549240a33e3742a98 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/pineview/Makefile.inc 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/33010/1 diff --git a/src/northbridge/intel/pineview/Makefile.inc b/src/northbridge/intel/pineview/Makefile.inc index c72fe3e..989a5ae 100644 --- a/src/northbridge/intel/pineview/Makefile.inc +++ b/src/northbridge/intel/pineview/Makefile.inc @@ -16,6 +16,7 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_PINEVIEW),y) +bootblock-y += ../../x86/early_reset.S bootblock-y += bootblock.c ramstage-y += ram_calc.c -- To view, visit https://review.coreboot.org/c/coreboot/+/33010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I61fe77113004ea664522bda549240a33e3742a98 Gerrit-Change-Number: 33010 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: samsung/lumpy: add cpu/gpu pwm backlight register values
by Matt DeVillier (Code Review) 25 May '19

25 May '19

Matt DeVillier has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/30565 ) Change subject: samsung/lumpy: add cpu/gpu pwm backlight register values ...................................................................... Abandoned duplicate of already-merged CB:30566 -- To view, visit https://review.coreboot.org/c/coreboot/+/30565 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b29f8a382550ff9ac162c0effccd40a7f141e15 Gerrit-Change-Number: 30565 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: abandon

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