coreboot-gerrit May 2019

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Change in ...coreboot[master]: mb/up/squared: Add mainboard
by Felix Singer (Code Review) 22 May '19

22 May '19

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31378 Change subject: mb/up/squared: Add mainboard ...................................................................... mb/up/squared: Add mainboard Change-Id: Ia913534ec176fc600fcd4ce3af335ebe682b0ed4 Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de> --- A src/mainboard/up/Kconfig A src/mainboard/up/Kconfig.name A src/mainboard/up/squared/Kconfig A src/mainboard/up/squared/Kconfig.name A src/mainboard/up/squared/acpi_tables.c A src/mainboard/up/squared/devicetree.cb A src/mainboard/up/squared/dsdt.asl 7 files changed, 174 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/31378/1 diff --git a/src/mainboard/up/Kconfig b/src/mainboard/up/Kconfig new file mode 100644 index 0000000..84277de --- /dev/null +++ b/src/mainboard/up/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_UP + +choice + prompt "Mainboard model" + +source "src/mainboard/up/*/Kconfig.name" + +endchoice + +source "src/mainboard/up/*/Kconfig" + +config MAINBOARD_VENDOR + string + default "Up" + +endif diff --git a/src/mainboard/up/Kconfig.name b/src/mainboard/up/Kconfig.name new file mode 100644 index 0000000..56be3e8 --- /dev/null +++ b/src/mainboard/up/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_UP + bool "Up" diff --git a/src/mainboard/up/squared/Kconfig b/src/mainboard/up/squared/Kconfig new file mode 100644 index 0000000..7271753 --- /dev/null +++ b/src/mainboard/up/squared/Kconfig @@ -0,0 +1,53 @@ +if BOARD_UP_SQUARED + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select USE_BLOBS + select ADD_FSP_BINARIES + select FSP_USE_REPO + select HAVE_ACPI_TABLES + select HAVE_ACPI_RESUME + select SOC_INTEL_APOLLOLAKE + select BOARD_ROMSIZE_KB_16384 + select ONBOARD_VGA_IS_PRIMARY + +config MAINBOARD_DIR + string + default "up/squared" + +config MAINBOARD_VENDOR + string + default "Up" + +config MAINBOARD_PART_NUMBER + string + default "Squared" + +config SUBSYSTEM_VENDOR_ID + hex + default 0x8086 + +config SUBSYSTEM_DEVICE_ID + hex + default 0x7270 + +config VGA_BIOS_ID + string + default "8086,5a85" + +config PXE_ROM_ID + string + default "10ec,8168" + +config MAX_CPUS + int + default 2 + +config DIMM_SPD_SIZE + int + default 512 + +config UART_FOR_CONSOLE + default 2 + +endif diff --git a/src/mainboard/up/squared/Kconfig.name b/src/mainboard/up/squared/Kconfig.name new file mode 100644 index 0000000..4d6a59b --- /dev/null +++ b/src/mainboard/up/squared/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_UP_SQUARED + bool "Squared" diff --git a/src/mainboard/up/squared/acpi_tables.c b/src/mainboard/up/squared/acpi_tables.c new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/up/squared/acpi_tables.c diff --git a/src/mainboard/up/squared/devicetree.cb b/src/mainboard/up/squared/devicetree.cb new file mode 100644 index 0000000..5d91e38 --- /dev/null +++ b/src/mainboard/up/squared/devicetree.cb @@ -0,0 +1,58 @@ +chip soc/intel/apollolake + + register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" + + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # - Host Bridge + device pci 00.1 off end # - DPTF + device pci 00.2 off end # - NPK + device pci 02.0 off end # - Gen + device pci 03.0 off end # - Iunit + device pci 0d.0 off end # - P2SB + device pci 0d.1 off end # - PMC + device pci 0d.2 off end # - SPI + device pci 0d.3 off end # - Shared SRAM + device pci 0e.0 on end # - Audio + device pci 0f.0 on end # - TXE + device pci 11.0 off end # - ISH + device pci 12.0 on end # - SATA + device pci 13.0 on end # - PCIe-A 0 + device pci 13.1 on end # - PCIe-A 1 + device pci 13.2 on end # - PCIe-A 2 + device pci 13.3 on end # - PCIe-A 3 + device pci 14.0 on end # - PCIe-B 1 + device pci 14.1 on end # - PCIe-B 2 + device pci 15.0 on end # - XHCI + device pci 15.1 on end # - XDCI + device pci 16.0 on end # - I2C 0 + device pci 16.1 on end # - I2C 1 + device pci 16.2 on end # - I2C 2 + device pci 16.3 on end # - I2C 3 + device pci 17.0 on end # - I2C 4 + device pci 17.1 on end # - I2C 5 + device pci 17.2 on end # - I2C 6 + device pci 17.3 on end # - I2C 7 + device pci 18.0 on end # - HSUART 0 + device pci 18.1 on end # - HSUART 1 + device pci 18.2 on end # - UART 2 + device pci 18.3 off end # - UART 3 + device pci 19.0 on end # - SPI 0 + device pci 19.1 on end # - SPI 1 + device pci 19.2 on end # - SPI 2 + device pci 1a.0 on end # - PWM + device pci 1b.0 off end # - SDCARD + device pci 1c.0 on end # - eMMC + device pci 1e.0 on end # - SDIO + device pci 1f.0 on end # - LPC + device pci 1f.1 on end # - SMBUS + end +end diff --git a/src/mainboard/up/squared/dsdt.asl b/src/mainboard/up/squared/dsdt.asl new file mode 100644 index 0000000..48b24b9 --- /dev/null +++ b/src/mainboard/up/squared/dsdt.asl @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + /* global NVS and variables */ + #include <soc/intel/apollolake/acpi/globalnvs.asl> + + /* CPU */ + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/apollolake/acpi/northbridge.asl> + #include <soc/intel/apollolake/acpi/southbridge.asl> + #include <soc/intel/apollolake/acpi/pch_hda.asl> + } + } + + /* Chipset specific sleep states */ + #include <soc/intel/apollolake/acpi/sleepstates.asl> +} -- To view, visit https://review.coreboot.org/c/coreboot/+/31378 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia913534ec176fc600fcd4ce3af335ebe682b0ed4 Gerrit-Change-Number: 31378 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: superio: Add ASpeed AST2400
by Christian Walter (Code Review) 22 May '19

22 May '19

Christian Walter has uploaded a new patch set (#26) to the change originally created by Frans Hendriks. ( https://review.coreboot.org/c/coreboot/+/23135 ) Change subject: superio: Add ASpeed AST2400 ...................................................................... superio: Add ASpeed AST2400 Add support for ASpeed AST2400. This device uses write twice 0xA5 to enter config mode. BUG = N/A TEST = ASRock D1521D4U Change-Id: I58fce31f0a2483e61e9d31f38ab5a059b8cf4f83 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de> --- M src/include/superio/conf_mode.h M src/superio/Makefile.inc A src/superio/aspeed/Makefile.inc A src/superio/aspeed/ast2400/Kconfig A src/superio/aspeed/ast2400/Makefile.inc A src/superio/aspeed/ast2400/ast2400.h A src/superio/aspeed/ast2400/superio.c A src/superio/aspeed/common/Kconfig A src/superio/aspeed/common/aspeed.h A src/superio/aspeed/common/early_serial.c M src/superio/common/conf_mode.c 11 files changed, 316 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/23135/26 -- To view, visit https://review.coreboot.org/c/coreboot/+/23135 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58fce31f0a2483e61e9d31f38ab5a059b8cf4f83 Gerrit-Change-Number: 23135 Gerrit-PatchSet: 26 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: src/soc/intel/skylake: Add KabyLake DT KConfig
by Christian Walter (Code Review) 22 May '19

22 May '19

Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32911 Change subject: src/soc/intel/skylake: Add KabyLake DT KConfig ...................................................................... src/soc/intel/skylake: Add KabyLake DT KConfig Change-Id: Ib603671fffdd80fbb1a19d99476f4f7298762043 Signed-off-by: Christian Walter <christian.walter(a)9elements.com> --- M src/soc/intel/skylake/Kconfig 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/32911/1 diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index fcfe2b6..3e11ad6 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -10,6 +10,13 @@ help Intel Kabylake support +config SOC_INTEL_KABYLAKE_DT + bool + default n + select SOC_INTEL_KABYLAKE + help + Intel Kabylake DT support + if SOC_INTEL_SKYLAKE config CPU_SPECIFIC_OPTIONS -- To view, visit https://review.coreboot.org/c/coreboot/+/32911 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib603671fffdd80fbb1a19d99476f4f7298762043 Gerrit-Change-Number: 32911 Gerrit-PatchSet: 1 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: newchange

2 2

Change in ...coreboot[master]: util/xcompile/xcompile: apply -march to clang as well as gcc
by Kyösti Mälkki (Code Review) 22 May '19

22 May '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32923 ) Change subject: util/xcompile/xcompile: apply -march to clang as well as gcc ...................................................................... Patch Set 1: Code-Review+1 (2 comments) Maybe we could get rid of the "config SSE" and just unconditionally set CR4 SSE nowadays? Still, -no-sse should ne implied or explicit for AMD ASEG SMM implementation and possibly amdfam10-15 raminit that appear to lack the clobbers for xmmX in its inline assembly. Could become an issue with the x86_64 build. Those can be followup fixes. https://review.coreboot.org/#/c/32923/1/util/xcompile/xcompile File util/xcompile/xcompile: https://review.coreboot.org/#/c/32923/1/util/xcompile/xcompile@257 PS1, Line 257: # flags. Note that this doesn't prevent a project using Seems like a stale comment after CB:20244, SMM modules tolerate SSE instructions nowadays. https://review.coreboot.org/#/c/32923/1/util/xcompile/xcompile@264 PS1, Line 264: CFLAGS_${TARCH} += -march=nocona -malign-data=abi This enables SSE instructions, while CR4 SSE enable bit might not be set. -- To view, visit https://review.coreboot.org/c/coreboot/+/32923 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a6a6136b01a64d46f730ed19ebbeaadaf2183df Gerrit-Change-Number: 32923 Gerrit-PatchSet: 1 Gerrit-Owner: Alan Green <avg(a)google.com> Gerrit-Reviewer: Alan Green <avg(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 22 May 2019 10:25:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: soc/intel/denverton_ns: Enable MC Exception
by Patrick Georgi (Code Review) 22 May '19

22 May '19

Patrick Georgi has uploaded a new patch set (#11) to the change originally created by Julien Viard de Galbert. ( https://review.coreboot.org/c/coreboot/+/25434 ) Change subject: soc/intel/denverton_ns: Enable MC Exception ...................................................................... soc/intel/denverton_ns: Enable MC Exception Change-Id: I9773c61d06bb6c68612e498a35b5ad22cd5a8a6e Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net> --- M src/soc/intel/denverton_ns/cpu.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/25434/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/25434 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9773c61d06bb6c68612e498a35b5ad22cd5a8a6e Gerrit-Change-Number: 25434 Gerrit-PatchSet: 11 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: util/sconfig: Move 'static' at beginning of declaration
by HAOUAS Elyes (Code Review) 22 May '19

22 May '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32900 Change subject: util/sconfig: Move 'static' at beginning of declaration ...................................................................... util/sconfig: Move 'static' at beginning of declaration When using -Werror=old-style-declaration, gcc reports an error: "'static' is not at beginning of declaration" Tested on 945G-M4 board. Change-Id: I7216a4fab2d5878066c871166e6a481d1f201a9d Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/sconfig/main.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/32900/1 diff --git a/util/sconfig/main.c b/util/sconfig/main.c index c3aa17f..548063f 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -701,7 +701,7 @@ return; } - fprintf(fil, "DEVTREE_CONST static struct device %s;\n", ptr->name); + fprintf(fil, "static DEVTREE_CONST struct device %s;\n", ptr->name); if (ptr->res) fprintf(fil, "DEVTREE_CONST struct resource %s_res[];\n", ptr->name); -- To view, visit https://review.coreboot.org/c/coreboot/+/32900 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7216a4fab2d5878066c871166e6a481d1f201a9d Gerrit-Change-Number: 32900 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 3

Change in ...coreboot[master]: soc/intel/cannonlake: Dump ME f/w version and status information.
by Tim Wawrzynczak (Code Review) 22 May '19

22 May '19

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32527 Change subject: soc/intel/cannonlake: Dump ME f/w version and status information. ...................................................................... soc/intel/cannonlake: Dump ME f/w version and status information. At the end of device enable, print the ME f/w version number. Before resume or loading payload, dump the ME's Host Firmware Status registers. BUG=b:131437724 BRANCH=none TEST=Prints what appears to be correct information on Kled (hatch_whl). Change-Id: Ibeb3a2a85cd84c9baa45f90f20a3dcf69f7d5646 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/cannonlake/Makefile.inc A src/soc/intel/cannonlake/me.c 2 files changed, 309 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/32527/1 diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 7ad0c7c..1328944 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -43,6 +43,7 @@ ramstage-y += i2c.c ramstage-y += lockdown.c ramstage-y += lpc.c +ramstage-y += me.c ramstage-y += memmap.c ramstage-y += nhlt.c ramstage-y += p2sb.c diff --git a/src/soc/intel/cannonlake/me.c b/src/soc/intel/cannonlake/me.c new file mode 100644 index 0000000..59ba879 --- /dev/null +++ b/src/soc/intel/cannonlake/me.c @@ -0,0 +1,308 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Google LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/pci_ops.h> +#include <bootstate.h> +#include <commonlib/helpers.h> +#include <console/console.h> +#include <device/pci.h> +#include <intelblocks/cse.h> +#include <soc/pci_devs.h> +#include <stdint.h> +#include <stdlib.h> + +/* Miscellaneous constants */ +enum +{ + MKHI_GEN_GROUP_ID = 0xFF, + MKHI_GET_FW_VERSION = 0x02, + ME_OPMODE_NORMAL = 0x00, + ME_WSTATE_NORMAL = 0x05, + BIOS_HOST_ADD = 0x00, + HECI_MKHI_ADD = 0x07, +}; + +/* HFSTS register offsets in PCI config space */ +enum +{ + PCI_ME_HFSTS1 = 0x40, + PCI_ME_HFSTS2 = 0x48, + PCI_ME_HFSTS3 = 0x60, + PCI_ME_HFSTS4 = 0x64, + PCI_ME_HFSTS5 = 0x68, + PCI_ME_HFSTS6 = 0x6C, +}; + +/* Host Firmware Status Register 1 */ +union hfsts1 +{ + uint32_t raw; + struct { + uint32_t working_state : 4; + uint32_t mfg_mode : 1; + uint32_t fpt_bad : 1; + uint32_t operation_state : 3; + uint32_t fw_init_complete : 1; + uint32_t ft_bup_ld_flr : 1; + uint32_t fw_upd_in_progress : 1; + uint32_t error_code : 4; + uint32_t operation_mode : 4; + uint32_t reset_count : 4; + uint32_t boot_options : 1; + uint32_t rsvd0 : 1; + uint32_t bist_state : 1; + uint32_t bist_reset_req : 1; + uint32_t power_source : 2; + uint32_t reserved1 : 1; + uint32_t d0i3_support_valid : 1; + } __packed fields; +}; + +/* Host Firmware Status Register 2 */ +union hfsts2 +{ + uint32_t raw; + struct { + uint32_t nftp_load_failure : 1; + uint32_t icc_prog_status : 2; + uint32_t invoke_mebx : 1; + uint32_t cpu_replaced : 1; + uint32_t rsvd0 : 1; + uint32_t mfs_failure : 1; + uint32_t warm_reset_rqst : 1; + uint32_t cpu_replaced_valid : 1; + uint32_t low_power_state : 1; + uint32_t me_power_gate : 1; + uint32_t ipu_needed : 1; + uint32_t forced_safe_boot : 1; + uint32_t rsvd1 : 2; + uint32_t listener_change : 1; + uint32_t status_data : 8; + uint32_t current_pmevent : 4; + uint32_t phase : 4; + } __packed fields; +}; + +/* Host Firmware Status Register 3 */ +union hfsts3 +{ + uint32_t raw; +}; + +/* Host Firmware Status Register 4 */ +union hfsts4 +{ + uint32_t raw; + struct { + uint32_t rsvd0 : 9; + uint32_t enforcement_flow : 1; + uint32_t sx_resume_type : 1; + uint32_t rsvd1 : 1; + uint32_t tpms_disconnected : 1; + uint32_t rvsd2 : 1; + uint32_t fwsts_valid : 1; + uint32_t boot_guard_self_test: 1; + uint32_t rsvd3 : 16; + } __packed fields; +}; + +/* Host Firmware Status Register 5 */ +union hfsts5 +{ + uint32_t raw; + struct { + uint32_t acm_active : 1; + uint32_t valid : 1; + uint32_t result_code_source : 1; + uint32_t error_status_code : 5; + uint32_t acm_done_sts : 1; + uint32_t timeout_count : 7; + uint32_t scrtm_indicator : 1; + uint32_t inc_boot_guard_acm : 4; + uint32_t inc_key_manifest : 4; + uint32_t inc_boot_policy : 4; + uint32_t rsvd0 : 2; + uint32_t start_enforcement : 1; + } __packed fields; +}; + +/* Host Firmware Status Register 6 */ +union hfsts6 +{ + uint32_t raw; + struct { + uint32_t force_boot_guard_acm: 1; + uint32_t cpu_debug_disable : 1; + uint32_t bsp_init_disable : 1; + uint32_t protect_bios_env : 1; + uint32_t rsvd0 : 2; + uint32_t error_enforce_policy: 2; + uint32_t measured_boot : 1; + uint32_t verified_boot : 1; + uint32_t boot_guard_acmsvn : 4; + uint32_t kmsvn : 4; + uint32_t bpmsvn : 4; + uint32_t key_manifest_id : 4; + uint32_t boot_policy_status : 1; + uint32_t error : 1; + uint32_t boot_guard_disable : 1; + uint32_t fpf_disable : 1; + uint32_t fpf_soc_lock : 1; + uint32_t txt_support : 1; + } __packed fields; +}; + +static uint32_t me_read_config32(int offset) +{ + return pci_read_config32(PCH_DEV_CSE, offset); +} + +/* + * From reading the documentation, this should work for both WHL and CML + * platforms + */ +static void print_me_version(void *unused) +{ + (void)unused; + + struct mkhi_hdr { + uint8_t group_id; + uint8_t command:7; + uint8_t is_resp:1; + uint8_t rsvd; + uint8_t result; + } __packed; + + struct version { + uint16_t minor; + uint16_t major; + uint16_t build; + uint16_t hotfix; + } __packed; + + struct fw_ver_resp { + struct mkhi_hdr hdr; + struct version code; + struct version rec; + struct version fitc; + } __packed; + + union hfsts1 hfsts1; + const struct mkhi_hdr fw_ver_msg = { + .group_id = MKHI_GEN_GROUP_ID, + .command = MKHI_GET_FW_VERSION, + }; + struct fw_ver_resp resp; + size_t resp_size = sizeof(resp); + + /* Ignore if UART debugging is disabled */ + if (!CONFIG(CONSOLE_SERIAL)) + return; + + hfsts1.raw = me_read_config32(PCI_ME_HFSTS1); + + /* + * Prerequisites: + * 1) HFSTS1 Current Working State is Normal + * 2) HFSTS1 Current Operation Mode is Normal + * 3) It's after DRAM INIT DONE message (taken care of by calling it + * during ramstage + */ + if ((hfsts1.fields.working_state != ME_WSTATE_NORMAL) || + (hfsts1.fields.operation_mode != ME_OPMODE_NORMAL)) + goto fail; + + heci_reset(); + + if (!heci_send(&fw_ver_msg, sizeof(fw_ver_msg), BIOS_HOST_ADD, + HECI_MKHI_ADD)) + goto fail; + + if (!heci_receive(&resp, &resp_size)) + goto fail; + + if (resp.hdr.result) + goto fail; + + printk(BIOS_DEBUG, "ME: Version: %d.%d.%d.%d\n", resp.code.major, + resp.code.minor, resp.code.hotfix, resp.code.build); + return; + +fail: + printk(BIOS_DEBUG, "ME: Version: Unavailable\n"); +} +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, print_me_version, NULL); + +static void dump_me_status(void *unused) +{ + + union hfsts1 hfsts1; + union hfsts2 hfsts2; + union hfsts3 hfsts3; + union hfsts4 hfsts4; + union hfsts5 hfsts5; + union hfsts6 hfsts6; + + (void)unused; + + hfsts1.raw = me_read_config32(PCI_ME_HFSTS1); + hfsts2.raw = me_read_config32(PCI_ME_HFSTS2); + hfsts3.raw = me_read_config32(PCI_ME_HFSTS3); + hfsts4.raw = me_read_config32(PCI_ME_HFSTS4); + hfsts5.raw = me_read_config32(PCI_ME_HFSTS5); + hfsts6.raw = me_read_config32(PCI_ME_HFSTS6); + + printk(BIOS_DEBUG, "ME: HFSTS1 : 0x%08X\n", hfsts1.raw); + printk(BIOS_DEBUG, "ME: HFSTS2 : 0x%08X\n", hfsts2.raw); + printk(BIOS_DEBUG, "ME: HFSTS3 : 0x%08X\n", hfsts3.raw); + printk(BIOS_DEBUG, "ME: HFSTS4 : 0x%08X\n", hfsts4.raw); + printk(BIOS_DEBUG, "ME: HFSTS5 : 0x%08X\n", hfsts5.raw); + printk(BIOS_DEBUG, "ME: HFSTS6 : 0x%08X\n", hfsts6.raw); + + printk(BIOS_DEBUG, "ME: Manufacturing Mode : %s\n", + hfsts1.fields.mfg_mode ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: FW Partition Table : %s\n", + hfsts1.fields.fpt_bad ? "BAD" : "OK"); + printk(BIOS_DEBUG, "ME: Bringup Loader Failure : %s\n", + hfsts1.fields.ft_bup_ld_flr ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Firmware Init Complete : %s\n", + hfsts1.fields.fw_init_complete ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Boot Options Present : %s\n", + hfsts1.fields.boot_options ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Update In Progress : %s\n", + hfsts1.fields.fw_upd_in_progress ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: D0i3 Support : %s\n", + hfsts1.fields.d0i3_support_valid ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Low Power State Enabled : %s\n", + hfsts2.fields.low_power_state ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: CPU Replaced : %s\n", + hfsts2.fields.cpu_replaced ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: CPU Replacement Valid : %s\n", + hfsts2.fields.cpu_replaced_valid ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Current Working State : %u\n", + hfsts1.fields.working_state); + printk(BIOS_DEBUG, "ME: Current Operation State : %u\n", + hfsts1.fields.operation_state); + printk(BIOS_DEBUG, "ME: Current Operation Mode : %u\n", + hfsts1.fields.operation_mode); + printk(BIOS_DEBUG, "ME: Error Code : %u\n", + hfsts1.fields.error_code); + printk(BIOS_DEBUG, "ME: CPU Debug Disabled : %s\n", + hfsts6.fields.cpu_debug_disable ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: TXT Support : %s\n", + hfsts6.fields.txt_support ? "YES" : "NO"); +} +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, dump_me_status, NULL); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, dump_me_status, NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/32527 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibeb3a2a85cd84c9baa45f90f20a3dcf69f7d5646 Gerrit-Change-Number: 32527 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

10 45

Change in ...coreboot[master]: soc/amd/common: Identify AGESA call pattern
by Kyösti Mälkki (Code Review) 22 May '19

22 May '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31488 Change subject: soc/amd/common: Identify AGESA call pattern ...................................................................... soc/amd/common: Identify AGESA call pattern The entry to AGESA always follows pattern: amd_create_struct() amd_dispatch() amd_release_struct() Separate the create/release_struct calls from the more relevant entry point details. Change-Id: I1037c9daef3365c8672a198ac60f47fc79ffaea1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/common/block/pi/agesawrapper.c 1 file changed, 46 insertions(+), 92 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/31488/1 diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c index 1c6c0aa..821535d 100644 --- a/src/soc/amd/common/block/pi/agesawrapper.c +++ b/src/soc/amd/common/block/pi/agesawrapper.c @@ -66,10 +66,9 @@ return module_dispatch(AMD_LATE_RUN_AP_TASK, StdHeader); } -static void *amd_create_struct(AMD_INTERFACE_PARAMS *aip, +static AGESA_STATUS amd_create_struct(AMD_INTERFACE_PARAMS *aip, AGESA_STRUCT_NAME func, void *buf, size_t len) { - AMD_CONFIG_PARAMS *StdHeader; AGESA_STATUS status; /* Should clone entire StdHeader here. */ @@ -78,8 +77,8 @@ /* If we provide the buffer, API expects it to have StdHeader already filled. */ - if (buf != NULL && len >= sizeof(*StdHeader)) { - memcpy(buf, &aip->StdHeader, sizeof(*StdHeader)); + if (buf != NULL && len >= sizeof(aip->StdHeader)) { + memcpy(buf, &aip->StdHeader, sizeof(aip->StdHeader)); aip->AllocationMethod = ByHost; aip->NewStructPtr = buf; aip->NewStructSize = len; @@ -102,9 +101,7 @@ if (!aip->NewStructPtr) die("No AGESA structure created"); - StdHeader = aip->NewStructPtr; - StdHeader->Func = aip->AgesaFunctionName; - return StdHeader; + return status; } static AGESA_STATUS amd_release_struct(AMD_INTERFACE_PARAMS *aip) @@ -112,14 +109,9 @@ return module_dispatch(AMD_RELEASE_STRUCT, &aip->StdHeader); } -static AGESA_STATUS amd_init_reset(void) +static AGESA_STATUS amd_init_reset(AMD_RESET_PARAMS *ResetParams) { AGESA_STATUS status; - AMD_RESET_PARAMS _ResetParams; - AMD_INTERFACE_PARAMS AmdParamStruct; - - AMD_RESET_PARAMS *ResetParams = amd_create_struct(&AmdParamStruct, - AMD_INIT_RESET, &_ResetParams, sizeof(AMD_RESET_PARAMS)); SetFchResetParams(&ResetParams->FchInterface); @@ -127,17 +119,12 @@ status = amd_dispatch(ResetParams); timestamp_add_now(TS_AGESA_INIT_RESET_DONE); - amd_release_struct(&AmdParamStruct); return status; } -static AGESA_STATUS amd_init_early(void) +static AGESA_STATUS amd_init_early(AMD_EARLY_PARAMS *EarlyParams) { AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - - AMD_EARLY_PARAMS *EarlyParams = amd_create_struct(&AmdParamStruct, - AMD_INIT_EARLY, NULL, 0); soc_customize_init_early(EarlyParams); OemCustomizeInitEarly(EarlyParams); @@ -146,8 +133,6 @@ status = amd_dispatch(EarlyParams); timestamp_add_now(TS_AGESA_INIT_EARLY_DONE); - amd_release_struct(&AmdParamStruct); - return status; } @@ -184,13 +169,9 @@ uma_size / MiB, uma_start); } -static AGESA_STATUS amd_init_post(void) +static AGESA_STATUS amd_init_post(AMD_POST_PARAMS *PostParams) { AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - - AMD_POST_PARAMS *PostParams = amd_create_struct(&AmdParamStruct, - AMD_INIT_POST, NULL, 0); PostParams->MemConfig.UmaMode = CONFIG_GFXUMA ? UMA_AUTO : UMA_NONE; PostParams->MemConfig.UmaSize = 0; @@ -230,18 +211,12 @@ print_init_post_settings(PostParams); - amd_release_struct(&AmdParamStruct); - return status; } -static AGESA_STATUS amd_init_env(void) +static AGESA_STATUS amd_init_env(AMD_ENV_PARAMS *EnvParams) { AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - - AMD_ENV_PARAMS *EnvParams = amd_create_struct(&AmdParamStruct, - AMD_INIT_ENV, NULL, 0); SetFchEnvParams(&EnvParams->FchInterface); SetNbEnvParams(&EnvParams->GnbEnvConfiguration); @@ -250,8 +225,6 @@ status = amd_dispatch(EnvParams); timestamp_add_now(TS_AGESA_INIT_ENV_DONE); - amd_release_struct(&AmdParamStruct); - return status; } @@ -281,17 +254,13 @@ } } -static AGESA_STATUS amd_init_mid(void) +static AGESA_STATUS amd_init_mid(AMD_MID_PARAMS *MidParams) { AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; /* Enable MMIO on AMD CPU Address Map Controller */ amd_initcpuio(); - AMD_MID_PARAMS *MidParams = amd_create_struct(&AmdParamStruct, - AMD_INIT_MID, NULL, 0); - SetFchMidParams(&MidParams->FchInterface); SetNbMidParams(&MidParams->GnbMidConfiguration); @@ -299,22 +268,12 @@ status = amd_dispatch(MidParams); timestamp_add_now(TS_AGESA_INIT_MID_DONE); - amd_release_struct(&AmdParamStruct); - return status; } -static AGESA_STATUS amd_init_late(void) +static AGESA_STATUS amd_init_late(AMD_LATE_PARAMS *LateParams) { AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdParamStruct; - - /* - * NOTE: if not call amdcreatestruct, the initializer - * (AmdInitLateInitializer) would not be called. - */ - AMD_LATE_PARAMS *LateParams = amd_create_struct(&AmdParamStruct, - AMD_INIT_LATE, NULL, 0); const struct device *dev = pcidev_path_on_root(IOMMU_DEVFN); if (dev && dev->enabled) { @@ -343,17 +302,12 @@ AcpiSlit, AcpiWheaMce, AcpiWheaCmc, AcpiAlib, AcpiIvrs, __func__); - amd_release_struct(&AmdParamStruct); return Status; } -static AGESA_STATUS amd_init_rtb(void) +static AGESA_STATUS amd_init_rtb(AMD_RTB_PARAMS *RtbParams) { AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdParamStruct; - - AMD_RTB_PARAMS *RtbParams = amd_create_struct(&AmdParamStruct, - AMD_INIT_RTB, NULL, 0); timestamp_add_now(TS_AGESA_INIT_RTB_START); Status = amd_dispatch(RtbParams); @@ -365,20 +319,14 @@ RtbParams->S3DataBlock.VolatileStorageSize)) printk(BIOS_ERR, "S3 data not saved, resuming impossible\n"); - amd_release_struct(&AmdParamStruct); - return Status; } -static AGESA_STATUS amd_init_resume(void) +static AGESA_STATUS amd_init_resume(AMD_RESUME_PARAMS *InitResumeParams) { AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; size_t nv_size; - AMD_RESUME_PARAMS *InitResumeParams = amd_create_struct(&AmdParamStruct, - AMD_INIT_RESUME, NULL, 0); - get_s3nv_info(&InitResumeParams->S3DataBlock.NvStorage, &nv_size); InitResumeParams->S3DataBlock.NvStorageSize = nv_size; @@ -386,23 +334,16 @@ status = amd_dispatch(InitResumeParams); timestamp_add_now(TS_AGESA_INIT_RESUME_DONE); - amd_release_struct(&AmdParamStruct); - return status; } -static AGESA_STATUS amd_s3late_restore(void) +static AGESA_STATUS amd_s3late_restore(AMD_S3LATE_PARAMS *S3LateParams) { AGESA_STATUS Status; - AMD_S3LATE_PARAMS _S3LateParams; - AMD_INTERFACE_PARAMS AmdParamStruct; size_t vol_size; amd_initcpuio(); - AMD_S3LATE_PARAMS *S3LateParams = amd_create_struct(&AmdParamStruct, - AMD_S3LATE_RESTORE, &_S3LateParams, sizeof(AMD_S3LATE_PARAMS)); - get_s3vol_info(&S3LateParams->S3DataBlock.VolatileStorage, &vol_size); S3LateParams->S3DataBlock.VolatileStorageSize = vol_size; @@ -410,21 +351,14 @@ Status = amd_dispatch(S3LateParams); timestamp_add_now(TS_AGESA_S3_LATE_DONE); - amd_release_struct(&AmdParamStruct); - return Status; } -static AGESA_STATUS amd_s3final_restore(void) +static AGESA_STATUS amd_s3final_restore(AMD_S3FINAL_PARAMS *S3FinalParams) { AGESA_STATUS Status; - AMD_S3FINAL_PARAMS _S3FinalParams; - AMD_INTERFACE_PARAMS AmdParamStruct; size_t vol_size; - AMD_S3FINAL_PARAMS *S3FinalParams = amd_create_struct(&AmdParamStruct, - AMD_S3FINAL_RESTORE, &_S3FinalParams, sizeof(AMD_S3FINAL_PARAMS)); - get_s3vol_info(&S3FinalParams->S3DataBlock.VolatileStorage, &vol_size); S3FinalParams->S3DataBlock.VolatileStorageSize = vol_size; @@ -432,22 +366,22 @@ Status = amd_dispatch(S3FinalParams); timestamp_add_now(TS_AGESA_S3_FINAL_DONE); - amd_release_struct(&AmdParamStruct); - return Status; } static AGESA_STATUS romstage_dispatch(AMD_CONFIG_PARAMS *StdHeader) { + void *Params = StdHeader; + switch (StdHeader->Func) { case AMD_INIT_RESET: - return amd_init_reset(); + return amd_init_reset(Params); case AMD_INIT_EARLY: - return amd_init_early(); + return amd_init_early(Params); case AMD_INIT_POST: - return amd_init_post(); + return amd_init_post(Params); case AMD_INIT_RESUME: - return amd_init_resume(); + return amd_init_resume(Params); default: return AGESA_UNSUPPORTED; } @@ -455,22 +389,25 @@ static AGESA_STATUS ramstage_dispatch(AMD_CONFIG_PARAMS *StdHeader) { + void *Params = StdHeader; + switch (StdHeader->Func) { case AMD_INIT_ENV: - return amd_init_env(); + return amd_init_env(Params); case AMD_INIT_MID: - return amd_init_mid(); + return amd_init_mid(Params); case AMD_INIT_LATE: - return amd_init_late(); + return amd_init_late(Params); case AMD_INIT_RTB: - return amd_init_rtb(); + return amd_init_rtb(Params); case AMD_S3LATE_RESTORE: - return amd_s3late_restore(); + return amd_s3late_restore(Params); case AMD_S3FINAL_RESTORE: - return amd_s3final_restore(); + return amd_s3final_restore(Params); default: return AGESA_UNSUPPORTED; } + } AGESA_STATUS agesa_execute_state(AGESA_STRUCT_NAME func) @@ -478,7 +415,23 @@ AGESA_STATUS status = AGESA_UNSUPPORTED; AMD_CONFIG_PARAMS template = {}; AMD_CONFIG_PARAMS *StdHeader = &template; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_INTERFACE_PARAMS *aip = &AmdParamStruct; + union { + AMD_RESET_PARAMS ResetParams; + AMD_S3LATE_PARAMS S3LateParams; + AMD_S3FINAL_PARAMS S3FinalParams; + } sp; + if ((func == AMD_INIT_RESET) || (func == AMD_S3LATE_RESTORE) || + (func == AMD_S3FINAL_RESTORE)) { + memset(&sp, 0, sizeof(sp)); + amd_create_struct(aip, func, &sp, sizeof(sp)); + } else { + amd_create_struct(aip, func, NULL, 0); + } + + StdHeader = aip->NewStructPtr; StdHeader->Func = func; if (ENV_ROMSTAGE) @@ -486,5 +439,6 @@ if (ENV_RAMSTAGE) status = ramstage_dispatch(StdHeader); + amd_release_struct(aip); return status; } -- To view, visit https://review.coreboot.org/c/coreboot/+/31488 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1037c9daef3365c8672a198ac60f47fc79ffaea1 Gerrit-Change-Number: 31488 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 6

Change in ...coreboot[master]: soc/fsp_baytrail: fix flashconsole on platform
by Matt DeVillier (Code Review) 22 May '19

22 May '19

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32879 Change subject: soc/fsp_baytrail: fix flashconsole on platform ...................................................................... soc/fsp_baytrail: fix flashconsole on platform Include spi.c in romstage. Since FSP 1.0 can't use NO_CAR_GLOBAL_MIGRATION, adjust global variables in spi.c to use CAR_GLOBAL. Adapted from early versions of CB:21107 Change-Id: I3487fb8ac317ce920bf1c3ef9d89590051932378 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/fsp_baytrail/Makefile.inc M src/soc/intel/fsp_baytrail/spi.c 2 files changed, 44 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/32879/1 diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc index 5ed635d..ca2b353 100644 --- a/src/soc/intel/fsp_baytrail/Makefile.inc +++ b/src/soc/intel/fsp_baytrail/Makefile.inc @@ -35,6 +35,7 @@ postcar-y += tsc_freq.c smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c ramstage-y += spi.c +romstage-y += spi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += spi.c ramstage-y += chip.c ramstage-y += iosf.c diff --git a/src/soc/intel/fsp_baytrail/spi.c b/src/soc/intel/fsp_baytrail/spi.c index 979ee57..9375d19 100644 --- a/src/soc/intel/fsp_baytrail/spi.c +++ b/src/soc/intel/fsp_baytrail/spi.c @@ -15,7 +15,7 @@ */ /* This file is derived from the flashrom project. */ - +#include <arch/early_variables.h> #include <stdint.h> #include <stdlib.h> #include <commonlib/helpers.h> @@ -33,7 +33,7 @@ typedef struct spi_slave ich_spi_slave; -static int ichspi_lock = 0; +static int g_ichspi_lock CAR_GLOBAL = 0; typedef struct ich9_spi_regs { uint32_t bfpr; @@ -81,7 +81,7 @@ uint16_t *control; } ich_spi_controller; -static ich_spi_controller cntlr; +static ich_spi_controller g_cntlr CAR_GLOBAL; enum { SPIS_SCIP = 0x0001, @@ -239,18 +239,19 @@ void spi_init(void) { + ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); ich9_spi_regs *ich9_spi = spi_regs(); - ichspi_lock = readw_(&ich9_spi->hsfs) & HSFS_FLOCKDN; - cntlr.opmenu = ich9_spi->opmenu; - cntlr.menubytes = sizeof(ich9_spi->opmenu); - cntlr.optype = &ich9_spi->optype; - cntlr.addr = &ich9_spi->faddr; - cntlr.data = (uint8_t *)ich9_spi->fdata; - cntlr.databytes = sizeof(ich9_spi->fdata); - cntlr.status = &ich9_spi->ssfs; - cntlr.control = (uint16_t *)ich9_spi->ssfc; - cntlr.preop = &ich9_spi->preop; + car_set_var(g_ichspi_lock, readw_(&ich9_spi->hsfs) & HSFS_FLOCKDN); + cntlr->opmenu = ich9_spi->opmenu; + cntlr->menubytes = sizeof(ich9_spi->opmenu); + cntlr->optype = &ich9_spi->optype; + cntlr->addr = &ich9_spi->faddr; + cntlr->data = (uint8_t *)ich9_spi->fdata; + cntlr->databytes = sizeof(ich9_spi->fdata); + cntlr->status = &ich9_spi->ssfs; + cntlr->control = (uint16_t *)ich9_spi->ssfc; + cntlr->preop = &ich9_spi->preop; } typedef struct spi_transaction { @@ -311,17 +312,18 @@ static int spi_setup_opcode(spi_transaction *trans) { + ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); uint16_t optypes; - uint8_t opmenu[cntlr.menubytes]; + uint8_t opmenu[cntlr->menubytes]; trans->opcode = trans->out[0]; spi_use_out(trans, 1); - if (!ichspi_lock) { + if (!car_get_var(g_ichspi_lock)) { /* The lock is off, so just use index 0. */ - writeb_(trans->opcode, cntlr.opmenu); - optypes = readw_(cntlr.optype); + writeb_(trans->opcode, cntlr->opmenu); + optypes = readw_(cntlr->optype); optypes = (optypes & 0xfffc) | (trans->type & 0x3); - writew_(optypes, cntlr.optype); + writew_(optypes, cntlr->optype); return 0; } else { /* The lock is on. See if what we need is on the menu. */ @@ -332,20 +334,20 @@ if (trans->opcode == SPI_OPCODE_WREN) return 0; - read_reg(cntlr.opmenu, opmenu, sizeof(opmenu)); - for (opcode_index = 0; opcode_index < cntlr.menubytes; + read_reg(cntlr->opmenu, opmenu, sizeof(opmenu)); + for (opcode_index = 0; opcode_index < cntlr->menubytes; opcode_index++) { if (opmenu[opcode_index] == trans->opcode) break; } - if (opcode_index == cntlr.menubytes) { + if (opcode_index == cntlr->menubytes) { printk(BIOS_DEBUG, "ICH SPI: Opcode %x not found\n", trans->opcode); return -1; } - optypes = readw_(cntlr.optype); + optypes = readw_(cntlr->optype); optype = (optypes >> (opcode_index * 2)) & 0x3; if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS && optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS && @@ -391,14 +393,15 @@ */ static int ich_status_poll(uint16_t bitmask, int wait_til_set) { + ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); int timeout = 40000; /* This will result in 400 ms */ uint16_t status = 0; while (timeout--) { - status = readw_(cntlr.status); + status = readw_(cntlr->status); if (wait_til_set ^ ((status & bitmask) == 0)) { if (wait_til_set) - writew_((status & bitmask), cntlr.status); + writew_((status & bitmask), cntlr->status); return status; } udelay(10); @@ -412,6 +415,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, size_t bytesout, void *din, size_t bytesin) { + ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); uint16_t control; int16_t opcode_index; int with_address; @@ -437,7 +441,7 @@ if (ich_status_poll(SPIS_SCIP, 0) == -1) return -1; - writew_(SPIS_CDS | SPIS_FCERR, cntlr.status); + writew_(SPIS_CDS | SPIS_FCERR, cntlr->status); spi_setup_type(&trans); if ((opcode_index = spi_setup_opcode(&trans)) < 0) @@ -445,13 +449,13 @@ if ((with_address = spi_setup_offset(&trans)) < 0) return -1; - if (!ichspi_lock && trans.opcode == SPI_OPCODE_WREN) { + if (!car_get_var(g_ichspi_lock) && trans.opcode == SPI_OPCODE_WREN) { /* * Treat Write Enable as Atomic Pre-Op if possible * in order to prevent the Management Engine from * issuing a transaction between WREN and DATA. */ - writew_(trans.opcode, cntlr.preop); + writew_(trans.opcode, cntlr->preop); return 0; } @@ -459,13 +463,13 @@ control = SPIC_SCGO | ((opcode_index & 0x07) << 4); /* Issue atomic preop cycle if needed */ - if (readw_(cntlr.preop)) + if (readw_(cntlr->preop)) control |= SPIC_ACS; if (!trans.bytesout && !trans.bytesin) { /* SPI addresses are 24 bit only */ if (with_address) - writel_(trans.offset & 0x00FFFFFF, cntlr.addr); + writel_(trans.offset & 0x00FFFFFF, cntlr->addr); /* * This is a 'no data' command (like Write Enable), its @@ -473,7 +477,7 @@ * spi_setup_opcode() above. Tell the chip to send the * command. */ - writew_(control, cntlr.control); + writew_(control, cntlr->control); /* wait for the result */ status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); @@ -495,7 +499,7 @@ * and followed by other SPI commands, and this sequence is controlled * by the SPI chip driver. */ - if (trans.bytesout > cntlr.databytes) { + if (trans.bytesout > cntlr->databytes) { printk(BIOS_DEBUG, "ICH SPI: Too much to write. Does your SPI chip driver use" " spi_crop_chunk()?\n"); return -1; @@ -509,28 +513,28 @@ uint32_t data_length; /* SPI addresses are 24 bit only */ - writel_(trans.offset & 0x00FFFFFF, cntlr.addr); + writel_(trans.offset & 0x00FFFFFF, cntlr->addr); if (trans.bytesout) - data_length = min(trans.bytesout, cntlr.databytes); + data_length = min(trans.bytesout, cntlr->databytes); else - data_length = min(trans.bytesin, cntlr.databytes); + data_length = min(trans.bytesin, cntlr->databytes); /* Program data into FDATA0 to N */ if (trans.bytesout) { - write_reg(trans.out, cntlr.data, data_length); + write_reg(trans.out, cntlr->data, data_length); spi_use_out(&trans, data_length); if (with_address) trans.offset += data_length; } /* Add proper control fields' values */ - control &= ~((cntlr.databytes - 1) << 8); + control &= ~((cntlr->databytes - 1) << 8); control |= SPIC_DS; control |= (data_length - 1) << 8; /* write it */ - writew_(control, cntlr.control); + writew_(control, cntlr->control); /* Wait for Cycle Done Status or Flash Cycle Error. */ status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); @@ -543,7 +547,7 @@ } if (trans.bytesin) { - read_reg(cntlr.data, trans.in, data_length); + read_reg(cntlr->data, trans.in, data_length); spi_use_in(&trans, data_length); if (with_address) trans.offset += data_length; @@ -552,7 +556,7 @@ spi_xfer_exit: /* Clear atomic preop now that xfer is done */ - writew_(0, cntlr.preop); + writew_(0, cntlr->preop); return 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/32879 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3487fb8ac317ce920bf1c3ef9d89590051932378 Gerrit-Change-Number: 32879 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/{baytrail/braswell/broadwell}: fix flashconsole on platform
by Matt DeVillier (Code Review) 22 May '19

22 May '19

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32878 Change subject: soc/{baytrail/braswell/broadwell}: fix flashconsole on platform ...................................................................... soc/{baytrail/braswell/broadwell}: fix flashconsole on platform Enabling flashconsole on these platforms fails to build due to spi.c not being compiled in prior to ramstage. Include in early stages (bootblock/romstage/postcar) as needed to enable flashconsole support. Early inclusion of monotonic_timer.c is needed for Broadwell as well. Change-Id: Idae0578ca92939246021bb85e34b0dcbd41df3b5 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/baytrail/Makefile.inc M src/soc/intel/braswell/Makefile.inc M src/soc/intel/broadwell/Makefile.inc 3 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/32878/1 diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index 0d4bac5..6e6eb9c 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -16,6 +16,8 @@ romstage-y += tsc_freq.c postcar-y += tsc_freq.c smm-y += tsc_freq.c +romstage-y += spi.c +postcar-y += spi.c ramstage-y += spi.c smm-y += spi.c ramstage-y += chip.c diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc index 6b466c6..e479a3c 100644 --- a/src/soc/intel/braswell/Makefile.inc +++ b/src/soc/intel/braswell/Makefile.inc @@ -15,10 +15,12 @@ romstage-y += memmap.c romstage-y += pmutil.c romstage-y += smbus.c +romstage-y += spi.c romstage-y += tsc_freq.c postcar-y += memmap.c postcar-y += iosf.c +postcar-y += spi.c postcar-y += tsc_freq.c ramstage-y += acpi.c diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index 40017eb..a79fa46 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -39,6 +39,9 @@ romstage-y += memmap.c postcar-y += memmap.c ramstage-y += minihd.c +bootblock-y += monotonic_timer.c +romstage-y += monotonic_timer.c +postcar-y += monotonic_timer.c ramstage-y += monotonic_timer.c smm-y += monotonic_timer.c ramstage-y += pch.c @@ -60,6 +63,9 @@ ramstage-y += smi.c smm-y += smihandler.c ramstage-y += smmrelocate.c +bootblock-y += spi.c +romstage-y += spi.c +postcar-y += spi.c ramstage-y += spi.c smm-$(CONFIG_SPI_FLASH_SMM) += spi.c ramstage-y += stage_cache.c -- To view, visit https://review.coreboot.org/c/coreboot/+/32878 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idae0578ca92939246021bb85e34b0dcbd41df3b5 Gerrit-Change-Number: 32878 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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