coreboot-gerrit May 2019

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Change in ...coreboot[master]: sb/intel/ibexpeak: Use common final SPI OPs setup
by Arthur Heymans (Code Review) 08 Jul '19

08 Jul '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33038 Change subject: sb/intel/ibexpeak: Use common final SPI OPs setup ...................................................................... sb/intel/ibexpeak: Use common final SPI OPs setup This also removes the relevant RCBA replays the mainboard dir. Change-Id: I75dd9d1bcd09d835f205a51c087d52ebb4e166f6 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/x201/mainboard.c M src/mainboard/packardbell/ms2290/mainboard.c M src/southbridge/intel/ibexpeak/lpc.c 3 files changed, 3 insertions(+), 54 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/33038/1 diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index b8129ad..d39a5bd 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -43,34 +43,6 @@ return ARRAY_SIZE(cst_entries); } -static void mainboard_init(struct device *dev) -{ - printk(BIOS_SPEW, "starting SPI configuration\n"); - - /* Configure SPI. */ - RCBA32(0x3800) = 0x07ff0500; - RCBA32(0x3804) = 0x3f046008; - RCBA32(0x3808) = 0x0058efc0; - RCBA32(0x384c) = 0x92000000; - RCBA32(0x3850) = 0x00000a0b; - RCBA32(0x3858) = 0x07ff0500; - RCBA32(0x385c) = 0x04ff0003; - RCBA32(0x3860) = 0x00020001; - RCBA32(0x3864) = 0x00000fff; - RCBA32(0x3874) = 0; - RCBA32(0x3890) = 0xf8400000; - RCBA32(0x3894) = 0x143b5006; - RCBA32(0x3898) = 0x05200302; - RCBA32(0x389c) = 0x0601209f; - RCBA32(0x38b0) = 0x00000004; - RCBA32(0x38b4) = 0x03040002; - RCBA32(0x38c8) = 0x00002005; - RCBA32(0x38c4) = 0x00802005; - RCBA32(0x3804) = 0x3f04e008; - - printk(BIOS_SPEW, "SPI configured\n"); -} - static void fill_ssdt(struct device *device) { drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 0); @@ -80,7 +52,6 @@ { u16 pmbase; - dev->ops->init = mainboard_init; dev->ops->acpi_fill_ssdt_generator = fill_ssdt; pmbase = pci_read_config32(pcidev_on_root(0x1f, 0), diff --git a/src/mainboard/packardbell/ms2290/mainboard.c b/src/mainboard/packardbell/ms2290/mainboard.c index 09310ae..6bb546f 100644 --- a/src/mainboard/packardbell/ms2290/mainboard.c +++ b/src/mainboard/packardbell/ms2290/mainboard.c @@ -50,31 +50,6 @@ { u16 pmbase; - printk(BIOS_SPEW, "starting SPI configuration\n"); - - /* Configure SPI. */ - RCBA32(0x3800) = 0x07ff0500; - RCBA32(0x3804) = 0x3f046008; - RCBA32(0x3808) = 0x0058efc0; - RCBA32(0x384c) = 0x92000000; - RCBA32(0x3850) = 0x00000a0b; - RCBA32(0x3858) = 0x07ff0500; - RCBA32(0x385c) = 0x04ff0003; - RCBA32(0x3860) = 0x00020001; - RCBA32(0x3864) = 0x00000fff; - RCBA32(0x3874) = 0; - RCBA32(0x3890) = 0xf8400000; - RCBA32(0x3894) = 0x143b5006; - RCBA32(0x3898) = 0x05200302; - RCBA32(0x389c) = 0x0601209f; - RCBA32(0x38b0) = 0x00000004; - RCBA32(0x38b4) = 0x03040002; - RCBA32(0x38c8) = 0x00002005; - RCBA32(0x38c4) = 0x00802005; - RCBA32(0x3804) = 0x3f04e008; - - printk(BIOS_SPEW, "SPI configured\n"); - int i; const u8 dmp[256] = { 0x00, 0x20, 0x00, 0x00, 0x00, 0x02, 0x89, 0xe4, 0x30, 0x00, 0x40, 0x14, 0x00, 0x00, 0x00, 0x11, diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index e7162b1..fa1ca92 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -38,6 +38,7 @@ #include "nvs.h" #include <southbridge/intel/common/pciehp.h> #include <southbridge/intel/common/acpi_pirq_gen.h> +#include <southbridge/intel/common/spi.h> #define NMI_OFF 0 @@ -785,6 +786,8 @@ static void lpc_final(struct device *dev) { + spi_finalize_ops(); + /* Call SMM finalize() handlers before resume */ if (CONFIG(HAVE_SMI_HANDLER)) { if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || -- To view, visit https://review.coreboot.org/c/coreboot/+/33038 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I75dd9d1bcd09d835f205a51c087d52ebb4e166f6 Gerrit-Change-Number: 33038 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sb/intel/i82801gx: Use common final SPI OPs setup
by Arthur Heymans (Code Review) 08 Jul '19

08 Jul '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33037 Change subject: sb/intel/i82801gx: Use common final SPI OPs setup ...................................................................... sb/intel/i82801gx: Use common final SPI OPs setup Change-Id: I30f80c237bccf8dc350249fd12ca6c4559d23d4f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/i82801gx/lpc.c 1 file changed, 2 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/33037/1 diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 948b6aa..b226b23 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -33,6 +33,7 @@ #include <drivers/intel/gma/i915.h> #include <southbridge/intel/common/acpi_pirq_gen.h> #include <southbridge/intel/common/pmbase.h> +#include <southbridge/intel/common/spi.h> #include "i82801gx.h" #include "nvs.h" @@ -620,11 +621,7 @@ if (!CONFIG(INTEL_CHIPSET_LOCKDOWN)) return; - SPIBAR16(PREOP) = SPI_OPPREFIX; - /* Set SPI opcode menu */ - SPIBAR16(OPTYPE) = SPI_OPTYPE; - SPIBAR32(OPMENU) = SPI_OPMENU_LOWER; - SPIBAR32(OPMENU + 4) = SPI_OPMENU_UPPER; + spi_finalize_ops(); /* Lock SPIBAR */ SPIBAR16(0) = SPIBAR16(0) | (1 << 15); -- To view, visit https://review.coreboot.org/c/coreboot/+/33037 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30f80c237bccf8dc350249fd12ca6c4559d23d4f Gerrit-Change-Number: 33037 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sb/intel/common: Add a common interface to set final OPs settings
by Arthur Heymans (Code Review) 08 Jul '19

08 Jul '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33036 Change subject: sb/intel/common: Add a common interface to set final OPs settings ...................................................................... sb/intel/common: Add a common interface to set final OPs settings This adds a common place to set the final opprefix, optype and opmenu, with a hook to override the opmenu. Change-Id: I162ae6bad7da3ea02b96854ee28e70594e210947 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/common/spi.c A src/southbridge/intel/common/spi.h 2 files changed, 79 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/33036/1 diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index bf2a44c..0794bb7 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -31,6 +31,8 @@ #include <spi-generic.h> +#include "spi.h" + #define HSFC_FCYCLE_OFF 1 /* 1-2: FLASH Cycle */ #define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_OFF) #define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */ @@ -1041,6 +1043,45 @@ return 0; } +void spi_finalize_ops(void) +{ + ich_spi_controller *cntlr = &g_cntlr; + u16 spi_opprefix;; + u16 optype = 0; + struct intel_spi_config spi_config = { + {0x06, 0x50}, /* OPPREFIXES: EWSR and WREN */ + { /* OPTYPE and OPCODE */ + {0x01, WRITE_NO_ADDR}, /* WRSR: Write Status Register */ + {0x02, WRITE_WITH_ADDR}, /* BYPR: Byte Program */ + {0x03, READ_WITH_ADDR}, /* READ: Read Data */ + {0x05, READ_NO_ADDR}, /* RDSR: Read Status Register */ + {0x20, WRITE_WITH_ADDR}, /* SE20: Sector Erase 0x20 */ + {0x9f, READ_NO_ADDR}, /* RDID: Read ID */ + {0xd8, WRITE_WITH_ADDR}, /* BED8: Block Erase 0xd8 */ + {0x0b, READ_WITH_ADDR}, /* FAST: Fast Read */ + } + }; + int i; + + if (g_ichspi_lock) + return; + + intel_southbridge_override_spi(&spi_config); + + spi_opprefix = spi_config.opprefixes[0] + | (spi_config.opprefixes[1] << 8); + writew_(spi_opprefix, cntlr->preop); + for (i = 0; i < ARRAY_SIZE(spi_config.ops); i++) { + optype |= (spi_config.ops[i].type & 3) << (i * 2); + writeb_(spi_config.ops[i].op, &cntlr->opmenu[i]); + } + writew_(optype, &cntlr->optype); +} + +__weak void intel_southbridge_override_spi(struct intel_spi_config *spi_config) +{ +} + static const struct spi_ctrlr spi_ctrlr = { .xfer_vector = xfer_vectors, .max_xfer_size = member_size(ich9_spi_regs, fdata), diff --git a/src/southbridge/intel/common/spi.h b/src/southbridge/intel/common/spi.h new file mode 100644 index 0000000..fcc5cd8 --- /dev/null +++ b/src/southbridge/intel/common/spi.h @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOUTHBRIDGE_INTEL_SPI_H +#define SOUTHBRIDGE_INTEL_SPI_H + +enum optype { + READ_NO_ADDR = 0, + WRITE_NO_ADDR = 1, + READ_WITH_ADDR = 2, + WRITE_WITH_ADDR = 3 +}; + +struct intel_spi_op { + u8 op; + enum optype type; +}; + +struct intel_spi_config { + u8 opprefixes[2]; + struct intel_spi_op ops[8]; +}; + +void spi_finalize_ops(void); +void intel_southbridge_override_spi(struct intel_spi_config *spi_config); + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/33036 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I162ae6bad7da3ea02b96854ee28e70594e210947 Gerrit-Change-Number: 33036 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: qemu-q35: die if started on wrong machine
by Patrick Rudolph (Code Review) 08 Jul '19

08 Jul '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31425 Change subject: qemu-q35: die if started on wrong machine ...................................................................... qemu-q35: die if started on wrong machine The QEMU machine "PC" doesn't support MCFG. Die in bootblock if the user selected the wrong qemu machine and print a message to use the correct machine type. Without this patch ramstage dies with non-helpful message: "get_pbus: dev is NULL!" Change-Id: I9d1b24176de971c5f827091bc5bc1bac8426f3f6 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/mainboard/emulation/qemu-q35/bootblock.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/31425/1 diff --git a/src/mainboard/emulation/qemu-q35/bootblock.c b/src/mainboard/emulation/qemu-q35/bootblock.c index 18a083d..96d3457 100644 --- a/src/mainboard/emulation/qemu-q35/bootblock.c +++ b/src/mainboard/emulation/qemu-q35/bootblock.c @@ -14,6 +14,7 @@ #include <arch/io.h> #include <bootblock_common.h> #include <southbridge/intel/i82801ix/i82801ix.h> +#include <console/console.h> /* Just define these here, there is no gm35.h file to include. */ #define D0F0_PCIEXBAR_LO 0x60 @@ -39,6 +40,11 @@ pci_io_write_config32(PCI_DEV(0,0,0), D0F0_PCIEXBAR_HI, reg); reg = CONFIG_MMCONF_BASE_ADDRESS | 1; /* 256MiB - 0-255 buses. */ pci_io_write_config32(PCI_DEV(0,0,0), D0F0_PCIEXBAR_LO, reg); + + /* MCFG is now active. If it's not qemu was started for machine PC */ + if (pci_read_config32(PCI_DEV(0,0,0), D0F0_PCIEXBAR_LO) != + (CONFIG_MMCONF_BASE_ADDRESS | 1)) + die("You must run qemu for machine Q35"); } static void enable_spi_prefetch(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/31425 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d1b24176de971c5f827091bc5bc1bac8426f3f6 Gerrit-Change-Number: 31425 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: payloads/external/Memtest86Plus: update to version 002 stable
by Martin Kepplinger (Code Review) 08 Jul '19

08 Jul '19

Martin Kepplinger has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32613 Change subject: payloads/external/Memtest86Plus: update to version 002 stable ...................................................................... payloads/external/Memtest86Plus: update to version 002 stable The memtest86plus project has been tagged as stable. Update the coreboot build accordingly. Change-Id: I078ac5d91e60a424efb5e14f39ae59e7ae9cbfe2 Signed-off-by: Martin Kepplinger <martink(a)posteo.de> --- M payloads/external/Memtest86Plus/Makefile 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/32613/1 diff --git a/payloads/external/Memtest86Plus/Makefile b/payloads/external/Memtest86Plus/Makefile index 4b3132d..b799f9e 100644 --- a/payloads/external/Memtest86Plus/Makefile +++ b/payloads/external/Memtest86Plus/Makefile @@ -15,7 +15,7 @@ TAG-$(CONFIG_MEMTEST_MASTER)=origin/master NAME-$(CONFIG_MEMTEST_MASTER)=Master -TAG-$(CONFIG_MEMTEST_STABLE)=3754fd440f4009b62244e0f95c56bbb12c2fffcb +TAG-$(CONFIG_MEMTEST_STABLE)=0bd34c22604660e4283316331f3e7bf8a3863753 NAME-$(CONFIG_MEMTEST_STABLE)=Stable TAG-$(CONFIG_MEMTEST_REVISION)=$(CONFIG_MEMTEST_REVISION_ID) -- To view, visit https://review.coreboot.org/c/coreboot/+/32613 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I078ac5d91e60a424efb5e14f39ae59e7ae9cbfe2 Gerrit-Change-Number: 32613 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Kepplinger <martink(a)posteo.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/hatch: Update GPIO settings
by Krishna P Bhat D (Code Review) 08 Jul '19

08 Jul '19

Krishna P Bhat D has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32176 Change subject: mb/google/hatch: Update GPIO settings ...................................................................... mb/google/hatch: Update GPIO settings This patch updates the following GPIO settings. 1. Set Native termination for GPP_G0 - G4 SD card pins. 2. Disable I2C #2 in devicetree. 3. Set GPP_B19, GPP_G7 to NF1. BUG=b:123907904 Change-Id: I4549ac7377d7f58f51cda0eb96a62604fd31d2f2 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> --- M src/mainboard/google/hatch/variants/baseboard/gpio.c M src/mainboard/google/hatch/variants/hatch/overridetree.cb M src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb 3 files changed, 11 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/32176/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 4d1c87e..10f851b 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -106,8 +106,8 @@ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* B18 : H1_SLAVE_SPI_MOSI_R */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), - /* B19 : GPP_B19 ==> NC */ - PAD_NC(GPP_B19, NONE), + /* B19 : Set to NF1 */ + PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), /* B20 : PCH_SPI_FPMCU_CLK_R */ PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), /* B21 : PCH_SPI_FPMCU_MISO */ @@ -329,21 +329,21 @@ PAD_NC(GPP_F23, NONE), /* G0 : SD_CMD */ - PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G0, NATIVE, DEEP, NF1), /* G1 : SD_DATA0 */ - PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G1, NATIVE, DEEP, NF1), /* G2 : SD_DATA1 */ - PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G2, NATIVE, DEEP, NF1), /* G3 : SD_DATA2 */ - PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G3, NATIVE, DEEP, NF1), /* G4 : SD_DATA3 */ - PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G4, NATIVE, DEEP, NF1), /* G5 : SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), /* G6 : SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), - /* G7 : SD_WP => NC */ - PAD_NC(GPP_G7, DN_20K), + /* G7 : Set to NF1 */ + PAD_CFG_NF(GPP_G7, NONE, DEEP, NF1), /* * H0 : HP_INT_L diff --git a/src/mainboard/google/hatch/variants/hatch/overridetree.cb b/src/mainboard/google/hatch/variants/hatch/overridetree.cb index 28644d1..57daba2 100644 --- a/src/mainboard/google/hatch/variants/hatch/overridetree.cb +++ b/src/mainboard/google/hatch/variants/hatch/overridetree.cb @@ -69,7 +69,7 @@ device i2c 49 on end end end # I2C #1 - device pci 15.2 on + device pci 15.2 off chip drivers/generic/gpio_keys register "name" = ""PENH"" register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_HIGH(GPP_A8)" diff --git a/src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb b/src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb index 9b772c2..098bca6 100644 --- a/src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb +++ b/src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb @@ -54,7 +54,7 @@ device i2c 49 on end end end # I2C #1 - device pci 15.2 on + device pci 15.2 off chip drivers/generic/gpio_keys register "name" = ""PENH"" register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_HIGH(GPP_A8)" -- To view, visit https://review.coreboot.org/c/coreboot/+/32176 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4549ac7377d7f58f51cda0eb96a62604fd31d2f2 Gerrit-Change-Number: 32176 Gerrit-PatchSet: 1 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: WIP: mediatek/mt8183: update dcxo setting
by Weiyi Lu (Code Review) 07 Jul '19

07 Jul '19

Hello Weiyi Lu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32323 to review the following change. Change subject: WIP: mediatek/mt8183: update dcxo setting ...................................................................... WIP: mediatek/mt8183: update dcxo setting Disable unused DCXO and power mode. BRANCH=none TEST=Boots correctly on Kukui. Change-Id: I2e5ce181ad327ccf852979da53baca4f249912fe Signed-off-by: Weiyi Lu <weiyi.lu(a)mediatek.com> --- M src/soc/mediatek/mt8183/include/soc/rtc.h M src/soc/mediatek/mt8183/rtc.c 2 files changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/32323/1 diff --git a/src/soc/mediatek/mt8183/include/soc/rtc.h b/src/soc/mediatek/mt8183/include/soc/rtc.h index 3d115fe..a721ff8 100644 --- a/src/soc/mediatek/mt8183/include/soc/rtc.h +++ b/src/soc/mediatek/mt8183/include/soc/rtc.h @@ -140,6 +140,7 @@ PMIC_RG_DCXO_CW15 = 0x07AE, PMIC_RG_DCXO_CW16 = 0x07B0, PMIC_RG_DCXO_CW21 = 0x07BA, + PMIC_RG_DCXO_CW23 = 0x07BE, PMIC_RG_DCXO_ELR0 = 0x07C4 }; diff --git a/src/soc/mediatek/mt8183/rtc.c b/src/soc/mediatek/mt8183/rtc.c index 62256eb..57f26e8 100644 --- a/src/soc/mediatek/mt8183/rtc.c +++ b/src/soc/mediatek/mt8183/rtc.c @@ -281,9 +281,10 @@ rtc_write(PMIC_RG_DCXO_CW16, 0x9855); /* 26M enable control */ - /* Enable clock buffer XO_SOC, XO_CEL */ - rtc_write(PMIC_RG_DCXO_CW00, 0x4805); + /* Enable clock buffer XO_SOC */ + rtc_write(PMIC_RG_DCXO_CW00, 0x4005); rtc_write(PMIC_RG_DCXO_CW11, 0x8000); + rtc_write(PMIC_RG_DCXO_CW23, 0x0053); /* Load thermal coefficient */ rtc_write(PMIC_RG_TOP_TMA_KEY, 0x9CA7); -- To view, visit https://review.coreboot.org/c/coreboot/+/32323 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e5ce181ad327ccf852979da53baca4f249912fe Gerrit-Change-Number: 32323 Gerrit-PatchSet: 1 Gerrit-Owner: Weiyi Lu <weiyi.lu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Weiyi Lu <weiyi.lu(a)mediatek.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: arch/mips: Make MIPS specific options depend on select ARCH_MIPS
by Arthur Heymans (Code Review) 07 Jul '19

07 Jul '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31312 Change subject: arch/mips: Make MIPS specific options depend on select ARCH_MIPS ...................................................................... arch/mips: Make MIPS specific options depend on select ARCH_MIPS Also don't define the default as this result in spurious lines in the .config. Change-Id: I7f35a5a9dcbc7b25b7806056e2b8e822fa94e428 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/mips/Kconfig M src/soc/imgtec/pistachio/Kconfig 2 files changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/31312/1 diff --git a/src/arch/mips/Kconfig b/src/arch/mips/Kconfig index 9e51d9c..b8570c1 100644 --- a/src/arch/mips/Kconfig +++ b/src/arch/mips/Kconfig @@ -16,12 +16,12 @@ config ARCH_MIPS bool - default n + +if ARCH_MIPS config ARCH_BOOTBLOCK_MIPS bool default n - select ARCH_MIPS select BOOTBLOCK_CUSTOM select C_ENVIRONMENT_BOOTBLOCK @@ -36,3 +36,5 @@ config ARCH_RAMSTAGE_MIPS bool default n + +endif # if ARCH_MIPS diff --git a/src/soc/imgtec/pistachio/Kconfig b/src/soc/imgtec/pistachio/Kconfig index 333216d..40b63c3 100644 --- a/src/soc/imgtec/pistachio/Kconfig +++ b/src/soc/imgtec/pistachio/Kconfig @@ -15,6 +15,7 @@ # config CPU_IMGTEC_PISTACHIO + select ARCH_MIPS select ARCH_BOOTBLOCK_MIPS select ARCH_VERSTAGE_MIPS select ARCH_ROMSTAGE_MIPS -- To view, visit https://review.coreboot.org/c/coreboot/+/31312 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f35a5a9dcbc7b25b7806056e2b8e822fa94e428 Gerrit-Change-Number: 31312 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mediatek/mt8183: Enable RTC eosc calibration feature to save power
by Ran Bi (Code Review) 06 Jul '19

06 Jul '19

Ran Bi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32339 Change subject: mediatek/mt8183: Enable RTC eosc calibration feature to save power ...................................................................... mediatek/mt8183: Enable RTC eosc calibration feature to save power When system shutdown, RTC enable eosc calibration feature to save power. Then coreboot RTC driver need to call rtc_enable_dcxo function at every boot up to switch RTC clock source to a more accurate one. BUG=b:128467245 BRANCH=none TEST=Boots correctly on Kukui Change-Id: Iee21e7611df8959cbbc63b6e6655cfb462147748 Signed-off-by: Ran Bi <ran.bi(a)mediatek.com> --- M src/soc/mediatek/mt8183/rtc.c 1 file changed, 4 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/32339/1 diff --git a/src/soc/mediatek/mt8183/rtc.c b/src/soc/mediatek/mt8183/rtc.c index 62256eb..ba05f86 100644 --- a/src/soc/mediatek/mt8183/rtc.c +++ b/src/soc/mediatek/mt8183/rtc.c @@ -197,12 +197,6 @@ goto err; } - /* using dcxo 32K clock */ - if (!rtc_enable_dcxo()) { - ret = -RTC_STATUS_OSC_SETTING_FAIL; - goto err; - } - if (recover) mdelay(20); @@ -311,6 +305,10 @@ pwrap_write_field(PMIC_RG_DCXO_CW02, 0xF, 0xF, 0); pwrap_write_field(PMIC_RG_SCK_TOP_CON0, 0x1, 0x1, 0); + /* using dcxo 32K clock */ + if (!rtc_enable_dcxo()) + rtc_info("rtc_enable_dcxo() fail\n"); + rtc_boot_common(); rtc_bbpu_power_on(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/32339 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee21e7611df8959cbbc63b6e6655cfb462147748 Gerrit-Change-Number: 32339 Gerrit-PatchSet: 1 Gerrit-Owner: Ran Bi <ran.bi(a)mediatek.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: arch/riscv: Don't select ARCH_RISCV_M on non-ARCH_RISCV platforms
by Arthur Heymans (Code Review) 02 Jul '19

02 Jul '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31311 Change subject: arch/riscv: Don't select ARCH_RISCV_M on non-ARCH_RISCV platforms ...................................................................... arch/riscv: Don't select ARCH_RISCV_M on non-ARCH_RISCV platforms Change-Id: I3e8c1cc5696d621e243696a3b5e34f62ab69a688 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/riscv/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/31311/1 diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig index 9d325af..f5253bb 100644 --- a/src/arch/riscv/Kconfig +++ b/src/arch/riscv/Kconfig @@ -24,6 +24,7 @@ # one implementation that will not have it due # to security concerns. bool + depends on ARCH_RISCV default n if ARCH_RISCV_M_DISABLED default y -- To view, visit https://review.coreboot.org/c/coreboot/+/31311 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e8c1cc5696d621e243696a3b5e34f62ab69a688 Gerrit-Change-Number: 31311 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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