coreboot-gerrit May 2019

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Change in ...coreboot[master]: [WIP] Documentation: How to run coreboot on PC Engines apu1
by Piotr Kleinschmidt (Code Review) 24 Jun '19

24 Jun '19

Piotr Kleinschmidt has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32907 Change subject: [WIP] Documentation: How to run coreboot on PC Engines apu1 ...................................................................... [WIP] Documentation: How to run coreboot on PC Engines apu1 There were no documentation about running coreboot on apu1 platform, so now it describes how to do this. Signed-off-by: Piotr Kleinschmidt <piotr.kleinschmidt(a)3mdeb.com> Change-Id: If79693e893c4afe52bf1c9aa8017ac6f650a96e4 --- A Documentation/mainboard/pcengines/apu1.md A Documentation/mainboard/pcengines/apu1c1_flash.jpg 2 files changed, 63 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/32907/1 diff --git a/Documentation/mainboard/pcengines/apu1.md b/Documentation/mainboard/pcengines/apu1.md new file mode 100644 index 0000000..20259a6 --- /dev/null +++ b/Documentation/mainboard/pcengines/apu1.md @@ -0,0 +1,63 @@ +# PC Engines apu1 + +This page describes how to run coreboot on PC Engines apu1 platform. + +## Technology + +| | | +| -----------|:-------------------------------------------------------| +| CPU | AMD G series T40E APU | +| CPU core | 1 GHz dual core (Bobcat core) with 64 bit support | +| | 32K data + 32K instruction + 512KB L2 cache per core | +| DRAM | 2 or 4 GB DDR3-1066 DRAM | +| Boot | From SD card, USB, m-SATA | +| Power | 6 to 12W of 12V power | +| Firmware | coreboot with support for iPXE and USB boot | + +## Flashing coreboot + +| Type | Value | +|---------------------|:-----------| +| Socketed flash | no | +| Model | MX25L1606E | +| Size | 2 MiB | +| Package | SOP-8 | +| Write protection | no | +| Dual BIOS feature | no | +| Internal flashing | yes | + +### Internal programming + +The SPI flash can be accessed using [flashrom]. It is important to execute +command with a `-c <chipname>` argument: + +`flashrom -p internal -c MX25L1606E -w coreboot.rom ` + +### External programming + +**IMPORTANT**: When programming SPI flash, first you need to enter apu1 in S5 +(Soft-off) power state. More details about that state is available in ACPI +Specification documentation. + +The external access to flash chip is available through standard SOP-8 clip or +SOP-8 header which is next to the flash chip on the board. Notice that not all +boards have a header soldered down originally. Hence, there could be an empty +slot with 8 eyelets, so you can solder down a header on your own. The SPI flash +chip and SPI header are marked in the picture below. + +There is no restrictions as to programmer device. However, [flashrom] is +strongly recommended. The example command to program SPI flash with a linux_spi +is: + +`flashrom -w coreboot.rom -p linux_spi:dev=/dev/spidev1.0,spispeed=16000 -c +"MX25L1606E"` + + +**apu1 platform with marked in SPI header and SPI flash chip** +![][apu1c1_flash] + +[apu1c1_flash]: apu1c1_flash.jpg + + +[flashrom]: https://flashrom.org/Flashrom +[here]: https://www.coreboot.org/Binary_situation diff --git a/Documentation/mainboard/pcengines/apu1c1_flash.jpg b/Documentation/mainboard/pcengines/apu1c1_flash.jpg new file mode 100644 index 0000000..069e976 --- /dev/null +++ b/Documentation/mainboard/pcengines/apu1c1_flash.jpg Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/32907 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If79693e893c4afe52bf1c9aa8017ac6f650a96e4 Gerrit-Change-Number: 32907 Gerrit-PatchSet: 1 Gerrit-Owner: Piotr Kleinschmidt <piotr.kleinschmidt(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mainboard: Use 'include <stdlib.h>' when appropriate
by HAOUAS Elyes (Code Review) 24 Jun '19

24 Jun '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32825 Change subject: mainboard: Use 'include <stdlib.h>' when appropriate ...................................................................... mainboard: Use 'include <stdlib.h>' when appropriate Change-Id: I2c8ccdab0962459b467ac7b582de8860ea1eecd5 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/advansus/a785e-i/get_bus_conf.c M src/mainboard/amd/bettong/BiosCallOuts.c M src/mainboard/amd/bimini_fam10/get_bus_conf.c M src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c M src/mainboard/amd/gardenia/BiosCallOuts.c M src/mainboard/amd/inagua/BiosCallOuts.c M src/mainboard/amd/inagua/buildOpts.c M src/mainboard/amd/lamar/BiosCallOuts.c M src/mainboard/amd/mahogany_fam10/get_bus_conf.c M src/mainboard/amd/olivehill/BiosCallOuts.c M src/mainboard/amd/olivehill/buildOpts.c M src/mainboard/amd/olivehillplus/BiosCallOuts.c M src/mainboard/amd/parmer/BiosCallOuts.c M src/mainboard/amd/parmer/buildOpts.c M src/mainboard/amd/persimmon/BiosCallOuts.c M src/mainboard/amd/persimmon/buildOpts.c M src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c M src/mainboard/amd/south_station/BiosCallOuts.c M src/mainboard/amd/south_station/buildOpts.c M src/mainboard/amd/thatcher/BiosCallOuts.c M src/mainboard/amd/thatcher/buildOpts.c M src/mainboard/amd/tilapia_fam10/get_bus_conf.c M src/mainboard/amd/torpedo/BiosCallOuts.c M src/mainboard/amd/torpedo/buildOpts.c M src/mainboard/amd/union_station/BiosCallOuts.c M src/mainboard/amd/union_station/buildOpts.c M src/mainboard/asrock/e350m1/BiosCallOuts.c M src/mainboard/asrock/e350m1/buildOpts.c M src/mainboard/asrock/imb-a180/BiosCallOuts.c M src/mainboard/asrock/imb-a180/buildOpts.c M src/mainboard/asus/am1i-a/BiosCallOuts.c M src/mainboard/asus/am1i-a/buildOpts.c M src/mainboard/asus/f2a85-m/BiosCallOuts.c M src/mainboard/asus/f2a85-m/buildOpts.c M src/mainboard/asus/kcma-d8/get_bus_conf.c M src/mainboard/asus/kfsn4-dre/get_bus_conf.c M src/mainboard/asus/kgpe-d16/get_bus_conf.c M src/mainboard/asus/m4a78-em/get_bus_conf.c M src/mainboard/asus/m4a785-m/get_bus_conf.c M src/mainboard/asus/m5a88-v/get_bus_conf.c M src/mainboard/avalue/eax-785e/get_bus_conf.c M src/mainboard/bap/ode_e20XX/BiosCallOuts.c M src/mainboard/bap/ode_e20XX/buildOpts.c M src/mainboard/bap/ode_e21XX/BiosCallOuts.c M src/mainboard/biostar/a68n_5200/BiosCallOuts.c M src/mainboard/biostar/a68n_5200/buildOpts.c M src/mainboard/biostar/am1ml/BiosCallOuts.c M src/mainboard/biostar/am1ml/buildOpts.c M src/mainboard/cavium/cn8100_sff_evb/romstage.c M src/mainboard/elmex/pcm205400/BiosCallOuts.c M src/mainboard/elmex/pcm205400/buildOpts.c M src/mainboard/gigabyte/ma785gm/get_bus_conf.c M src/mainboard/gigabyte/ma785gmt/get_bus_conf.c M src/mainboard/gigabyte/ma78gm/get_bus_conf.c M src/mainboard/gizmosphere/gizmo/BiosCallOuts.c M src/mainboard/gizmosphere/gizmo/buildOpts.c M src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c M src/mainboard/gizmosphere/gizmo2/buildOpts.c M src/mainboard/google/beltino/romstage.c M src/mainboard/google/beltino/variants/mccloud/hda_verb.c M src/mainboard/google/beltino/variants/monroe/hda_verb.c M src/mainboard/google/beltino/variants/panther/hda_verb.c M src/mainboard/google/beltino/variants/tricky/hda_verb.c M src/mainboard/google/beltino/variants/zako/hda_verb.c M src/mainboard/google/cyan/variants/banon/gpio.c M src/mainboard/google/cyan/variants/celes/gpio.c M src/mainboard/google/cyan/variants/cyan/gpio.c M src/mainboard/google/cyan/variants/edgar/gpio.c M src/mainboard/google/cyan/variants/kefka/gpio.c M src/mainboard/google/cyan/variants/reks/gpio.c M src/mainboard/google/cyan/variants/relm/gpio.c M src/mainboard/google/cyan/variants/setzer/gpio.c M src/mainboard/google/cyan/variants/terra/gpio.c M src/mainboard/google/cyan/variants/ultima/gpio.c M src/mainboard/google/cyan/variants/wizpig/gpio.c M src/mainboard/google/daisy/memory.c M src/mainboard/google/foster/pmic.c M src/mainboard/google/gale/boardid.c M src/mainboard/google/glados/mainboard.c M src/mainboard/google/gru/boardid.c M src/mainboard/google/link/i915.c M src/mainboard/google/nyan/pmic.c M src/mainboard/google/nyan_big/boardid.c M src/mainboard/google/nyan_big/pmic.c M src/mainboard/google/nyan_blaze/boardid.c M src/mainboard/google/nyan_blaze/pmic.c M src/mainboard/google/oak/boardid.c M src/mainboard/google/oak/sdram_configs.c M src/mainboard/google/peach_pit/mainboard.c M src/mainboard/google/peach_pit/memory.c M src/mainboard/google/peach_pit/romstage.c M src/mainboard/google/rambi/variants/banjo/gpio.c M src/mainboard/google/rambi/variants/candy/gpio.c M src/mainboard/google/rambi/variants/clapper/gpio.c M src/mainboard/google/rambi/variants/enguarde/gpio.c M src/mainboard/google/rambi/variants/glimmer/gpio.c M src/mainboard/google/rambi/variants/gnawty/gpio.c M src/mainboard/google/rambi/variants/heli/gpio.c M src/mainboard/google/rambi/variants/kip/gpio.c M src/mainboard/google/rambi/variants/ninja/gpio.c M src/mainboard/google/rambi/variants/orco/gpio.c M src/mainboard/google/rambi/variants/quawks/gpio.c M src/mainboard/google/rambi/variants/rambi/gpio.c M src/mainboard/google/rambi/variants/squawks/gpio.c M src/mainboard/google/rambi/variants/sumo/gpio.c M src/mainboard/google/rambi/variants/swanky/gpio.c M src/mainboard/google/rambi/variants/winky/gpio.c M src/mainboard/google/slippy/variants/falco/romstage.c M src/mainboard/google/smaug/boardid.c M src/mainboard/google/smaug/pmic.c M src/mainboard/google/storm/boardid.c M src/mainboard/google/veyron/boardid.c M src/mainboard/google/veyron/romstage.c M src/mainboard/google/veyron_mickey/boardid.c M src/mainboard/google/veyron_mickey/romstage.c M src/mainboard/google/veyron_rialto/boardid.c M src/mainboard/google/veyron_rialto/romstage.c M src/mainboard/hp/abm/BiosCallOuts.c M src/mainboard/hp/abm/buildOpts.c M src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c M src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c M src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c M src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c M src/mainboard/intel/kblrvp/mainboard.c M src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c M src/mainboard/jetway/nf81-t56n-lf/buildOpts.c M src/mainboard/jetway/pa78vm5/get_bus_conf.c M src/mainboard/lenovo/g505s/BiosCallOuts.c M src/mainboard/lenovo/g505s/buildOpts.c M src/mainboard/lippert/frontrunner-af/BiosCallOuts.c M src/mainboard/lippert/frontrunner-af/buildOpts.c M src/mainboard/lippert/frontrunner-af/mainboard.c M src/mainboard/lippert/toucan-af/BiosCallOuts.c M src/mainboard/lippert/toucan-af/buildOpts.c M src/mainboard/lippert/toucan-af/mainboard.c M src/mainboard/msi/ms7721/BiosCallOuts.c M src/mainboard/msi/ms7721/buildOpts.c M src/mainboard/msi/ms9652_fam10/get_bus_conf.c M src/mainboard/opencellular/elgon/romstage.c M src/mainboard/pcengines/apu1/BiosCallOuts.c M src/mainboard/pcengines/apu1/buildOpts.c M src/mainboard/pcengines/apu2/BiosCallOuts.c M src/mainboard/roda/rk9/mainboard.c M src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c M src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c M src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c M src/mainboard/tyan/s2912_fam10/get_bus_conf.c 147 files changed, 3 insertions(+), 195 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/32825/1 diff --git a/src/mainboard/advansus/a785e-i/get_bus_conf.c b/src/mainboard/advansus/a785e-i/get_bus_conf.c index 6b5ae68..7aca540 100644 --- a/src/mainboard/advansus/a785e-i/get_bus_conf.c +++ b/src/mainboard/advansus/a785e-i/get_bus_conf.c @@ -15,7 +15,6 @@ #include <device/pci.h> #include <stdint.h> -#include <stdlib.h> #include <cpu/amd/multicore.h> #include <cpu/amd/amdfam10_sysconf.h> diff --git a/src/mainboard/amd/bettong/BiosCallOuts.c b/src/mainboard/amd/bettong/BiosCallOuts.c index d318d0c..e017cf8 100644 --- a/src/mainboard/amd/bettong/BiosCallOuts.c +++ b/src/mainboard/amd/bettong/BiosCallOuts.c @@ -20,7 +20,6 @@ #include <northbridge/amd/agesa/BiosCallOuts.h> #include <northbridge/amd/pi/00660F01/chip.h> #include <FchPlatform.h> -#include <stdlib.h> #include <string.h> #include <northbridge/amd/pi/dimmSpd.h> #include <northbridge/amd/pi/agesawrapper.h> diff --git a/src/mainboard/amd/bimini_fam10/get_bus_conf.c b/src/mainboard/amd/bimini_fam10/get_bus_conf.c index 4021c51..a9db67a 100644 --- a/src/mainboard/amd/bimini_fam10/get_bus_conf.c +++ b/src/mainboard/amd/bimini_fam10/get_bus_conf.c @@ -15,7 +15,6 @@ #include <device/pci.h> #include <stdint.h> -#include <stdlib.h> #include <cpu/amd/multicore.h> #include <cpu/amd/amdfam10_sysconf.h> diff --git a/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c b/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c index 056daa2..22ce064 100644 --- a/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c +++ b/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c @@ -19,7 +19,6 @@ #include <northbridge/amd/agesa/BiosCallOuts.h> #include <device/azalia.h> #include <FchPlatform.h> -#include <stdlib.h> #include "imc.h" #include "hudson.h" diff --git a/src/mainboard/amd/gardenia/BiosCallOuts.c b/src/mainboard/amd/gardenia/BiosCallOuts.c index d4fb55a..ee92326 100644 --- a/src/mainboard/amd/gardenia/BiosCallOuts.c +++ b/src/mainboard/amd/gardenia/BiosCallOuts.c @@ -16,7 +16,6 @@ #include <amdblocks/agesawrapper.h> #include <amdblocks/BiosCallOuts.h> #include <soc/southbridge.h> -#include <stdlib.h> void platform_FchParams_env(FCH_DATA_BLOCK *FchParams_env) { diff --git a/src/mainboard/amd/inagua/BiosCallOuts.c b/src/mainboard/amd/inagua/BiosCallOuts.c index b6267a6..0a24def 100644 --- a/src/mainboard/amd/inagua/BiosCallOuts.c +++ b/src/mainboard/amd/inagua/BiosCallOuts.c @@ -18,7 +18,6 @@ #include <northbridge/amd/agesa/BiosCallOuts.h> #include <SB800.h> #include <southbridge/amd/cimx/sb800/gpio_oem.h> -#include <stdlib.h> static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr); static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr); diff --git a/src/mainboard/amd/inagua/buildOpts.c b/src/mainboard/amd/inagua/buildOpts.c index fe6fac0..f1e46c9 100644 --- a/src/mainboard/amd/inagua/buildOpts.c +++ b/src/mainboard/amd/inagua/buildOpts.c @@ -25,7 +25,6 @@ * */ -#include <stdlib.h> /* Select the CPU family. */ diff --git a/src/mainboard/amd/lamar/BiosCallOuts.c b/src/mainboard/amd/lamar/BiosCallOuts.c index 8e49e8e..142f9ea 100644 --- a/src/mainboard/amd/lamar/BiosCallOuts.c +++ b/src/mainboard/amd/lamar/BiosCallOuts.c @@ -17,7 +17,6 @@ #include <console/console.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include <FchPlatform.h> -#include <stdlib.h> #include <device/azalia.h> #include "imc.h" diff --git a/src/mainboard/amd/mahogany_fam10/get_bus_conf.c b/src/mainboard/amd/mahogany_fam10/get_bus_conf.c index ee2a6ca..24e44e6 100644 --- a/src/mainboard/amd/mahogany_fam10/get_bus_conf.c +++ b/src/mainboard/amd/mahogany_fam10/get_bus_conf.c @@ -15,7 +15,6 @@ #include <device/pci.h> #include <stdint.h> -#include <stdlib.h> #include <cpu/amd/multicore.h> #include <cpu/amd/amdfam10_sysconf.h> diff --git a/src/mainboard/amd/olivehill/BiosCallOuts.c b/src/mainboard/amd/olivehill/BiosCallOuts.c index b6a8a3a..1865034 100644 --- a/src/mainboard/amd/olivehill/BiosCallOuts.c +++ b/src/mainboard/amd/olivehill/BiosCallOuts.c @@ -17,7 +17,6 @@ #include <northbridge/amd/agesa/BiosCallOuts.h> #include <northbridge/amd/agesa/state_machine.h> #include <FchPlatform.h> -#include <stdlib.h> #include "imc.h" diff --git a/src/mainboard/amd/olivehill/buildOpts.c b/src/mainboard/amd/olivehill/buildOpts.c index 65b86b8..bb8527d 100644 --- a/src/mainboard/amd/olivehill/buildOpts.c +++ b/src/mainboard/amd/olivehill/buildOpts.c @@ -25,7 +25,6 @@ * */ -#include <stdlib.h> #include <AGESA.h> #define INSTALL_FT3_SOCKET_SUPPORT TRUE diff --git a/src/mainboard/amd/olivehillplus/BiosCallOuts.c b/src/mainboard/amd/olivehillplus/BiosCallOuts.c index 8975dc8..98fc5e7 100644 --- a/src/mainboard/amd/olivehillplus/BiosCallOuts.c +++ b/src/mainboard/amd/olivehillplus/BiosCallOuts.c @@ -17,7 +17,6 @@ #include <console/console.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include <FchPlatform.h> -#include <stdlib.h> #include "imc.h" #include "hudson.h" diff --git a/src/mainboard/amd/parmer/BiosCallOuts.c b/src/mainboard/amd/parmer/BiosCallOuts.c index 0c54211..89062b6 100644 --- a/src/mainboard/amd/parmer/BiosCallOuts.c +++ b/src/mainboard/amd/parmer/BiosCallOuts.c @@ -17,7 +17,6 @@ #include <northbridge/amd/agesa/BiosCallOuts.h> #include <northbridge/amd/agesa/state_machine.h> #include <FchPlatform.h> -#include <stdlib.h> #include "imc.h" diff --git a/src/mainboard/amd/parmer/buildOpts.c b/src/mainboard/amd/parmer/buildOpts.c index 7ff6caa..93fcd35 100644 --- a/src/mainboard/amd/parmer/buildOpts.c +++ b/src/mainboard/amd/parmer/buildOpts.c @@ -25,7 +25,6 @@ * */ -#include <stdlib.h> #include <AGESA.h> /* Select the CPU family. */ diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.c b/src/mainboard/amd/persimmon/BiosCallOuts.c index 60ce3ee..b1403ec 100644 --- a/src/mainboard/amd/persimmon/BiosCallOuts.c +++ b/src/mainboard/amd/persimmon/BiosCallOuts.c @@ -17,7 +17,6 @@ #include <amdlib.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include <SB800.h> -#include <stdlib.h> static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr); static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr); diff --git a/src/mainboard/amd/persimmon/buildOpts.c b/src/mainboard/amd/persimmon/buildOpts.c index d99cc81..9212ec1 100644 --- a/src/mainboard/amd/persimmon/buildOpts.c +++ b/src/mainboard/amd/persimmon/buildOpts.c @@ -25,7 +25,6 @@ * */ -#include <stdlib.h> /* Select the CPU family. */ diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c b/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c index e1f2409..727767f 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c @@ -18,10 +18,8 @@ #include <device/pci_ops.h> #include <stdint.h> #include <cpu/amd/multicore.h> - #include <cpu/amd/amdfam10_sysconf.h> -#include <stdlib.h> #include "mb_sysconf.h" /* Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables */ diff --git a/src/mainboard/amd/south_station/BiosCallOuts.c b/src/mainboard/amd/south_station/BiosCallOuts.c index ecb7e1c..9cfb646 100644 --- a/src/mainboard/amd/south_station/BiosCallOuts.c +++ b/src/mainboard/amd/south_station/BiosCallOuts.c @@ -18,7 +18,6 @@ #include <northbridge/amd/agesa/BiosCallOuts.h> #include <SB800.h> #include <southbridge/amd/cimx/sb800/gpio_oem.h> -#include <stdlib.h> static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr); static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr); diff --git a/src/mainboard/amd/south_station/buildOpts.c b/src/mainboard/amd/south_station/buildOpts.c index 244229d..929408f 100644 --- a/src/mainboard/amd/south_station/buildOpts.c +++ b/src/mainboard/amd/south_station/buildOpts.c @@ -25,7 +25,6 @@ * */ -#include <stdlib.h> /* Select the CPU family. */ diff --git a/src/mainboard/amd/thatcher/BiosCallOuts.c b/src/mainboard/amd/thatcher/BiosCallOuts.c index f23161d..cc56a9a 100644 --- a/src/mainboard/amd/thatcher/BiosCallOuts.c +++ b/src/mainboard/amd/thatcher/BiosCallOuts.c @@ -17,7 +17,6 @@ #include <northbridge/amd/agesa/BiosCallOuts.h> #include <northbridge/amd/agesa/state_machine.h> #include <FchPlatform.h> -#include <stdlib.h> #include "imc.h" diff --git a/src/mainboard/amd/thatcher/buildOpts.c b/src/mainboard/amd/thatcher/buildOpts.c index 96847a7..cc1069d 100644 --- a/src/mainboard/amd/thatcher/buildOpts.c +++ b/src/mainboard/amd/thatcher/buildOpts.c @@ -25,7 +25,6 @@ * */ -#include <stdlib.h> #include <AGESA.h> /* Select the CPU family. */ diff --git a/src/mainboard/amd/tilapia_fam10/get_bus_conf.c b/src/mainboard/amd/tilapia_fam10/get_bus_conf.c index 37a3774..24e6f02 100644 --- a/src/mainboard/amd/tilapia_fam10/get_bus_conf.c +++ b/src/mainboard/amd/tilapia_fam10/get_bus_conf.c @@ -15,9 +15,7 @@ #include <device/pci.h> #include <stdint.h> -#include <stdlib.h> #include <cpu/amd/multicore.h> - #include <cpu/amd/amdfam10_sysconf.h> /* Global variables for MB layouts and these will be shared by irqtable mptable diff --git a/src/mainboard/amd/torpedo/BiosCallOuts.c b/src/mainboard/amd/torpedo/BiosCallOuts.c index e7b0e29..5002354 100644 --- a/src/mainboard/amd/torpedo/BiosCallOuts.c +++ b/src/mainboard/amd/torpedo/BiosCallOuts.c @@ -17,7 +17,6 @@ #include <amdlib.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include "Hudson-2.h" -#include <stdlib.h> #include <southbridge/amd/cimx/sb900/gpio_oem.h> static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr); diff --git a/src/mainboard/amd/torpedo/buildOpts.c b/src/mainboard/amd/torpedo/buildOpts.c index fbeee9a..89b3810 100644 --- a/src/mainboard/amd/torpedo/buildOpts.c +++ b/src/mainboard/amd/torpedo/buildOpts.c @@ -25,7 +25,6 @@ * */ -#include <stdlib.h> #include <AGESA.h> diff --git a/src/mainboard/amd/union_station/BiosCallOuts.c b/src/mainboard/amd/union_station/BiosCallOuts.c index ecb7e1c..9cfb646 100644 --- a/src/mainboard/amd/union_station/BiosCallOuts.c +++ b/src/mainboard/amd/union_station/BiosCallOuts.c @@ -18,7 +18,6 @@ #include <northbridge/amd/agesa/BiosCallOuts.h> #include <SB800.h> #include <southbridge/amd/cimx/sb800/gpio_oem.h> -#include <stdlib.h> static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr); static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr); diff --git a/src/mainboard/amd/union_station/buildOpts.c b/src/mainboard/amd/union_station/buildOpts.c index 244229d..470d977 100644 --- a/src/mainboard/amd/union_station/buildOpts.c +++ b/src/mainboard/amd/union_station/buildOpts.c @@ -25,9 +25,6 @@ * */ -#include <stdlib.h> - - /* Select the CPU family. */ #define INSTALL_FAMILY_10_SUPPORT FALSE #define INSTALL_FAMILY_12_SUPPORT FALSE diff --git a/src/mainboard/asrock/e350m1/BiosCallOuts.c b/src/mainboard/asrock/e350m1/BiosCallOuts.c index 491027a..5d7211c 100644 --- a/src/mainboard/asrock/e350m1/BiosCallOuts.c +++ b/src/mainboard/asrock/e350m1/BiosCallOuts.c @@ -17,7 +17,6 @@ #include <amdlib.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include <SB800.h> -#include <stdlib.h> static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr); diff --git a/src/mainboard/asrock/e350m1/buildOpts.c b/src/mainboard/asrock/e350m1/buildOpts.c index 14621e0..9c6b3bd 100644 --- a/src/mainboard/asrock/e350m1/buildOpts.c +++ b/src/mainboard/asrock/e350m1/buildOpts.c @@ -25,10 +25,8 @@ * */ -#include <stdlib.h> #include <AGESA.h> - /* Select the CPU family. */ #define INSTALL_FAMILY_10_SUPPORT FALSE #define INSTALL_FAMILY_12_SUPPORT FALSE diff --git a/src/mainboard/asrock/imb-a180/BiosCallOuts.c b/src/mainboard/asrock/imb-a180/BiosCallOuts.c index e05d5c0..983f9a8 100644 --- a/src/mainboard/asrock/imb-a180/BiosCallOuts.c +++ b/src/mainboard/asrock/imb-a180/BiosCallOuts.c @@ -18,7 +18,6 @@ #include <northbridge/amd/agesa/BiosCallOuts.h> #include <northbridge/amd/agesa/state_machine.h> #include <FchPlatform.h> -#include <stdlib.h> const BIOS_CALLOUT_STRUCT BiosCallouts[] = { diff --git a/src/mainboard/asrock/imb-a180/buildOpts.c b/src/mainboard/asrock/imb-a180/buildOpts.c index d9d62e2..caa5e3b 100644 --- a/src/mainboard/asrock/imb-a180/buildOpts.c +++ b/src/mainboard/asrock/imb-a180/buildOpts.c @@ -25,7 +25,6 @@ * */ -#include <stdlib.h> #include <AGESA.h> #define INSTALL_FT3_SOCKET_SUPPORT TRUE diff --git a/src/mainboard/asus/am1i-a/BiosCallOuts.c b/src/mainboard/asus/am1i-a/BiosCallOuts.c index ce54741..5e54ac9 100644 --- a/src/mainboard/asus/am1i-a/BiosCallOuts.c +++ b/src/mainboard/asus/am1i-a/BiosCallOuts.c @@ -21,7 +21,6 @@ #include <northbridge/amd/agesa/BiosCallOuts.h> #include <northbridge/amd/agesa/state_machine.h> #include <FchPlatform.h> -#include <stdlib.h> #include <pc80/mc146818rtc.h> #include <types.h> diff --git a/src/mainboard/asus/am1i-a/buildOpts.c b/src/mainboard/asus/am1i-a/buildOpts.c index 30c0699..74216f0 100644 --- a/src/mainboard/asus/am1i-a/buildOpts.c +++ b/src/mainboard/asus/am1i-a/buildOpts.c @@ -25,7 +25,6 @@ * */ -#include <stdlib.h> #include <AGESA.h> #define INSTALL_FT3_SOCKET_SUPPORT TRUE diff --git a/src/mainboard/asus/f2a85-m/BiosCallOuts.c b/src/mainboard/asus/f2a85-m/BiosCallOuts.c index 9e60ca7..15ce47e 100644 --- a/src/mainboard/asus/f2a85-m/BiosCallOuts.c +++ b/src/mainboard/asus/f2a85-m/BiosCallOuts.c @@ -18,7 +18,6 @@ #include <northbridge/amd/agesa/state_machine.h> #include <vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h> -#include <stdlib.h> const BIOS_CALLOUT_STRUCT BiosCallouts[] = { diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c index dc20dc7..8a1391d 100644 --- a/src/mainboard/asus/f2a85-m/buildOpts.c +++ b/src/mainboard/asus/f2a85-m/buildOpts.c @@ -25,7 +25,6 @@ * */ -#include <stdlib.h> #include <vendorcode/amd/agesa/f15tn/AGESA.h> diff --git a/src/mainboard/asus/kcma-d8/get_bus_conf.c b/src/mainboard/asus/kcma-d8/get_bus_conf.c index cc64dea..8fd10a1 100644 --- a/src/mainboard/asus/kcma-d8/get_bus_conf.c +++ b/src/mainboard/asus/kcma-d8/get_bus_conf.c @@ -16,7 +16,6 @@ #include <device/pci.h> #include <stdint.h> -#include <stdlib.h> #include <cpu/amd/multicore.h> #include <cpu/amd/amdfam10_sysconf.h> diff --git a/src/mainboard/asus/kfsn4-dre/get_bus_conf.c b/src/mainboard/asus/kfsn4-dre/get_bus_conf.c index dd7ebc9..ea32741 100644 --- a/src/mainboard/asus/kfsn4-dre/get_bus_conf.c +++ b/src/mainboard/asus/kfsn4-dre/get_bus_conf.c @@ -22,7 +22,6 @@ #include <device/pci.h> #include <device/pci_ops.h> #include <stdint.h> -#include <stdlib.h> #include <cpu/amd/multicore.h> #include <cpu/amd/amdfam10_sysconf.h> diff --git a/src/mainboard/asus/kgpe-d16/get_bus_conf.c b/src/mainboard/asus/kgpe-d16/get_bus_conf.c index 81d0fc1..e1e07df 100644 --- a/src/mainboard/asus/kgpe-d16/get_bus_conf.c +++ b/src/mainboard/asus/kgpe-d16/get_bus_conf.c @@ -16,7 +16,6 @@ #include <device/pci.h> #include <stdint.h> -#include <stdlib.h> #include <cpu/amd/multicore.h> #include <cpu/amd/amdfam10_sysconf.h> diff --git a/src/mainboard/asus/m4a78-em/get_bus_conf.c b/src/mainboard/asus/m4a78-em/get_bus_conf.c index ee2a6ca..77d55a8 100644 --- a/src/mainboard/asus/m4a78-em/get_bus_conf.c +++ b/src/mainboard/asus/m4a78-em/get_bus_conf.c @@ -15,9 +15,7 @@ #include <device/pci.h> #include <stdint.h> -#include <stdlib.h> #include <cpu/amd/multicore.h> - #include <cpu/amd/amdfam10_sysconf.h> /* Global variables for MB layouts and these will be shared by irqtable mptable diff --git a/src/mainboard/asus/m4a785-m/get_bus_conf.c b/src/mainboard/asus/m4a785-m/get_bus_conf.c index ee2a6ca..77d55a8 100644 --- a/src/mainboard/asus/m4a785-m/get_bus_conf.c +++ b/src/mainboard/asus/m4a785-m/get_bus_conf.c @@ -15,9 +15,7 @@ #include <device/pci.h> #include <stdint.h> -#include <stdlib.h> #include <cpu/amd/multicore.h> - #include <cpu/amd/amdfam10_sysconf.h> /* Global variables for MB layouts and these will be shared by irqtable mptable diff --git a/src/mainboard/asus/m5a88-v/get_bus_conf.c b/src/mainboard/asus/m5a88-v/get_bus_conf.c index 6b5ae68..7aca540 100644 --- a/src/mainboard/asus/m5a88-v/get_bus_conf.c +++ b/src/mainboard/asus/m5a88-v/get_bus_conf.c @@ -15,7 +15,6 @@ #include <device/pci.h> #include <stdint.h> -#include <stdlib.h> #include <cpu/amd/multicore.h> #include <cpu/amd/amdfam10_sysconf.h> diff --git a/src/mainboard/avalue/eax-785e/get_bus_conf.c b/src/mainboard/avalue/eax-785e/get_bus_conf.c index 6b5ae68..7aca540 100644 --- a/src/mainboard/avalue/eax-785e/get_bus_conf.c +++ b/src/mainboard/avalue/eax-785e/get_bus_conf.c @@ -15,7 +15,6 @@ #include <device/pci.h> #include <stdint.h> -#include <stdlib.h> #include <cpu/amd/multicore.h> #include <cpu/amd/amdfam10_sysconf.h> diff --git a/src/mainboard/bap/ode_e20XX/BiosCallOuts.c b/src/mainboard/bap/ode_e20XX/BiosCallOuts.c index 4f5ab88..9883ae6 100644 --- a/src/mainboard/bap/ode_e20XX/BiosCallOuts.c +++ b/src/mainboard/bap/ode_e20XX/BiosCallOuts.c @@ -18,7 +18,6 @@ #include <northbridge/amd/agesa/BiosCallOuts.h> #include <northbridge/amd/agesa/state_machine.h> #include <FchPlatform.h> -#include <stdlib.h> #include <spd_bin.h> #include "imc.h" diff --git a/src/mainboard/bap/ode_e20XX/buildOpts.c b/src/mainboard/bap/ode_e20XX/buildOpts.c index 6c405cc..daf13b6 100644 --- a/src/mainboard/bap/ode_e20XX/buildOpts.c +++ b/src/mainboard/bap/ode_e20XX/buildOpts.c @@ -25,7 +25,6 @@ * */ -#include <stdlib.h> #include <AGESA.h> #define INSTALL_FT3_SOCKET_SUPPORT TRUE diff --git a/src/mainboard/bap/ode_e21XX/BiosCallOuts.c b/src/mainboard/bap/ode_e21XX/BiosCallOuts.c index 6458b97..2e38028 100644 --- a/src/mainboard/bap/ode_e21XX/BiosCallOuts.c +++ b/src/mainboard/bap/ode_e21XX/BiosCallOuts.c @@ -17,7 +17,6 @@ #include <console/console.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include <FchPlatform.h> -#include <stdlib.h> #include <spd_bin.h> #include "imc.h" diff --git a/src/mainboard/biostar/a68n_5200/BiosCallOuts.c b/src/mainboard/biostar/a68n_5200/BiosCallOuts.c index 8f55fb6..cc5081b 100644 --- a/src/mainboard/biostar/a68n_5200/BiosCallOuts.c +++ b/src/mainboard/biostar/a68n_5200/BiosCallOuts.c @@ -17,7 +17,6 @@ #include <northbridge/amd/agesa/BiosCallOuts.h> #include <northbridge/amd/agesa/state_machine.h> #include <FchPlatform.h> -#include <stdlib.h> #include "imc.h" diff --git a/src/mainboard/biostar/a68n_5200/buildOpts.c b/src/mainboard/biostar/a68n_5200/buildOpts.c index 65b86b8..bb8527d 100644 --- a/src/mainboard/biostar/a68n_5200/buildOpts.c +++ b/src/mainboard/biostar/a68n_5200/buildOpts.c @@ -25,7 +25,6 @@ * */ -#include <stdlib.h> #include <AGESA.h> #define INSTALL_FT3_SOCKET_SUPPORT TRUE diff --git a/src/mainboard/biostar/am1ml/BiosCallOuts.c b/src/mainboard/biostar/am1ml/BiosCallOuts.c index 17c25ae..6181226 100644 --- a/src/mainboard/biostar/am1ml/BiosCallOuts.c +++ b/src/mainboard/biostar/am1ml/BiosCallOuts.c @@ -20,7 +20,6 @@ #include <northbridge/amd/agesa/BiosCallOuts.h> #include <northbridge/amd/agesa/state_machine.h> #include <FchPlatform.h> -#include <stdlib.h> const BIOS_CALLOUT_STRUCT BiosCallouts[] = { diff --git a/src/mainboard/biostar/am1ml/buildOpts.c b/src/mainboard/biostar/am1ml/buildOpts.c index 30c0699..74216f0 100644 --- a/src/mainboard/biostar/am1ml/buildOpts.c +++ b/src/mainboard/biostar/am1ml/buildOpts.c @@ -25,7 +25,6 @@ * */ -#include <stdlib.h> #include <AGESA.h> #define INSTALL_FT3_SOCKET_SUPPORT TRUE diff --git a/src/mainboard/cavium/cn8100_sff_evb/romstage.c b/src/mainboard/cavium/cn8100_sff_evb/romstage.c index b60b9cd..81a4100 100644 --- a/src/mainboard/cavium/cn8100_sff_evb/romstage.c +++ b/src/mainboard/cavium/cn8100_sff_evb/romstage.c @@ -18,7 +18,6 @@ #include <soc/sdram.h> #include <soc/timer.h> #include <soc/mmu.h> -#include <stdlib.h> #include <libbdk-hal/bdk-config.h> extern const struct bdk_devicetree_key_value devtree[]; diff --git a/src/mainboard/elmex/pcm205400/BiosCallOuts.c b/src/mainboard/elmex/pcm205400/BiosCallOuts.c index 6e2eaed..ee0b4f2 100644 --- a/src/mainboard/elmex/pcm205400/BiosCallOuts.c +++ b/src/mainboard/elmex/pcm205400/BiosCallOuts.c @@ -17,7 +17,6 @@ #include <amdlib.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include <SB800.h> -#include <stdlib.h> static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr); static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr); diff --git a/src/mainboard/elmex/pcm205400/buildOpts.c b/src/mainboard/elmex/pcm205400/buildOpts.c index 863a552..40c4fe1 100644 --- a/src/mainboard/elmex/pcm205400/buildOpts.c +++ b/src/mainboard/elmex/pcm205400/buildOpts.c @@ -25,9 +25,6 @@ * */ -#include <stdlib.h> - - /* Select the cpu family. */ #define INSTALL_FAMILY_10_SUPPORT FALSE #define INSTALL_FAMILY_12_SUPPORT FALSE diff --git a/src/mainboard/gigabyte/ma785gm/get_bus_conf.c b/src/mainboard/gigabyte/ma785gm/get_bus_conf.c index ee2a6ca..77d55a8 100644 --- a/src/mainboard/gigabyte/ma785gm/get_bus_conf.c +++ b/src/mainboard/gigabyte/ma785gm/get_bus_conf.c @@ -15,9 +15,7 @@ #include <device/pci.h> #include <stdint.h> -#include <stdlib.h> #include <cpu/amd/multicore.h> - #include <cpu/amd/amdfam10_sysconf.h> /* Global variables for MB layouts and these will be shared by irqtable mptable diff --git a/src/mainboard/gigabyte/ma785gmt/get_bus_conf.c b/src/mainboard/gigabyte/ma785gmt/get_bus_conf.c index 5c53476..16fdca1 100644 --- a/src/mainboard/gigabyte/ma785gmt/get_bus_conf.c +++ b/src/mainboard/gigabyte/ma785gmt/get_bus_conf.c @@ -15,7 +15,6 @@ #include <device/pci.h> #include <stdint.h> -#include <stdlib.h> #include <cpu/amd/multicore.h> #include <cpu/amd/amdfam10_sysconf.h> diff --git a/src/mainboard/gigabyte/ma78gm/get_bus_conf.c b/src/mainboard/gigabyte/ma78gm/get_bus_conf.c index ee2a6ca..77d55a8 100644 --- a/src/mainboard/gigabyte/ma78gm/get_bus_conf.c +++ b/src/mainboard/gigabyte/ma78gm/get_bus_conf.c @@ -15,9 +15,7 @@ #include <device/pci.h> #include <stdint.h> -#include <stdlib.h> #include <cpu/amd/multicore.h> - #include <cpu/amd/amdfam10_sysconf.h> /* Global variables for MB layouts and these will be shared by irqtable mptable diff --git a/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c b/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c index 5fc1718..233c40f 100644 --- a/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c +++ b/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c @@ -16,7 +16,6 @@ #include <AGESA.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include <SB800.h> -#include <stdlib.h> static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr); diff --git a/src/mainboard/gizmosphere/gizmo/buildOpts.c b/src/mainboard/gizmosphere/gizmo/buildOpts.c index b934808..5a17cfa 100644 --- a/src/mainboard/gizmosphere/gizmo/buildOpts.c +++ b/src/mainboard/gizmosphere/gizmo/buildOpts.c @@ -26,10 +26,6 @@ * */ -#include <stdlib.h> - - - /* Select the CPU family. */ #define INSTALL_FAMILY_10_SUPPORT FALSE #define INSTALL_FAMILY_12_SUPPORT FALSE diff --git a/src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c b/src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c index 99162d8..c9e27d8 100644 --- a/src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c +++ b/src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c @@ -17,7 +17,6 @@ #include <northbridge/amd/agesa/BiosCallOuts.h> #include <northbridge/amd/agesa/state_machine.h> #include <FchPlatform.h> -#include <stdlib.h> #include "imc.h" diff --git a/src/mainboard/gizmosphere/gizmo2/buildOpts.c b/src/mainboard/gizmosphere/gizmo2/buildOpts.c index 6c405cc..daf13b6 100644 --- a/src/mainboard/gizmosphere/gizmo2/buildOpts.c +++ b/src/mainboard/gizmosphere/gizmo2/buildOpts.c @@ -25,7 +25,6 @@ * */ -#include <stdlib.h> #include <AGESA.h> #define INSTALL_FT3_SOCKET_SUPPORT TRUE diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c index 70a8c19..ac6cdb5 100644 --- a/src/mainboard/google/beltino/romstage.c +++ b/src/mainboard/google/beltino/romstage.c @@ -15,7 +15,6 @@ */ #include <stdint.h> -#include <stdlib.h> #include <cpu/intel/romstage.h> #include <cpu/intel/haswell/haswell.h> #include <northbridge/intel/haswell/haswell.h> diff --git a/src/mainboard/google/beltino/variants/mccloud/hda_verb.c b/src/mainboard/google/beltino/variants/mccloud/hda_verb.c index 4d65f36..233a8ee 100644 --- a/src/mainboard/google/beltino/variants/mccloud/hda_verb.c +++ b/src/mainboard/google/beltino/variants/mccloud/hda_verb.c @@ -16,8 +16,6 @@ #ifndef HDA_VERB_H #define HDA_VERB_H -#include <stdlib.h> - #include <device/azalia_device.h> const u32 cim_verb_data[] = { diff --git a/src/mainboard/google/beltino/variants/monroe/hda_verb.c b/src/mainboard/google/beltino/variants/monroe/hda_verb.c index 8482ec3..8281fb8 100644 --- a/src/mainboard/google/beltino/variants/monroe/hda_verb.c +++ b/src/mainboard/google/beltino/variants/monroe/hda_verb.c @@ -16,8 +16,6 @@ #ifndef HDA_VERB_H #define HDA_VERB_H -#include <stdlib.h> - #include <device/azalia_device.h> const u32 cim_verb_data[] = { diff --git a/src/mainboard/google/beltino/variants/panther/hda_verb.c b/src/mainboard/google/beltino/variants/panther/hda_verb.c index 4d65f36..233a8ee 100644 --- a/src/mainboard/google/beltino/variants/panther/hda_verb.c +++ b/src/mainboard/google/beltino/variants/panther/hda_verb.c @@ -16,8 +16,6 @@ #ifndef HDA_VERB_H #define HDA_VERB_H -#include <stdlib.h> - #include <device/azalia_device.h> const u32 cim_verb_data[] = { diff --git a/src/mainboard/google/beltino/variants/tricky/hda_verb.c b/src/mainboard/google/beltino/variants/tricky/hda_verb.c index 4d65f36..233a8ee 100644 --- a/src/mainboard/google/beltino/variants/tricky/hda_verb.c +++ b/src/mainboard/google/beltino/variants/tricky/hda_verb.c @@ -16,8 +16,6 @@ #ifndef HDA_VERB_H #define HDA_VERB_H -#include <stdlib.h> - #include <device/azalia_device.h> const u32 cim_verb_data[] = { diff --git a/src/mainboard/google/beltino/variants/zako/hda_verb.c b/src/mainboard/google/beltino/variants/zako/hda_verb.c index 4d65f36..233a8ee 100644 --- a/src/mainboard/google/beltino/variants/zako/hda_verb.c +++ b/src/mainboard/google/beltino/variants/zako/hda_verb.c @@ -16,8 +16,6 @@ #ifndef HDA_VERB_H #define HDA_VERB_H -#include <stdlib.h> - #include <device/azalia_device.h> const u32 cim_verb_data[] = { diff --git a/src/mainboard/google/cyan/variants/banon/gpio.c b/src/mainboard/google/cyan/variants/banon/gpio.c index 6983d91..2a3e8fc 100644 --- a/src/mainboard/google/cyan/variants/banon/gpio.c +++ b/src/mainboard/google/cyan/variants/banon/gpio.c @@ -16,7 +16,6 @@ #include <mainboard/google/cyan/irqroute.h> #include <soc/gpio.h> -#include <stdlib.h> /* South East Community */ static const struct soc_gpio_map gpse_gpio_map[] = { diff --git a/src/mainboard/google/cyan/variants/celes/gpio.c b/src/mainboard/google/cyan/variants/celes/gpio.c index c416053..6f53f2e 100644 --- a/src/mainboard/google/cyan/variants/celes/gpio.c +++ b/src/mainboard/google/cyan/variants/celes/gpio.c @@ -16,7 +16,6 @@ #include <mainboard/google/cyan/irqroute.h> #include <soc/gpio.h> -#include <stdlib.h> /* South East Community */ static const struct soc_gpio_map gpse_gpio_map[] = { diff --git a/src/mainboard/google/cyan/variants/cyan/gpio.c b/src/mainboard/google/cyan/variants/cyan/gpio.c index c26e7b6..05ba93e 100644 --- a/src/mainboard/google/cyan/variants/cyan/gpio.c +++ b/src/mainboard/google/cyan/variants/cyan/gpio.c @@ -16,7 +16,6 @@ #include <mainboard/google/cyan/irqroute.h> #include <soc/gpio.h> -#include <stdlib.h> /* South East Community */ static const struct soc_gpio_map gpse_gpio_map[] = { diff --git a/src/mainboard/google/cyan/variants/edgar/gpio.c b/src/mainboard/google/cyan/variants/edgar/gpio.c index 2010ac5..59486af 100644 --- a/src/mainboard/google/cyan/variants/edgar/gpio.c +++ b/src/mainboard/google/cyan/variants/edgar/gpio.c @@ -16,7 +16,6 @@ #include <mainboard/google/cyan/irqroute.h> #include <soc/gpio.h> -#include <stdlib.h> /* South East Community */ static const struct soc_gpio_map gpse_gpio_map[] = { diff --git a/src/mainboard/google/cyan/variants/kefka/gpio.c b/src/mainboard/google/cyan/variants/kefka/gpio.c index 0ef2842..1036cc6 100644 --- a/src/mainboard/google/cyan/variants/kefka/gpio.c +++ b/src/mainboard/google/cyan/variants/kefka/gpio.c @@ -16,8 +16,6 @@ #include <mainboard/google/cyan/irqroute.h> #include <soc/gpio.h> -#include <stdlib.h> - /* South East Community */ static const struct soc_gpio_map gpse_gpio_map[] = { diff --git a/src/mainboard/google/cyan/variants/reks/gpio.c b/src/mainboard/google/cyan/variants/reks/gpio.c index e0d82cf..955dc51 100644 --- a/src/mainboard/google/cyan/variants/reks/gpio.c +++ b/src/mainboard/google/cyan/variants/reks/gpio.c @@ -16,7 +16,6 @@ #include <mainboard/google/cyan/irqroute.h> #include <soc/gpio.h> -#include <stdlib.h> /* South East Community */ static const struct soc_gpio_map gpse_gpio_map[] = { diff --git a/src/mainboard/google/cyan/variants/relm/gpio.c b/src/mainboard/google/cyan/variants/relm/gpio.c index 9cb80e6..e9014ac 100644 --- a/src/mainboard/google/cyan/variants/relm/gpio.c +++ b/src/mainboard/google/cyan/variants/relm/gpio.c @@ -16,8 +16,6 @@ #include <mainboard/google/cyan/irqroute.h> #include <soc/gpio.h> -#include <stdlib.h> - /* South East Community */ static const struct soc_gpio_map gpse_gpio_map[] = { diff --git a/src/mainboard/google/cyan/variants/setzer/gpio.c b/src/mainboard/google/cyan/variants/setzer/gpio.c index 83f742e..517d069 100644 --- a/src/mainboard/google/cyan/variants/setzer/gpio.c +++ b/src/mainboard/google/cyan/variants/setzer/gpio.c @@ -16,8 +16,6 @@ #include <mainboard/google/cyan/irqroute.h> #include <soc/gpio.h> -#include <stdlib.h> - /* South East Community */ static const struct soc_gpio_map gpse_gpio_map[] = { diff --git a/src/mainboard/google/cyan/variants/terra/gpio.c b/src/mainboard/google/cyan/variants/terra/gpio.c index b4feebf..dc10cef 100644 --- a/src/mainboard/google/cyan/variants/terra/gpio.c +++ b/src/mainboard/google/cyan/variants/terra/gpio.c @@ -16,7 +16,6 @@ #include <mainboard/google/cyan/irqroute.h> #include <soc/gpio.h> -#include <stdlib.h> /* South East Community */ static const struct soc_gpio_map gpse_gpio_map[] = { diff --git a/src/mainboard/google/cyan/variants/ultima/gpio.c b/src/mainboard/google/cyan/variants/ultima/gpio.c index fe8c934..3cae313 100644 --- a/src/mainboard/google/cyan/variants/ultima/gpio.c +++ b/src/mainboard/google/cyan/variants/ultima/gpio.c @@ -16,7 +16,6 @@ #include <mainboard/google/cyan/irqroute.h> #include <soc/gpio.h> -#include <stdlib.h> /* South East Community */ static const struct soc_gpio_map gpse_gpio_map[] = { diff --git a/src/mainboard/google/cyan/variants/wizpig/gpio.c b/src/mainboard/google/cyan/variants/wizpig/gpio.c index affe893..ecd74ef 100644 --- a/src/mainboard/google/cyan/variants/wizpig/gpio.c +++ b/src/mainboard/google/cyan/variants/wizpig/gpio.c @@ -16,7 +16,6 @@ #include <mainboard/google/cyan/irqroute.h> #include <soc/gpio.h> -#include <stdlib.h> /* South East Community */ static const struct soc_gpio_map gpse_gpio_map[] = { diff --git a/src/mainboard/google/daisy/memory.c b/src/mainboard/google/daisy/memory.c index 009604b..c5b752c 100644 --- a/src/mainboard/google/daisy/memory.c +++ b/src/mainboard/google/daisy/memory.c @@ -20,7 +20,6 @@ #include <soc/dmc.h> #include <soc/clk.h> #include <stddef.h> -#include <stdlib.h> const struct mem_timings mem_timings[] = { { diff --git a/src/mainboard/google/foster/pmic.c b/src/mainboard/google/foster/pmic.c index 13e2a47..a7bceda 100644 --- a/src/mainboard/google/foster/pmic.c +++ b/src/mainboard/google/foster/pmic.c @@ -20,7 +20,6 @@ #include <device/i2c_simple.h> #include <reset.h> #include <stdint.h> -#include <stdlib.h> #include "pmic.h" diff --git a/src/mainboard/google/gale/boardid.c b/src/mainboard/google/gale/boardid.c index 96fc936..082cc26 100644 --- a/src/mainboard/google/gale/boardid.c +++ b/src/mainboard/google/gale/boardid.c @@ -16,7 +16,6 @@ #include <boardid.h> #include <gpio.h> #include <console/console.h> -#include <stdlib.h> /* * Gale boards dedicate to the board ID three GPIOs in ternary mode: 64, 65 diff --git a/src/mainboard/google/glados/mainboard.c b/src/mainboard/google/glados/mainboard.c index 8b04a65..19dd316 100644 --- a/src/mainboard/google/glados/mainboard.c +++ b/src/mainboard/google/glados/mainboard.c @@ -20,7 +20,6 @@ #include <console/console.h> #include <device/device.h> #include <gpio.h> -#include <stdlib.h> #include <soc/nhlt.h> #include <variant/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/google/gru/boardid.c b/src/mainboard/google/gru/boardid.c index 4630a91..efba922 100644 --- a/src/mainboard/google/gru/boardid.c +++ b/src/mainboard/google/gru/boardid.c @@ -16,7 +16,6 @@ #include <boardid.h> #include <console/console.h> #include <gpio.h> -#include <stdlib.h> #include <soc/saradc.h> static const int id_readings[] = { diff --git a/src/mainboard/google/link/i915.c b/src/mainboard/google/link/i915.c index 12d424c..eca5bf5 100644 --- a/src/mainboard/google/link/i915.c +++ b/src/mainboard/google/link/i915.c @@ -15,7 +15,6 @@ #include <types.h> #include <string.h> -#include <stdlib.h> #include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> diff --git a/src/mainboard/google/nyan/pmic.c b/src/mainboard/google/nyan/pmic.c index d226459..cfe0a8c 100644 --- a/src/mainboard/google/nyan/pmic.c +++ b/src/mainboard/google/nyan/pmic.c @@ -19,7 +19,6 @@ #include <delay.h> #include <device/i2c_simple.h> #include <stdint.h> -#include <stdlib.h> #include <reset.h> #include "pmic.h" diff --git a/src/mainboard/google/nyan_big/boardid.c b/src/mainboard/google/nyan_big/boardid.c index 2a2911c..49a9938 100644 --- a/src/mainboard/google/nyan_big/boardid.c +++ b/src/mainboard/google/nyan_big/boardid.c @@ -16,7 +16,6 @@ #include <boardid.h> #include <console/console.h> #include <gpio.h> -#include <stdlib.h> uint32_t board_id(void) { diff --git a/src/mainboard/google/nyan_big/pmic.c b/src/mainboard/google/nyan_big/pmic.c index 948d867..9e44f54 100644 --- a/src/mainboard/google/nyan_big/pmic.c +++ b/src/mainboard/google/nyan_big/pmic.c @@ -19,7 +19,6 @@ #include <delay.h> #include <device/i2c_simple.h> #include <stdint.h> -#include <stdlib.h> #include <reset.h> #include "pmic.h" diff --git a/src/mainboard/google/nyan_blaze/boardid.c b/src/mainboard/google/nyan_blaze/boardid.c index 2a2911c..49a9938 100644 --- a/src/mainboard/google/nyan_blaze/boardid.c +++ b/src/mainboard/google/nyan_blaze/boardid.c @@ -16,7 +16,6 @@ #include <boardid.h> #include <console/console.h> #include <gpio.h> -#include <stdlib.h> uint32_t board_id(void) { diff --git a/src/mainboard/google/nyan_blaze/pmic.c b/src/mainboard/google/nyan_blaze/pmic.c index 948d867..9e44f54 100644 --- a/src/mainboard/google/nyan_blaze/pmic.c +++ b/src/mainboard/google/nyan_blaze/pmic.c @@ -19,7 +19,6 @@ #include <delay.h> #include <device/i2c_simple.h> #include <stdint.h> -#include <stdlib.h> #include <reset.h> #include "pmic.h" diff --git a/src/mainboard/google/oak/boardid.c b/src/mainboard/google/oak/boardid.c index 91e2df3..ada2de5 100644 --- a/src/mainboard/google/oak/boardid.c +++ b/src/mainboard/google/oak/boardid.c @@ -16,7 +16,6 @@ #include <boardid.h> #include <gpio.h> #include <console/console.h> -#include <stdlib.h> #include "gpio.h" static int board_id_value = -1; diff --git a/src/mainboard/google/oak/sdram_configs.c b/src/mainboard/google/oak/sdram_configs.c index 65b12ce..3419108 100644 --- a/src/mainboard/google/oak/sdram_configs.c +++ b/src/mainboard/google/oak/sdram_configs.c @@ -16,7 +16,6 @@ #include <boardid.h> #include <console/console.h> #include <soc/emi.h> -#include <stdlib.h> static const struct mt8173_sdram_params sdram_configs[] = { #include "sdram_inf/sdram-lpddr3-H9CCNNN8GTMLAR-2GB.inc" /* ram_code = 0000 */ diff --git a/src/mainboard/google/peach_pit/mainboard.c b/src/mainboard/google/peach_pit/mainboard.c index 0441e52..da958c08 100644 --- a/src/mainboard/google/peach_pit/mainboard.c +++ b/src/mainboard/google/peach_pit/mainboard.c @@ -33,7 +33,6 @@ #include <soc/dp.h> #include <soc/fimd.h> #include <soc/usb.h> -#include <stdlib.h> #include <string.h> #include <symbols.h> #include <vbe.h> diff --git a/src/mainboard/google/peach_pit/memory.c b/src/mainboard/google/peach_pit/memory.c index a5e3d9e..541e3b0 100644 --- a/src/mainboard/google/peach_pit/memory.c +++ b/src/mainboard/google/peach_pit/memory.c @@ -19,7 +19,6 @@ #include <soc/gpio.h> #include <soc/setup.h> #include <stddef.h> -#include <stdlib.h> const struct mem_timings mem_timings = { .mem_manuf = MEM_MANUF_SAMSUNG, diff --git a/src/mainboard/google/peach_pit/romstage.c b/src/mainboard/google/peach_pit/romstage.c index fdbe534..0c2cb3e 100644 --- a/src/mainboard/google/peach_pit/romstage.c +++ b/src/mainboard/google/peach_pit/romstage.c @@ -33,7 +33,6 @@ #include <soc/setup.h> #include <soc/trustzone.h> #include <soc/wakeup.h> -#include <stdlib.h> #include <timestamp.h> #include <types.h> diff --git a/src/mainboard/google/rambi/variants/banjo/gpio.c b/src/mainboard/google/rambi/variants/banjo/gpio.c index bfb2c9a..e22c8db 100644 --- a/src/mainboard/google/rambi/variants/banjo/gpio.c +++ b/src/mainboard/google/rambi/variants/banjo/gpio.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <soc/gpio.h> #include <mainboard/google/rambi/irqroute.h> diff --git a/src/mainboard/google/rambi/variants/candy/gpio.c b/src/mainboard/google/rambi/variants/candy/gpio.c index 3cbfbaf..61050e5 100644 --- a/src/mainboard/google/rambi/variants/candy/gpio.c +++ b/src/mainboard/google/rambi/variants/candy/gpio.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <soc/gpio.h> #include <mainboard/google/rambi/irqroute.h> diff --git a/src/mainboard/google/rambi/variants/clapper/gpio.c b/src/mainboard/google/rambi/variants/clapper/gpio.c index 385b406..17303c3 100644 --- a/src/mainboard/google/rambi/variants/clapper/gpio.c +++ b/src/mainboard/google/rambi/variants/clapper/gpio.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <soc/gpio.h> #include <mainboard/google/rambi/irqroute.h> diff --git a/src/mainboard/google/rambi/variants/enguarde/gpio.c b/src/mainboard/google/rambi/variants/enguarde/gpio.c index 2802aa6..784ed23 100644 --- a/src/mainboard/google/rambi/variants/enguarde/gpio.c +++ b/src/mainboard/google/rambi/variants/enguarde/gpio.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <soc/gpio.h> #include <mainboard/google/rambi/irqroute.h> diff --git a/src/mainboard/google/rambi/variants/glimmer/gpio.c b/src/mainboard/google/rambi/variants/glimmer/gpio.c index 8cfe90e..504d64a 100644 --- a/src/mainboard/google/rambi/variants/glimmer/gpio.c +++ b/src/mainboard/google/rambi/variants/glimmer/gpio.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <soc/gpio.h> #include <mainboard/google/rambi/irqroute.h> diff --git a/src/mainboard/google/rambi/variants/gnawty/gpio.c b/src/mainboard/google/rambi/variants/gnawty/gpio.c index e79dc5a..7e2361c 100644 --- a/src/mainboard/google/rambi/variants/gnawty/gpio.c +++ b/src/mainboard/google/rambi/variants/gnawty/gpio.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <soc/gpio.h> #include <mainboard/google/rambi/irqroute.h> diff --git a/src/mainboard/google/rambi/variants/heli/gpio.c b/src/mainboard/google/rambi/variants/heli/gpio.c index 2a61c55..bcb1430 100644 --- a/src/mainboard/google/rambi/variants/heli/gpio.c +++ b/src/mainboard/google/rambi/variants/heli/gpio.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <soc/gpio.h> #include <mainboard/google/rambi/irqroute.h> diff --git a/src/mainboard/google/rambi/variants/kip/gpio.c b/src/mainboard/google/rambi/variants/kip/gpio.c index 3d79d37..56942bd 100644 --- a/src/mainboard/google/rambi/variants/kip/gpio.c +++ b/src/mainboard/google/rambi/variants/kip/gpio.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <soc/gpio.h> #include <mainboard/google/rambi/irqroute.h> diff --git a/src/mainboard/google/rambi/variants/ninja/gpio.c b/src/mainboard/google/rambi/variants/ninja/gpio.c index 85d565e..2d8285c 100644 --- a/src/mainboard/google/rambi/variants/ninja/gpio.c +++ b/src/mainboard/google/rambi/variants/ninja/gpio.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <soc/gpio.h> #include <mainboard/google/rambi/irqroute.h> diff --git a/src/mainboard/google/rambi/variants/orco/gpio.c b/src/mainboard/google/rambi/variants/orco/gpio.c index f2bbe8a..afa50cf 100644 --- a/src/mainboard/google/rambi/variants/orco/gpio.c +++ b/src/mainboard/google/rambi/variants/orco/gpio.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <soc/gpio.h> #include <mainboard/google/rambi/irqroute.h> diff --git a/src/mainboard/google/rambi/variants/quawks/gpio.c b/src/mainboard/google/rambi/variants/quawks/gpio.c index 3d79d37..56942bd 100644 --- a/src/mainboard/google/rambi/variants/quawks/gpio.c +++ b/src/mainboard/google/rambi/variants/quawks/gpio.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <soc/gpio.h> #include <mainboard/google/rambi/irqroute.h> diff --git a/src/mainboard/google/rambi/variants/rambi/gpio.c b/src/mainboard/google/rambi/variants/rambi/gpio.c index 3d79d37..56942bd 100644 --- a/src/mainboard/google/rambi/variants/rambi/gpio.c +++ b/src/mainboard/google/rambi/variants/rambi/gpio.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <soc/gpio.h> #include <mainboard/google/rambi/irqroute.h> diff --git a/src/mainboard/google/rambi/variants/squawks/gpio.c b/src/mainboard/google/rambi/variants/squawks/gpio.c index 3d79d37..56942bd 100644 --- a/src/mainboard/google/rambi/variants/squawks/gpio.c +++ b/src/mainboard/google/rambi/variants/squawks/gpio.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <soc/gpio.h> #include <mainboard/google/rambi/irqroute.h> diff --git a/src/mainboard/google/rambi/variants/sumo/gpio.c b/src/mainboard/google/rambi/variants/sumo/gpio.c index 0856c29..c4cc40a 100644 --- a/src/mainboard/google/rambi/variants/sumo/gpio.c +++ b/src/mainboard/google/rambi/variants/sumo/gpio.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <soc/gpio.h> #include <mainboard/google/rambi/irqroute.h> diff --git a/src/mainboard/google/rambi/variants/swanky/gpio.c b/src/mainboard/google/rambi/variants/swanky/gpio.c index a713549..3b62880 100644 --- a/src/mainboard/google/rambi/variants/swanky/gpio.c +++ b/src/mainboard/google/rambi/variants/swanky/gpio.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <soc/gpio.h> #include <mainboard/google/rambi/irqroute.h> diff --git a/src/mainboard/google/rambi/variants/winky/gpio.c b/src/mainboard/google/rambi/variants/winky/gpio.c index dcdf6f5..9c3a338 100644 --- a/src/mainboard/google/rambi/variants/winky/gpio.c +++ b/src/mainboard/google/rambi/variants/winky/gpio.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <soc/gpio.h> #include <mainboard/google/rambi/irqroute.h> diff --git a/src/mainboard/google/slippy/variants/falco/romstage.c b/src/mainboard/google/slippy/variants/falco/romstage.c index 25f8d27..a1e8473 100644 --- a/src/mainboard/google/slippy/variants/falco/romstage.c +++ b/src/mainboard/google/slippy/variants/falco/romstage.c @@ -14,8 +14,8 @@ * GNU General Public License for more details. */ +#include <stddef.h> #include <stdint.h> -#include <stdlib.h> #include <string.h> #include <cbfs.h> #include <console/console.h> diff --git a/src/mainboard/google/smaug/boardid.c b/src/mainboard/google/smaug/boardid.c index 2512f83..74f6f11 100644 --- a/src/mainboard/google/smaug/boardid.c +++ b/src/mainboard/google/smaug/boardid.c @@ -15,7 +15,6 @@ #include <boardid.h> #include <soc/sdram.h> -#include <stdlib.h> #include "gpio.h" diff --git a/src/mainboard/google/smaug/pmic.c b/src/mainboard/google/smaug/pmic.c index 9add211..49a0702 100644 --- a/src/mainboard/google/smaug/pmic.c +++ b/src/mainboard/google/smaug/pmic.c @@ -20,7 +20,6 @@ #include <device/i2c_simple.h> #include <reset.h> #include <stdint.h> -#include <stdlib.h> #include "pmic.h" diff --git a/src/mainboard/google/storm/boardid.c b/src/mainboard/google/storm/boardid.c index 87f6d2a..d952155 100644 --- a/src/mainboard/google/storm/boardid.c +++ b/src/mainboard/google/storm/boardid.c @@ -16,7 +16,6 @@ #include <boardid.h> #include <gpio.h> #include <console/console.h> -#include <stdlib.h> /* * Storm boards dedicate to the board ID three GPIOs in tertiary mode: 29, 30 diff --git a/src/mainboard/google/veyron/boardid.c b/src/mainboard/google/veyron/boardid.c index c9c68cc..bf311cf 100644 --- a/src/mainboard/google/veyron/boardid.c +++ b/src/mainboard/google/veyron/boardid.c @@ -16,7 +16,6 @@ #include <boardid.h> #include <console/console.h> #include <gpio.h> -#include <stdlib.h> uint32_t board_id(void) { diff --git a/src/mainboard/google/veyron/romstage.c b/src/mainboard/google/veyron/romstage.c index 3870b63..eba96c4 100644 --- a/src/mainboard/google/veyron/romstage.c +++ b/src/mainboard/google/veyron/romstage.c @@ -27,7 +27,6 @@ #include <soc/grf.h> #include <soc/rk808.h> #include <soc/tsadc.h> -#include <stdlib.h> #include <symbols.h> #include <timestamp.h> #include <types.h> diff --git a/src/mainboard/google/veyron_mickey/boardid.c b/src/mainboard/google/veyron_mickey/boardid.c index 3833dbe..9c53e37 100644 --- a/src/mainboard/google/veyron_mickey/boardid.c +++ b/src/mainboard/google/veyron_mickey/boardid.c @@ -16,7 +16,6 @@ #include <boardid.h> #include <console/console.h> #include <gpio.h> -#include <stdlib.h> uint32_t board_id(void) { diff --git a/src/mainboard/google/veyron_mickey/romstage.c b/src/mainboard/google/veyron_mickey/romstage.c index c8a9842..d20bdb4 100644 --- a/src/mainboard/google/veyron_mickey/romstage.c +++ b/src/mainboard/google/veyron_mickey/romstage.c @@ -27,7 +27,6 @@ #include <soc/grf.h> #include <soc/rk808.h> #include <soc/tsadc.h> -#include <stdlib.h> #include <symbols.h> #include <timestamp.h> #include <types.h> diff --git a/src/mainboard/google/veyron_rialto/boardid.c b/src/mainboard/google/veyron_rialto/boardid.c index 3833dbe..9c53e37 100644 --- a/src/mainboard/google/veyron_rialto/boardid.c +++ b/src/mainboard/google/veyron_rialto/boardid.c @@ -16,7 +16,6 @@ #include <boardid.h> #include <console/console.h> #include <gpio.h> -#include <stdlib.h> uint32_t board_id(void) { diff --git a/src/mainboard/google/veyron_rialto/romstage.c b/src/mainboard/google/veyron_rialto/romstage.c index d9fc42b..ac651ef 100644 --- a/src/mainboard/google/veyron_rialto/romstage.c +++ b/src/mainboard/google/veyron_rialto/romstage.c @@ -27,7 +27,6 @@ #include <soc/grf.h> #include <soc/rk808.h> #include <soc/tsadc.h> -#include <stdlib.h> #include <symbols.h> #include <timestamp.h> #include <types.h> diff --git a/src/mainboard/hp/abm/BiosCallOuts.c b/src/mainboard/hp/abm/BiosCallOuts.c index 4728c59..df0cb34 100644 --- a/src/mainboard/hp/abm/BiosCallOuts.c +++ b/src/mainboard/hp/abm/BiosCallOuts.c @@ -18,7 +18,6 @@ #include <northbridge/amd/agesa/BiosCallOuts.h> #include <northbridge/amd/agesa/state_machine.h> #include <FchPlatform.h> -#include <stdlib.h> const BIOS_CALLOUT_STRUCT BiosCallouts[] = { diff --git a/src/mainboard/hp/abm/buildOpts.c b/src/mainboard/hp/abm/buildOpts.c index bc1b172..f965d0d 100644 --- a/src/mainboard/hp/abm/buildOpts.c +++ b/src/mainboard/hp/abm/buildOpts.c @@ -30,7 +30,6 @@ * @e \$Revision: 23714 $ @e \$Date: 2009-12-09 17:28:37 -0600 (Wed, 09 Dec 2009) $ */ -#include <stdlib.h> #include <AGESA.h> #define INSTALL_FT3_SOCKET_SUPPORT TRUE diff --git a/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c b/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c index e217aa7..c159c19 100644 --- a/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c +++ b/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c @@ -21,10 +21,8 @@ #include <string.h> #include <stdint.h> #include <cpu/amd/multicore.h> - #include <cpu/amd/amdfam10_sysconf.h> -#include <stdlib.h> #include "mb_sysconf.h" // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables diff --git a/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c b/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c index 2b1ac04..afa2fce 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c @@ -16,10 +16,8 @@ #include <AGESA.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include <northbridge/amd/agesa/state_machine.h> - #include <southbridge/amd/agesa/hudson/imc.h> #include <vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h> -#include <stdlib.h> const BIOS_CALLOUT_STRUCT BiosCallouts[] = { diff --git a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c index c6d62ed..e56d513 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c @@ -27,7 +27,6 @@ #include "mainboard.h" -#include <stdlib.h> #include <vendorcode/amd/agesa/f15tn/AGESA.h> diff --git a/src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c b/src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c index 237ef2a..89ac836 100644 --- a/src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c +++ b/src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c @@ -15,7 +15,6 @@ #include <device/pci.h> #include <stdint.h> -#include <stdlib.h> #include <cpu/amd/multicore.h> #include <cpu/amd/amdfam10_sysconf.h> diff --git a/src/mainboard/intel/kblrvp/mainboard.c b/src/mainboard/intel/kblrvp/mainboard.c index 78c7ae4..a21b1cf 100644 --- a/src/mainboard/intel/kblrvp/mainboard.c +++ b/src/mainboard/intel/kblrvp/mainboard.c @@ -18,12 +18,12 @@ #include <arch/acpi.h> #include <device/device.h> #include <gpio.h> -#include <stdlib.h> #include <soc/nhlt.h> #include <vendorcode/google/chromeos/chromeos.h> -#include "ec.h" #include <variant/gpio.h> +#include "ec.h" + static void mainboard_init(struct device *dev) { if (CONFIG(EC_GOOGLE_CHROMEEC)) diff --git a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c index 86999fb..d71e5d8 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c +++ b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c @@ -15,11 +15,9 @@ #include <AGESA.h> #include <northbridge/amd/agesa/BiosCallOuts.h> - #include <amdlib.h> #include <vendorcode/amd/cimx/sb800/SB800.h> #include <stdint.h> -#include <stdlib.h> static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr); static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr); diff --git a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c index 65986e2..1ad822a 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c +++ b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c @@ -25,8 +25,6 @@ * */ -#include <stdlib.h> - #include <vendorcode/amd/agesa/f14/AGESA.h> /* Include the files that instantiate the configuration definitions. */ @@ -41,7 +39,6 @@ #include <vendorcode/amd/agesa/f14/Proc/Mem/mm.h> #include <vendorcode/amd/agesa/f14/Proc/Mem/mn.h> - /* Select the CPU family. */ #define INSTALL_FAMILY_10_SUPPORT FALSE #define INSTALL_FAMILY_12_SUPPORT FALSE diff --git a/src/mainboard/jetway/pa78vm5/get_bus_conf.c b/src/mainboard/jetway/pa78vm5/get_bus_conf.c index ee2a6ca..77d55a8 100644 --- a/src/mainboard/jetway/pa78vm5/get_bus_conf.c +++ b/src/mainboard/jetway/pa78vm5/get_bus_conf.c @@ -15,9 +15,7 @@ #include <device/pci.h> #include <stdint.h> -#include <stdlib.h> #include <cpu/amd/multicore.h> - #include <cpu/amd/amdfam10_sysconf.h> /* Global variables for MB layouts and these will be shared by irqtable mptable diff --git a/src/mainboard/lenovo/g505s/BiosCallOuts.c b/src/mainboard/lenovo/g505s/BiosCallOuts.c index 2b1ac04..afa2fce 100644 --- a/src/mainboard/lenovo/g505s/BiosCallOuts.c +++ b/src/mainboard/lenovo/g505s/BiosCallOuts.c @@ -16,10 +16,8 @@ #include <AGESA.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include <northbridge/amd/agesa/state_machine.h> - #include <southbridge/amd/agesa/hudson/imc.h> #include <vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h> -#include <stdlib.h> const BIOS_CALLOUT_STRUCT BiosCallouts[] = { diff --git a/src/mainboard/lenovo/g505s/buildOpts.c b/src/mainboard/lenovo/g505s/buildOpts.c index c3e40ce..559e1a6 100644 --- a/src/mainboard/lenovo/g505s/buildOpts.c +++ b/src/mainboard/lenovo/g505s/buildOpts.c @@ -27,8 +27,6 @@ #include "mainboard.h" -#include <stdlib.h> - #include <vendorcode/amd/agesa/f15tn/AGESA.h> /* Include the files that instantiate the configuration definitions. */ @@ -43,7 +41,6 @@ #include <vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h> #include <vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h> - /* Select the CPU family. */ #define INSTALL_FAMILY_10_SUPPORT FALSE #define INSTALL_FAMILY_12_SUPPORT FALSE diff --git a/src/mainboard/lippert/frontrunner-af/BiosCallOuts.c b/src/mainboard/lippert/frontrunner-af/BiosCallOuts.c index 9ce9ec7..6d7f8cb 100644 --- a/src/mainboard/lippert/frontrunner-af/BiosCallOuts.c +++ b/src/mainboard/lippert/frontrunner-af/BiosCallOuts.c @@ -18,7 +18,6 @@ #include <northbridge/amd/agesa/BiosCallOuts.h> #include <SB800.h> #include <southbridge/amd/cimx/sb800/gpio_oem.h> -#include <stdlib.h> /* Should AGESA_GNB_PCIE_SLOT_RESET use agesa_NoopSuccess? * diff --git a/src/mainboard/lippert/frontrunner-af/buildOpts.c b/src/mainboard/lippert/frontrunner-af/buildOpts.c index 0563243..e5681aa 100644 --- a/src/mainboard/lippert/frontrunner-af/buildOpts.c +++ b/src/mainboard/lippert/frontrunner-af/buildOpts.c @@ -25,10 +25,6 @@ * */ -#include <stdlib.h> - - - /* Select the CPU family. */ #define INSTALL_FAMILY_10_SUPPORT FALSE #define INSTALL_FAMILY_12_SUPPORT FALSE diff --git a/src/mainboard/lippert/frontrunner-af/mainboard.c b/src/mainboard/lippert/frontrunner-af/mainboard.c index 6530276..74f3aba 100644 --- a/src/mainboard/lippert/frontrunner-af/mainboard.c +++ b/src/mainboard/lippert/frontrunner-af/mainboard.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/mainboard/lippert/toucan-af/BiosCallOuts.c b/src/mainboard/lippert/toucan-af/BiosCallOuts.c index 7e6d0c4..c7b3b1b 100644 --- a/src/mainboard/lippert/toucan-af/BiosCallOuts.c +++ b/src/mainboard/lippert/toucan-af/BiosCallOuts.c @@ -18,7 +18,6 @@ #include <northbridge/amd/agesa/BiosCallOuts.h> #include <SB800.h> #include <southbridge/amd/cimx/sb800/gpio_oem.h> -#include <stdlib.h> /* Should AGESA_GNB_PCIE_SLOT_RESET use agesa_NoopSuccess? * diff --git a/src/mainboard/lippert/toucan-af/buildOpts.c b/src/mainboard/lippert/toucan-af/buildOpts.c index 0563243..e5681aa 100644 --- a/src/mainboard/lippert/toucan-af/buildOpts.c +++ b/src/mainboard/lippert/toucan-af/buildOpts.c @@ -25,10 +25,6 @@ * */ -#include <stdlib.h> - - - /* Select the CPU family. */ #define INSTALL_FAMILY_10_SUPPORT FALSE #define INSTALL_FAMILY_12_SUPPORT FALSE diff --git a/src/mainboard/lippert/toucan-af/mainboard.c b/src/mainboard/lippert/toucan-af/mainboard.c index b7126ea..59f140b 100644 --- a/src/mainboard/lippert/toucan-af/mainboard.c +++ b/src/mainboard/lippert/toucan-af/mainboard.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/mainboard/msi/ms7721/BiosCallOuts.c b/src/mainboard/msi/ms7721/BiosCallOuts.c index b3cac1d..ccad187 100644 --- a/src/mainboard/msi/ms7721/BiosCallOuts.c +++ b/src/mainboard/msi/ms7721/BiosCallOuts.c @@ -17,9 +17,7 @@ #include <AGESA.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include <northbridge/amd/agesa/state_machine.h> - #include <vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h> -#include <stdlib.h> const BIOS_CALLOUT_STRUCT BiosCallouts[] = { diff --git a/src/mainboard/msi/ms7721/buildOpts.c b/src/mainboard/msi/ms7721/buildOpts.c index 9e57e39..8edadda 100644 --- a/src/mainboard/msi/ms7721/buildOpts.c +++ b/src/mainboard/msi/ms7721/buildOpts.c @@ -25,8 +25,6 @@ * */ -#include <stdlib.h> - #include <vendorcode/amd/agesa/f15tn/AGESA.h> /* Include the files that instantiate the configuration definitions. */ @@ -41,7 +39,6 @@ #include <vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h> #include <vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h> - /* Select the CPU family. */ #define INSTALL_FAMILY_10_SUPPORT FALSE #define INSTALL_FAMILY_12_SUPPORT FALSE diff --git a/src/mainboard/msi/ms9652_fam10/get_bus_conf.c b/src/mainboard/msi/ms9652_fam10/get_bus_conf.c index 74b14b4..9d8ece9 100644 --- a/src/mainboard/msi/ms9652_fam10/get_bus_conf.c +++ b/src/mainboard/msi/ms9652_fam10/get_bus_conf.c @@ -21,10 +21,8 @@ #include <string.h> #include <stdint.h> #include <cpu/amd/multicore.h> - #include <cpu/amd/amdfam10_sysconf.h> -#include <stdlib.h> #include "mb_sysconf.h" // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables diff --git a/src/mainboard/opencellular/elgon/romstage.c b/src/mainboard/opencellular/elgon/romstage.c index 94c09ec..d907351 100644 --- a/src/mainboard/opencellular/elgon/romstage.c +++ b/src/mainboard/opencellular/elgon/romstage.c @@ -19,7 +19,6 @@ #include <soc/sdram.h> #include <soc/timer.h> #include <soc/mmu.h> -#include <stdlib.h> #include <console/console.h> #include <program_loading.h> #include <libbdk-hal/bdk-config.h> diff --git a/src/mainboard/pcengines/apu1/BiosCallOuts.c b/src/mainboard/pcengines/apu1/BiosCallOuts.c index df5f037..8408112 100644 --- a/src/mainboard/pcengines/apu1/BiosCallOuts.c +++ b/src/mainboard/pcengines/apu1/BiosCallOuts.c @@ -18,7 +18,6 @@ #include <spd_bin.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include <SB800.h> -#include <stdlib.h> #include "gpio_ftns.h" diff --git a/src/mainboard/pcengines/apu1/buildOpts.c b/src/mainboard/pcengines/apu1/buildOpts.c index 1f73eee..60ce0bb 100644 --- a/src/mainboard/pcengines/apu1/buildOpts.c +++ b/src/mainboard/pcengines/apu1/buildOpts.c @@ -25,9 +25,6 @@ * */ -#include <stdlib.h> - - /* Select the CPU family. */ #define INSTALL_FAMILY_10_SUPPORT FALSE #define INSTALL_FAMILY_12_SUPPORT FALSE diff --git a/src/mainboard/pcengines/apu2/BiosCallOuts.c b/src/mainboard/pcengines/apu2/BiosCallOuts.c index edacb22..13320f1 100644 --- a/src/mainboard/pcengines/apu2/BiosCallOuts.c +++ b/src/mainboard/pcengines/apu2/BiosCallOuts.c @@ -18,7 +18,6 @@ #include <spd_bin.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include <FchPlatform.h> -#include <stdlib.h> #include "gpio_ftns.h" #include "imc.h" diff --git a/src/mainboard/roda/rk9/mainboard.c b/src/mainboard/roda/rk9/mainboard.c index 3f72398..6057901 100644 --- a/src/mainboard/roda/rk9/mainboard.c +++ b/src/mainboard/roda/rk9/mainboard.c @@ -14,7 +14,6 @@ */ #include <stdint.h> -#include <stdlib.h> #include <arch/io.h> #include <device/device.h> #include <drivers/intel/gma/int15.h> diff --git a/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c index 6279d9c..5f4d9f3 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c +++ b/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c @@ -21,10 +21,8 @@ #include <string.h> #include <stdint.h> #include <cpu/amd/multicore.h> - #include <cpu/amd/amdfam10_sysconf.h> -#include <stdlib.h> #include "mb_sysconf.h" // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables diff --git a/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c index f32312d..1d06155 100644 --- a/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c +++ b/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c @@ -21,10 +21,8 @@ #include <string.h> #include <stdint.h> #include <cpu/amd/multicore.h> - #include <cpu/amd/amdfam10_sysconf.h> -#include <stdlib.h> #include "mb_sysconf.h" // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables diff --git a/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c index 8bc96c2..58a23bb 100644 --- a/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c +++ b/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c @@ -16,9 +16,7 @@ #include <device/pci.h> #include <device/pci_ops.h> #include <stdint.h> -#include <stdlib.h> #include <cpu/amd/multicore.h> - #include <cpu/amd/amdfam10_sysconf.h> /* Global variables for MB layouts and these will be shared by irqtable mptable diff --git a/src/mainboard/tyan/s2912_fam10/get_bus_conf.c b/src/mainboard/tyan/s2912_fam10/get_bus_conf.c index f589ef6..dc30718 100644 --- a/src/mainboard/tyan/s2912_fam10/get_bus_conf.c +++ b/src/mainboard/tyan/s2912_fam10/get_bus_conf.c @@ -21,10 +21,8 @@ #include <string.h> #include <stdint.h> #include <cpu/amd/multicore.h> - #include <cpu/amd/amdfam10_sysconf.h> -#include <stdlib.h> #include "mb_sysconf.h" // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables -- To view, visit https://review.coreboot.org/c/coreboot/+/32825 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c8ccdab0962459b467ac7b582de8860ea1eecd5 Gerrit-Change-Number: 32825 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: riscv: currently riscv does not support fit payload, remove redundant...
by Xiang Wang (Code Review) 23 Jun '19

23 Jun '19

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31477 Change subject: riscv: currently riscv does not support fit payload, remove redundant code ...................................................................... riscv: currently riscv does not support fit payload, remove redundant code This code is not necessary and will trigger an error when I try to boot linux with bbl.If you want to add this code, it is recommended to add it with the support code of the fit payload. Change-Id: If6929897c7f12d8acb079eeebaef512ae506ca8b Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/arch/riscv/boot.c 1 file changed, 1 insertion(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/31477/1 diff --git a/src/arch/riscv/boot.c b/src/arch/riscv/boot.c index 29064b1..0c8143f 100644 --- a/src/arch/riscv/boot.c +++ b/src/arch/riscv/boot.c @@ -32,14 +32,7 @@ { void (*doit)(int hart_id, void *fdt); int hart_id; - void *fdt = prog_entry_arg(prog); - - /* - * If prog_entry_arg is not set (e.g. by fit_payload), use fdt from HLS - * instead. - */ - if (fdt == NULL) - fdt = HLS()->fdt; + void *fdt = HLS()->fdt; if (ENV_RAMSTAGE && prog_type(prog) == PROG_PAYLOAD) { run_payload(prog, fdt, RISCV_PAYLOAD_MODE_S); -- To view, visit https://review.coreboot.org/c/coreboot/+/31477 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6929897c7f12d8acb079eeebaef512ae506ca8b Gerrit-Change-Number: 31477 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: riscv: Fix MENTRY_FRAME_SIZE to fit different machine lengths
by Xiang Wang (Code Review) 23 Jun '19

23 Jun '19

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31976 Change subject: riscv: Fix MENTRY_FRAME_SIZE to fit different machine lengths ...................................................................... riscv: Fix MENTRY_FRAME_SIZE to fit different machine lengths Change-Id: Iabe390963bcbeb9ec6016faa8312d101431942da Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/arch/riscv/include/mcall.h 1 file changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/31976/1 diff --git a/src/arch/riscv/include/mcall.h b/src/arch/riscv/include/mcall.h index 192d2b4..652d21b 100644 --- a/src/arch/riscv/include/mcall.h +++ b/src/arch/riscv/include/mcall.h @@ -20,14 +20,16 @@ // nice to have. #if __riscv_xlen == 64 #define HLS_SIZE 88 +/* We save 37 registers, currently. */ +#define MENTRY_FRAME_SIZE (HLS_SIZE + 37 * 8) #endif #if __riscv_xlen == 32 #define HLS_SIZE 52 +/* We save 37 registers, currently. */ +#define MENTRY_FRAME_SIZE (HLS_SIZE + 37 * 4) #endif -/* We save 37 registers, currently. */ -#define MENTRY_FRAME_SIZE (HLS_SIZE + 37 * 8) #ifndef __ASSEMBLER__ -- To view, visit https://review.coreboot.org/c/coreboot/+/31976 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabe390963bcbeb9ec6016faa8312d101431942da Gerrit-Change-Number: 31976 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-MessageType: newchange

3 6

Change in ...coreboot[master]: src/cpu: Use 'include <stdlib.h>' when appropriate
by HAOUAS Elyes (Code Review) 22 Jun '19

22 Jun '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32821 Change subject: src/cpu: Use 'include <stdlib.h>' when appropriate ...................................................................... src/cpu: Use 'include <stdlib.h>' when appropriate Change-Id: I44346594bc106eed73a1268b82f026b69e5f4512 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/allwinner/a10/clock.c M src/cpu/amd/family_10h-family_15h/init_cpus.h M src/cpu/intel/haswell/finalize.c M src/cpu/intel/model_2065x/finalize.c M src/cpu/intel/model_206ax/finalize.c M src/cpu/ti/am335x/gpio.c M src/cpu/ti/am335x/uart.c M src/cpu/x86/mtrr/mtrr.c 8 files changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/32821/1 diff --git a/src/cpu/allwinner/a10/clock.c b/src/cpu/allwinner/a10/clock.c index 76198b7..9e4e93d 100644 --- a/src/cpu/allwinner/a10/clock.c +++ b/src/cpu/allwinner/a10/clock.c @@ -22,7 +22,6 @@ #include <console/console.h> #include <delay.h> #include <lib.h> -#include <stdlib.h> static struct a10_ccm *const ccm = (void *)A1X_CCM_BASE; diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.h b/src/cpu/amd/family_10h-family_15h/init_cpus.h index 5d653d1..cca0049 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.h +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.h @@ -16,7 +16,6 @@ #ifndef INIT_CPUS_H #define INIT_CPUS_H -#include <stdlib.h> #include <cpu/x86/lapic.h> #include <cpu/x86/mtrr.h> #include <cpu/amd/msr.h> diff --git a/src/cpu/intel/haswell/finalize.c b/src/cpu/intel/haswell/finalize.c index cc2d1a4..16e54d7 100644 --- a/src/cpu/intel/haswell/finalize.c +++ b/src/cpu/intel/haswell/finalize.c @@ -15,7 +15,6 @@ */ #include <stdint.h> -#include <stdlib.h> #include <arch/cpu.h> #include <cpu/x86/msr.h> #include "haswell.h" diff --git a/src/cpu/intel/model_2065x/finalize.c b/src/cpu/intel/model_2065x/finalize.c index 5b85601..724e09c 100644 --- a/src/cpu/intel/model_2065x/finalize.c +++ b/src/cpu/intel/model_2065x/finalize.c @@ -15,7 +15,6 @@ */ #include <stdint.h> -#include <stdlib.h> #include <arch/cpu.h> #include <cpu/x86/msr.h> #include <cpu/intel/speedstep.h> diff --git a/src/cpu/intel/model_206ax/finalize.c b/src/cpu/intel/model_206ax/finalize.c index 30b00bb..98ce555 100644 --- a/src/cpu/intel/model_206ax/finalize.c +++ b/src/cpu/intel/model_206ax/finalize.c @@ -15,7 +15,6 @@ */ #include <stdint.h> -#include <stdlib.h> #include <arch/cpu.h> #include <cpu/x86/msr.h> #include <cpu/intel/speedstep.h> diff --git a/src/cpu/ti/am335x/gpio.c b/src/cpu/ti/am335x/gpio.c index 2685839..8660f2c 100644 --- a/src/cpu/ti/am335x/gpio.c +++ b/src/cpu/ti/am335x/gpio.c @@ -16,7 +16,6 @@ #include <console/console.h> #include <cpu/ti/am335x/gpio.h> #include <stdint.h> -#include <stdlib.h> static struct am335x_gpio_regs *gpio_regs_and_bit(unsigned int gpio, uint32_t *bit) diff --git a/src/cpu/ti/am335x/uart.c b/src/cpu/ti/am335x/uart.c index c482a85..4e9d012 100644 --- a/src/cpu/ti/am335x/uart.c +++ b/src/cpu/ti/am335x/uart.c @@ -12,7 +12,6 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <types.h> #include <console/uart.h> #include <device/mmio.h> diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index d87c3d4..91ff14a 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -22,7 +22,6 @@ */ #include <stddef.h> -#include <stdlib.h> #include <string.h> #include <bootstate.h> #include <console/console.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/32821 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44346594bc106eed73a1268b82f026b69e5f4512 Gerrit-Change-Number: 32821 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 2

Change in ...coreboot[master]: soc/intel/common: Add SMBIOS type 131 fields
by Francois Toguo Fotso (Code Review) 21 Jun '19

21 Jun '19

Francois Toguo Fotso has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33067 Change subject: soc/intel/common: Add SMBIOS type 131 fields ...................................................................... soc/intel/common: Add SMBIOS type 131 fields Fill SMBIOS type 131 for intel SOCs. BUG=none TEST=Boot to OS and check with dmidecode that entry is added. Change-Id: Ida4e1a95e20289fbab01e773c18e00ce74aa8223 Signed-off-by: Francois Toguo <francois.toguo.fotso(a)intel.com> --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 692 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/33067/1 diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 302e6de..3aaf817 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -17,6 +17,7 @@ #include <assert.h> #include <commonlib/helpers.h> #include <console/console.h> +#include <cpu/x86/msr.h> #include <device/mmio.h> #include <delay.h> #include <device/pci.h> @@ -25,6 +26,7 @@ #include <intelblocks/cse.h> #include <soc/iomap.h> #include <soc/pci_devs.h> +#include <smbios.h> #include <string.h> #include <timer.h> @@ -68,6 +70,37 @@ #define MEI_HDR_CSE_ADDR_START 0 #define MEI_HDR_CSE_ADDR (((1 << 8) - 1) << MEI_HDR_CSE_ADDR_START) +#define MKHI_GROUP_ID_GEN 0xff +#define MKHI_GROUP_ID_FWCAPS 0x03 +#define MKHI_FWCAPS_GET_RULE 0x02 +#define MKHI_GROUP_ID_PTFTYPE 0x03 +#define MKHI_PTFTYPE_GET_RULE 0x02 +#define MKHI_GROUP_ID_FW_STATE 0x03 +#define MKHI_FW_STATE_GET_RULE 0x02 +#define MKHI_GET_FW_VERSION 0x02 +#define MKHI_GET_FW_VERSION 0x02 +#define MKHI_GET_PLATFORM_TYPE 0x02 +#define MEI_HOST_ADDRESS 0 +#define MEI_ADDRESS_MKHI 0x07 +#define TXT_IN_VMX_AND_SMX_MSR 0xFF03 +#define DEFAULT_PCI_BUS_NUMBER_PCH 0x0 +#define PCI_FN_PCH_LAN 6 +#define SMBIOS_INTEL_TYPE131 0x83 +#define BITS_0_THROUGH_2_MASK 0x7 +#define BITS_3_THROUGH_7_MASK 0x38 +#define WORD_0_MASK 0x0000ffff +#define WORD_1_MASK 0xffff0000 + +union mkhi_header { + uint32_t data; + struct { + uint32_t group_id: 8; + uint32_t command: 7; + uint32_t is_response: 1; + uint32_t reserved: 8; + uint32_t result: 8; + } __packed fields; +}; struct cse_device { uintptr_t sec_bar; @@ -491,8 +524,489 @@ return 0; } +/* Get ME firmware version */ +int mkhi_get_fw_version(me_fw_version *version) +{ + int res; + size_t reply_size; + + struct fw_version_cmd { + union mkhi_header mkhi_hdr; + } __packed msg; + + struct fw_version_response { + union mkhi_header mkhi_hdr; + me_fw_version version_info; + } __packed rsp; + + msg.mkhi_hdr.fields.group_id = MKHI_GROUP_ID_GEN; + msg.mkhi_hdr.fields.command = MKHI_GET_FW_VERSION; + msg.mkhi_hdr.fields.is_response = 0; + + res = heci_send(&msg, sizeof(msg), BIOS_HOST_ADDR, HECI_MKHI_ADDR); + + if (!res) { + printk(BIOS_ERR, "Failed to send HECI message.\n"); + return 0; + } + + reply_size = sizeof(rsp); + res = heci_receive(&rsp, &reply_size); + + if (!res) { + printk(BIOS_ERR, "Failed to receive HECI reply.\n"); + return 0; + } + + if (rsp.mkhi_hdr.fields.result != 0) { + printk(BIOS_ERR, "Failed to get ME version.\n"); + return 0; + } + + memcpy(version, &rsp.version_info, sizeof(rsp.version_info)); + + return 1; +} + + +/* Get ME Firmware Capabilities */ +int mkhi_get_fwcaps(me_fwcaps *f_cap) +{ + int res; + size_t reply_size; + + struct fw_version_cmd { + union mkhi_header mkhi_hdr; + u32 rule_id; + } __packed msg; + + msg.mkhi_hdr.fields.group_id = MKHI_GROUP_ID_FWCAPS; + msg.mkhi_hdr.fields.command = MKHI_FWCAPS_GET_RULE; + msg.mkhi_hdr.fields.is_response = 0; + msg.rule_id = 0; + + struct fw_version_response { + union mkhi_header mkhi_hdr; + me_fwcaps fwcaps; + } __packed rsp; + rsp.fwcaps.id = 0; + rsp.fwcaps.length = 0x4; + + res = heci_send(&msg, sizeof(msg), BIOS_HOST_ADDR, HECI_MKHI_ADDR); + + if (!res) { + printk(BIOS_ERR, "Failed to send HECI message.\n"); + return 0; + } + + reply_size = sizeof(rsp); + res = heci_receive(&rsp, &reply_size); + + if (!res) { + printk(BIOS_ERR, "Failed to receive HECI reply.\n"); + return 0; + } + + if (rsp.mkhi_hdr.fields.result != 0) { + printk(BIOS_ERR, "Failed to get ME FW CAPS.\n"); + return 0; + } + + memcpy(f_cap, &rsp.fwcaps, sizeof(rsp.fwcaps)); + + return 1; +} + +/* Get ME Firmware configuration state */ +int mkhi_get_fw_fea_state(mefwcaps_sku *f_cap) +{ + int res; + size_t reply_size; + + struct fw_version_cmd { + union mkhi_header mkhi_hdr; + u32 rule_id; + } __packed msg; + + msg.mkhi_hdr.fields.group_id = MKHI_GROUP_ID_FW_STATE; + msg.mkhi_hdr.fields.command = MKHI_FW_STATE_GET_RULE; + msg.mkhi_hdr.fields.is_response = 0; + msg.rule_id = 0x20; + + struct fw_version_response { + union mkhi_header mkhi_hdr; + me_fwcaps fwcaps; + } __packed rsp; + rsp.fwcaps.id = 0; + rsp.fwcaps.length = 0x4; + + res = heci_send(&msg, sizeof(msg), BIOS_HOST_ADDR, HECI_MKHI_ADDR); + + if (!res) { + printk(BIOS_ERR, "Failed to send HECI message.\n"); + return 0; + } + + reply_size = sizeof(rsp); + res = heci_receive(&rsp, &reply_size); + + if (!res) { + printk(BIOS_ERR, "Failed to receive HECI reply.\n"); + return 0; + } + + if (rsp.mkhi_hdr.fields.result != 0) { + printk(BIOS_ERR, "Failed to get ME FW CAPS CONFIG.\n"); + return 0; + } + + memcpy(f_cap, &rsp.fwcaps.caps_sku, sizeof(rsp.fwcaps.caps_sku)); + + return 1; +} + +int mkhi_get_platform_type(me_platform_type *platf_type) +{ + int res; + size_t reply_size; + + struct fw_version_cmd { + union mkhi_header mkhi_hdr; + u32 rule_id; + } __packed msg; + + msg.mkhi_hdr.fields.group_id = MKHI_GROUP_ID_PTFTYPE; + msg.mkhi_hdr.fields.command = MKHI_PTFTYPE_GET_RULE; + msg.mkhi_hdr.fields.is_response = 0; + msg.rule_id = 0x1d; + + struct fw_version_response { + union mkhi_header mkhi_hdr; + uint32_t id; + uint8_t length; + me_platform_type platf_type; + } __packed rsp; + rsp.id = 0; + rsp.length = sizeof(union mkhi_header) + sizeof(me_platform_type); + + res = heci_send(&msg, sizeof(msg), BIOS_HOST_ADDR, HECI_MKHI_ADDR); + + if (!res) { + printk(BIOS_ERR, "Failed to send HECI message.\n"); + return 0; + } + + reply_size = sizeof(rsp); + res = heci_receive(&rsp, &reply_size); + + if (!res) { + printk(BIOS_ERR, "Failed to receive HECI reply.\n"); + return 0; + } + + if (rsp.mkhi_hdr.fields.result != 0) { + printk(BIOS_ERR, "Failed to get PLATFORM TTYPE .\n"); + return 0; + } + + memcpy(platf_type, &rsp.platf_type, sizeof(rsp.platf_type)); + + return 1; +} + +void get_me_cpu_capab(cpu_cap *cpu_capabilities) +{ + msr_t msr; + u32 feature_flag = cpuid(1).ecx; + msr = rdmsr(IA32_FEATURE_CONTROL); + + if (feature_flag & CPUID_SMX) + cpu_capabilities->lt_txt_cap = 1; + else + cpu_capabilities->lt_txt_cap = 0; + + if ((msr.lo & TXT_IN_VMX_AND_SMX_MSR) == TXT_IN_VMX_AND_SMX_MSR) + cpu_capabilities->lt_txt_enabled = 1; + else + cpu_capabilities->lt_txt_enabled = 0; + + if (feature_flag & CPUID_VMX) + cpu_capabilities->vtx_cap = 1; + else + cpu_capabilities->vtx_cap = 0; + + if (msr.lo & (1 << 2)) + cpu_capabilities->vtx_enabled = 1; + else + cpu_capabilities->vtx_enabled = 0; + + return; +} + +/* + * MEBX is a UEFI Option ROM for the ME. + * Missing without the UEFI payload. All 0s for coreboot + */ +void get_mebx_version(mebx_ver *mebx_version ) +{ + mebx_version->major = 0; + mebx_version->minor = 0; + mebx_version->hotfix = 0; + mebx_version->build = 0; + + return; +} + +void get_pch_capab(pch_cap *pch_capabilities) +{ + pch_capabilities->function_number = PCI_FUNC(PCH_DEVFN_LPC); + pch_capabilities->device_number = PCH_DEV_SLOT_LPC; + pch_capabilities->bus_number = DEFAULT_PCI_BUS_NUMBER_PCH; + pch_capabilities->device_id = pci_read_config16(PCH_DEV_LPC, PCI_DEVICE_ID); + return; +} + + +void get_me_platf_capab(me_cap *platf_cap) +{ + + me_fw_version version; + if (mkhi_get_fw_version(&version)) + { + platf_cap->me_major_ver = version.code_major; + platf_cap->me_minor_ver = version.code_minor; + platf_cap->me_build_ver = version.code_build_number; + platf_cap->me_hotfix_ver = version.code_hot_fix; + } else { + platf_cap->me_major_ver = 0; + platf_cap->me_minor_ver = 0; + platf_cap->me_build_ver = 0; + platf_cap->me_hotfix_ver = 0; + } + + platf_cap->me_enabled = 1; + + me_fwcaps fw_caps; + if (mkhi_get_fwcaps(&fw_caps)) + { + if (fw_caps.caps_sku.kvm) + platf_cap->intel_kvm = 1; + } else { + platf_cap->intel_kvm = 0; + } + + me_platform_type platf_type; + if (mkhi_get_platform_type(&platf_type)) + { + switch (platf_type.brand) + { + case IntelAmtBrand: + platf_cap->intel_amt_fw = 1; + platf_cap->local_wakeup_timer = 1; + break; + + case IntelStandardManageabilityBrand: + platf_cap->intel_amt_fw_std = 1; + break; + } + } else { + platf_cap->intel_amt_fw = 0; + platf_cap->local_wakeup_timer = 0; + platf_cap->intel_amt_fw_std = 0; + } + + return; +} + + +void get_me_platf_config_state(u32 *config_state) +{ + u32 state = 0; + mefwcaps_sku fwcaps; + if (mkhi_get_fw_fea_state(&fwcaps)) + { + state |= fwcaps.full_net ? (1 << 8) : 0; + state |= fwcaps.std_net ? (1 << 9) : 0; + state |= fwcaps.manageability ? (1 << 10) : 0; + state |= fwcaps.integrated_touch ? (1 << 11) : 0; + state |= fwcaps.intel_cls ? (1 << 12) : 0; + state |= fwcaps.ish ? (1 << 13) : 0; + state |= fwcaps.pavp ? (1 << 14) : 0; + state |= fwcaps.ipv6 ? (1 << 15) : 0; + state |= fwcaps.kvm ? (1 << 16) : 0; + state |= fwcaps.dal ? (1 << 17) : 0; + state |= fwcaps.tls ? (1 << 18) : 0; + state |= fwcaps.wlan ? (1 << 19) : 0; + state |= fwcaps.ptt ? (1 << 20) : 0; + } + *config_state = state; + + return; +} + + +void get_network_device_lan(network_dev *nwk_dev) +{ + nwk_dev->function_number = PCI_FN_PCH_LAN; + nwk_dev->device_number = PCH_DEV_SLOT_LPC; + nwk_dev->bus_number = DEFAULT_PCI_BUS_NUMBER_PCH; + nwk_dev->device_id = pci_read_config16(PCH_DEV_LPC, PCI_DEVICE_ID); + + return; +} + +void get_bios_sec_capab(bios_cap *bios_sec_cap) +{ + u32 cpu_feature_flag = cpuid(1).ecx; + if (cpu_feature_flag & CPUID_VMX) + { + bios_sec_cap->vtx_support = 1; + bios_sec_cap->vtd_support = 1; + } else { + bios_sec_cap->vtx_support = 0; + bios_sec_cap->vtd_support = 0; + } + + if (cpu_feature_flag & CPUID_SMX) + bios_sec_cap->txt_support = 1; + else + bios_sec_cap->txt_support = 0; + + return; +} + +void generate_type131_data(me_smbios_info *me_info, struct smbios_type131 *type131) +{ + + u32 cpu_capb = 0, bios_sec_cap = 0; + u64 pch_capb = 0, mebx_version = 0; + u32 platf_cap[3] = {0,0,0}, nwk_dev_lan[3] = {0,0,0}; + int i,j; + + /* CPU capabilities bits setting*/ + cpu_cap c_cap_data = me_info->cpu_capabilities; + cpu_capb |= (c_cap_data.vtx_enabled) ? (1 << 0) : 0; + cpu_capb |= (c_cap_data.lt_txt_cap) ? (1 << 1) : 0; + cpu_capb |= (c_cap_data.lt_txt_cap) ? (1 << 2) : 0; + cpu_capb |= (c_cap_data.lt_txt_enabled) ? (1 << 3) : 0; + cpu_capb |= (c_cap_data.vtx_cap) ? (1 << 4) : 0; + cpu_capb |= (c_cap_data.vtx_enabled) ? (1 << 5) : 0; + cpu_capb &= 0x3f; + type131->cpu_capability = cpu_capb; + + /* MEBx: ME BIOS Extensions bits setting*/ + u64 mask_0 = 0; + mebx_version |= me_info->mebx_version.major; + mebx_version |= (mask_0 | (me_info->mebx_version.minor)) << 16; + mebx_version |= (mask_0 | (me_info->mebx_version.hotfix)) << 32; + mebx_version |= (mask_0 | (me_info->mebx_version.build)) << 48; + type131->intel_mebx_version = mebx_version; + + /* PCH capabilities bits setting*/ + pch_cap ph_cap = me_info->pch_capabilities; + pch_capb |= ph_cap.function_number & BITS_0_THROUGH_2_MASK; + pch_capb |= (ph_cap.device_number << 3) & BITS_3_THROUGH_7_MASK; + pch_capb |= (ph_cap.bus_number << 8) & 0xff00; + pch_capb |= (ph_cap.device_id << 16) & WORD_1_MASK; + type131->pch_capability = pch_capb; + + /* ME platform capabilities bits setting */ + me_cap pf_cap = me_info->me_capabilities; + platf_cap[0] |= (pf_cap.me_enabled) ? 1: 0; + platf_cap[0] |= (pf_cap.intel_amt_fw) ? (1 << 3) : 0; + platf_cap[0] |= (pf_cap.intel_amt_fw_std) ? (1 << 4) : 0; + platf_cap[0] |= (pf_cap.intel_kvm) ? (1 << 14) : 0; + platf_cap[0] |= (pf_cap.local_wakeup_timer) ? (1 << 15) : 0; + platf_cap[1] |= pf_cap.me_minor_ver & WORD_0_MASK; + platf_cap[1] |= pf_cap.me_major_ver << 16; + platf_cap[2] |= pf_cap.me_build_ver & WORD_0_MASK; + platf_cap[2] |= pf_cap.me_hotfix_ver << 16; + + for (i=0; i < 3; i++) + memcpy(&type131->me_platf_capabilities[i], &platf_cap[i], 4); + + /* ME platform configuration state bits setting*/ + u32 config_state = 0; + get_me_platf_config_state(&config_state); + type131->me_feature_state = config_state; + + /* Network device LAN */ + network_dev net_dev = me_info->network_device; + nwk_dev_lan[0] |= net_dev.function_number & BITS_0_THROUGH_2_MASK; + nwk_dev_lan[0] |= (net_dev.device_number << 3) & BITS_3_THROUGH_7_MASK; + nwk_dev_lan[0] |= (net_dev.bus_number << 8) & 0xff00; + nwk_dev_lan[0] |= (net_dev.device_id << 16) & WORD_1_MASK; + nwk_dev_lan[1] = 0; + nwk_dev_lan[2] = 0; + for (j=0; j < 3; j++) + memcpy(&type131->network_device_lan[j],&nwk_dev_lan[j],4); + + /* BIOS securities capabilities bits setting */ + bios_cap b_cap = me_info->bios_sec_capab; + bios_sec_cap |= (b_cap.vtd_support) ? (1 << 1) : 0; + bios_sec_cap |= (b_cap.txt_support) ? (1 << 2) : 0; + bios_sec_cap |= (b_cap.vtx_support) ? (1 << 5) : 0; + type131->bios_sec_capabilities = bios_sec_cap; + + /* unique id for Intel vPro: vPro or 0x76 0x50 0x72 0x6F*/ + memcpy(&type131->structure_id, "vPro",4); + type131->reserved = 0; + + return; +} + +void save_me_smbios_info(me_smbios_info *me_info) +{ + /* CPU capabilities */ + get_me_cpu_capab(&me_info->cpu_capabilities); + + /* MEBx: ME BIOS Extensions */ + get_mebx_version(&me_info->mebx_version); + + /* PCH capabilities */ + get_pch_capab(&me_info->pch_capabilities); + + /* ME platform capabilities */ + get_me_platf_capab(&me_info->me_capabilities); + + /* ME platform configuration state */ + get_me_platf_config_state(&me_info->me_fw_config); + + /* Network device LAN */ + get_network_device_lan(&me_info->network_device); + + /* BIOS securities capabilities */ + get_bios_sec_capab(&me_info->bios_sec_capab); + + me_info->reserved = 0; + + return; +} + #if ENV_RAMSTAGE +#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES) +static int smbios_write_type131_info(struct device *dev, int *handle, unsigned long *current) +{ + me_smbios_info me_info; + save_me_smbios_info(&me_info); + + struct smbios_type131 *t = (struct smbios_type131 *)*current; + int len = sizeof(struct smbios_type131); + + memset(t, 0, sizeof(struct smbios_type131)); + t->type = SMBIOS_INTEL_TYPE131; + t->length = len - 2; + t->handle = *handle; + + generate_type131_data(&me_info, t); + + len = t->length + smbios_string_table_len(t->eos); + *current += len; + return len; +} +#endif + static void update_sec_bar(struct device *dev) { g_cse.sec_bar = find_resource(dev, PCI_BASE_ADDRESS_0)->base; @@ -511,6 +1025,9 @@ .read_resources = pci_dev_read_resources, .enable_resources = pci_dev_enable_resources, .init = pci_dev_init, +#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES) + .get_smbios_data = smbios_write_type131_info, +#endif .ops_pci = &pci_dev_ops_pci, }; diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index d7c4d9f..24b5927 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -47,4 +47,179 @@ #define BIOS_HOST_ADDR 0x00 #define HECI_MKHI_ADDR 0x07 +typedef struct { + u32 vmx_state : 1; /* VMX state (On/Off) */ + u32 smx_state : 1; /* SMX state (On/Off) */ + u32 lt_txt_cap : 1; /* LT/TXT capability */ + u32 lt_txt_enabled : 1; /* LT/TXT Enabled state */ + u32 vtx_cap : 1; /* VT-x capability */ + u32 vtx_enabled : 1; /* VT-x Enabled state */ + u32 reserved : 26; +}__packed cpu_cap; + +typedef struct { + u32 function_number : 3; /* PCI Device Function Number */ + u32 device_number : 5; /* PCI Device Device Number */ + u32 bus_number : 8; /* PCI Device Bus Number */ + u32 device_id : 16; + u32 reserved : 32; +}__packed pch_cap; + +typedef struct { + u32 me_enabled : 1; /* ME enabled/Disabled */ + u32 reserved : 2; + u32 intel_amt_fw : 1; /* Intel AMT FW support */ + u32 intel_amt_fw_std : 1; /* Intel AMT Standard FW support */ + u32 reserved_1 : 9; + u32 intel_kvm : 1; /* Intel KVM supported */ + u32 local_wakeup_timer : 1; /* Local Wakeup Timer support */ + u32 reserved_2 : 16; + u32 me_minor_ver : 16; + u32 me_major_ver : 16; + u32 me_build_ver : 16; + u32 me_hotfix_ver : 16; +}__packed me_cap; + +typedef struct { + uint16_t code_minor; + uint16_t code_major; + uint16_t code_build_number; + uint16_t code_hot_fix; + uint16_t recovery_minor; + uint16_t recovery_major; + uint16_t recovery_build_number; + uint16_t recovery_hot_fix; + uint16_t fitcminor; + uint16_t fitcmajor; + uint16_t fitcbuildno; + uint16_t fitchotfix; +} __packed me_fw_version; + +typedef struct { + uint32_t full_net : 1; /* Full Network manageability */ + uint32_t std_net : 1; /* Regular Network manageability */ + uint32_t manageability : 1; /* Manageability */ + uint32_t reserved_1 : 1; + u32 integrated_touch : 1; /* Intel Integrated Touch */ + uint32_t reserved_2 : 1; + uint32_t intel_cls : 1; /* IntelR Capab Licensing Service */ + uint32_t reserved_3 : 3; + u32 ish : 1; /* IntelR Sensor Hub */ + uint32_t reserve_4 : 1; + uint32_t pavp : 1; /* Protected Audio Video Path (PAVP) */ + uint32_t reserved_5 : 4; + uint32_t ipv6 : 1; + uint32_t kvm : 1; + uint32_t reserve_6 : 1; + u32 dal : 1; /* Dynamic Application Loader (DAL) */ + u32 tls : 1; /* [21] Cipher Transport Layer (TLS) */ + uint32_t reserve_7 : 1; + uint32_t wlan : 1; /* Wireless LAN (WLAN) */ + uint32_t reserve_8 : 1; + uint32_t ptt : 1; /* Platform Trust Technology */ + uint32_t reserved_9 : 2; +}__packed mefwcaps_sku; + +typedef struct { + uint32_t id; + uint8_t length; + mefwcaps_sku caps_sku; + uint32_t reserved :3; +} __packed me_fwcaps; + + +/* Platform Type */ +typedef enum { + NoBrand, + IntelAmtBrand, + IntelStandardManageabilityBrand, + IntelReservedBrand1, + IntelReservedBrand2, + IntelReservedBrand3 +} platform_brand; + +typedef struct { + u32 function_number : 3; + u32 device_number : 5; + u32 bus_number : 8; + u32 device_id : 16; + u32 reserved1 : 16; + u32 reserved2 : 16; + u32 reserved3 : 32; +}__packed network_dev; + +typedef struct { + u32 reserved1 : 1; + u32 vtd_support : 1; ///< [1] BIOS supports VT-d + u32 txt_support : 1; ///< [2] BIOS supports TXT + u32 reserved2 : 1; + u32 reserved3 : 1; + u32 vtx_support : 1; ///< [5] BIOS supports VT-x + u32 reserved4 : 26; +}__packed bios_cap; + +typedef struct { + u16 major; + u16 minor; + u16 hotfix; + u16 build; +}__packed mebx_ver; + +typedef struct { + u32 mobile: 1; + u32 desktop: 1; + u32 server: 1; + u32 workstation: 1; + u32 corporate: 1; + u32 consumer: 1; + u32 regular_super_sku: 1; + u32 rsvd: 1; + u32 image_type: 4; + u32 brand: 4; + u32 rsvd1: 16; +} __packed me_platform_type; + +/* This is definition for SMBIOS Oem data type 131 */ +typedef struct { + cpu_cap cpu_capabilities; + mebx_ver mebx_version; + pch_cap pch_capabilities; + me_cap me_capabilities; + u32 me_fw_config; + network_dev network_device; + bios_cap bios_sec_capab; + u8 structure_identifier[4]; + u32 reserved; +}__packed me_smbios_info; + +struct smbios_type131 { + u8 type; + u8 length; + u16 handle; + u32 cpu_capability; + u64 intel_mebx_version; + u64 pch_capability; + u32 me_platf_capabilities[3]; + u32 me_feature_state; + u32 network_device_lan[3]; + u32 bios_sec_capabilities; + u32 structure_id; + u32 reserved; + u8 eos[2]; +}__packed ; + +int mkhi_get_fw_version(me_fw_version *version); +int mkhi_get_platform_type(me_platform_type *platf_type); +int mkhi_get_fw_fea_state(mefwcaps_sku *f_cap); +int mkhi_get_fwcaps(me_fwcaps *f_cap); +void get_me_cpu_capab(cpu_cap *cpu_capabilities); +void get_mebx_version(mebx_ver *mebx_verion); +void get_pch_capab(pch_cap *pch_capabilities); +void get_me_platf_capab(me_cap *platf_cap); +void get_me_platf_config_state(u32 *config_state); +void get_network_device_lan(network_dev *nwk_dev); +void get_bios_sec_capab(bios_cap *bios_sec_cap); +void save_me_smbios_info(me_smbios_info *me_info); +void generate_type131_data(me_smbios_info *me_info, struct smbios_type131 *type131); + #endif // SOC_INTEL_COMMON_MSR_H -- To view, visit https://review.coreboot.org/c/coreboot/+/33067 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida4e1a95e20289fbab01e773c18e00ce74aa8223 Gerrit-Change-Number: 33067 Gerrit-PatchSet: 1 Gerrit-Owner: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-MessageType: newchange

3 8

Change in ...coreboot[master]: mediatek/mt8183: add support for SAMSUNG EMCP DDR
by huayang duan (Code Review) 21 Jun '19

21 Jun '19

huayang duan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32243 Change subject: mediatek/mt8183: add support for SAMSUNG EMCP DDR ...................................................................... mediatek/mt8183: add support for SAMSUNG EMCP DDR BUG=b:80501386 BRANCH=none TEST=Boots correctly on EMCP DRAM Change-Id: I5fcc8673a2fbd7ec3a8776ab61c57f8903ddda20 --- M src/mainboard/google/kukui/sdram_configs.c M src/mainboard/google/kukui/sdram_params/Makefile.inc A src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c 4 files changed, 44 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/32243/1 diff --git a/src/mainboard/google/kukui/sdram_configs.c b/src/mainboard/google/kukui/sdram_configs.c old mode 100644 new mode 100755 index cbfb08d..ca74fa7 --- a/src/mainboard/google/kukui/sdram_configs.c +++ b/src/mainboard/google/kukui/sdram_configs.c @@ -21,6 +21,7 @@ static const char *const sdram_configs[] = { [1] = "sdram-lpddr4x-H9HCNNNCPMALHR-4GB", [2] = "sdram-lpddr4x-MT53E1G32D4NQ-4GB", + [3] = "sdram-lpddr4x-KMDP6001DA-B425-4GB", }; static struct sdram_params params; diff --git a/src/mainboard/google/kukui/sdram_params/Makefile.inc b/src/mainboard/google/kukui/sdram_params/Makefile.inc old mode 100644 new mode 100755 index 1e11140..d685b1a --- a/src/mainboard/google/kukui/sdram_params/Makefile.inc +++ b/src/mainboard/google/kukui/sdram_params/Makefile.inc @@ -1,6 +1,7 @@ sdram-params := sdram-params += sdram-lpddr4x-H9HCNNNCPMALHR-4GB sdram-params += sdram-lpddr4x-MT53E1G32D4NQ-4GB +sdram-params += sdram-lpddr4x-KMDP6001DA-B425-4GB $(foreach params,$(sdram-params), \ $(eval cbfs-files-y += $(params)) \ diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c new file mode 100755 index 0000000..1e0c362 --- /dev/null +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/emi.h> + +struct sdram_params params = { + .impedance = { + [ODT_OFF] = {0x9, 0x7, 0x0, 0xF}, + [ODT_ON] = {0xA, 0x9, 0x0, 0xE} + }, + .wr_level = { + [CHANNEL_A] = { {0x21, 0x21}, {0x20, 0x20} }, + [CHANNEL_B] = { {0x1E, 0x1F}, {0x1D, 0x1E} } + }, + .cbt_cs = { + [CHANNEL_A] = {0x1, 0x1}, + [CHANNEL_B] = {0x2, 0x2} + }, + .cbt_mr12 = { + [CHANNEL_A] = {0x56, 0x56}, + [CHANNEL_B] = {0x58, 0x5C} + }, + .emi_cona_val = 0xF053F154, + .emi_conh_val = 0x44440003, + .emi_conf_val = 0x00421000, + .chn_emi_cona_val = {0x0444F051, 0x0444F051}, + .cbt_mode_extern = CBT_NORMAL_MODE, + .delay_cell_unit = 868, +}; diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c old mode 100644 new mode 100755 index 11a46bb..1fefd34 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -32,7 +32,7 @@ enum { FIRST_DQ_DELAY = 0, - FIRST_DQS_DELAY = -10, + FIRST_DQS_DELAY = -16, MAX_DQDLY_TAPS = 16, MAX_RX_DQDLY_TAPS = 63, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/32243 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5fcc8673a2fbd7ec3a8776ab61c57f8903ddda20 Gerrit-Change-Number: 32243 Gerrit-PatchSet: 1 Gerrit-Owner: huayang duan <huayangduan(a)gmail.com> Gerrit-MessageType: newchange

7 24

Change in ...coreboot[master]: mediatek/mt8183: fix mode register setting fail issue
by huayang duan (Code Review) 21 Jun '19

21 Jun '19

huayang duan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32284 Change subject: mediatek/mt8183: fix mode register setting fail issue ...................................................................... mediatek/mt8183: fix mode register setting fail issue the mode register setting of DRAM maybe failed without delay operate, need add delay after each MR write. BUG=b:80501386 BRANCH=none TEST=Boots correctly and stress test pass on Kukui. Change-Id: I51785e90b2014994be5018bfe543245d44626242 Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> --- M src/soc/mediatek/mt8183/dramc_init_setting.c 1 file changed, 128 insertions(+), 44 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/32284/1 diff --git a/src/soc/mediatek/mt8183/dramc_init_setting.c b/src/soc/mediatek/mt8183/dramc_init_setting.c old mode 100644 new mode 100755 index d275127..98108c6 --- a/src/soc/mediatek/mt8183/dramc_init_setting.c +++ b/src/soc/mediatek/mt8183/dramc_init_setting.c @@ -18,6 +18,7 @@ #include <soc/dramc_pi_api.h> #include <soc/dramc_register.h> #include <soc/infracfg.h> +#include <delay.h> struct reg_init_value { u32 *addr; @@ -620,7 +621,52 @@ {&ch[1].phy.shu[0].rk[1].b[1].dq[1], 0x22000000}, {&ch[1].phy.shu[0].b[0].dll[1], 0x00022501}, - /* dramc mode register init */ + /* update the ac timing */ + {&ch[0].ao.shu[0].actim[0], 0x06020c07}, + {&ch[0].ao.shu[0].actim[1], 0x10080501}, + {&ch[0].ao.shu[0].actim[2], 0x07070201}, + {&ch[0].ao.shu[0].actim[3], 0x6164002c}, + {&ch[0].ao.shu[0].actim[4], 0x22650077}, + {&ch[0].ao.shu[0].actim[5], 0x0a000c0b}, + {&ch[0].ao.shu[0].actim_xrt, 0x05030609}, + {&ch[0].ao.shu[0].ac_time_05t, 0x000106e1}, + {&ch[0].ao.catraining1, 0x0b000000}, + {&ch[0].ao.shu[0].rk[0].dqsctl, 0x00000004}, + {&ch[0].ao.shu[0].rk[1].dqsctl, 0x00000004}, + {&ch[0].ao.shu[0].odtctrl, 0xc001004f}, + {&ch[0].ao.shu[0].conf[1], 0x34000d0f}, + {&ch[0].ao.shu[0].conf[2], 0x9007640f}, + {&ch[0].ao.shu[0].scintv, 0x4e39eb36}, + {&ch[0].ao.shu[0].ckectrl, 0x33210000}, + {&ch[0].ao.ckectrl, 0x88d02440}, + {&ch[0].ao.shu[0].rankctl, 0x64300003}, + {&ch[0].ao.shu[0].rankctl, 0x64301203}, + {&ch[1].ao.shu[0].actim[0], 0x06020c07}, + {&ch[1].ao.shu[0].actim[1], 0x10080501}, + {&ch[1].ao.shu[0].actim[2], 0x07070201}, + {&ch[1].ao.shu[0].actim[3], 0x6164002c}, + {&ch[1].ao.shu[0].actim[4], 0x22650077}, + {&ch[1].ao.shu[0].actim[5], 0x0a000c0b}, + {&ch[1].ao.shu[0].actim_xrt, 0x05030609}, + {&ch[1].ao.shu[0].ac_time_05t, 0x000106e1}, + {&ch[1].ao.catraining1, 0x0b000000}, + {&ch[1].ao.shu[0].rk[0].dqsctl, 0x00000004}, + {&ch[1].ao.shu[0].rk[1].dqsctl, 0x00000004}, + {&ch[1].ao.shu[0].odtctrl, 0xc001004f}, + {&ch[1].ao.shu[0].conf[1], 0x34000d0f}, + {&ch[1].ao.shu[0].conf[2], 0x9007640f}, + {&ch[1].ao.shu[0].scintv, 0x4e39eb36}, + {&ch[1].ao.shu[0].ckectrl, 0x33210000}, + {&ch[1].ao.ckectrl, 0x88d02440}, + {&ch[1].ao.shu[0].rankctl, 0x64300003}, + {&ch[1].ao.shu[0].rankctl, 0x64301203}, + {&ch[0].ao.arbctl, 0x00000c80}, + {&ch[0].ao.rstmask, 0x00000000}, + {&ch[0].ao.arbctl, 0x00000c80}, +}; + +struct reg_init_value dramc_mode_reg_init_sequence[] = { + /* dramc power on sequence */ {&ch[0].phy.misc_ctrl1, 0x8100908c}, {&ch[1].phy.misc_ctrl1, 0x8100908c}, {&ch[0].ao.ckectrl, 0x88d02480}, @@ -632,6 +678,8 @@ {&ch[0].ao.ckectrl, 0x88d02440}, {&ch[1].ao.ckectrl, 0x88d02440}, {&ch[0].ao.mrs, 0x00000000}, + + /* CH0 dramc ZQ Calibration */ {&ch[0].ao.dramc_pd_ctrl, 0xc4000107}, {&ch[0].ao.ckectrl, 0x88d02440}, {&ch[0].ao.mrs, 0x00000000}, @@ -641,70 +689,104 @@ {&ch[0].ao.mrs, 0x00000000}, {&ch[0].ao.dramc_pd_ctrl, 0xc4000107}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR13 */ {&ch[0].ao.mrs, 0x00000d18}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR12 */ {&ch[0].ao.mrs, 0x00000c5d}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR1 */ {&ch[0].ao.mrs, 0x00000156}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR2 */ {&ch[0].ao.mrs, 0x0000020b}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR11 */ {&ch[0].ao.mrs, 0x00000b00}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR22 */ {&ch[0].ao.mrs, 0x00001638}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR14 */ {&ch[0].ao.mrs, 0x00000e5d}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR3 */ {&ch[0].ao.mrs, 0x00000330}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR13 */ {&ch[0].ao.mrs, 0x00000d58}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR12 */ {&ch[0].ao.mrs, 0x00000c5d}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR1 */ {&ch[0].ao.mrs, 0x00000156}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR2 */ {&ch[0].ao.mrs, 0x0000022d}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR11 */ {&ch[0].ao.mrs, 0x00000b23}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR22 */ {&ch[0].ao.mrs, 0x00001634}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR14 */ {&ch[0].ao.mrs, 0x00000e10}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR3 */ {&ch[0].ao.mrs, 0x00000330}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* dramc ZQ Calibration */ {&ch[0].ao.mrs, 0x01000330}, {&ch[0].ao.dramc_pd_ctrl, 0xc4000107}, {&ch[0].ao.ckectrl, 0x88d02440}, @@ -715,76 +797,112 @@ {&ch[0].ao.mrs, 0x01000330}, {&ch[0].ao.dramc_pd_ctrl, 0xc4000107}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR13 */ {&ch[0].ao.mrs, 0x01000d18}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR12 */ {&ch[0].ao.mrs, 0x01000c5d}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR1 */ {&ch[0].ao.mrs, 0x01000156}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR2 */ {&ch[0].ao.mrs, 0x0100020b}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR11 */ {&ch[0].ao.mrs, 0x01000b00}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR22 */ {&ch[0].ao.mrs, 0x01001638}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR14 */ {&ch[0].ao.mrs, 0x01000e5d}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR3 */ {&ch[0].ao.mrs, 0x01000330}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR13 */ {&ch[0].ao.mrs, 0x01000d58}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR12 */ {&ch[0].ao.mrs, 0x01000c5d}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR1 */ {&ch[0].ao.mrs, 0x01000156}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR2 */ {&ch[0].ao.mrs, 0x0100022d}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR11 */ {&ch[0].ao.mrs, 0x01000b23}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR22 */ {&ch[0].ao.mrs, 0x01001634}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR14 */ {&ch[0].ao.mrs, 0x01000e10}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR3 */ {&ch[0].ao.mrs, 0x01000330}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR13 */ {&ch[0].ao.mrs, 0x00000330}, {&ch[0].ao.ckectrl, 0x88d02440}, {&ch[0].ao.mrs, 0x00000dd8}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR13 */ {&ch[0].ao.mrs, 0x01000dd8}, {&ch[0].ao.ckectrl, 0x88d02440}, {&ch[0].ao.mrs, 0x01000dd8}, @@ -792,9 +910,12 @@ {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, {&ch[0].ao.mrs, 0x01000dd8}, + {&ch[0].ao.shu[0].hwset_mr13, 0x00d8000d}, {&ch[0].ao.shu[0].hwset_vrcg, 0x00d8000d}, {&ch[0].ao.shu[0].hwset_mr2, 0x002d0002}, + + /* CH1 dramc ZQ Calibration */ {&ch[1].ao.mrs, 0x00000000}, {&ch[1].ao.dramc_pd_ctrl, 0xc4000107}, {&ch[1].ao.ckectrl, 0x88d02440}, @@ -961,49 +1082,6 @@ {&ch[1].ao.shu[0].hwset_mr2, 0x002d0002}, {&ch[0].ao.mrs, 0x00000dd8}, {&ch[1].ao.mrs, 0x00000dd8}, - - /* update the ac timing */ - {&ch[0].ao.shu[0].actim[0], 0x06020c07}, - {&ch[0].ao.shu[0].actim[1], 0x10080501}, - {&ch[0].ao.shu[0].actim[2], 0x07070201}, - {&ch[0].ao.shu[0].actim[3], 0x6164002c}, - {&ch[0].ao.shu[0].actim[4], 0x22650077}, - {&ch[0].ao.shu[0].actim[5], 0x0a000c0b}, - {&ch[0].ao.shu[0].actim_xrt, 0x05030609}, - {&ch[0].ao.shu[0].ac_time_05t, 0x000106e1}, - {&ch[0].ao.catraining1, 0x0b000000}, - {&ch[0].ao.shu[0].rk[0].dqsctl, 0x00000004}, - {&ch[0].ao.shu[0].rk[1].dqsctl, 0x00000004}, - {&ch[0].ao.shu[0].odtctrl, 0xc001004f}, - {&ch[0].ao.shu[0].conf[1], 0x34000d0f}, - {&ch[0].ao.shu[0].conf[2], 0x9007640f}, - {&ch[0].ao.shu[0].scintv, 0x4e39eb36}, - {&ch[0].ao.shu[0].ckectrl, 0x33210000}, - {&ch[0].ao.ckectrl, 0x88d02440}, - {&ch[0].ao.shu[0].rankctl, 0x64300003}, - {&ch[0].ao.shu[0].rankctl, 0x64301203}, - {&ch[1].ao.shu[0].actim[0], 0x06020c07}, - {&ch[1].ao.shu[0].actim[1], 0x10080501}, - {&ch[1].ao.shu[0].actim[2], 0x07070201}, - {&ch[1].ao.shu[0].actim[3], 0x6164002c}, - {&ch[1].ao.shu[0].actim[4], 0x22650077}, - {&ch[1].ao.shu[0].actim[5], 0x0a000c0b}, - {&ch[1].ao.shu[0].actim_xrt, 0x05030609}, - {&ch[1].ao.shu[0].ac_time_05t, 0x000106e1}, - {&ch[1].ao.catraining1, 0x0b000000}, - {&ch[1].ao.shu[0].rk[0].dqsctl, 0x00000004}, - {&ch[1].ao.shu[0].rk[1].dqsctl, 0x00000004}, - {&ch[1].ao.shu[0].odtctrl, 0xc001004f}, - {&ch[1].ao.shu[0].conf[1], 0x34000d0f}, - {&ch[1].ao.shu[0].conf[2], 0x9007640f}, - {&ch[1].ao.shu[0].scintv, 0x4e39eb36}, - {&ch[1].ao.shu[0].ckectrl, 0x33210000}, - {&ch[1].ao.ckectrl, 0x88d02440}, - {&ch[1].ao.shu[0].rankctl, 0x64300003}, - {&ch[1].ao.shu[0].rankctl, 0x64301203}, - {&ch[0].ao.arbctl, 0x00000c80}, - {&ch[0].ao.rstmask, 0x00000000}, - {&ch[0].ao.arbctl, 0x00000c80}, }; void dramc_init(void) @@ -1011,4 +1089,10 @@ for (int i = 0; i < ARRAY_SIZE(dramc_init_sequence); i++) write32(dramc_init_sequence[i].addr, dramc_init_sequence[i].value); + + for (int i = 0; i < ARRAY_SIZE(dramc_mode_reg_init_sequence); i++) { + write32(dramc_mode_reg_init_sequence[i].addr, + dramc_mode_reg_init_sequence[i].value); + udelay(2); + } } -- To view, visit https://review.coreboot.org/c/coreboot/+/32284 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51785e90b2014994be5018bfe543245d44626242 Gerrit-Change-Number: 32284 Gerrit-PatchSet: 1 Gerrit-Owner: huayang duan <huayangduan(a)gmail.com> Gerrit-MessageType: newchange

6 15

Change in ...coreboot[master]: mediatek/mt8183: enable DDR low power feature
by huayang duan (Code Review) 21 Jun '19

21 Jun '19

huayang duan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32010 Change subject: mediatek/mt8183: enable DDR low power feature ...................................................................... mediatek/mt8183: enable DDR low power feature BUG=b:80501386 BRANCH=none TEST=Boots correctly and stress test pass on Kukui. Change-Id: Ic48580e7e5db25dc1c29dabf41c4e3816fb946d3 Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com --- M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h M src/soc/mediatek/mt8183/include/soc/dramc_register.h M src/soc/mediatek/mt8183/include/soc/emi.h 6 files changed, 132 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/32010/1 diff --git a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c index 3ca5c22..15771ee 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c @@ -154,9 +154,6 @@ for (size_t r = 0; r < 2; r++) for (size_t b = 0; b < 2; b++) { - /* Track rising and update rising/falling together */ - clrbits_le32(&ch[chn].phy.r[r].b[b].rxdvs[2], - 0x1 << 29); clrsetbits_le32(&ch[chn].phy.r[r].b[b].rxdvs[7], (0x3f << 0) | (0x3f << 8) | (0x7f << 16) | (0x7f << 24), @@ -172,8 +169,6 @@ (0x3 << 18) | (0x3 << 16)); } - clrbits_le32(&ch[chn].phy.ca_cmd[10], (0x7 << 28) | (0x7 << 24)); - /* Rx DLY tracking setting (Static) */ clrsetbits_le32(&ch[chn].phy.b0_rxdvs[0], (0x1 << 29) | (0xf << 4) | (0x1 << 0), @@ -181,6 +176,7 @@ clrsetbits_le32(&ch[chn].phy.b1_rxdvs[0], (0x1 << 29) | (0xf << 4) | (0x1 << 0), (0x1 << 29) | (0x0 << 4) | (0x1 << 0)); + clrbits_le32(&ch[chn].phy.ca_cmd[10], (0x7 << 28) | (0x7 << 24)); for (u8 b = 0; b < 2; b++) { clrsetbits_le32(&ch[chn].phy.b[b].dq[9], @@ -201,10 +197,12 @@ static void dramc_hw_dqs_gating_tracking(u8 chn) { - setbits_le32(&ch[chn].ao.stbcal, (0x3 << 26) | (0x1 << 0)); + clrsetbits_le32(&ch[chn].ao.stbcal, + (0x1 << 21) | (0x3 << 15) | (0x1f << 8) | (0x1 << 4), + (0x3 << 26) | (0x1 << 0)); clrsetbits_le32(&ch[chn].ao.stbcal1, (0xffff << 16) | (0x1 << 8) | (0x1 << 6), - (0x1 << 16) | (0x1 << 8) | (0x0 << 6)); + (0x1 << 16) | (0x1 << 8) | (0x1 << 6)); clrsetbits_le32(&ch[chn].phy.misc_ctrl0, (0x1 << 24) | (0x1f << 11) | (0xf << 0), @@ -262,6 +260,72 @@ dramc_set_broadcast(broadcast_bak); } + +static void DramcDummyReadForTrackingEnable(u8 chn) +{ + setbits_le32(&ch[chn].ao.dummy_rd, 0x3 << 16); + + for (size_t r = 0; r < 2; r++) + for (size_t i = 0; i < 4; i++) + write32(&ch[chn].ao.rk[r].dummy_rd_wdata[i], + 0xaaaa5555); + + clrsetbits_le32(&ch[chn].ao.test2_4, 0x7 << 28, 0x4 << 28); + for (size_t r = 0; r < 2; r++) { + clrsetbits_le32(&ch[chn].ao.rk[r].dummy_rd_adr, + (0x1ffff << 0) | (0x7ff << 17) | (0xf << 28), + (0x7fff << 0) | (0x3f0 << 17)); + setbits_le32(&ch[chn].ao.rk[r].dummy_rd_bk, 0x7 << 0); + } + + clrbits_le32(&ch[chn].ao.dummy_rd, 0x1 << 25 | 0x1 << 20); +} + +static void SetCKE2RankIndependent(u8 chn) +{ + clrsetbits_le32(&ch[chn].ao.rkcfg, (0x1 << 15) | (0x1 << 12), 0x1 << 2); + clrsetbits_le32(&ch[chn].ao.ckectrl, + (0x1 << 1) | (0xf << 8) | (0x7 << 13), + (0x4 << 8) | (0x2 << 13)); + + for (u8 shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++) + setbits_le32(&ch[chn].ao.shu[shu].conf[2], + (0x1 << 29) | (0x1 << 31)); + clrbits_le32(&ch[chn].ao.dramctrl, 0x1 << 9); +} + +static void dramc_pa_improve(u8 chn) +{ + clrbits_le32(&ch[chn].ao.clkar, 0xffff); + clrbits_le32(&ch[chn].ao.srefctrl, 0xf << 12); + clrbits_le32(&ch[chn].ao.zqcs, 0x1 << 19); + clrbits_le32(&ch[chn].ao.pre_tdqsck[0], 0x1 << 17); + clrbits_le32(&ch[chn].ao.zqcs, 0x1 << 19); + clrbits_le32(&ch[chn].ao.pre_tdqsck[0], 0x1 << 17); + + for (u8 shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++) + clrbits_le32(&ch[chn].ao.shu[shu].odtctrl, 0x3 << 2); +} + +static void dramc_set_mr13_vrcg_to_Normal(u8 chn) +{ + for (u8 rank = 0; rank < RANK_MAX; rank++) + dramc_mode_reg_write_by_rank(chn, rank, 13, 0xd0); + + for (u8 shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++) + clrbits_le32(&ch[chn].ao.shu[shu].hwset_vrcg, 0x1 << 19); +} + +static void dramc_enable_dramc_dcm(void) +{ + for (size_t chn = 0; chn < CHANNEL_MAX; chn++) { + clrsetbits_le32(&ch[chn].ao.dramc_pd_ctrl, + (0x7 << 0) | (0x1 << 26) | (0x1 << 30) | (0x1 << 31), + (0x7 << 0) | (0x1 << 30) | (0x1 << 31)); + setbits_le32(&ch[chn].ao.clkar, 0x1 << 31); + } +} + void dramc_runtime_config(void) { clrbits_le32(&ch[0].ao.refctrl0, 0x1 << 29); @@ -270,39 +334,83 @@ transfer_pll_to_spm_control(); setbits_le32(&mtk_spm->spm_power_on_val0, 0x3 << 25); + dramc_show("%s with: broadcast %d\n", __func__, dramc_get_broadcast()); + + + /* RX_TRACKING: ON */ for (u8 chn = 0; chn < CHANNEL_MAX; chn++) dramc_rx_input_delay_tracking(chn); + /* HW_GATING: ON */ dramc_hw_gating_init(); dramc_hw_gating_onoff(CHANNEL_A, true); + dramc_hw_gating_onoff(CHANNEL_B, true); + /* HW_GATING DBG: OFF */ for (size_t chn = 0; chn < CHANNEL_MAX; chn++) clrbits_le32(&ch[chn].ao.stbcal2, (0x3 << 4) | (0x3 << 8) | (0x1 << 28)); + /* DUMMY_READ_FOR_TRACKING: ON */ + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + DramcDummyReadForTrackingEnable(chn); + + /* ZQCS_ENABLE_LP4: ON */ clrbits_le32(&ch[0].ao.spcmdctrl, 0x1 << 30); clrbits_le32(&ch[1].ao.spcmdctrl, 0x1 << 30); + /* LOWPOWER_GOLDEN_SETTINGS(DCM): ON */ dramc_phy_low_power_enable(); dramc_enable_phy_dcm(true); + /* DUMMY_READ_FOR_DQS_GATING_RETRY: OFF */ for (size_t chn = 0; chn < CHANNEL_MAX; chn++) for (size_t shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++) clrbits_le32(&ch[chn].ao.shu[shu].dqsg_retry, (0x1 << 1) | (0x3 << 13)); + /* SPM_CONTROL_AFTERK: ON */ write32(&ch[0].phy.misc_spm_ctrl0, 0xfbffefff); write32(&ch[1].phy.misc_spm_ctrl0, 0xfbffefff); write32(&ch[0].phy.misc_spm_ctrl2, 0xffffffef); write32(&ch[1].phy.misc_spm_ctrl2, 0x7fffffef); + /* IMPEDANCE_TRACKING: ON */ dramc_impedance_tracking_enable(); for (size_t chn = 0; chn < CHANNEL_MAX; chn++) { + /* TEMP_SENSOR: ON */ clrbits_le32(&ch[chn].ao.spcmdctrl, 0x3 << 28); setbits_le32(&ch[chn].ao.hw_mrr_fun, (0x1 << 0) | (0x1 << 11)); - clrbits_le32(&ch[0].ao.refctrl0, 0x1 << 18); - setbits_le32(&ch[chn].phy.dvfs_emi_clk, 0x1 << 24); - setbits_le32(&ch[chn].ao.dvfsdll, 0x1 << 7); + + /* PER_BANK_REFRESH: ON */ + clrbits_le32(&ch[chn].ao.refctrl0, 0x1 << 18); + + /* HW_SAVE_FOR_SR: ON */ + clrbits_le32(&ch[chn].ao.rstmask, (0x1 << 25) | (0x1 << 28)); + setbits_le32(&ch[chn].ao.refctrl1, 0x1 << 0); + clrsetbits_le32(&ch[chn].ao.srefctrl, 0x1 << 20, 0x1 << 22); + + /* SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON */ + SetCKE2RankIndependent(chn); + + /* CLK_FREE_FUN_FOR_DRAMC_PSEL: ON */ + clrbits_le32(&ch[chn].ao.refctrl1, (0x1 << 6) | (0x3 << 2)); + clrbits_le32(&ch[chn].ao.clkar, 0x1 << 19); + + /* PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: ON */ + dramc_pa_improve(chn); + + /* DRAM DRS DISABLE */ + clrsetbits_le32(&ch[chn].ao.drsctrl, + (0x1 << 21) | (0x3f << 12) | (0xf << 8) | (0x1 << 6), + (0x1 << 19) | (0x3 << 12) | (0x8 << 8) | + (0x3 << 4) | (0x1 << 2) | (0x1 << 0)); + setbits_le32(&ch[chn].ao.dummy_rd, 0x3 << 26); + + dramc_set_mr13_vrcg_to_Normal(chn); } + + enable_emi_dcm(); + dramc_enable_dramc_dcm(); } diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c index f3c76a9..11a46bb 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -127,7 +127,7 @@ setbits_le32(&ch[chn].ao.ckectrl, ckectrl_bak); } -static void dramc_mode_reg_write_by_rank(u8 chn, u8 rank, +void dramc_mode_reg_write_by_rank(u8 chn, u8 rank, u8 mr_idx, u8 value) { u32 mrs_back = read32(&ch[chn].ao.mrs) & MRS_MRSRK_MASK; diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c index 757a453..b7d7d7b 100644 --- a/src/soc/mediatek/mt8183/emi.c +++ b/src/soc/mediatek/mt8183/emi.c @@ -292,6 +292,15 @@ emi_init2(params); } +void enable_emi_dcm(void) +{ + clrsetbits_le32(&emi_regs->conm, 0xff << 24, 0x0 << 24); + clrsetbits_le32(&emi_regs->conn, 0xff << 24, 0x0 << 24); + + for (size_t chn = 0; chn < CHANNEL_MAX; chn++) + clrsetbits_le32(&ch[chn].emi.chn_conb, 0xff << 24, 0x0 << 24); +} + static void do_calib(const struct sdram_params *params) { dramc_apply_pre_calibration_config(); diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h index 781443a..7e0f34e 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h @@ -127,4 +127,6 @@ void dramc_calibrate_all_channels(const struct sdram_params *params); void dramc_hw_gating_onoff(u8 chn, bool onoff); void dramc_enable_phy_dcm(bool bEn); +void dramc_mode_reg_write_by_rank(u8 chn, u8 rank, u8 mr_idx, u8 value); + #endif /* _DRAMC_PI_API_MT8183_H */ diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_register.h b/src/soc/mediatek/mt8183/include/soc/dramc_register.h index 2487504..f0720a7 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_register.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_register.h @@ -265,10 +265,7 @@ struct dramc_ao_regs_rk { uint32_t dqsosc; uint32_t rsvd_1[5]; - uint32_t dummy_rd_wdata0; - uint32_t dummy_rd_wdata1; - uint32_t dummy_rd_wdata2; - uint32_t dummy_rd_wdata3; + uint32_t dummy_rd_wdata[4]; uint32_t dummy_rd_adr; uint32_t dummy_rd_bk; uint32_t pre_tdqsck[12]; diff --git a/src/soc/mediatek/mt8183/include/soc/emi.h b/src/soc/mediatek/mt8183/include/soc/emi.h index 81e3d91..2c04a50 100644 --- a/src/soc/mediatek/mt8183/include/soc/emi.h +++ b/src/soc/mediatek/mt8183/include/soc/emi.h @@ -38,6 +38,7 @@ int complex_mem_test(u8 *start, unsigned int len); size_t sdram_size(void); const struct sdram_params *get_sdram_config(void); +void enable_emi_dcm(void); void mt_set_emi(const struct sdram_params *params); void mt_mem_init(const struct sdram_params *params); -- To view, visit https://review.coreboot.org/c/coreboot/+/32010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic48580e7e5db25dc1c29dabf41c4e3816fb946d3 Gerrit-Change-Number: 32010 Gerrit-PatchSet: 1 Gerrit-Owner: huayang duan <huayangduan(a)gmail.com> Gerrit-MessageType: newchange

8 20

Change in ...coreboot[master]: device_tree: Update comment style to C89
by Julius Werner (Code Review) 21 Jun '19

21 Jun '19

Hello Patrick Rudolph, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32875 to review the following change. Change subject: device_tree: Update comment style to C89 ...................................................................... device_tree: Update comment style to C89 This code was copied from depthcharge which uses C99 comment style, but coreboot uses C89 comment style. Update to match coreboot. Change-Id: Ib67bb9ff17b7688826071453ab58894a0835ce10 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M src/include/device_tree.h M src/lib/device_tree.c M src/lib/fit.c 3 files changed, 119 insertions(+), 109 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/32875/1 diff --git a/src/include/device_tree.h b/src/include/device_tree.h index 8d86bc5..56a9361 100644 --- a/src/include/device_tree.h +++ b/src/include/device_tree.h @@ -74,9 +74,9 @@ const char *name; uint32_t phandle; - // List of struct device_tree_property-s. + /* List of struct device_tree_property-s. */ struct list_node properties; - // List of struct device_tree_nodes. + /* List of struct device_tree_nodes. */ struct list_node children; struct list_node list_node; @@ -108,18 +108,18 @@ * which were consumed reading the requested value. */ -// Read the property, if any, at offset offset. +/* Read the property, if any, at offset offset. */ int fdt_next_property(const void *blob, uint32_t offset, struct fdt_property *prop); -// Read the name of the node, if any, at offset offset. +/* Read the name of the node, if any, at offset offset. */ int fdt_node_name(const void *blob, uint32_t offset, const char **name); void fdt_print_node(const void *blob, uint32_t offset); int fdt_skip_node(const void *blob, uint32_t offset); -// Read a flattened device tree into a heirarchical structure which refers to -// the contents of the flattened tree in place. Modifying the flat tree -// invalidates the unflattened one. +/* Read a flattened device tree into a heirarchical structure which refers to + the contents of the flattened tree in place. Modifying the flat tree + invalidates the unflattened one. */ struct device_tree *fdt_unflatten(const void *blob); @@ -128,42 +128,42 @@ * Unflattened device tree functions. */ -// Figure out how big a device tree would be if it were flattened. +/* Figure out how big a device tree would be if it were flattened. */ uint32_t dt_flat_size(const struct device_tree *tree); -// Flatten a device tree into the buffer pointed to by dest. +/* Flatten a device tree into the buffer pointed to by dest. */ void dt_flatten(const struct device_tree *tree, void *dest); void dt_print_node(const struct device_tree_node *node); -// Read #address-cells and #size-cells properties from a node. +/* Read #address-cells and #size-cells properties from a node. */ void dt_read_cell_props(const struct device_tree_node *node, u32 *addrcp, u32 *sizecp); -// Look up or create a node relative to a parent node, through its path -// represented as an array of strings. +/* Look up or create a node relative to a parent node, through its path + represented as an array of strings. */ struct device_tree_node *dt_find_node(struct device_tree_node *parent, const char **path, u32 *addrcp, u32 *sizecp, int create); struct device_tree_node *dt_find_node_by_phandle(struct device_tree_node *root, uint32_t phandle); -// Look up or create a node in the tree, through its path -// represented as a string of '/' separated node names. +/* Look up or create a node in the tree, through its path + represented as a string of '/' separated node names. */ struct device_tree_node *dt_find_node_by_path(struct device_tree *tree, const char *path, u32 *addrcp, u32 *sizecp, int create); -// Look up a node through an alias. +/* Look up a node through an alias. */ struct device_tree_node *dt_find_node_by_alias(struct device_tree *tree, const char *alias); -// Look up a node relative to a parent node, through its compatible string. +/* Look up a node relative to a parent node, through its compatible string. */ struct device_tree_node *dt_find_compat(struct device_tree_node *parent, const char *compatible); -// Look up the next child of a parent node, through its compatible string. It -// uses child pointer as the marker to find next. +/* Look up the next child of a parent node, through its compatible string. It + uses child pointer as the marker to find next. */ struct device_tree_node *dt_find_next_compat_child(struct device_tree_node *parent, struct device_tree_node *child, const char *compat); -// Look up a node relative to a parent node, through its property value. +/* Look up a node relative to a parent node, through its property value. */ struct device_tree_node *dt_find_prop_value(struct device_tree_node *parent, const char *name, void *data, size_t size); -// Write src into *dest as a 'length'-byte big-endian integer. +/* Write src into *dest as a 'length'-byte big-endian integer. */ void dt_write_int(u8 *dest, u64 src, size_t length); -// Delete a property +/* Delete a property */ void dt_delete_prop(struct device_tree_node *node, const char *name); -// Add different kinds of properties to a node, or update existing ones. +/* Add different kinds of properties to a node, or update existing ones. */ void dt_add_bin_prop(struct device_tree_node *node, const char *name, void *data, size_t size); void dt_add_string_prop(struct device_tree_node *node, const char *name, diff --git a/src/lib/device_tree.c b/src/lib/device_tree.c index 05f2ea9..338ac45 100644 --- a/src/lib/device_tree.c +++ b/src/lib/device_tree.c @@ -133,7 +133,7 @@ offset += size; } - printk(BIOS_DEBUG, "\n"); // empty line between props and nodes + printk(BIOS_DEBUG, "\n"); /* empty line between props and nodes */ while ((size = print_flat_node(blob, offset, depth + 1))) offset += size; @@ -277,9 +277,9 @@ uint32_t min_offset = 0; min_offset = MIN(struct_offset, strings_offset); min_offset = MIN(min_offset, reserve_offset); - // Assume everything up to the first non-header component is part of - // the header and needs to be preserved. This will protect us against - // new elements being added in the future. + /* Assume everything up to the first non-header component is part of + the header and needs to be preserved. This will protect us against + new elements being added in the future. */ tree->header_size = min_offset; struct device_tree_reserve_map_entry *entry; @@ -307,25 +307,25 @@ static void dt_flat_prop_size(struct device_tree_property *prop, uint32_t *struct_size, uint32_t *strings_size) { - // Starting token. + /* Starting token. */ *struct_size += sizeof(uint32_t); - // Size. + /* Size. */ *struct_size += sizeof(uint32_t); - // Name offset. + /* Name offset. */ *struct_size += sizeof(uint32_t); - // Property value. + /* Property value. */ *struct_size += ALIGN_UP(prop->prop.size, sizeof(uint32_t)); - // Property name. + /* Property name. */ *strings_size += strlen(prop->prop.name) + 1; } static void dt_flat_node_size(struct device_tree_node *node, uint32_t *struct_size, uint32_t *strings_size) { - // Starting token. + /* Starting token. */ *struct_size += sizeof(uint32_t); - // Node name. + /* Node name. */ *struct_size += ALIGN_UP(strlen(node->name) + 1, sizeof(uint32_t)); struct device_tree_property *prop; @@ -336,7 +336,7 @@ list_for_each(child, node->children, list_node) dt_flat_node_size(child, struct_size, strings_size); - // End token. + /* End token. */ *struct_size += sizeof(uint32_t); } @@ -353,7 +353,7 @@ dt_flat_node_size(tree->root, &struct_size, &strings_size); size += struct_size; - // End token. + /* End token. */ size += sizeof(uint32_t); size += strings_size; @@ -478,7 +478,7 @@ static void print_node(const struct device_tree_node *node, int depth) { print_indent(depth); - if (depth == 0) // root node has no name, print a starting slash + if (depth == 0) /* root node has no name, print a starting slash */ printk(BIOS_DEBUG, "/"); printk(BIOS_DEBUG, "%s {\n", node->name); @@ -486,7 +486,7 @@ list_for_each(prop, node->properties, list_node) print_property(&prop->prop, depth + 1); - printk(BIOS_DEBUG, "\n"); // empty line between props and nodes + printk(BIOS_DEBUG, "\n"); /* empty line between props and nodes */ struct device_tree_node *child; list_for_each(child, node->children, list_node) @@ -546,13 +546,13 @@ { struct device_tree_node *node, *found = NULL; - // Update #address-cells and #size-cells for this level. + /* Update #address-cells and #size-cells for this level. */ dt_read_cell_props(parent, addrcp, sizecp); if (!*path) return parent; - // Find the next node in the path, if it exists. + /* Find the next node in the path, if it exists. */ list_for_each(node, parent->children, list_node) { if (!strcmp(node->name, *path)) { found = node; @@ -560,7 +560,7 @@ } } - // Otherwise create it or return NULL. + /* Otherwise create it or return NULL. */ if (!found) { if (!create) return NULL; @@ -607,8 +607,8 @@ int i; struct device_tree_node *node = NULL; - if (path[0] == '/') { // regular path - if (path[1] == '\0') { // special case: "/" is root node + if (path[0] == '/') { /* regular path */ + if (path[1] == '\0') { /* special case: "/" is root node */ dt_read_cell_props(tree->root, addrcp, sizecp); return tree->root; } @@ -618,7 +618,7 @@ return NULL; parent = tree->root; - } else { // alias + } else { /* alias */ char *alias; alias = duped_str = strdup(path); @@ -639,7 +639,7 @@ } if (!sub_path) { - // it's just the alias, no sub-path + /* it's just the alias, no sub-path */ free(duped_str); return parent; } @@ -754,7 +754,7 @@ struct device_tree_node *dt_find_compat(struct device_tree_node *parent, const char *compat) { - // Check if the parent node itself is compatible. + /* Check if the parent node itself is compatible. */ if (dt_check_compat_match(parent, compat)) return parent; @@ -1089,11 +1089,11 @@ if (!reserved) return NULL; - // Binding doc says this should have the same #{address,size}-cells as - // the root. + /* Binding doc says this should have the same #{address,size}-cells as + the root. */ dt_add_u32_prop(reserved, "#address-cells", addr); dt_add_u32_prop(reserved, "#size-cells", size); - // Binding doc says this should be empty (i.e., 1:1 mapping from root). + /* Binding doc says this should be empty (1:1 mapping from root). */ dt_add_bin_prop(reserved, "ranges", NULL, 0); return reserved; @@ -1139,7 +1139,7 @@ static uint32_t dt_adjust_all_phandles(struct device_tree_node *node, uint32_t base) { - uint32_t new_max = MAX(base, 1); // make sure we don't return 0 + uint32_t new_max = MAX(base, 1); /* make sure we don't return 0 */ struct device_tree_property *prop; struct device_tree_node *child; @@ -1152,7 +1152,7 @@ if (!node->phandle) return 0; new_max = MAX(new_max, node->phandle); - } // no break -- can have more than one phandle prop + } /* no break -- can have more than one phandle prop */ list_for_each(child, node->children, list_node) new_max = MAX(new_max, dt_adjust_all_phandles(child, base)); @@ -1178,11 +1178,13 @@ struct device_tree_node *fixup_child; int i; - // For local fixups the /__local_fixup__ subtree contains the same node - // hierarchy as the main tree we're fixing up. Each property contains - // the fixup offsets for the respective property in the main tree. For - // each property in the fixup node, find the corresponding property in - // the base node and apply fixups to all offsets it specifies. + /* + * For local fixups the /__local_fixup__ subtree contains the same node + * hierarchy as the main tree we're fixing up. Each property contains + * the fixup offsets for the respective property in the main tree. For + * each property in the fixup node, find the corresponding property in + * the base node and apply fixups to all offsets it specifies. + */ list_for_each(fixup_prop, fixup->properties, list_node) { struct device_tree_property *base_prop = NULL; list_for_each(prop, node->properties, list_node) @@ -1191,8 +1193,8 @@ break; } - // We should always find a corresponding base prop for a fixup, - // and fixup props contain a list of 32-bit fixup offsets. + /* We should always find a corresponding base prop for a fixup, + and fixup props contain a list of 32-bit fixup offsets. */ if (!base_prop || fixup_prop->prop.size % sizeof(uint32_t)) return -1; @@ -1202,8 +1204,8 @@ return -1; } - // Now recursively descend both the base tree and the /__local_fixups__ - // subtree in sync to apply all fixups. + /* Now recursively descend both the base tree and the /__local_fixups__ + subtree in sync to apply all fixups. */ list_for_each(fixup_child, fixup->children, list_node) { struct device_tree_node *base_child = NULL; list_for_each(child, node->children, list_node) @@ -1212,7 +1214,7 @@ break; } - // All fixup nodes should have a corresponding base node. + /* All fixup nodes should have a corresponding base node. */ if (!base_child) return -1; @@ -1236,10 +1238,10 @@ const char *base_path) { struct device_tree_property *prop; - char buf[512]; // Should be enough for maximum DT path length? - char node_path[64]; // easily enough for /fragment@XXXX/__overlay__ + char buf[512]; /* Should be enough for maximum DT path length? */ + char node_path[64]; /* easily enough for /fragment@XXXX/__overlay__ */ - if (!symbols) // If the overlay has no /__symbols__ node, we're done! + if (!symbols) /* If the overlay has no /__symbols__ node, we're done! */ return; int len = snprintf(node_path, sizeof(node_path), "/%s/__overlay__", @@ -1273,10 +1275,10 @@ { struct device_tree_property *prop; - // External fixup properties are encoded as "<path>:<prop>:<offset>". + /* External fixup properties are encoded as "<path>:<prop>:<offset>". */ char *entry = fixup->prop.data; while ((void *)entry < fixup->prop.data + fixup->prop.size) { - // okay to destroy fixup property value, won't be needed again + /* okay to destroy fixup property value, won't need it again */ char *node_path = entry; entry = strchr(node_path, ':'); if (!entry) @@ -1301,18 +1303,18 @@ break; } - // Move entry to first char after number, must be a '\0'. + /* Move entry to first char after number, must be a '\0'. */ uint32_t offset = skip_atoi((const char **)&entry); if (!ovl_prop || offset + 4 > ovl_prop->prop.size || entry[0]) return -1; - entry++; // jump over '\0' to potential next fixup + entry++; /* jump over '\0' to potential next fixup */ be32enc(ovl_prop->prop.data + offset, phandle); - // If this is a /fragment@X:target property, update - // references to this fragment in the overlay __symbols__ now. + /* If this is a /fragment@X:target property, update references + to this fragment in the overlay __symbols__ now. */ if (offset == 0 && !strcmp(prop_name, "target") && - !strchr(node_path + 1, '/')) // only toplevel nodes + !strchr(node_path + 1, '/')) /* only toplevel nodes */ dt_fix_symbols(overlay_symbols, ovl_node, base_path); } @@ -1339,27 +1341,29 @@ { struct device_tree_property *fix; - // If we have any external fixups, the base tree must have /__symbols__. + /* If we have any external fixups, base tree must have /__symbols__. */ if (!symbols) return -1; - // Unlike /__local_fixups__, /__fixups__ is not a whole subtree that - // mirrors the node hierarchy. It's just a directory of fixup properties - // that each directly contain all information necessary to apply them. + /* + * Unlike /__local_fixups__, /__fixups__ is not a whole subtree that + * mirrors the node hierarchy. It's just a directory of fixup properties + * that each directly contain all information necessary to apply them. + */ list_for_each(fix, fixups->properties, list_node) { - // The name of a fixup property is the label of the node we want - // a property to phandle-reference. Look it up in /__symbols__. + /* The name of a fixup property is the label of the node we want + a property to phandle-reference. Look up in /__symbols__. */ const char *path = dt_find_string_prop(symbols, fix->prop.name); if (!path) return -1; - // Find the node the label pointed to to figure out its phandle. + /* Find node the label pointed to to figure out its phandle. */ struct device_tree_node *node = dt_find_node_by_path(tree, path, NULL, NULL, 0); if (!node) return -1; - // Write it into the overlay property(s) pointing to that node. + /* Write into the overlay property(s) pointing to that node. */ if (dt_fixup_external(overlay, fix, node->phandle, path, overlay_symbols) < 0) return -1; @@ -1446,23 +1450,23 @@ struct device_tree_node *fragment, struct device_tree_node *overlay_symbols) { - // The actually overlaid nodes/props are in an __overlay__ child node. + /* The actual overlaid nodes/props are in an __overlay__ child node. */ static const char *overlay_path[] = { "__overlay__", NULL }; struct device_tree_node *overlay = dt_find_node(fragment, overlay_path, NULL, NULL, 0); - // If it doesn't have an __overlay__ child, it's not a fragment. + /* If it doesn't have an __overlay__ child, it's not a fragment. */ if (!overlay) return 0; - // The target node of the fragment can be given by path or by phandle. + /* Target node of the fragment can be given by path or by phandle. */ struct device_tree_property *prop; struct device_tree_property *phandle = NULL; struct device_tree_property *path = NULL; list_for_each(prop, fragment->properties, list_node) { if (!strcmp(prop->prop.name, "target")) { phandle = prop; - break; // phandle target has priority, stop looking here + break; /* phandle target has priority, stop looking */ } if (!strcmp(prop->prop.name, "target-path")) path = prop; @@ -1474,7 +1478,7 @@ return -1; target = dt_find_node_by_phandle(tree->root, be32dec(phandle->prop.data)); - // Symbols already updated as part of dt_fixup_external(target). + /* Symbols already updated as part of dt_fixup_external(). */ } else if (path) { target = dt_find_node_by_path(tree, path->prop.data, NULL, NULL, 0); @@ -1499,10 +1503,12 @@ */ int dt_apply_overlay(struct device_tree *tree, struct device_tree *overlay) { - // First, we need to make sure phandles inside the overlay don't clash - // with those in the base tree. We just define the highest phandle value - // in the base tree as the "phandle offset" for this overlay and - // increment all phandles in it by that value. + /* + * First, we need to make sure phandles inside the overlay don't clash + * with those in the base tree. We just define the highest phandle value + * in the base tree as the "phandle offset" for this overlay and + * increment all phandles in it by that value. + */ uint32_t phandle_base = tree->max_phandle; uint32_t new_max = dt_adjust_all_phandles(overlay->root, phandle_base); if (!new_max) { @@ -1511,8 +1517,8 @@ } tree->max_phandle = new_max; - // Now that we changed phandles in the overlay, we need to update any - // nodes referring to them. Those are listed in /__local_fixups__. + /* Now that we changed phandles in the overlay, we need to update any + nodes referring to them. Those are listed in /__local_fixups__. */ struct device_tree_node *local_fixups = dt_find_node_by_path(overlay, "/__local_fixups__", NULL, NULL, 0); if (local_fixups && dt_fixup_locals(overlay->root, local_fixups, @@ -1521,16 +1527,18 @@ return -1; } - // Besides local phandle references (from nodes within the overlay to - // other nodes within the overlay), the overlay may also contain phandle - // references to the base tree. These are stored with invalid values and - // must be updated now. /__symbols__ contains a list of all labels in - // the base tree, and /__fixups__ describes all nodes in the overlay - // that contain external phandle references. - // We also take this opportunity to update all /fragment@X/__overlay__/ - // prefixes in the overlay's /__symbols__ node to the correct path that - // the fragment will be placed in later, since this is the only step - // where we have all necessary information for that easily available. + /* + * Besides local phandle references (from nodes within the overlay to + * other nodes within the overlay), the overlay may also contain phandle + * references to the base tree. These are stored with invalid values and + * must be updated now. /__symbols__ contains a list of all labels in + * the base tree, and /__fixups__ describes all nodes in the overlay + * that contain external phandle references. + * We also take this opportunity to update all /fragment@X/__overlay__/ + * prefixes in the overlay's /__symbols__ node to the correct path that + * the fragment will be placed in later, since this is the only step + * where we have all necessary information for that easily available. + */ struct device_tree_node *symbols = dt_find_node_by_path(tree, "/__symbols__", NULL, NULL, 0); struct device_tree_node *fixups = dt_find_node_by_path(overlay, @@ -1544,8 +1552,8 @@ return -1; } - // After all this fixing up, we can finally merge the overlay into the - // tree (one fragment at a time, because for some reason it's split up). + /* After all this fixing up, we can finally merge overlay into the tree + (one fragment at a time, because for some reason it's split up). */ struct device_tree_node *fragment; list_for_each(fragment, overlay->root->children, list_node) if (dt_import_fragment(tree, fragment, overlay_symbols) < 0) { @@ -1554,11 +1562,13 @@ return -1; } - // We need to also update /__symbols__ to include labels from this - // overlay, in case we want to load further overlays with external - // phandle references to it. If the base tree already has a /__symbols__ - // we merge them together, otherwise we just insert the overlay's - // /__symbols__ node into the base tree root. + /* + * We need to also update /__symbols__ to include labels from this + * overlay, in case we want to load further overlays with external + * phandle references to it. If the base tree already has a /__symbols__ + * we merge them together, otherwise we just insert the overlay's + * /__symbols__ node into the base tree root. + */ if (overlay_symbols) { if (symbols) dt_copy_subtree(symbols, overlay_symbols, 0); diff --git a/src/lib/fit.c b/src/lib/fit.c index 0d3cb2d..be243d7 100644 --- a/src/lib/fit.c +++ b/src/lib/fit.c @@ -419,8 +419,8 @@ */ static int fit_update_compat(struct fit_config_node *config) { - // If there was no "compatible" property in config node, this is a - // legacy FIT image. Must extract compat prop from FDT itself. + /* If there was no "compatible" property in config node, this is a + legacy FIT image. Must extract compat prop from FDT itself. */ if (!config->compat.name) { void *fdt_blob = config->fdt->data; const struct fdt_header *fdt_header = fdt_blob; @@ -434,7 +434,7 @@ return -1; } - // FDT overlays are not supported in legacy FIT images. + /* FDT overlays are not supported in legacy FIT images. */ if (config->overlays.next) { printk(BIOS_ERR, "ERROR: config %s has overlay but no compat!\n", -- To view, visit https://review.coreboot.org/c/coreboot/+/32875 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib67bb9ff17b7688826071453ab58894a0835ce10 Gerrit-Change-Number: 32875 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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coreboot-gerrit May 2019