coreboot-gerrit May 2019

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Change in ...coreboot[master]: soc/apl: Add HdAudioDspUaaCompliance to devicetree
by Felix Singer (Code Review) 01 Jul '19

01 Jul '19

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32047 Change subject: soc/apl: Add HdAudioDspUaaCompliance to devicetree ...................................................................... soc/apl: Add HdAudioDspUaaCompliance to devicetree Change-Id: I1522ae81cba5fc08605f4eb349b2977facd3f669 Signed-off-by: Felix Singer <felix.singer(a)9elements.com> --- M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/chip.h 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/32047/1 diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 30a537b..5f83906 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -741,6 +741,8 @@ /* Disable FSP from locking access to the RTC NVRAM */ silconfig->RtcLock = 0; + silconfig->HdAudioDspUaaCompliance = cfg->hdaudio_dsp_uaa_compliance; + /* Enable Audio clk gate and power gate */ silconfig->HDAudioClkGate = cfg->hdaudio_clk_gate_enable; silconfig->HDAudioPwrGate = cfg->hdaudio_pwr_gate_enable; diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index b9e368c..e3bcfe5 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -127,6 +127,8 @@ uint8_t hdaudio_pwr_gate_enable; uint8_t hdaudio_bios_config_lockdown; + uint8_t hdaudio_dsp_uaa_compliance; + /* SLP S3 minimum assertion width. */ int slp_s3_assertion_width_usecs; -- To view, visit https://review.coreboot.org/c/coreboot/+/32047 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1522ae81cba5fc08605f4eb349b2977facd3f669 Gerrit-Change-Number: 32047 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/apl: Add C-States configuration options
by Felix Singer (Code Review) 01 Jul '19

01 Jul '19

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32050 Change subject: soc/apl: Add C-States configuration options ...................................................................... soc/apl: Add C-States configuration options FSP-S options: - C1e - PkgCStateLimit - CStateAutoDemotion - CStateUnDemotion - PkgCStateDemotion - PkgCStateUnDemotion Change-Id: I2ac16aa896fc851378cc049aaf385573e3a69320 Signed-off-by: Felix Singer <felix.singer(a)9elements.com> --- M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/chip.h 2 files changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/32050/1 diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 30a537b..15f2ba8 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -741,6 +741,13 @@ /* Disable FSP from locking access to the RTC NVRAM */ silconfig->RtcLock = 0; + silconfig->C1e = cfg->c1e; + silconfig->PkgCStateLimit = cfg->pkg_cstate_limit; + silconfig->CStateAutoDemotion = cfg->cstate_auto_demotion; + silconfig->CStateUnDemotion = cfg->cstate_undemotion; + silconfig->PkgCStateDemotion = cfg->pkg_cstate_demotion; + silconfig->PkgCStateUnDemotion = cfg->pkg_cstate_undemotion; + /* Enable Audio clk gate and power gate */ silconfig->HDAudioClkGate = cfg->hdaudio_clk_gate_enable; silconfig->HDAudioPwrGate = cfg->hdaudio_pwr_gate_enable; diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index b9e368c..6015acf 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -120,6 +120,13 @@ /* PL2 override value in mW for APL */ uint16_t tdp_pl2_override_mw; + uint8_t c1e; + uint8_t pkg_cstate_limit; + uint8_t cstate_auto_demotion; + uint8_t cstate_undemotion; + uint8_t pkg_cstate_demotion; + uint8_t pkg_cstate_undemotion; + /* Configure Audio clk gate and power gate * IOSF-SB port ID 92 offset 0x530 [5] and [3] */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32050 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ac16aa896fc851378cc049aaf385573e3a69320 Gerrit-Change-Number: 32050 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: G505S AtomBIOS ROMs: known good binaries with a script to check their...
by mikeb mikeb (Code Review) 29 Jun '19

29 Jun '19

Hello Mike Banon, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31944 to review the following change. Change subject: G505S AtomBIOS ROMs: known good binaries with a script to check their SHA256 ...................................................................... G505S AtomBIOS ROMs: known good binaries with a script to check their SHA256 This change is a mirror for the known good AMD Lenovo G505S AtomBIOS ROMs from this repository - https://github.com/g505s-opensource-researcher/g505s-atombios AtomBIOS ROMs are required to enable the integrated and discrete VGA adapters, however to add the discrete GPU support you will also need to apply these patches: https://review.coreboot.org/c/coreboot/+/31929 G505S dGPU support: scripts for applying the unofficial (not-merged-yet) patches Here are the SHA256 checksums for these AtomBIOS ROMs: 6104e6989ea3f494d7bfa30573bf38e830f1068bab9980caec5e890e0ccbfced ./pci1002,990b.rom - for integrated GPU (iGPU) HD-8650G 6052b5def3fda2a93f6c4d55ec91b819429e212e26cdb8e0fcca54599c9c92ed ./pci1002,6663.rom - for discrete GPU (dGPU) HD-8570M 15d74515332bc512de66e0dc910d8600aeb134bf715bbc34a4faac0257f4a0dc ./pci1002,6665.rom - for discrete GPU (dGPU) R5-M230 Save to ./coreboot/ then run ./extract_atombios_roms.sh and ./check... . Could analyze these ROMs with AtomDis - https://cgit.freedesktop.org/~mhopf/AtomDis/ pci1002,990b.rom (for iGPU HD-8650G) has been taken from G505S with R5-M230, and despite the tiny voltage difference - it's working great for all G505S versions. https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/ GZNWISLFHUTYN6C7RTWSQUMJIFOUHMED/ Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I0cb38927e3f5ae0f0850ca8bc79be791c51ae503 --- A check_atombios_roms.sh A extract_atombios_roms.sh A pci1002,6663.rom.txt A pci1002,6665.rom.txt A pci1002,990b.rom.txt A sha256sums_atombios_correct.txt 6 files changed, 8,082 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/31944/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/31944 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0cb38927e3f5ae0f0850ca8bc79be791c51ae503 Gerrit-Change-Number: 31944 Gerrit-PatchSet: 1 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: G505S dGPU support: scripts for applying the unofficial (not-merged-y...
by mikeb mikeb (Code Review) 29 Jun '19

29 Jun '19

Hello Mike Banon, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31929 to review the following change. Change subject: G505S dGPU support: scripts for applying the unofficial (not-merged-yet) updates ...................................................................... G505S dGPU support: scripts for applying the unofficial (not-merged-yet) updates These scripts will help you to securely and conveniently apply the three changes 31357, 31448, 31450 to add the discrete GPU support for AMD Lenovo G505S laptop. Save to ./coreboot/ then run ./get_dgpu_patches.sh , ./check... and ./apply... https://review.coreboot.org/c/coreboot/+/31357 src/mainboard/lenovo/g505s: Disable SeaBIOS options not supported by hardware https://review.coreboot.org/c/coreboot/+/31448 src/device/pci: Add support for discrete VGA initialization and OpROM loading https://review.coreboot.org/c/coreboot/+/31450 lenovo/g505s: Add the discrete VGA support for AMD Lenovo G505S laptop Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I956f360681762b4321ba5d967f8a27b4a0387a73 --- A apply_dgpu_patches.sh A check_dgpu_patches.sh A get_dgpu_patches.sh A sha256sums_dgpu_correct.txt 4 files changed, 50 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/31929/1 diff --git a/apply_dgpu_patches.sh b/apply_dgpu_patches.sh new file mode 100755 index 0000000..972800a --- /dev/null +++ b/apply_dgpu_patches.sh @@ -0,0 +1,16 @@ +#!/bin/sh +### +### https://review.coreboot.org/c/coreboot/+/31357 +### src/mainboard/lenovo/g505s: Disable SeaBIOS options not supported by hardware +### +patch -p1 < f5c1e4d.diff +### +### https://review.coreboot.org/c/coreboot/+/31448 +### src/device/pci: Add support for discrete VGA initialization and OpROM loading +### +patch -p1 < 828c74a.diff +### +### https://review.coreboot.org/c/coreboot/+/31450 +### lenovo/g505s: Add the discrete VGA support for AMD Lenovo G505S laptop +### +patch -p1 < 54dd729.diff diff --git a/check_dgpu_patches.sh b/check_dgpu_patches.sh new file mode 100755 index 0000000..cae1e9f --- /dev/null +++ b/check_dgpu_patches.sh @@ -0,0 +1,11 @@ +#!/bin/sh +rm -f ./sha256sums_dgpu_my.txt +sha256sum ./f5c1e4d.diff > ./sha256sums_dgpu_my.txt +sha256sum ./828c74a.diff >> ./sha256sums_dgpu_my.txt +sha256sum ./54dd729.diff >> ./sha256sums_dgpu_my.txt +if cmp -s "./sha256sums_dgpu_my.txt" "./sha256sums_dgpu_correct.txt" +then + echo "SHA256 checksums are correct, please run ./apply_dgpu_patches.sh" +else + echo "! MISMATCH ! See ./sha256sums_dgpu_my.txt and ./sha256sums_dgpu_correct.txt" +fi diff --git a/get_dgpu_patches.sh b/get_dgpu_patches.sh new file mode 100755 index 0000000..c1703df --- /dev/null +++ b/get_dgpu_patches.sh @@ -0,0 +1,20 @@ +#!/bin/sh +rm -f ./*.diff && rm -f ./patch\?zip +### +### https://review.coreboot.org/c/coreboot/+/31357 +### src/mainboard/lenovo/g505s: Disable SeaBIOS options not supported by hardware +### +wget https://review.coreboot.org/changes/31357/revisions/6/patch?zip +unzip ./patch\?zip && rm -f ./patch\?zip # && patch -p1 < f5c1e4d.diff +### +### https://review.coreboot.org/c/coreboot/+/31448 +### src/device/pci: Add support for discrete VGA initialization and OpROM loading +### +wget https://review.coreboot.org/changes/31448/revisions/8/patch?zip +unzip ./patch\?zip && rm -f ./patch\?zip # && patch -p1 < 828c74a.diff +### +### https://review.coreboot.org/c/coreboot/+/31450 +### lenovo/g505s: Add the discrete VGA support for AMD Lenovo G505S laptop +### +wget https://review.coreboot.org/changes/31450/revisions/8/patch?zip +unzip ./patch\?zip && rm -f ./patch\?zip # && patch -p1 < 54dd729.diff diff --git a/sha256sums_dgpu_correct.txt b/sha256sums_dgpu_correct.txt new file mode 100644 index 0000000..b519a6a --- /dev/null +++ b/sha256sums_dgpu_correct.txt @@ -0,0 +1,3 @@ +1e6dff37ae1b8080c431f25b7a12c561bd949dfa68f6487a1bece39941f74195 ./f5c1e4d.diff +1879c633478c105eb9d66afa97fc59db0c850a813d4bcdb3693a6f52645092d8 ./828c74a.diff +a055e0d1fff668b95da68b7b6c7274d000bbf90572747b4f33de7f5f59a5bb44 ./54dd729.diff -- To view, visit https://review.coreboot.org/c/coreboot/+/31929 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I956f360681762b4321ba5d967f8a27b4a0387a73 Gerrit-Change-Number: 31929 Gerrit-PatchSet: 1 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/mainboard/lenovo/g505s: Disable SeaBIOS options not supported by ...
by mikeb mikeb (Code Review) 29 Jun '19

29 Jun '19

Hello Mike Banon, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31357 to review the following change. Change subject: src/mainboard/lenovo/g505s: Disable SeaBIOS options not supported by hardware ...................................................................... src/mainboard/lenovo/g505s: Disable SeaBIOS options not supported by hardware G505S does not have any SAS or NVMe controllers and could not have a TPM, so it makes sense to disable the related SeaBIOS options for this laptop. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I5b2ee6403d7d2298725729d8d833e37627a4f202 --- M src/mainboard/lenovo/g505s/Kconfig A src/mainboard/lenovo/g505s/config_seabios 2 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/31357/1 diff --git a/src/mainboard/lenovo/g505s/Kconfig b/src/mainboard/lenovo/g505s/Kconfig index 883ef27..71ab909 100644 --- a/src/mainboard/lenovo/g505s/Kconfig +++ b/src/mainboard/lenovo/g505s/Kconfig @@ -55,4 +55,8 @@ string default "1002,990b" +config PAYLOAD_CONFIGFILE + string + default "$(top)/src/mainboard/$(MAINBOARDDIR)/config_seabios" if PAYLOAD_SEABIOS + endif # BOARD_LENOVO_G505S diff --git a/src/mainboard/lenovo/g505s/config_seabios b/src/mainboard/lenovo/g505s/config_seabios new file mode 100644 index 0000000..8d3957b --- /dev/null +++ b/src/mainboard/lenovo/g505s/config_seabios @@ -0,0 +1,6 @@ +# +# SeaBIOS custom configuration for Lenovo G505S +# +# CONFIG_MEGASAS is not set +# CONFIG_NVME is not set +# CONFIG_TCGBIOS is not set -- To view, visit https://review.coreboot.org/c/coreboot/+/31357 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b2ee6403d7d2298725729d8d833e37627a4f202 Gerrit-Change-Number: 31357 Gerrit-PatchSet: 1 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: MAINTAINERS: Add myself as a maintainer for apple boards
by Evgeny Zinoviev (Code Review) 28 Jun '19

28 Jun '19

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33148 Change subject: MAINTAINERS: Add myself as a maintainer for apple boards ...................................................................... MAINTAINERS: Add myself as a maintainer for apple boards Change-Id: I33bf45c81cc4be157ea71806900a545ee68ecee8 Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- M MAINTAINERS 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/33148/1 diff --git a/MAINTAINERS b/MAINTAINERS index 04f784f..9905540 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -164,6 +164,11 @@ S: Maintained F: src/mainboard/lenovo/ +APPLE MAINBOARDS +M: Evgeny Zinoviev <me(a)ch1p.io> +S: Maintained +F: src/mainboard/apple/ + GETAC P470 MAINBOARD M: Patrick Georgi <patrick(a)georgi.software> S: Maintained -- To view, visit https://review.coreboot.org/c/coreboot/+/33148 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33bf45c81cc4be157ea71806900a545ee68ecee8 Gerrit-Change-Number: 33148 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: intel/945 boards: Use smp_write_pci_intsrc()
by Kyösti Mälkki (Code Review) 25 Jun '19

25 Jun '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30740 Change subject: intel/945 boards: Use smp_write_pci_intsrc() ...................................................................... intel/945 boards: Use smp_write_pci_intsrc() Radically reduces line lengths and splits '(bus<<2) | INT' to separate parameters. Change-Id: I0cfd714da3d2773affdb34d1dab2ac32879e2cfd Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/apple/macbook21/mptable.c M src/mainboard/lenovo/t60/mptable.c M src/mainboard/lenovo/x60/mptable.c M src/mainboard/lenovo/z61t/mptable.c 4 files changed, 62 insertions(+), 62 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/30740/1 diff --git a/src/mainboard/apple/macbook21/mptable.c b/src/mainboard/apple/macbook21/mptable.c index f508eaf..b11b7bb 100644 --- a/src/mainboard/apple/macbook21/mptable.c +++ b/src/mainboard/apple/macbook21/mptable.c @@ -42,21 +42,21 @@ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, isa_bus, 0x00, MP_APIC_ALL, 0x00); smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x00, MP_APIC_ALL, 0x01); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x01 << 2), 0x02, 0x10); /* PCIe root 0.02.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x02 << 2), 0x02, 0x10); /* VGA 0.02.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1b << 2), 0x02, 0x16); /* HD Audio 0:1b.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2), 0x02, 0x11); /* PCIe 0:1c.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x01, 0x02, 0x10); /* PCIe 0:1c.1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x02, 0x02, 0x12); /* PCIe 0:1c.2 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x03, 0x02, 0x13); /* PCIe 0:1c.3 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) , 0x02, 0x15); /* USB 0:1d.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x01, 0x02, 0x13); /* USB 0:1d.1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x02, 0x02, 0x12); /* USB 0:1d.2 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x03, 0x02, 0x10); /* USB 0:1d.3 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) , 0x02, 0x12); /* LPC 0:1f.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) | 0x01, 0x02, 0x13); /* IDE 0:1f.1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) | 0x03, 0x02, 0x10); /* SATA 0:1f.3 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x03, (0x03 << 2) , 0x02, 0x13); /* Firewire 3:03.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x01, 0x00, 0x02, 0x10); /* PCIe root 0.01.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x02, 0x00, 0x02, 0x10); /* VGA 0.02.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1b, 0x00, 0x02, 0x16); /* HD Audio 0:1b.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x00, 0x02, 0x11); /* PCIe 0:1c.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x01, 0x02, 0x10); /* PCIe 0:1c.1 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x02, 0x02, 0x12); /* PCIe 0:1c.2 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x03, 0x02, 0x13); /* PCIe 0:1c.3 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x00, 0x02, 0x15); /* USB 0:1d.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x01, 0x02, 0x13); /* USB 0:1d.1 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x02, 0x02, 0x12); /* USB 0:1d.2 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x03, 0x02, 0x10); /* USB 0:1d.3 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1f, 0x00, 0x02, 0x12); /* LPC 0:1f.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1f, 0x01, 0x02, 0x13); /* IDE 0:1f.1 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1f, 0x03, 0x02, 0x10); /* SATA 0:1f.3 */ + smp_write_pci_intsrc(mc, mp_INT, 0x03, 0x03, 0x00, 0x02, 0x13); /* Firewire 3:03.0 */ mptable_lintsrc(mc, isa_bus); return mptable_finalize(mc); diff --git a/src/mainboard/lenovo/t60/mptable.c b/src/mainboard/lenovo/t60/mptable.c index 8a9ee48..86c6f6d 100644 --- a/src/mainboard/lenovo/t60/mptable.c +++ b/src/mainboard/lenovo/t60/mptable.c @@ -42,21 +42,21 @@ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, isa_bus, 0x00, MP_APIC_ALL, 0x00); smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x00, MP_APIC_ALL, 0x01); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x01 << 2), 0x02, 0x10); /* PCIe root 0.02.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x02 << 2), 0x02, 0x10); /* VGA 0.02.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1b << 2), 0x02, 0x11); /* HD Audio 0:1b.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2), 0x02, 0x14); /* PCIe 0:1c.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x01, 0x02, 0x15); /* PCIe 0:1c.1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x02, 0x02, 0x16); /* PCIe 0:1c.2 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x03, 0x02, 0x17); /* PCIe 0:1c.3 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) , 0x02, 0x10); /* USB 0:1d.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x01, 0x02, 0x11); /* USB 0:1d.1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x02, 0x02, 0x12); /* USB 0:1d.2 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x03, 0x02, 0x13); /* USB 0:1d.3 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) , 0x02, 0x17); /* LPC 0:1f.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) | 0x01, 0x02, 0x10); /* IDE 0:1f.1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) | 0x02, 0x02, 0x10); /* SATA 0:1f.2 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x06, (0x00 << 2) | 0x00, 0x02, 0x10); /* Cardbus 6:00.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x01, 0x00, 0x02, 0x10); /* PCIe root 0.01.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x02, 0x00, 0x02, 0x10); /* VGA 0.02.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1b, 0x00, 0x02, 0x11); /* HD Audio 0:1b.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x00, 0x02, 0x14); /* PCIe 0:1c.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x01, 0x02, 0x15); /* PCIe 0:1c.1 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x02, 0x02, 0x16); /* PCIe 0:1c.2 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x03, 0x02, 0x17); /* PCIe 0:1c.3 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x00, 0x02, 0x10); /* USB 0:1d.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x01, 0x02, 0x11); /* USB 0:1d.1 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x02, 0x02, 0x12); /* USB 0:1d.2 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x03, 0x02, 0x13); /* USB 0:1d.3 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1f, 0x00, 0x02, 0x17); /* LPC 0:1f.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1f, 0x01, 0x02, 0x10); /* IDE 0:1f.1 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1f, 0x02, 0x02, 0x10); /* SATA 0:1f.2 */ + smp_write_pci_intsrc(mc, mp_INT, 0x06, 0x00, 0x00, 0x02, 0x10); /* Cardbus 6:00.0 */ mptable_lintsrc(mc, isa_bus); return mptable_finalize(mc); diff --git a/src/mainboard/lenovo/x60/mptable.c b/src/mainboard/lenovo/x60/mptable.c index 7b23d5a..091fea7 100644 --- a/src/mainboard/lenovo/x60/mptable.c +++ b/src/mainboard/lenovo/x60/mptable.c @@ -42,23 +42,23 @@ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, isa_bus, 0x00, MP_APIC_ALL, 0x00); smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x00, MP_APIC_ALL, 0x01); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x01 << 2), 0x02, 0x10); /* PCIe root 0.02.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x02 << 2), 0x02, 0x10); /* VGA 0.02.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1b << 2), 0x02, 0x11); /* HD Audio 0:1b.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2), 0x02, 0x14); /* PCIe 0:1c.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x01, 0x02, 0x15); /* PCIe 0:1c.1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x02, 0x02, 0x16); /* PCIe 0:1c.2 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x03, 0x02, 0x17); /* PCIe 0:1c.3 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) , 0x02, 0x10); /* USB 0:1d.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x01, 0x02, 0x11); /* USB 0:1d.1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x02, 0x02, 0x12); /* USB 0:1d.2 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x03, 0x02, 0x13); /* USB 0:1d.3 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) , 0x02, 0x17); /* LPC 0:1f.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) | 0x01, 0x02, 0x10); /* IDE 0:1f.1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) | 0x02, 0x02, 0x10); /* SATA 0:1f.2 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x05, (0x00 << 2) | 0x00, 0x02, 0x10); /* Cardbus 5:00.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x05, (0x00 << 2) | 0x01, 0x02, 0x11); /* Firewire 5:00.1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x05, (0x00 << 2) | 0x02, 0x02, 0x12); /* SDHC 5:00.2 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x01, 0x00, 0x02, 0x10); /* PCIe root 0.01.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x02, 0x00, 0x02, 0x10); /* VGA 0.02.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1b, 0x00, 0x02, 0x11); /* HD Audio 0:1b.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x00, 0x02, 0x14); /* PCIe 0:1c.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x01, 0x02, 0x15); /* PCIe 0:1c.1 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x02, 0x02, 0x16); /* PCIe 0:1c.2 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x03, 0x02, 0x17); /* PCIe 0:1c.3 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x00, 0x02, 0x10); /* USB 0:1d.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x01, 0x02, 0x11); /* USB 0:1d.1 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x02, 0x02, 0x12); /* USB 0:1d.2 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x03, 0x02, 0x13); /* USB 0:1d.3 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1f, 0x00, 0x02, 0x17); /* LPC 0:1f.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1f, 0x01, 0x02, 0x10); /* IDE 0:1f.1 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1f, 0x02, 0x02, 0x10); /* SATA 0:1f.2 */ + smp_write_pci_intsrc(mc, mp_INT, 0x05, 0x00, 0x00, 0x02, 0x10); /* Cardbus 5:00.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x05, 0x00, 0x01, 0x02, 0x11); /* Firewire 5:00.1 */ + smp_write_pci_intsrc(mc, mp_INT, 0x05, 0x00, 0x02, 0x02, 0x12); /* SDHC 5:00.2 */ mptable_lintsrc(mc, isa_bus); return mptable_finalize(mc); diff --git a/src/mainboard/lenovo/z61t/mptable.c b/src/mainboard/lenovo/z61t/mptable.c index 8a9ee48..86c6f6d 100644 --- a/src/mainboard/lenovo/z61t/mptable.c +++ b/src/mainboard/lenovo/z61t/mptable.c @@ -42,21 +42,21 @@ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, isa_bus, 0x00, MP_APIC_ALL, 0x00); smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x00, MP_APIC_ALL, 0x01); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x01 << 2), 0x02, 0x10); /* PCIe root 0.02.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x02 << 2), 0x02, 0x10); /* VGA 0.02.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1b << 2), 0x02, 0x11); /* HD Audio 0:1b.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2), 0x02, 0x14); /* PCIe 0:1c.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x01, 0x02, 0x15); /* PCIe 0:1c.1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x02, 0x02, 0x16); /* PCIe 0:1c.2 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x03, 0x02, 0x17); /* PCIe 0:1c.3 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) , 0x02, 0x10); /* USB 0:1d.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x01, 0x02, 0x11); /* USB 0:1d.1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x02, 0x02, 0x12); /* USB 0:1d.2 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x03, 0x02, 0x13); /* USB 0:1d.3 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) , 0x02, 0x17); /* LPC 0:1f.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) | 0x01, 0x02, 0x10); /* IDE 0:1f.1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) | 0x02, 0x02, 0x10); /* SATA 0:1f.2 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x06, (0x00 << 2) | 0x00, 0x02, 0x10); /* Cardbus 6:00.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x01, 0x00, 0x02, 0x10); /* PCIe root 0.01.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x02, 0x00, 0x02, 0x10); /* VGA 0.02.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1b, 0x00, 0x02, 0x11); /* HD Audio 0:1b.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x00, 0x02, 0x14); /* PCIe 0:1c.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x01, 0x02, 0x15); /* PCIe 0:1c.1 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x02, 0x02, 0x16); /* PCIe 0:1c.2 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x03, 0x02, 0x17); /* PCIe 0:1c.3 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x00, 0x02, 0x10); /* USB 0:1d.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x01, 0x02, 0x11); /* USB 0:1d.1 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x02, 0x02, 0x12); /* USB 0:1d.2 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x03, 0x02, 0x13); /* USB 0:1d.3 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1f, 0x00, 0x02, 0x17); /* LPC 0:1f.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1f, 0x01, 0x02, 0x10); /* IDE 0:1f.1 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1f, 0x02, 0x02, 0x10); /* SATA 0:1f.2 */ + smp_write_pci_intsrc(mc, mp_INT, 0x06, 0x00, 0x00, 0x02, 0x10); /* Cardbus 6:00.0 */ mptable_lintsrc(mc, isa_bus); return mptable_finalize(mc); -- To view, visit https://review.coreboot.org/c/coreboot/+/30740 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0cfd714da3d2773affdb34d1dab2ac32879e2cfd Gerrit-Change-Number: 30740 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 5

Change in ...coreboot[master]: security/vboot: Add VBNV flags to save the Cr50 recovery switch state
by Keith Short (Code Review) 24 Jun '19

24 Jun '19

Keith Short has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31800 Change subject: security/vboot: Add VBNV flags to save the Cr50 recovery switch state ...................................................................... security/vboot: Add VBNV flags to save the Cr50 recovery switch state Add flags to save the Cr50 recovery switch state. This ensures that the Cr50 recovery switch state is only read during verstage. BUG=b:123360379 BRANCH=none TEST=build coreboot on sarien and arcada. Test normal boot and recovery boot on arcada - confirm that that tpm transaction errors are gone. Change-Id: Id30a7b203e5aac8631971eb102986427b8362a71 Signed-off-by: Keith Short <keithshort(a)chromium.org> --- M src/mainboard/google/sarien/chromeos.c M src/security/vboot/vbnv.c M src/security/vboot/vbnv.h M src/security/vboot/vbnv_layout.h 4 files changed, 71 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/31800/1 diff --git a/src/mainboard/google/sarien/chromeos.c b/src/mainboard/google/sarien/chromeos.c index 1e363fd..308b682 100644 --- a/src/mainboard/google/sarien/chromeos.c +++ b/src/mainboard/google/sarien/chromeos.c @@ -20,18 +20,12 @@ #include <variant/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> #include <security/tpm/tss.h> +#include <security/vboot/vbnv.h> #include <device/device.h> #include <intelblocks/pmclib.h> #include <soc/pmc.h> #include <soc/pci_devs.h> -enum rec_mode_state { - REC_MODE_UNINITIALIZED, - REC_MODE_NOT_REQUESTED, - REC_MODE_REQUESTED, -}; -static enum rec_mode_state saved_rec_mode; - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -84,30 +78,33 @@ int get_recovery_mode_switch(void) { - enum rec_mode_state state = saved_rec_mode; + int rec_switch; uint8_t recovery_button_state = 0; - /* Check the global variable first. */ - if (state == REC_MODE_NOT_REQUESTED) - return 0; - else if (state == REC_MODE_REQUESTED) - return 1; + /* + * Only verstage performs a real check of the Cr50 recovery switch. + * The recovery switch state is cleared on the first access by the AP + * so there's no point in querying the Cr50 at later stages. All other + * stages use the state saved in VBNV. + */ + if (!ENV_VERSTAGE && + !get_recovery_switch_from_vbnv(&rec_switch)) + return rec_switch; - state = REC_MODE_NOT_REQUESTED; + rec_switch = 0; /* Read state from the GPIO controlled by servo. */ if (cros_get_gpio_value(CROS_GPIO_REC)) - state = REC_MODE_REQUESTED; + rec_switch = 1; /* Read one-time recovery request from cr50. */ else if (tlcl_cr50_get_recovery_button(&recovery_button_state) == TPM_SUCCESS) - state = recovery_button_state ? - REC_MODE_REQUESTED : REC_MODE_NOT_REQUESTED; + rec_switch = !!recovery_button_state; /* Store the state in case this is called again in verstage. */ - saved_rec_mode = state; + set_recovery_switch_into_vbnv(rec_switch); - return state == REC_MODE_REQUESTED; + return rec_switch; } int get_lid_switch(void) diff --git a/src/security/vboot/vbnv.c b/src/security/vboot/vbnv.c index 636e5e3..8156fc5 100644 --- a/src/security/vboot/vbnv.c +++ b/src/security/vboot/vbnv.c @@ -140,6 +140,42 @@ return vbnv_data(RECOVERY_OFFSET); } +/* Save the recovery switch state into VBNV. */ +void set_recovery_switch_into_vbnv(int recovery_switch) +{ + uint8_t vbnv_copy[VBOOT_VBNV_BLOCK_SIZE]; + + read_vbnv(vbnv_copy); + + vbnv_copy[MISC_FLAGS_OFFSET] |= MISC_FLAGS_RECOVERY_SWITCH_VALID_MASK; + if (recovery_switch) + vbnv_copy[MISC_FLAGS_OFFSET] |= + MISC_FLAGS_RECOVERY_SWITCH_STATE_MASK; + else + vbnv_copy[MISC_FLAGS_OFFSET] &= + ~MISC_FLAGS_RECOVERY_SWITCH_STATE_MASK; + + vbnv_copy[CRC_OFFSET] = crc8_vbnv(vbnv_copy, CRC_OFFSET); + + save_vbnv(vbnv_copy); +} + +/* Read the recovery switch state from VBNV. */ +int get_recovery_switch_from_vbnv(int *recovery_switch) +{ + uint8_t misc_flags; + vbnv_setup(); + misc_flags = vbnv_data(MISC_FLAGS_OFFSET); + + if (!(misc_flags & MISC_FLAGS_RECOVERY_SWITCH_VALID_MASK)) + return -1; + + *recovery_switch = + !!(misc_flags & MISC_FLAGS_RECOVERY_SWITCH_STATE_MASK); + + return 0; +} + /* Read the BOOT_OPROM_NEEDED flag from VBNV. */ int vboot_wants_oprom(void) { diff --git a/src/security/vboot/vbnv.h b/src/security/vboot/vbnv.h index c8e689f..367a376 100644 --- a/src/security/vboot/vbnv.h +++ b/src/security/vboot/vbnv.h @@ -25,6 +25,22 @@ void regen_vbnv_crc(uint8_t *vbnv_copy); int get_recovery_mode_from_vbnv(void); void set_recovery_mode_into_vbnv(int recovery_reason); + +/** + * Save the recovery switch state into VBNV + * + * @param recovery_switch Current state of the recovery switch. + */ +void set_recovery_switch_into_vbnv(int recovery_switch); +/** + * Get the recovery switch date from VBNV + * + * @param recovery_switch On success, set to the saved recovery switch state. + * + * @return 0 on success, !=0 if recovery switch state not saved. + */ +int get_recovery_switch_from_vbnv(int *recovery_switch); + int vboot_wants_oprom(void); /* Read the USB Device Controller(UDC) enable flag from VBNV. */ diff --git a/src/security/vboot/vbnv_layout.h b/src/security/vboot/vbnv_layout.h index a9326e4..322fcf7 100644 --- a/src/security/vboot/vbnv_layout.h +++ b/src/security/vboot/vbnv_layout.h @@ -43,7 +43,9 @@ #define DEV_ENABLE_UDC 0x40 #define MISC_FLAGS_OFFSET 8 -#define MISC_FLAGS_BATTERY_CUTOFF_MASK 0x08 +#define MISC_FLAGS_BATTERY_CUTOFF_MASK 0x08 +#define MISC_FLAGS_RECOVERY_SWITCH_VALID_MASK 0x10 +#define MISC_FLAGS_RECOVERY_SWITCH_STATE_MASK 0x20 #define KERNEL_FIELD_OFFSET 11 #define CRC_OFFSET 15 -- To view, visit https://review.coreboot.org/c/coreboot/+/31800 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id30a7b203e5aac8631971eb102986427b8362a71 Gerrit-Change-Number: 31800 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Short <keithshort(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mainboard/sarien: Save the Cr50 recovery switch state in VBNV
by Keith Short (Code Review) 24 Jun '19

24 Jun '19

Keith Short has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31801 Change subject: mainboard/sarien: Save the Cr50 recovery switch state in VBNV ...................................................................... mainboard/sarien: Save the Cr50 recovery switch state in VBNV Update sarien so the Cr50 recovery switch is only read during verstage and save the recovery switch state to VBNV. BUG=b:123360379 BRANCH=none TEST=build coreboot on sarien and arcada. Test normal boot and recovery boot on arcada - confirm that that tpm transaction errors are gone. Change-Id: Iadf0cec651b3a26ceebadfeb637e189805c328bf Signed-off-by: Keith Short <keithshort(a)chromium.org> --- M src/mainboard/google/sarien/chromeos.c 1 file changed, 16 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/31801/1 diff --git a/src/mainboard/google/sarien/chromeos.c b/src/mainboard/google/sarien/chromeos.c index 1e363fd..308b682 100644 --- a/src/mainboard/google/sarien/chromeos.c +++ b/src/mainboard/google/sarien/chromeos.c @@ -20,18 +20,12 @@ #include <variant/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> #include <security/tpm/tss.h> +#include <security/vboot/vbnv.h> #include <device/device.h> #include <intelblocks/pmclib.h> #include <soc/pmc.h> #include <soc/pci_devs.h> -enum rec_mode_state { - REC_MODE_UNINITIALIZED, - REC_MODE_NOT_REQUESTED, - REC_MODE_REQUESTED, -}; -static enum rec_mode_state saved_rec_mode; - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -84,30 +78,33 @@ int get_recovery_mode_switch(void) { - enum rec_mode_state state = saved_rec_mode; + int rec_switch; uint8_t recovery_button_state = 0; - /* Check the global variable first. */ - if (state == REC_MODE_NOT_REQUESTED) - return 0; - else if (state == REC_MODE_REQUESTED) - return 1; + /* + * Only verstage performs a real check of the Cr50 recovery switch. + * The recovery switch state is cleared on the first access by the AP + * so there's no point in querying the Cr50 at later stages. All other + * stages use the state saved in VBNV. + */ + if (!ENV_VERSTAGE && + !get_recovery_switch_from_vbnv(&rec_switch)) + return rec_switch; - state = REC_MODE_NOT_REQUESTED; + rec_switch = 0; /* Read state from the GPIO controlled by servo. */ if (cros_get_gpio_value(CROS_GPIO_REC)) - state = REC_MODE_REQUESTED; + rec_switch = 1; /* Read one-time recovery request from cr50. */ else if (tlcl_cr50_get_recovery_button(&recovery_button_state) == TPM_SUCCESS) - state = recovery_button_state ? - REC_MODE_REQUESTED : REC_MODE_NOT_REQUESTED; + rec_switch = !!recovery_button_state; /* Store the state in case this is called again in verstage. */ - saved_rec_mode = state; + set_recovery_switch_into_vbnv(rec_switch); - return state == REC_MODE_REQUESTED; + return rec_switch; } int get_lid_switch(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/31801 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iadf0cec651b3a26ceebadfeb637e189805c328bf Gerrit-Change-Number: 31801 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Short <keithshort(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Documentation: How to run coreboot on PC Engines APU2
by Piotr Kleinschmidt (Code Review) 24 Jun '19

24 Jun '19

Piotr Kleinschmidt has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33146 Change subject: Documentation: How to run coreboot on PC Engines APU2 ...................................................................... Documentation: How to run coreboot on PC Engines APU2 There is no documentation about running coreboot on apu2 platform, so now it describes how to do this. Change-Id: Id1d553c7f7485358960d92e714d50ba0f75b3581 Signed-off-by: Piotr Kleinschmidt <piotr.kleinschmidt(a)3mdeb.com> --- A Documentation/mainboard/pcengines/apu2.jpg A Documentation/mainboard/pcengines/apu2.md A Documentation/mainboard/pcengines/apu2_spi.jpg 3 files changed, 110 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/33146/1 diff --git a/Documentation/mainboard/pcengines/apu2.jpg b/Documentation/mainboard/pcengines/apu2.jpg new file mode 100644 index 0000000..d221857 --- /dev/null +++ b/Documentation/mainboard/pcengines/apu2.jpg Binary files differ diff --git a/Documentation/mainboard/pcengines/apu2.md b/Documentation/mainboard/pcengines/apu2.md new file mode 100644 index 0000000..a8aa3d2 --- /dev/null +++ b/Documentation/mainboard/pcengines/apu2.md @@ -0,0 +1,110 @@ +# PC Engines APU2 + +This page describes how to run coreboot on PC Engines APU2 platform. + +## Technology + +```eval_rst ++------------+---------------------------------------------------------------+ +| CPU | AMD G series GX-412TC | ++------------+---------------------------------------------------------------+ +| CPU core | 1 GHz quad Jaguar core with 64 bit support | +| | 32K data + 32K instruction cache per core, shared 2MB L2 cache| ++------------+---------------------------------------------------------------+ +| DRAM | 2 or 4 GB DDR3-1333 DRAM | ++------------+---------------------------------------------------------------+ +| Boot | From SD card, USB, mSATA SSD, SATA | ++------------+---------------------------------------------------------------+ +| Power | 6 to 12W of 12V power | ++------------+---------------------------------------------------------------+ +| Firmware | coreboot with support for iPXE and USB boot | ++------------+---------------------------------------------------------------+ +``` + +## Required proprietary blobs + +To build working coreboot image some blobs are needed. + +```eval_rst ++-----------------+---------------------------------+---------------------+ +| Binary file | Apply | Required / Optional | ++=====================+=============================+=====================+ +| AmdPubKey.bin | AMD Platform Security Processor | Required | ++-----------------+---------------------------------+---------------------+ +| AGESA.bin | AGESA Platform Initialization | Required | ++-----------------+---------------------------------+---------------------+ +| xhci.bin | AMD XHCI controller | Optional | ++-----------------+---------------------------------+---------------------+ +``` + +## Flashing coreboot + +```eval_rst ++---------------------+--------------------------+ +| Type | Value | ++=====================+==========================+ +| Socketed flash | no | ++---------------------+--------------------------+ +| Model | MX25L1606E | ++---------------------+--------------------------+ +| Size | 2 MiB | ++---------------------+--------------------------+ +| Package | SOP-8 | ++---------------------+--------------------------+ +| Write protection | jumper on WP# pin | ++---------------------+--------------------------+ +| Dual BIOS feature | no | ++---------------------+--------------------------+ +| Internal flashing | Super IO Nuvoton NCT5104D| ++---------------------+--------------------------+ +``` + +### Internal programming + +The SPI flash can be accessed using [flashrom]. It is important to execute +command with a `-c <chipname>` argument: + + flashrom -p internal -c "MX25L1606E" -w coreboot.rom + +### External programming + +**IMPORTANT**: When programming SPI flash, first you need to enter apu2 in S5 +(Soft-off) power state. S5 state can be forced by shorting power button pin on +J2 header. + +The external access to flash chip is available through standard SOP-8 clip or +SOP-8 header next to the flash chip on the board. Notice that not all boards +have a header soldered down originally. Hence, there could be an empty slot with +8 eyelets, so you can solder down a header on your own. The SPI flash chip and +SPI header are marked in the picture below. Also there is SPI header and SPI +flash pin layout included. + +There is no restrictions as to the programmer device. It is only recommended to +flash firmware without supplying power. External programming can be performed, +for example using OrangePi and Armbian. You can exploit linux_spi driver which +provide communication with SPI devices. Example command to program SPI flash +with OrangePi using linux_spi: + + flashrom -f -w coreboot.rom -p linux_spi:dev=/dev/spidev1.0,spispeed=16000 + + +**apu2 platform with marked in SPI header and SPI flash chip** + +![][apu2_flash] + +**SPI header pin layout** + +![][spi_header] + + +## Schematics + +PC Engines APU2 platform schematics are available for free on PC Engines +official site. Depending on the configuration: +- [apu2b](https://www.pcengines.ch/schema/apu2b.pdf) +- [apu2c](https://www.pcengines.ch/schema/apu2c.pdf) +- [apu2d](https://www.pcengines.ch/schema/apu2d.pdf) + +[apu2_flash]: apu2.jpg +[spi_header]: apu2_spi.jpg +[flashrom]: https://flashrom.org/Flashrom diff --git a/Documentation/mainboard/pcengines/apu2_spi.jpg b/Documentation/mainboard/pcengines/apu2_spi.jpg new file mode 100644 index 0000000..f8a5b58 --- /dev/null +++ b/Documentation/mainboard/pcengines/apu2_spi.jpg Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/33146 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id1d553c7f7485358960d92e714d50ba0f75b3581 Gerrit-Change-Number: 33146 Gerrit-PatchSet: 1 Gerrit-Owner: Piotr Kleinschmidt <piotr.kleinschmidt(a)3mdeb.com> Gerrit-MessageType: newchange

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