coreboot-gerrit May 2019

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Change in ...coreboot[master]: Update chromeec submodule to upstream master
by Martin Roth (Code Review) 14 Jul '19

14 Jul '19

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32342 Change subject: Update chromeec submodule to upstream master ...................................................................... Update chromeec submodule to upstream master Updating from commit id 11bd4c0f4: 2018-05-22 21:57:16 -0700 - (bip: enabled PPC interrupts) to commit id 8841b815c: 2019-04-17 13:33:39 +0000 - (ish: add missing EOI in LAPIC error irq handler) This brings in 2056 new commits. Change-Id: I13e1ce005f20aa6e68f2e6ef7f94222a9173eb16 Signed-off-by: Martin Roth <martinroth(a)google.com> --- M 3rdparty/chromeec 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/32342/1 diff --git a/3rdparty/chromeec b/3rdparty/chromeec index 11bd4c0..8841b81 160000 --- a/3rdparty/chromeec +++ b/3rdparty/chromeec @@ -1 +1 @@ -Subproject commit 11bd4c0f4d11357ab830982d7dec164813c886dd +Subproject commit 8841b815c195aadacb8f0f6e625041c3427bbd97 -- To view, visit https://review.coreboot.org/c/coreboot/+/32342 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13e1ce005f20aa6e68f2e6ef7f94222a9173eb16 Gerrit-Change-Number: 32342 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Update fsp submodule to upstream master
by Martin Roth (Code Review) 14 Jul '19

14 Jul '19

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32343 Change subject: Update fsp submodule to upstream master ...................................................................... Update fsp submodule to upstream master Updating from commit id 162719b: 2018-09-27 10:55:19 -0700 - (Add SplitFspBin.py) to commit id 8699794: 2019-04-04 15:19:28 -0700 - (Denverton-NS Production Validated 004) This brings in 10 new commits. Change-Id: Ibb185df3bf1f4657256c7b8885a3f0c7695cc798 Signed-off-by: Martin Roth <martinroth(a)google.com> --- M 3rdparty/fsp 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/32343/1 diff --git a/3rdparty/fsp b/3rdparty/fsp index 162719b..8699794 160000 --- a/3rdparty/fsp +++ b/3rdparty/fsp @@ -1 +1 @@ -Subproject commit 162719b6cb5efc6c50dcb23dfdb378358573e2b6 +Subproject commit 86997945d03e1471f5dcdbbbb8d6118e5a6ecd38 -- To view, visit https://review.coreboot.org/c/coreboot/+/32343 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb185df3bf1f4657256c7b8885a3f0c7695cc798 Gerrit-Change-Number: 32343 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: drivers/wifi: Add generic WiFi driver
by Karthik Ramasubramanian (Code Review) 13 Jul '19

13 Jul '19

Hello Karthikeyan Ramasubramanian, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/33155 to review the following change. Change subject: drivers/wifi: Add generic WiFi driver ...................................................................... drivers/wifi: Add generic WiFi driver Add generic WiFi driver to support common device operations across multiple types of WiFi controller. BUG=None BRANCH=None TEST=Boot to ChromeOS. Ensure that the SSDT table contains SAR tables and wakeup GPE information. Ensure that the SSDT table is same after the change. Change-Id: Ica5edf95a37c8ed60f7e159d94fd58af5d41c0ef Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/drivers/intel/wifi/Kconfig M src/drivers/intel/wifi/chip.h M src/drivers/intel/wifi/wifi.c A src/drivers/wifi/Kconfig A src/drivers/wifi/Makefile.inc A src/drivers/wifi/generic.c A src/drivers/wifi/generic_wifi.h 7 files changed, 295 insertions(+), 206 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/33155/1 diff --git a/src/drivers/intel/wifi/Kconfig b/src/drivers/intel/wifi/Kconfig index 4dc4d7f..7cf9391 100644 --- a/src/drivers/intel/wifi/Kconfig +++ b/src/drivers/intel/wifi/Kconfig @@ -2,6 +2,7 @@ bool "Support Intel PCI-e WiFi adapters" depends on ARCH_X86 default y if PCIEXP_PLUGIN_SUPPORT + select DRIVERS_GENERIC_WIFI if HAVE_ACPI_TABLES help When enabled, add identifiers in ACPI and SMBIOS tables to make OS drivers work with certain Intel PCI-e WiFi chipsets. diff --git a/src/drivers/intel/wifi/chip.h b/src/drivers/intel/wifi/chip.h index 1b3c2a5..72ff951 100644 --- a/src/drivers/intel/wifi/chip.h +++ b/src/drivers/intel/wifi/chip.h @@ -13,26 +13,13 @@ * GNU General Public License for more details. */ -#ifndef _WIFI_CHIP_H_ -#define _WIFI_CHIP_H_ +#ifndef _INTEL_WIFI_CHIP_H_ +#define _INTEL_WIFI_CHIP_H_ -/* WRDS Spec Revision */ -#define WRDS_REVISION 0x0 - -/* EWRD Spec Revision */ -#define EWRD_REVISION 0x0 - -/* WRDS Domain type */ -#define WRDS_DOMAIN_TYPE_WIFI 0x7 - -/* EWRD Domain type */ -#define EWRD_DOMAIN_TYPE_WIFI 0x7 - -/* WGDS Domain type */ -#define WGDS_DOMAIN_TYPE_WIFI 0x7 +#include "drivers/wifi/generic_wifi.h" struct drivers_intel_wifi_config { - unsigned wake; /* Wake pin for ACPI _PRW */ + unsigned int wake; /* Wake pin for ACPI _PRW */ }; -#endif /* _WIFI_CHIP_H_ */ +#endif /* _INTEL_WIFI_CHIP_H_ */ diff --git a/src/drivers/intel/wifi/wifi.c b/src/drivers/intel/wifi/wifi.c index 83cfaa9..546c925 100644 --- a/src/drivers/intel/wifi/wifi.c +++ b/src/drivers/intel/wifi/wifi.c @@ -15,19 +15,16 @@ * GNU General Public License for more details. */ -#include <arch/acpi_device.h> -#include <arch/acpigen.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> #include <device/pci_ids.h> #include <elog.h> -#include <sar.h> #include <smbios.h> #include <string.h> -#include <wrdd.h> #include "chip.h" +#include "drivers/wifi/generic_wifi.h" #define PMCS_DR 0xcc #define PME_STS (1 << 15) @@ -65,194 +62,15 @@ } #endif -__weak -int get_wifi_sar_limits(struct wifi_sar_limits *sar_limits) -{ - return -1; -} - #if CONFIG(HAVE_ACPI_TABLES) -static void emit_sar_acpi_structures(void) -{ - int i, j, package_size; - struct wifi_sar_limits sar_limits; - struct wifi_sar_delta_table *wgds; - - /* Retrieve the sar limits data */ - if (get_wifi_sar_limits(&sar_limits) < 0) { - printk(BIOS_ERR, "Error: failed from getting SAR limits!\n"); - return; - } - - /* - * Name ("WRDS", Package () { - * Revision, - * Package () { - * Domain Type, // 0x7:WiFi - * WiFi SAR BIOS, // BIOS SAR Enable/disable - * SAR Table Set // Set#1 of SAR Table (10 bytes) - * } - * }) - */ - acpigen_write_name("WRDS"); - acpigen_write_package(2); - acpigen_write_dword(WRDS_REVISION); - /* Emit 'Domain Type' + 'WiFi SAR BIOS' + 10 bytes for Set#1 */ - package_size = 1 + 1 + BYTES_PER_SAR_LIMIT; - acpigen_write_package(package_size); - acpigen_write_dword(WRDS_DOMAIN_TYPE_WIFI); - acpigen_write_dword(CONFIG(SAR_ENABLE)); - for (i = 0; i < BYTES_PER_SAR_LIMIT; i++) - acpigen_write_byte(sar_limits.sar_limit[0][i]); - acpigen_pop_len(); - acpigen_pop_len(); - - /* - * Name ("EWRD", Package () { - * Revision, - * Package () { - * Domain Type, // 0x7:WiFi - * Dynamic SAR Enable, // Dynamic SAR Enable/disable - * Extended SAR sets, // Number of optional SAR table sets - * SAR Table Set, // Set#2 of SAR Table (10 bytes) - * SAR Table Set, // Set#3 of SAR Table (10 bytes) - * SAR Table Set // Set#4 of SAR Table (10 bytes) - * } - * }) - */ - acpigen_write_name("EWRD"); - acpigen_write_package(2); - acpigen_write_dword(EWRD_REVISION); - /* - * Emit 'Domain Type' + "Dynamic SAR Enable' + 'Extended SAR sets' - * + number of bytes for Set#2 & 3 & 4 - */ - package_size = 1 + 1 + 1 + (NUM_SAR_LIMITS - 1) * BYTES_PER_SAR_LIMIT; - acpigen_write_package(package_size); - acpigen_write_dword(EWRD_DOMAIN_TYPE_WIFI); - acpigen_write_dword(CONFIG(DSAR_ENABLE)); - acpigen_write_dword(CONFIG_DSAR_SET_NUM); - for (i = 1; i < NUM_SAR_LIMITS; i++) - for (j = 0; j < BYTES_PER_SAR_LIMIT; j++) - acpigen_write_byte(sar_limits.sar_limit[i][j]); - acpigen_pop_len(); - acpigen_pop_len(); - - - if (!CONFIG(GEO_SAR_ENABLE)) - return; - - /* - * Name ("WGDS", Package() { - * Revision, - * Package() { - * DomainType, // 0x7:WiFi - * WgdsWiFiSarDeltaGroup1PowerMax1, // Group 1 FCC 2400 Max - * WgdsWiFiSarDeltaGroup1PowerChainA1, // Group 1 FCC 2400 A Offset - * WgdsWiFiSarDeltaGroup1PowerChainB1, // Group 1 FCC 2400 B Offset - * WgdsWiFiSarDeltaGroup1PowerMax2, // Group 1 FCC 5200 Max - * WgdsWiFiSarDeltaGroup1PowerChainA2, // Group 1 FCC 5200 A Offset - * WgdsWiFiSarDeltaGroup1PowerChainB2, // Group 1 FCC 5200 B Offset - * WgdsWiFiSarDeltaGroup2PowerMax1, // Group 2 EC Jap 2400 Max - * WgdsWiFiSarDeltaGroup2PowerChainA1, // Group 2 EC Jap 2400 A Offset - * WgdsWiFiSarDeltaGroup2PowerChainB1, // Group 2 EC Jap 2400 B Offset - * WgdsWiFiSarDeltaGroup2PowerMax2, // Group 2 EC Jap 5200 Max - * WgdsWiFiSarDeltaGroup2PowerChainA2, // Group 2 EC Jap 5200 A Offset - * WgdsWiFiSarDeltaGroup2PowerChainB2, // Group 2 EC Jap 5200 B Offset - * WgdsWiFiSarDeltaGroup3PowerMax1, // Group 3 ROW 2400 Max - * WgdsWiFiSarDeltaGroup3PowerChainA1, // Group 3 ROW 2400 A Offset - * WgdsWiFiSarDeltaGroup3PowerChainB1, // Group 3 ROW 2400 B Offset - * WgdsWiFiSarDeltaGroup3PowerMax2, // Group 3 ROW 5200 Max - * WgdsWiFiSarDeltaGroup3PowerChainA2, // Group 3 ROW 5200 A Offset - * WgdsWiFiSarDeltaGroup3PowerChainB2, // Group 3 ROW 5200 B Offset - * } - * }) - */ - - wgds = &sar_limits.wgds; - acpigen_write_name("WGDS"); - acpigen_write_package(2); - acpigen_write_dword(wgds->version); - /* Emit 'Domain Type' + - * Group specific delta of power (6 bytes * NUM_WGDS_SAR_GROUPS) - */ - package_size = sizeof(sar_limits.wgds.group) + 1; - acpigen_write_package(package_size); - acpigen_write_dword(WGDS_DOMAIN_TYPE_WIFI); - for (i = 0; i < SAR_NUM_WGDS_GROUPS; i++) { - acpigen_write_byte(wgds->group[i].power_max_2400mhz); - acpigen_write_byte(wgds->group[i].power_chain_a_2400mhz); - acpigen_write_byte(wgds->group[i].power_chain_b_2400mhz); - acpigen_write_byte(wgds->group[i].power_max_5200mhz); - acpigen_write_byte(wgds->group[i].power_chain_a_5200mhz); - acpigen_write_byte(wgds->group[i].power_chain_b_5200mhz); - } - - acpigen_pop_len(); - acpigen_pop_len(); -} - static void intel_wifi_fill_ssdt(struct device *dev) { struct drivers_intel_wifi_config *config = dev->chip_info; - const char *path = acpi_device_path(dev->bus->dev); - u32 address; + struct generic_wifi_config generic_config = { + .wake = config->wake, + }; - if (!path || !dev->enabled) - return; - - /* Device */ - acpigen_write_scope(path); - acpigen_write_device(acpi_device_name(dev)); - acpigen_write_name_integer("_UID", 0); - if (dev->chip_ops) - acpigen_write_name_string("_DDN", dev->chip_ops->name); - - /* Address */ - address = PCI_SLOT(dev->path.pci.devfn) & 0xffff; - address <<= 16; - address |= PCI_FUNC(dev->path.pci.devfn) & 0xffff; - acpigen_write_name_dword("_ADR", address); - - /* Wake capabilities */ - if (config && config->wake) - acpigen_write_PRW(config->wake, 3); - - /* Fill regulatory domain structure */ - if (CONFIG(HAVE_REGULATORY_DOMAIN)) { - /* - * Name ("WRDD", Package () { - * WRDD_REVISION, // Revision - * Package () { - * WRDD_DOMAIN_TYPE_WIFI, // Domain Type, 7:WiFi - * wifi_regulatory_domain() // Country Identifier - * } - * }) - */ - acpigen_write_name("WRDD"); - acpigen_write_package(2); - acpigen_write_integer(WRDD_REVISION); - acpigen_write_package(2); - acpigen_write_dword(WRDD_DOMAIN_TYPE_WIFI); - acpigen_write_dword(wifi_regulatory_domain()); - acpigen_pop_len(); - acpigen_pop_len(); - } - - /* Fill Wifi sar related ACPI structures */ - if (CONFIG(USE_SAR)) - emit_sar_acpi_structures(); - - acpigen_pop_len(); /* Device */ - acpigen_pop_len(); /* Scope */ - - printk(BIOS_INFO, "%s.%s: %s %s\n", path, acpi_device_name(dev), - dev->chip_ops ? dev->chip_ops->name : "", dev_path(dev)); -} - -static const char *intel_wifi_acpi_name(const struct device *dev) -{ - return "WIFI"; + generic_wifi_fill_ssdt(dev, &generic_config); } #endif @@ -282,7 +100,7 @@ #endif .ops_pci = &pci_ops, #if CONFIG(HAVE_ACPI_TABLES) - .acpi_name = intel_wifi_acpi_name, + .acpi_name = generic_wifi_acpi_name, .acpi_fill_ssdt_generator = intel_wifi_fill_ssdt, #endif }; diff --git a/src/drivers/wifi/Kconfig b/src/drivers/wifi/Kconfig new file mode 100644 index 0000000..966dc55 --- /dev/null +++ b/src/drivers/wifi/Kconfig @@ -0,0 +1,4 @@ +config DRIVERS_GENERIC_WIFI + bool + default n + depends on HAVE_ACPI_TABLES diff --git a/src/drivers/wifi/Makefile.inc b/src/drivers/wifi/Makefile.inc new file mode 100644 index 0000000..d37015c --- /dev/null +++ b/src/drivers/wifi/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_GENERIC_WIFI) += generic.c diff --git a/src/drivers/wifi/generic.c b/src/drivers/wifi/generic.c new file mode 100644 index 0000000..acf1e45 --- /dev/null +++ b/src/drivers/wifi/generic.c @@ -0,0 +1,229 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 or (at your option) + * any later version of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi_device.h> +#include <arch/acpigen.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <sar.h> +#include <string.h> +#include <wrdd.h> +#include "generic_wifi.h" + +/* WRDS Spec Revision */ +#define WRDS_REVISION 0x0 + +/* EWRD Spec Revision */ +#define EWRD_REVISION 0x0 + +/* WRDS Domain type */ +#define WRDS_DOMAIN_TYPE_WIFI 0x7 + +/* EWRD Domain type */ +#define EWRD_DOMAIN_TYPE_WIFI 0x7 + +/* WGDS Domain type */ +#define WGDS_DOMAIN_TYPE_WIFI 0x7 + +__weak +int get_wifi_sar_limits(struct wifi_sar_limits *sar_limits) +{ + return -1; +} + +static void emit_sar_acpi_structures(void) +{ + int i, j, package_size; + struct wifi_sar_limits sar_limits; + struct wifi_sar_delta_table *wgds; + + /* Retrieve the sar limits data */ + if (get_wifi_sar_limits(&sar_limits) < 0) { + printk(BIOS_ERR, "Error: failed from getting SAR limits!\n"); + return; + } + + /* + * Name ("WRDS", Package () { + * Revision, + * Package () { + * Domain Type, // 0x7:WiFi + * WiFi SAR BIOS, // BIOS SAR Enable/disable + * SAR Table Set // Set#1 of SAR Table (10 bytes) + * } + * }) + */ + acpigen_write_name("WRDS"); + acpigen_write_package(2); + acpigen_write_dword(WRDS_REVISION); + /* Emit 'Domain Type' + 'WiFi SAR BIOS' + 10 bytes for Set#1 */ + package_size = 1 + 1 + BYTES_PER_SAR_LIMIT; + acpigen_write_package(package_size); + acpigen_write_dword(WRDS_DOMAIN_TYPE_WIFI); + acpigen_write_dword(CONFIG(SAR_ENABLE)); + for (i = 0; i < BYTES_PER_SAR_LIMIT; i++) + acpigen_write_byte(sar_limits.sar_limit[0][i]); + acpigen_pop_len(); + acpigen_pop_len(); + + /* + * Name ("EWRD", Package () { + * Revision, + * Package () { + * Domain Type, // 0x7:WiFi + * Dynamic SAR Enable, // Dynamic SAR Enable/disable + * Extended SAR sets, // Number of optional SAR table sets + * SAR Table Set, // Set#2 of SAR Table (10 bytes) + * SAR Table Set, // Set#3 of SAR Table (10 bytes) + * SAR Table Set // Set#4 of SAR Table (10 bytes) + * } + * }) + */ + acpigen_write_name("EWRD"); + acpigen_write_package(2); + acpigen_write_dword(EWRD_REVISION); + /* + * Emit 'Domain Type' + "Dynamic SAR Enable' + 'Extended SAR sets' + * + number of bytes for Set#2 & 3 & 4 + */ + package_size = 1 + 1 + 1 + (NUM_SAR_LIMITS - 1) * BYTES_PER_SAR_LIMIT; + acpigen_write_package(package_size); + acpigen_write_dword(EWRD_DOMAIN_TYPE_WIFI); + acpigen_write_dword(CONFIG(DSAR_ENABLE)); + acpigen_write_dword(CONFIG_DSAR_SET_NUM); + for (i = 1; i < NUM_SAR_LIMITS; i++) + for (j = 0; j < BYTES_PER_SAR_LIMIT; j++) + acpigen_write_byte(sar_limits.sar_limit[i][j]); + acpigen_pop_len(); + acpigen_pop_len(); + + + if (!CONFIG(GEO_SAR_ENABLE)) + return; + + /* + * Name ("WGDS", Package() { + * Revision, + * Package() { + * DomainType, // 0x7:WiFi + * WgdsWiFiSarDeltaGroup1PowerMax1, // Group 1 FCC 2400 Max + * WgdsWiFiSarDeltaGroup1PowerChainA1, // Group 1 FCC 2400 A Offset + * WgdsWiFiSarDeltaGroup1PowerChainB1, // Group 1 FCC 2400 B Offset + * WgdsWiFiSarDeltaGroup1PowerMax2, // Group 1 FCC 5200 Max + * WgdsWiFiSarDeltaGroup1PowerChainA2, // Group 1 FCC 5200 A Offset + * WgdsWiFiSarDeltaGroup1PowerChainB2, // Group 1 FCC 5200 B Offset + * WgdsWiFiSarDeltaGroup2PowerMax1, // Group 2 EC Jap 2400 Max + * WgdsWiFiSarDeltaGroup2PowerChainA1, // Group 2 EC Jap 2400 A Offset + * WgdsWiFiSarDeltaGroup2PowerChainB1, // Group 2 EC Jap 2400 B Offset + * WgdsWiFiSarDeltaGroup2PowerMax2, // Group 2 EC Jap 5200 Max + * WgdsWiFiSarDeltaGroup2PowerChainA2, // Group 2 EC Jap 5200 A Offset + * WgdsWiFiSarDeltaGroup2PowerChainB2, // Group 2 EC Jap 5200 B Offset + * WgdsWiFiSarDeltaGroup3PowerMax1, // Group 3 ROW 2400 Max + * WgdsWiFiSarDeltaGroup3PowerChainA1, // Group 3 ROW 2400 A Offset + * WgdsWiFiSarDeltaGroup3PowerChainB1, // Group 3 ROW 2400 B Offset + * WgdsWiFiSarDeltaGroup3PowerMax2, // Group 3 ROW 5200 Max + * WgdsWiFiSarDeltaGroup3PowerChainA2, // Group 3 ROW 5200 A Offset + * WgdsWiFiSarDeltaGroup3PowerChainB2, // Group 3 ROW 5200 B Offset + * } + * }) + */ + + wgds = &sar_limits.wgds; + acpigen_write_name("WGDS"); + acpigen_write_package(2); + acpigen_write_dword(wgds->version); + /* Emit 'Domain Type' + + * Group specific delta of power (6 bytes * NUM_WGDS_SAR_GROUPS) + */ + package_size = sizeof(sar_limits.wgds.group) + 1; + acpigen_write_package(package_size); + acpigen_write_dword(WGDS_DOMAIN_TYPE_WIFI); + for (i = 0; i < SAR_NUM_WGDS_GROUPS; i++) { + acpigen_write_byte(wgds->group[i].power_max_2400mhz); + acpigen_write_byte(wgds->group[i].power_chain_a_2400mhz); + acpigen_write_byte(wgds->group[i].power_chain_b_2400mhz); + acpigen_write_byte(wgds->group[i].power_max_5200mhz); + acpigen_write_byte(wgds->group[i].power_chain_a_5200mhz); + acpigen_write_byte(wgds->group[i].power_chain_b_5200mhz); + } + + acpigen_pop_len(); + acpigen_pop_len(); +} + +void generic_wifi_fill_ssdt(struct device *dev, + struct generic_wifi_config *config) +{ + const char *path = acpi_device_path(dev->bus->dev); + u32 address; + + if (!path || !dev->enabled) + return; + + /* Device */ + acpigen_write_scope(path); + acpigen_write_device(acpi_device_name(dev)); + acpigen_write_name_integer("_UID", 0); + if (dev->chip_ops) + acpigen_write_name_string("_DDN", dev->chip_ops->name); + + /* Address */ + address = PCI_SLOT(dev->path.pci.devfn) & 0xffff; + address <<= 16; + address |= PCI_FUNC(dev->path.pci.devfn) & 0xffff; + acpigen_write_name_dword("_ADR", address); + + /* Wake capabilities */ + if (config && config->wake) + acpigen_write_PRW(config->wake, 3); + + /* Fill regulatory domain structure */ + if (CONFIG(HAVE_REGULATORY_DOMAIN)) { + /* + * Name ("WRDD", Package () { + * WRDD_REVISION, // Revision + * Package () { + * WRDD_DOMAIN_TYPE_WIFI, // Domain Type, 7:WiFi + * wifi_regulatory_domain() // Country Identifier + * } + * }) + */ + acpigen_write_name("WRDD"); + acpigen_write_package(2); + acpigen_write_integer(WRDD_REVISION); + acpigen_write_package(2); + acpigen_write_dword(WRDD_DOMAIN_TYPE_WIFI); + acpigen_write_dword(wifi_regulatory_domain()); + acpigen_pop_len(); + acpigen_pop_len(); + } + + /* Fill Wifi sar related ACPI structures */ + if (CONFIG(USE_SAR)) + emit_sar_acpi_structures(); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ + + printk(BIOS_INFO, "%s.%s: %s %s\n", path, acpi_device_name(dev), + dev->chip_ops ? dev->chip_ops->name : "", dev_path(dev)); +} + +const char *generic_wifi_acpi_name(const struct device *dev) +{ + return "WIFI"; +} diff --git a/src/drivers/wifi/generic_wifi.h b/src/drivers/wifi/generic_wifi.h new file mode 100644 index 0000000..fdcf66a --- /dev/null +++ b/src/drivers/wifi/generic_wifi.h @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _GENERIC_WIFI_H_ +#define _GENERIC_WIFI_H_ + +/** + * struct generic_wifi_config - Data structure to contain common wifi config + * @wake: Wake pin for ACPI _PRW + */ +struct generic_wifi_config { + unsigned int wake; +}; + +/** + * wifi_fill_ssdt() - Fill ACPI SSDT table for WiFi controller + * @dev: Device structure corresponding to WiFi controller. + * @config: Common wifi config required to fill ACPI SSDT table. + * + * This function implements common device operation to help fill ACPI SSDT + * table for WiFi controller. + */ +void generic_wifi_fill_ssdt(struct device *dev, + struct generic_wifi_config *config); + +/** + * wifi_acpi_name() - Get ACPI name for WiFi controller + * @dev: Device structure corresponding to WiFi controller. + * + * This function implements common device operation to get the ACPI name for + * WiFi controller. + * + * Return: string representing the ACPI name for WiFi controller. + */ +const char *generic_wifi_acpi_name(const struct device *dev); + +#endif /* _GENERIC_WIFI_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/33155 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica5edf95a37c8ed60f7e159d94fd58af5d41c0ef Gerrit-Change-Number: 33155 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-MessageType: newchange

6 30

Change in ...coreboot[master]: [TEST] udelay() in postcar
by Kyösti Mälkki (Code Review) 12 Jul '19

12 Jul '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31327 Change subject: [TEST] udelay() in postcar ...................................................................... [TEST] udelay() in postcar Change-Id: I7aeaa8487a15be92b259c6902a7142d7b04e52c2 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/postcar.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/31327/1 diff --git a/src/arch/x86/postcar.c b/src/arch/x86/postcar.c index ea05824..957ca92 100644 --- a/src/arch/x86/postcar.c +++ b/src/arch/x86/postcar.c @@ -19,6 +19,7 @@ #include <cpu/x86/mtrr.h> #include <main_decl.h> #include <program_loading.h> +#include <delay.h> /* * Systems without a native coreboot cache-as-ram teardown may implement @@ -28,6 +29,8 @@ void main(void) { + udelay(1); + late_car_teardown(); console_init(); -- To view, visit https://review.coreboot.org/c/coreboot/+/31327 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7aeaa8487a15be92b259c6902a7142d7b04e52c2 Gerrit-Change-Number: 31327 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

1 1

Change in ...coreboot[master]: cpu/intel soc/intel: Fix udelay() for postcar
by Kyösti Mälkki (Code Review) 12 Jul '19

12 Jul '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31326 Change subject: cpu/intel soc/intel: Fix udelay() for postcar ...................................................................... cpu/intel soc/intel: Fix udelay() for postcar We need tsc_freq_mhz() in postcar stage. Change-Id: I56bc98c1ad91928c319839f03c361d15ce20b719 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/haswell/Makefile.inc M src/cpu/intel/model_2065x/Makefile.inc M src/cpu/intel/model_206ax/Makefile.inc M src/soc/intel/baytrail/Makefile.inc M src/soc/intel/broadwell/Makefile.inc 5 files changed, 12 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/31326/1 diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index c317c09..8a2f960 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -1,10 +1,12 @@ -ramstage-y += haswell_init.c -ramstage-y += tsc_freq.c romstage-y += romstage.c romstage-y += tsc_freq.c romstage-y += ../car/romstage.c +postcar-y += tsc_freq.c + ramstage-y += acpi.c +ramstage-y += haswell_init.c +ramstage-y += tsc_freq.c ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc index ec8643a..73c51dc 100644 --- a/src/cpu/intel/model_2065x/Makefile.inc +++ b/src/cpu/intel/model_2065x/Makefile.inc @@ -10,8 +10,9 @@ subdirs-y += ../smm/gen1 subdirs-y += ../common -ramstage-y += tsc_freq.c romstage-y += tsc_freq.c +postcar-y += tsc_freq.c +ramstage-y += tsc_freq.c smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c ramstage-y += acpi.c diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc index d193e60..ec08c81 100644 --- a/src/cpu/intel/model_206ax/Makefile.inc +++ b/src/cpu/intel/model_206ax/Makefile.inc @@ -17,8 +17,9 @@ romstage-y += common.c smm-$(CONFIG_HAVE_SMI_HANDLER) += common.c -ramstage-y += tsc_freq.c romstage-y += tsc_freq.c +postcar-y += tsc_freq.c +ramstage-y += tsc_freq.c smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index 1debea9..cb721ea 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -12,8 +12,9 @@ ramstage-y += memmap.c romstage-y += memmap.c postcar-y += memmap.c -ramstage-y += tsc_freq.c romstage-y += tsc_freq.c +postcar-y += tsc_freq.c +ramstage-y += tsc_freq.c smm-y += tsc_freq.c ramstage-y += spi.c smm-y += spi.c diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index acb71fe..f360b96 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -58,8 +58,9 @@ romstage-y += stage_cache.c postcar-y += stage_cache.c ramstage-y += systemagent.c -ramstage-y += tsc_freq.c +postcar-y += tsc_freq.c romstage-y += tsc_freq.c +ramstage-y += tsc_freq.c smm-y += tsc_freq.c bootblock-$(CONFIG_USBDEBUG) += usb_debug.c romstage-$(CONFIG_USBDEBUG) += usb_debug.c -- To view, visit https://review.coreboot.org/c/coreboot/+/31326 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I56bc98c1ad91928c319839f03c361d15ce20b719 Gerrit-Change-Number: 31326 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

2 3

Change in ...coreboot[master]: include: Implement abs()
by Patrick Rudolph (Code Review) 11 Jul '19

11 Jul '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32501 Change subject: include: Implement abs() ...................................................................... include: Implement abs() There are a few external libraries that make use of this simple function. Change-Id: I0719de6558cf9224ecbbd46b6f8a8040e8225a79 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/include/stdlib.h 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/32501/1 diff --git a/src/include/stdlib.h b/src/include/stdlib.h index 34ef93a..a396a3b 100644 --- a/src/include/stdlib.h +++ b/src/include/stdlib.h @@ -11,4 +11,9 @@ /* We never free memory */ static inline void free(void *ptr) {} +static inline int abs(int i) +{ + return i < 0 ? -i : i; +} + #endif /* STDLIB_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32501 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0719de6558cf9224ecbbd46b6f8a8040e8225a79 Gerrit-Change-Number: 32501 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

3 7

Change in ...coreboot[master]: vendorcode/eltan Add hashing library used for measured and verified b...
by Frans Hendriks (Code Review) 10 Jul '19

10 Jul '19

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30831 Change subject: vendorcode/eltan Add hashing library used for measured and verified boot. ...................................................................... vendorcode/eltan Add hashing library used for measured and verified boot. To avoid having the whole 3rdparty/vboot/firmware included a small hashing library has been created. Create library which is a 'wrapper' using only sha1, sha256 and sha512 of 3rdparty/vboot/firmware. Fucntions cb_sha1(), cb_sha256() and cb_sha512 can be used for hashing. BUG=N/A TEST=Created binary and verify logging on Facebok FBG-1701 Change-Id: If828bde54c79e836a5b05ff0447645d7e06e819a Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- A src/vendorcode/eltan/security/include/cb_sha1.h A src/vendorcode/eltan/security/include/cb_sha256.h A src/vendorcode/eltan/security/include/cb_sha512.h A src/vendorcode/eltan/security/include/cryptolib.h A src/vendorcode/eltan/security/lib/Makefile.inc A src/vendorcode/eltan/security/lib/cb_sha1.c A src/vendorcode/eltan/security/lib/cb_sha256.c A src/vendorcode/eltan/security/lib/cb_sha512.c 8 files changed, 297 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/30831/1 diff --git a/src/vendorcode/eltan/security/include/cb_sha1.h b/src/vendorcode/eltan/security/include/cb_sha1.h new file mode 100644 index 0000000..3b72355 --- /dev/null +++ b/src/vendorcode/eltan/security/include/cb_sha1.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018. Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SECURITY_SHA1_H__ +#define __SECURITY_SHA1_H__ + +uint8_t *cb_sha1(const uint8_t *data, uint64_t len, uint8_t *digest); + +#endif diff --git a/src/vendorcode/eltan/security/include/cb_sha256.h b/src/vendorcode/eltan/security/include/cb_sha256.h new file mode 100644 index 0000000..3b45f73 --- /dev/null +++ b/src/vendorcode/eltan/security/include/cb_sha256.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018. Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SECURITY_SHA256_H__ +#define __SECURITY_SHA256_H__ + +uint8_t *cb_sha256(const uint8_t *data, uint64_t len, uint8_t *digest); +uint8_t *cb_sha256_ex(const uint8_t *data, uint64_t len, uint8_t *digest, + bool endian); + +#endif diff --git a/src/vendorcode/eltan/security/include/cb_sha512.h b/src/vendorcode/eltan/security/include/cb_sha512.h new file mode 100644 index 0000000..a383cf0 --- /dev/null +++ b/src/vendorcode/eltan/security/include/cb_sha512.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018. Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SECURITY_SHA512_H__ +#define __SECURITY_SHA512_H__ + +uint8_t *cb_sha512(const uint8_t *data, uint64_t len, uint8_t *digest); +uint8_t *cb_sha512_ex(const uint8_t *data, uint64_t len, uint8_t *digest, + bool endian); + +#endif diff --git a/src/vendorcode/eltan/security/include/cryptolib.h b/src/vendorcode/eltan/security/include/cryptolib.h new file mode 100644 index 0000000..ac1668a --- /dev/null +++ b/src/vendorcode/eltan/security/include/cryptolib.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018. Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SECURITY_CRYPTOLIB_H__ +#define __SECURITY_CRYPTOLIB_H__ + +#define NEED_VB2_SHA_LIBRARY + +#include <2rsa.h> +#include <vb21_common.h> +#include <vb2_api.h> + +#include "cb_sha1.h" +#include "cb_sha512.h" +#include "cb_sha256.h" + +#endif \ No newline at end of file diff --git a/src/vendorcode/eltan/security/lib/Makefile.inc b/src/vendorcode/eltan/security/lib/Makefile.inc new file mode 100644 index 0000000..9e2fc39 --- /dev/null +++ b/src/vendorcode/eltan/security/lib/Makefile.inc @@ -0,0 +1,52 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2018 Eltan B.V. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +SECURITYLIB_INCLUDES = -I3rdparty/vboot/firmware/2lib/include -I3rdparty/vboot/firmware/lib21/include + +CPPFLAGS_common+=$(SECURITYLIB_INCLUDES) + +ifeq ($(CONFIG_VERIFIED_BOOT),y) +bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += $(top)/3rdparty/vboot/firmware/2lib/2common.c +bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += $(top)/3rdparty/vboot/firmware/2lib/2rsa.c +bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += $(top)/3rdparty/vboot/firmware/2lib/2sha_utility.c +bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += $(top)/3rdparty/vboot/firmware/lib21/packed_key.c +ifeq ($(CONFIG_VERIFIED_BOOT_USE_SHA512),y) +bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += cb_sha512.c +bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += $(top)/3rdparty/vboot/firmware/2lib/2sha512.c +else +bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += cb_sha256.c +bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += $(top)/3rdparty/vboot/firmware/2lib/2sha256.c +endif +endif + +ifeq ($(CONFIG_MBOOT),y) +ramstage-y += $(top)/3rdparty/vboot/firmware/2lib/2sha1.c +ramstage-y += $(top)/3rdparty/vboot/firmware/2lib/2sha512.c +ramstage-y += $(top)/3rdparty/vboot/firmware/2lib/2sha256.c +ramstage-y += cb_sha1.c +ramstage-y += cb_sha512.c +ramstage-y += cb_sha256.c + +romstage-y += $(top)/3rdparty/vboot/firmware/2lib/2common.c +romstage-y += $(top)/3rdparty/vboot/firmware/2lib/2rsa.c +romstage-y += $(top)/3rdparty/vboot/firmware/2lib/2sha1.c +romstage-y += $(top)/3rdparty/vboot/firmware/2lib/2sha256.c +romstage-y += $(top)/3rdparty/vboot/firmware/2lib/2sha512.c +romstage-y += $(top)/3rdparty/vboot/firmware/2lib/2sha_utility.c +romstage-y += $(top)/3rdparty/vboot/firmware/lib21/packed_key.c +romstage-y += cb_sha1.c +romstage-y += cb_sha512.c +romstage-y += cb_sha256.c +endif \ No newline at end of file diff --git a/src/vendorcode/eltan/security/lib/cb_sha1.c b/src/vendorcode/eltan/security/lib/cb_sha1.c new file mode 100644 index 0000000..fd96943 --- /dev/null +++ b/src/vendorcode/eltan/security/lib/cb_sha1.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cryptolib.h> + +uint8_t *cb_sha1(const uint8_t *data, uint64_t len, uint8_t *digest) +{ + struct vb2_sha1_context ctx; + + vb2_sha1_init(&ctx); + vb2_sha1_update(&ctx, data, len); + vb2_sha1_finalize(&ctx, digest); + + return digest; +} diff --git a/src/vendorcode/eltan/security/lib/cb_sha256.c b/src/vendorcode/eltan/security/lib/cb_sha256.c new file mode 100644 index 0000000..b02ebb2 --- /dev/null +++ b/src/vendorcode/eltan/security/lib/cb_sha256.c @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cryptolib.h> + +uint8_t *cb_sha256_ex(const uint8_t *data, uint64_t len, uint8_t *digest, + bool endian) +{ + int i; + const uint8_t *input_ptr; + uint8_t result[VB2_SHA256_DIGEST_SIZE]; + uint8_t *result_ptr; + uint64_t remaining_len; + struct vb2_sha256_context ctx; + + vb2_sha256_init(&ctx); + + input_ptr = data; + remaining_len = len; + + /* Process data in at most UINT32_MAX byte chunks at a time. */ + while (remaining_len) { + uint32_t block_size; + block_size = (uint32_t) ((remaining_len >= UINT32_MAX) ? + UINT32_MAX : remaining_len); + vb2_sha256_update(&ctx, input_ptr, block_size); + remaining_len -= block_size; + input_ptr += block_size; + } + + result_ptr = result; + vb2_sha256_finalize(&ctx, result_ptr); + for (i = 0; i < VB2_SHA256_DIGEST_SIZE; ++i) { + if (endian) { + /* use big endian here */ + digest[i] = *result_ptr++; + } else { + /* use little endian here */ + digest[VB2_SHA256_DIGEST_SIZE - i - 1] = *result_ptr++; + } + } + return digest; +} + +uint8_t *cb_sha256(const uint8_t *data, uint64_t len, uint8_t *digest) +{ + /* Returned the little endian SHA256 digest */ + return cb_sha256_ex(data, len, digest, 0); +} \ No newline at end of file diff --git a/src/vendorcode/eltan/security/lib/cb_sha512.c b/src/vendorcode/eltan/security/lib/cb_sha512.c new file mode 100644 index 0000000..9d713e7 --- /dev/null +++ b/src/vendorcode/eltan/security/lib/cb_sha512.c @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cryptolib.h> + +uint8_t *cb_sha512_ex(const uint8_t *data, uint64_t len, uint8_t *digest, + bool endian) +{ + int i; + const uint8_t *input_ptr; + uint8_t result[VB2_SHA512_DIGEST_SIZE]; + uint8_t *result_ptr; + uint64_t remaining_len; + struct vb2_sha512_context ctx; + + vb2_sha512_init(&ctx); + + input_ptr = data; + remaining_len = len; + + /* Process data in at most UINT32_MAX byte chunks at a time. */ + while (remaining_len) { + uint32_t block_size; + block_size = (uint32_t) ((remaining_len >= UINT32_MAX) ? + UINT32_MAX : remaining_len); + vb2_sha512_update(&ctx, input_ptr, block_size); + remaining_len -= block_size; + input_ptr += block_size; + } + + result_ptr = result; + vb2_sha512_finalize(&ctx, result_ptr); + for (i = 0; i < VB2_SHA512_DIGEST_SIZE; ++i) { + if (endian) { + /* use big endian here */ + digest[i] = *result_ptr++; + } else { + /* use little endian here */ + digest[VB2_SHA512_DIGEST_SIZE - i - 1] = *result_ptr++; + } + } + return digest; +} + +uint8_t *cb_sha512(const uint8_t *data, uint64_t len, uint8_t *digest) +{ + /* Returned the little endian SHA512 digest */ + return cb_sha512_ex(data, len, digest, 0); +} \ No newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/30831 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If828bde54c79e836a5b05ff0447645d7e06e819a Gerrit-Change-Number: 30831 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

4 18

Change in ...coreboot[master]: soc/intel/braswell/acpi/lpc.asl: Allocate used ROM size only
by Frans Hendriks (Code Review) 10 Jul '19

10 Jul '19

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31822 Change subject: soc/intel/braswell/acpi/lpc.asl: Allocate used ROM size only ...................................................................... soc/intel/braswell/acpi/lpc.asl: Allocate used ROM size only Fixed ROM area is allocated. Reduce the ROM size using CONFIG_COREBOOT_ROMSIZE. BUG=N/A TEST=Facebook FBG-1701 booting Embedded Linux Change-Id: I7a47bf2600f546271c5a65641d29f868ff2748bf Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/soc/intel/braswell/acpi/lpc.asl 1 file changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/31822/1 diff --git a/src/soc/intel/braswell/acpi/lpc.asl b/src/soc/intel/braswell/acpi/lpc.asl index 6b2ecec..a28eb38 100644 --- a/src/soc/intel/braswell/acpi/lpc.asl +++ b/src/soc/intel/braswell/acpi/lpc.asl @@ -3,7 +3,7 @@ * * Copyright (C) 2007-2009 coresystems GmbH * Copyright (C) 2013 Google Inc. - * Copyright (C) 2018 Eltan B.V. + * Copyright (C) 2018-2019 Eltan B.V. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -44,7 +44,10 @@ Name (_HID, EISAID("INT0800")) Name (_CRS, ResourceTemplate() { - Memory32Fixed(ReadOnly, 0xff000000, 0x01000000) + Memory32Fixed(ReadOnly, 0xffffffff - + (CONFIG_COREBOOT_ROMSIZE_KB*1024) + 1, + CONFIG_COREBOOT_ROMSIZE_KB*1024) + }) } -- To view, visit https://review.coreboot.org/c/coreboot/+/31822 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a47bf2600f546271c5a65641d29f868ff2748bf Gerrit-Change-Number: 31822 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

4 19

Change in ...coreboot[master]: src/arch/x86: Prevent attack on null pointer dereference
by John Zhao (Code Review) 08 Jul '19

08 Jul '19

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33051 Change subject: src/arch/x86: Prevent attack on null pointer dereference ...................................................................... src/arch/x86: Prevent attack on null pointer dereference Clang Static Analyzer version 8.0.0 detects null pointer argument in call to memory copy function. Add sanity check for pointer header to prevent null pointer dereference. TEST=Built and boot up to kernel. Change-Id: I7027b7cae3009a5481048bfa0536a6cbd9bef683 Signed-off-by: John Zhao <john.zhao(a)intel.com> --- M src/arch/x86/acpi.c 1 file changed, 52 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/33051/1 diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index d1dcd03..97190d2 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -218,6 +218,9 @@ memset((void *)madt, 0, sizeof(acpi_madt_t)); + if (!header) + return; + /* Fill out header fields. */ memcpy(header->signature, "APIC", 4); memcpy(header->oem_id, OEM_ID, 6); @@ -248,6 +251,9 @@ memset((void *)mcfg, 0, sizeof(acpi_mcfg_t)); + if (!header) + return; + /* Fill out header fields. */ memcpy(header->signature, "MCFG", 4); memcpy(header->oem_id, OEM_ID, 6); @@ -302,6 +308,9 @@ if (!lasa) return; + if (!header) + return; + /* Fill out header fields. */ memcpy(header->signature, "TCPA", 4); memcpy(header->oem_id, OEM_ID, 6); @@ -361,6 +370,9 @@ if (!lasa) tpm2_log_len = 0; + if (!header) + return; + /* Fill out header fields. */ memcpy(header->signature, "TPM2", 4); memcpy(header->oem_id, OEM_ID, 6); @@ -481,6 +493,9 @@ memset((void *)srat, 0, sizeof(acpi_srat_t)); + if (!header) + return; + /* Fill out header fields. */ memcpy(header->signature, "SRAT", 4); memcpy(header->oem_id, OEM_ID, 6); @@ -508,6 +523,9 @@ memset((void *)dmar, 0, sizeof(acpi_dmar_t)); + if (!header) + return; + /* Fill out header fields. */ memcpy(header->signature, "DMAR", 4); memcpy(header->oem_id, OEM_ID, 6); @@ -669,6 +687,9 @@ memset((void *)slit, 0, sizeof(acpi_slit_t)); + if (!header) + return; + /* Fill out header fields. */ memcpy(header->signature, "SLIT", 4); memcpy(header->oem_id, OEM_ID, 6); @@ -694,6 +715,9 @@ memset((void *)hpet, 0, sizeof(acpi_hpet_t)); + if (!header) + return; + /* Fill out header fields. */ memcpy(header->signature, "HPET", 4); memcpy(header->oem_id, OEM_ID, 6); @@ -728,6 +752,9 @@ memset((void *)vfct, 0, sizeof(struct acpi_vfct)); + if (!header) + return; + /* Fill out header fields. */ memcpy(header->signature, "VFCT", 4); memcpy(header->oem_id, OEM_ID, 6); @@ -754,6 +781,9 @@ memset((void *)ivrs, 0, sizeof(acpi_ivrs_t)); + if (!header) + return; + /* Fill out header fields. */ memcpy(header->signature, "IVRS", 4); memcpy(header->oem_id, OEM_ID, 6); @@ -807,6 +837,10 @@ current = (uintptr_t)dbg2; memset(dbg2, 0, sizeof(acpi_dbg2_header_t)); header = &(dbg2->header); + + if (!header) + return; + header->revision = get_acpi_table_revision(DBG2); memcpy(header->signature, "DBG2", 4); memcpy(header->oem_id, OEM_ID, 6); @@ -926,6 +960,9 @@ { acpi_header_t *header = &(rsdt->header); + if (!header) + return; + /* Fill out header fields. */ memcpy(header->signature, "RSDT", 4); memcpy(header->oem_id, oem_id, 6); @@ -946,6 +983,9 @@ { acpi_header_t *header = &(xsdt->header); + if (!header) + return; + /* Fill out header fields. */ memcpy(header->signature, "XSDT", 4); memcpy(header->oem_id, oem_id, 6); @@ -1046,7 +1086,8 @@ memcpy(pos, data, data_len); len += data_len; - header->length += len; + if(header) + header->length += len; return len; } @@ -1058,6 +1099,9 @@ acpi_header_t *header = &(hest->header); memset(hest, 0, sizeof(acpi_hest_t)); + + if (!header) + return; memcpy(header->signature, "HEST", 4); memcpy(header->oem_id, OEM_ID, 6); @@ -1080,6 +1124,9 @@ memset(bert, 0, sizeof(acpi_bert_t)); + if (!header) + return; + memcpy(header->signature, "BERT", 4); memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); @@ -1101,6 +1148,10 @@ acpi_header_t *header = &(fadt->header); memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + + if (!header) + return; + memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); header->revision = get_acpi_table_revision(FADT); -- To view, visit https://review.coreboot.org/c/coreboot/+/33051 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7027b7cae3009a5481048bfa0536a6cbd9bef683 Gerrit-Change-Number: 33051 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

5 7

Change in ...coreboot[master]: sb/intel/lynxpoint: Use common final SPI OPs setup
by Arthur Heymans (Code Review) 08 Jul '19

08 Jul '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33039 Change subject: sb/intel/lynxpoint: Use common final SPI OPs setup ...................................................................... sb/intel/lynxpoint: Use common final SPI OPs setup Change-Id: I12e238b3a33c909103986822bd7398e1c3bac676 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/lynxpoint/lpc.c 1 file changed, 2 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/33039/1 diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index b0f57c1..4efb83e 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -36,6 +36,7 @@ #include <drivers/intel/gma/i915.h> #include <southbridge/intel/common/acpi_pirq_gen.h> #include <southbridge/intel/common/rtc.h> +#include <southbridge/intel/common/spi.h> #define NMI_OFF 0 @@ -960,10 +961,7 @@ static void lpc_final(struct device *dev) { - RCBA16(0x3894) = SPI_OPPREFIX; - RCBA16(0x3896) = SPI_OPTYPE; - RCBA32(0x3898) = SPI_OPMENU_LOWER; - RCBA32(0x389c) = SPI_OPMENU_UPPER; + spi_finalize_ops(); if (acpi_is_wakeup_s3() || CONFIG(INTEL_CHIPSET_LOCKDOWN)) outb(APM_CNT_FINALIZE, APM_CNT); -- To view, visit https://review.coreboot.org/c/coreboot/+/33039 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12e238b3a33c909103986822bd7398e1c3bac676 Gerrit-Change-Number: 33039 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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