coreboot-gerrit May 2019

coreboot-gerrit@coreboot.org

1 participants
1485 discussions

Change in ...coreboot[master]: google/kukui: Enable config for coreboot display
by yongqiang niu (Code Review) 31 Jul '19

31 Jul '19

yongqiang niu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31521 Change subject: google/kukui: Enable config for coreboot display ...................................................................... google/kukui: Enable config for coreboot display BUG=b:80501386,b:117254947 BRANCH=none TEST=Boots correctly on Kukui Change-Id: I478e06686158dd77b075bcef8a41763ae26c79f9 Signed-off-by: Yongqiang Niu <yongqiang.niu(a)mediatek.com> --- M src/mainboard/google/kukui/Kconfig 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/31521/1 diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig index 9f477e5..9d2634a 100644 --- a/src/mainboard/google/kukui/Kconfig +++ b/src/mainboard/google/kukui/Kconfig @@ -37,6 +37,9 @@ select EC_GOOGLE_CHROMEEC_SPI select MAINBOARD_HAS_SPI_TPM_CR50 if VBOOT select MAINBOARD_HAS_TPM2 if VBOOT + select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_FORCE_NATIVE_VGA_INIT + select HAVE_LINEAR_FRAMEBUFFER config MAINBOARD_DIR string -- To view, visit https://review.coreboot.org/c/coreboot/+/31521 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I478e06686158dd77b075bcef8a41763ae26c79f9 Gerrit-Change-Number: 31521 Gerrit-PatchSet: 1 Gerrit-Owner: yongqiang niu <yongqiang.niu(a)mediatek.com> Gerrit-MessageType: newchange

4 6

Change in ...coreboot[master]: payloads/external: add opensbi for risc-v
by Xiang Wang (Code Review) 29 Jul '19

29 Jul '19

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32393 Change subject: payloads/external: add opensbi for risc-v ...................................................................... payloads/external: add opensbi for risc-v Change-Id: I501584ed0dc1dc528ea2e95e1b93b32b71a470d7 Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- A payloads/external/opensbi/COPYING.BSD A payloads/external/opensbi/Makefile A payloads/external/opensbi/README.md A payloads/external/opensbi/docs/contributing.md A payloads/external/opensbi/docs/doxygen.cfg A payloads/external/opensbi/docs/firmware/fw.md A payloads/external/opensbi/docs/firmware/fw_jump.md A payloads/external/opensbi/docs/firmware/fw_payload.md A payloads/external/opensbi/docs/firmware/payload_linux.md A payloads/external/opensbi/docs/firmware/payload_uboot.md A payloads/external/opensbi/docs/library_usage.md A payloads/external/opensbi/docs/platform/platform.md A payloads/external/opensbi/docs/platform/qemu_sifive_u.md A payloads/external/opensbi/docs/platform/qemu_virt.md A payloads/external/opensbi/docs/platform/sifive_fu540.md A payloads/external/opensbi/docs/platform_guide.md A payloads/external/opensbi/firmware/external_deps.mk A payloads/external/opensbi/firmware/fw_base.S A payloads/external/opensbi/firmware/fw_base.ldS A payloads/external/opensbi/firmware/fw_jump.S A payloads/external/opensbi/firmware/fw_jump.elf.ldS A payloads/external/opensbi/firmware/fw_payload.S A payloads/external/opensbi/firmware/fw_payload.elf.ldS A payloads/external/opensbi/firmware/objects.mk A payloads/external/opensbi/firmware/payloads/objects.mk A payloads/external/opensbi/firmware/payloads/test.elf.ldS A payloads/external/opensbi/firmware/payloads/test_head.S A payloads/external/opensbi/firmware/payloads/test_main.c A payloads/external/opensbi/include/sbi/riscv_asm.h A payloads/external/opensbi/include/sbi/riscv_atomic.h A payloads/external/opensbi/include/sbi/riscv_barrier.h A payloads/external/opensbi/include/sbi/riscv_encoding.h A payloads/external/opensbi/include/sbi/riscv_fp.h A payloads/external/opensbi/include/sbi/riscv_io.h A payloads/external/opensbi/include/sbi/riscv_locks.h A payloads/external/opensbi/include/sbi/sbi_bitops.h A payloads/external/opensbi/include/sbi/sbi_bits.h A payloads/external/opensbi/include/sbi/sbi_console.h A payloads/external/opensbi/include/sbi/sbi_const.h A payloads/external/opensbi/include/sbi/sbi_ecall.h A payloads/external/opensbi/include/sbi/sbi_ecall_interface.h A payloads/external/opensbi/include/sbi/sbi_emulate_csr.h A payloads/external/opensbi/include/sbi/sbi_error.h A payloads/external/opensbi/include/sbi/sbi_hart.h A payloads/external/opensbi/include/sbi/sbi_illegal_insn.h A payloads/external/opensbi/include/sbi/sbi_init.h A payloads/external/opensbi/include/sbi/sbi_ipi.h A payloads/external/opensbi/include/sbi/sbi_misaligned_ldst.h A payloads/external/opensbi/include/sbi/sbi_platform.h A payloads/external/opensbi/include/sbi/sbi_scratch.h A payloads/external/opensbi/include/sbi/sbi_system.h A payloads/external/opensbi/include/sbi/sbi_timer.h A payloads/external/opensbi/include/sbi/sbi_trap.h A payloads/external/opensbi/include/sbi/sbi_types.h A payloads/external/opensbi/include/sbi/sbi_unpriv.h A payloads/external/opensbi/include/sbi/sbi_version.h A payloads/external/opensbi/lib/objects.mk A payloads/external/opensbi/lib/riscv_asm.c A payloads/external/opensbi/lib/riscv_atomic.c A payloads/external/opensbi/lib/riscv_hardfp.S A payloads/external/opensbi/lib/riscv_locks.c A payloads/external/opensbi/lib/sbi_console.c A payloads/external/opensbi/lib/sbi_ecall.c A payloads/external/opensbi/lib/sbi_emulate_csr.c A payloads/external/opensbi/lib/sbi_hart.c A payloads/external/opensbi/lib/sbi_illegal_insn.c A payloads/external/opensbi/lib/sbi_init.c A payloads/external/opensbi/lib/sbi_ipi.c A payloads/external/opensbi/lib/sbi_misaligned_ldst.c A payloads/external/opensbi/lib/sbi_system.c A payloads/external/opensbi/lib/sbi_timer.c A payloads/external/opensbi/lib/sbi_trap.c A payloads/external/opensbi/platform/common/include/plat/irqchip/plic.h A payloads/external/opensbi/platform/common/include/plat/serial/sifive-uart.h A payloads/external/opensbi/platform/common/include/plat/serial/uart8250.h A payloads/external/opensbi/platform/common/include/plat/string.h A payloads/external/opensbi/platform/common/include/plat/sys/clint.h A payloads/external/opensbi/platform/common/include/plat/tinyfdt.h A payloads/external/opensbi/platform/common/irqchip/objects.mk A payloads/external/opensbi/platform/common/irqchip/plic.c A payloads/external/opensbi/platform/common/libc/objects.mk A payloads/external/opensbi/platform/common/libc/string.c A payloads/external/opensbi/platform/common/libfdt/Makefile.libfdt A payloads/external/opensbi/platform/common/libfdt/TODO A payloads/external/opensbi/platform/common/libfdt/fdt.c A payloads/external/opensbi/platform/common/libfdt/fdt.h A payloads/external/opensbi/platform/common/libfdt/fdt_addresses.c A payloads/external/opensbi/platform/common/libfdt/fdt_empty_tree.c A payloads/external/opensbi/platform/common/libfdt/fdt_overlay.c A payloads/external/opensbi/platform/common/libfdt/fdt_ro.c A payloads/external/opensbi/platform/common/libfdt/fdt_rw.c A payloads/external/opensbi/platform/common/libfdt/fdt_strerror.c A payloads/external/opensbi/platform/common/libfdt/fdt_sw.c A payloads/external/opensbi/platform/common/libfdt/fdt_wip.c A payloads/external/opensbi/platform/common/libfdt/libfdt.h A payloads/external/opensbi/platform/common/libfdt/libfdt_env.h A payloads/external/opensbi/platform/common/libfdt/libfdt_internal.h A payloads/external/opensbi/platform/common/libfdt/objects.mk A payloads/external/opensbi/platform/common/libfdt/version.lds A payloads/external/opensbi/platform/common/objects.mk A payloads/external/opensbi/platform/common/serial/objects.mk A payloads/external/opensbi/platform/common/serial/sifive-uart.c A payloads/external/opensbi/platform/common/serial/uart8250.c A payloads/external/opensbi/platform/common/sys/clint.c A payloads/external/opensbi/platform/common/sys/objects.mk A payloads/external/opensbi/platform/common/tinyfdt.c A payloads/external/opensbi/platform/kendryte/k210/config.mk A payloads/external/opensbi/platform/kendryte/k210/k210.dts A payloads/external/opensbi/platform/kendryte/k210/objects.mk A payloads/external/opensbi/platform/kendryte/k210/platform.c A payloads/external/opensbi/platform/kendryte/k210/platform.h A payloads/external/opensbi/platform/kendryte/k210/sysctl.c A payloads/external/opensbi/platform/kendryte/k210/sysctl.h A payloads/external/opensbi/platform/kendryte/k210/uarths.c A payloads/external/opensbi/platform/kendryte/k210/uarths.h A payloads/external/opensbi/platform/qemu/sifive_u/config.mk A payloads/external/opensbi/platform/qemu/sifive_u/objects.mk A payloads/external/opensbi/platform/qemu/sifive_u/platform.c A payloads/external/opensbi/platform/qemu/virt/config.mk A payloads/external/opensbi/platform/qemu/virt/objects.mk A payloads/external/opensbi/platform/qemu/virt/platform.c A payloads/external/opensbi/platform/sifive/fu540/HiFiveUnleashed-MicroSemi-Expansion.dts A payloads/external/opensbi/platform/sifive/fu540/config.mk A payloads/external/opensbi/platform/sifive/fu540/objects.mk A payloads/external/opensbi/platform/sifive/fu540/platform.c A payloads/external/opensbi/platform/template/config.mk A payloads/external/opensbi/platform/template/objects.mk A payloads/external/opensbi/platform/template/platform.c A payloads/external/opensbi/scripts/create-binary-archive.sh 129 files changed, 20,462 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/32393/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/32393 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I501584ed0dc1dc528ea2e95e1b93b32b71a470d7 Gerrit-Change-Number: 32393 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-MessageType: newchange

2 7

Change in ...coreboot[master]: payloads/external/opensbi: fix to boot for fu540
by Xiang Wang (Code Review) 29 Jul '19

29 Jul '19

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32395 Change subject: payloads/external/opensbi: fix to boot for fu540 ...................................................................... payloads/external/opensbi: fix to boot for fu540 1. Fix link address to prevent conflict with coreboot 2. Correct source fdt alignment to prevent copy errors Change-Id: I3477dd8fd44026753c061f34c060700bbcda4f4b Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M payloads/external/opensbi/firmware/fw_base.S M payloads/external/opensbi/platform/sifive/fu540/config.mk 2 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/32395/1 diff --git a/payloads/external/opensbi/firmware/fw_base.S b/payloads/external/opensbi/firmware/fw_base.S index 3bf7c6a..ffd9878 100644 --- a/payloads/external/opensbi/firmware/fw_base.S +++ b/payloads/external/opensbi/firmware/fw_base.S @@ -113,7 +113,7 @@ */ beqz a1, _fdt_reloc_done /* Mask values in a3 and a4 */ - li a3, ~0xf + li a3, ~(__SIZEOF_POINTER__ - 1) li a4, 0xff /* t1 = destination FDT start address */ add s0, a0, zero diff --git a/payloads/external/opensbi/platform/sifive/fu540/config.mk b/payloads/external/opensbi/platform/sifive/fu540/config.mk index 352c156..18a2c37 100644 --- a/payloads/external/opensbi/platform/sifive/fu540/config.mk +++ b/payloads/external/opensbi/platform/sifive/fu540/config.mk @@ -19,13 +19,13 @@ PLATFORM_SYS_CLINT=y # Blobs to build -FW_TEXT_START=0x80000000 +FW_TEXT_START=0x82000000 FW_JUMP=y -FW_JUMP_ADDR=0x80200000 -FW_JUMP_FDT_ADDR=0x82200000 +FW_JUMP_ADDR=0x82200000 +FW_JUMP_FDT_ADDR=0x84200000 FW_PAYLOAD=y FW_PAYLOAD_OFFSET=0x200000 -FW_PAYLOAD_FDT_ADDR=0x82200000 +FW_PAYLOAD_FDT_ADDR=0x84200000 # External Libraries to include PLATFORM_INCLUDE_LIBFDT=y -- To view, visit https://review.coreboot.org/c/coreboot/+/32395 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3477dd8fd44026753c061f34c060700bbcda4f4b Gerrit-Change-Number: 32395 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-MessageType: newchange

1 1

Change in ...coreboot[master]: google/kukui: Init SSPM
by Erin Lo (Code Review) 26 Jul '19

26 Jul '19

Erin Lo has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31835 Change subject: google/kukui: Init SSPM ...................................................................... google/kukui: Init SSPM Load SSPM firmware and boot up SSPM. BUG=b:80501386 BRANCH=none Test=We can see "sspm is alive" in ATF stage if SSPM enabled and ipi success Change-Id: I9285034fc8ce38b40134f5eb7b986a663175e620 Signed-off-by: Erin Lo <erin.lo(a)mediatek.com> --- M src/mainboard/google/kukui/Makefile.inc M src/mainboard/google/kukui/mainboard.c 2 files changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/31835/1 diff --git a/src/mainboard/google/kukui/Makefile.inc b/src/mainboard/google/kukui/Makefile.inc index a0556c1..807a11d 100644 --- a/src/mainboard/google/kukui/Makefile.inc +++ b/src/mainboard/google/kukui/Makefile.inc @@ -25,3 +25,8 @@ ramstage-y += mainboard.c ramstage-y += memlayout.ld ramstage-y += reset.c + +cbfs-files-y += sspm.bin +sspm.bin-file := 3rdparty/blobs/mainboard/google/kukui/sspm.bin +sspm.bin-type := raw +sspm.bin-compression := $(CBFS_COMPRESS_FLAG) diff --git a/src/mainboard/google/kukui/mainboard.c b/src/mainboard/google/kukui/mainboard.c index e1d8f5f..6447223 100644 --- a/src/mainboard/google/kukui/mainboard.c +++ b/src/mainboard/google/kukui/mainboard.c @@ -16,6 +16,7 @@ #include <device/device.h> #include <soc/gpio.h> #include <soc/mmu_operations.h> +#include <soc/sspm.h> #include <soc/usb.h> static void configure_emmc(void) @@ -41,6 +42,7 @@ { configure_emmc(); configure_usb(); + sspm_init(); } static void mainboard_enable(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/31835 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9285034fc8ce38b40134f5eb7b986a663175e620 Gerrit-Change-Number: 31835 Gerrit-PatchSet: 1 Gerrit-Owner: Erin Lo <erin.lo(a)mediatek.com> Gerrit-MessageType: newchange

7 29

Change in ...coreboot[master]: crossgcc: Add nasm to toolchain
by Martin Roth (Code Review) 25 Jul '19

25 Jul '19

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33024 Change subject: crossgcc: Add nasm to toolchain ...................................................................... crossgcc: Add nasm to toolchain Tianocore payload uses nasm. Supply it in the coreboot toolchain instead of relying on system version. Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: I086cbe6c46f7c09b2a7a83e177b32fd1bdf99266 --- M util/crossgcc/Makefile M util/crossgcc/Makefile.inc M util/crossgcc/buildgcc A util/crossgcc/sum/nasm-2.14.02.tar.bz2.cksum 4 files changed, 34 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/33024/1 diff --git a/util/crossgcc/Makefile b/util/crossgcc/Makefile index a8ea815..e7cee98 100644 --- a/util/crossgcc/Makefile +++ b/util/crossgcc/Makefile @@ -10,12 +10,12 @@ all all_with_gdb: $(MAKE) build-i386 build-x64 build-arm build-mips \ build-riscv build-aarch64 build-ppc64 build-nds32le \ - build_clang build_iasl build_make + build_clang build_iasl build_make build_nasm all_without_gdb: $(MAKE) SKIP_GDB=1 build-i386 build-x64 build-arm build-mips \ build-riscv build-aarch64 build-ppc64 build-nds32le \ - build_clang build_iasl build_make + build_clang build_iasl build_make build_nasm build_tools: build_gcc build_gdb @@ -43,6 +43,9 @@ build_make: bash ./buildgcc -P make $(if $(CPUS),-j $(CPUS)) $(if $(KEEP_SOURCES),-t) $(BUILDGCC_OPTIONS) -d $(DEST) +build_nasm: + bash ./buildgcc -P nasm $(if $(CPUS),-j $(CPUS)) $(if $(KEEP_SOURCES),-t) $(BUILDGCC_OPTIONS) -d $(DEST) + ########################################################### build-i386: @$(MAKE) build_tools BUILD_PLATFORM=i386-elf @@ -86,5 +89,6 @@ .PHONY: build_gcc build_iasl build_gdb build_clang all all_with_gdb \ all_without_gdb build_tools build-i386 build-x64 build-arm \ build-aarch64 build-mips build-riscv build-ppc64 build-nds32le \ + build-nasm \ clean distclean clean_tempfiles .NOTPARALLEL: diff --git a/util/crossgcc/Makefile.inc b/util/crossgcc/Makefile.inc index 8f8257c..0ef6b9c 100644 --- a/util/crossgcc/Makefile.inc +++ b/util/crossgcc/Makefile.inc @@ -23,6 +23,7 @@ @echo ' iasl - Build coreboot IASL compiler (built by all cross targets)' @echo ' clang - Build coreboot clang compiler' @echo ' gnumake - Build coreboot make' + @echo ' nasm - Build coreboot nasm' @echo ' test-toolchain - Reports if toolchain components are out of date' @echo ' crossgcc-ARCH - Build cross-compiler for specific architecture' @echo ' crosstools-ARCH - Build cross-compiler with GDB for specific architecture' @@ -41,7 +42,7 @@ crossgcc-mips crossgcc-riscv crossgcc-power8 crossgcc-clean iasl \ clang crosstools-i386 crosstools-x64 crosstools-arm \ crosstools-aarch64 crosstools-mips crosstools-riscv crosstools-power8 \ - jenkins-build-toolchain gnumake + jenkins-build-toolchain gnumake nasm $(foreach arch,$(TOOLCHAIN_ARCHES),crossgcc-$(arch)): clean-for-update $(MAKE) -C util/crossgcc $(patsubst crossgcc-%,build-%,$@) build_iasl SKIP_GDB=1 @@ -58,6 +59,9 @@ gnumake: clean-for-update $(MAKE) -C util/crossgcc build_make +nasm: clean-for-update + $(MAKE) -C util/crossgcc build_nasm + $(foreach arch,$(TOOLCHAIN_ARCHES),crosstools-$(arch)): clean-for-update $(MAKE) -C util/crossgcc $(patsubst crosstools-%,build-%,$@) build_iasl diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 327027a..9280032 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -61,6 +61,7 @@ CLANG_VERSION=8.0.0 MAKE_VERSION=4.2.1 CMAKE_VERSION=3.14.2 +NASM_VERSION=2.14.02 # GCC toolchain archive locations # These are sanitized by the jenkins toolchain test builder, so if @@ -82,11 +83,13 @@ CTE_ARCHIVE="https://releases.llvm.org/${CLANG_VERSION}/clang-tools-extra-${CLANG_VERSIO…" MAKE_ARCHIVE="https://ftpmirror.gnu.org/make/make-${MAKE_VERSION}.tar.bz2" CMAKE_ARCHIVE="https://cmake.org/files/v3.14/cmake-${CMAKE_VERSION}.tar.gz" +NASM_ARCHIVE="https://www.nasm.us/pub/nasm/releasebuilds/${NASM_VERSION}/nasm-${NASM_VERS…" ALL_ARCHIVES="$GMP_ARCHIVE $MPFR_ARCHIVE $MPC_ARCHIVE \ $GCC_ARCHIVE $BINUTILS_ARCHIVE $GDB_ARCHIVE $IASL_ARCHIVE \ $PYTHON_ARCHIVE $EXPAT_ARCHIVE $LLVM_ARCHIVE $CFE_ARCHIVE \ - $CRT_ARCHIVE $CTE_ARCHIVE $MAKE_ARCHIVE $CMAKE_ARCHIVE" + $CRT_ARCHIVE $CTE_ARCHIVE $MAKE_ARCHIVE $CMAKE_ARCHIVE \ + $NASM_ARCHIVE" # GCC toolchain directories GMP_DIR="gmp-${GMP_VERSION}" @@ -107,6 +110,7 @@ CTE_DIR="clang-tools-extra-${CLANG_VERSION}.src" MAKE_DIR="make-${MAKE_VERSION}" CMAKE_DIR="cmake-${CMAKE_VERSION}" +NASM_DIR="nasm-${NASM_VERSION}" unset MAKELEVEL MAKEFLAGS @@ -910,6 +914,17 @@ normalize_dirs } +build_NASM() { + CC="$(hostcc host)" CXX="$(hostcxx host)" CFLAGS="$HOSTCFLAGS" + ../${NASM_DIR}/configure --prefix="$TARGETDIR" \ + || touch .failed + # shellcheck disable=SC2086 + $MAKE $JOBS || touch .failed + $MAKE install DESTDIR=$DESTDIR || touch .failed + + normalize_dirs +} + print_supported() { case "$PRINTSUPPORTED" in AUTOCONF|autoconf) printf "%s\n" "$GCC_AUTOCONF_VERSION";; @@ -924,6 +939,7 @@ MPFR|mpfr) printf "%s\n" "$MPFR_VERSION";; PYTHON|python) printf "%s\n" "$PYTHON_VERSION";; MAKE|make) printf "%s\n" "$MAKE_VERSION";; + NASM|nasm) printf "%s\n" "${NASM_VERSION}";; *) printf "Unknown tool %s\n" "$PRINTSUPPORTED";; esac } @@ -1044,8 +1060,12 @@ NAME="CMake" PACKAGES=CMAKE ;; + NASM|nasm) + NAME="NASM" + PACKAGES=NASM + ;; *) - printf "${red}ERROR: Unsupported package $PACKAGE. (Supported packages are GCC, GDB, CLANG, IASL, MAKE)${NC}\n\n"; + printf "${red}ERROR: Unsupported package $PACKAGE. (Supported packages are GCC, GDB, CLANG, IASL, MAKE, and NASM)${NC}\n\n"; exit 1 ;; esac diff --git a/util/crossgcc/sum/nasm-2.14.02.tar.bz2.cksum b/util/crossgcc/sum/nasm-2.14.02.tar.bz2.cksum new file mode 100644 index 0000000..f3b9de9 --- /dev/null +++ b/util/crossgcc/sum/nasm-2.14.02.tar.bz2.cksum @@ -0,0 +1 @@ +fe098ee4dc9c4c983696c4948e64b23e4098b92b tarballs/nasm-2.14.02.tar.bz2 -- To view, visit https://review.coreboot.org/c/coreboot/+/33024 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I086cbe6c46f7c09b2a7a83e177b32fd1bdf99266 Gerrit-Change-Number: 33024 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

5 11

Change in ...coreboot[master]: crossgcc: Upgrade CMake to 3.14.4
by HAOUAS Elyes (Code Review) 25 Jul '19

25 Jul '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33053 Change subject: crossgcc: Upgrade CMake to 3.14.4 ...................................................................... crossgcc: Upgrade CMake to 3.14.4 Change: "In CMake 3.14.0 through 3.14.3, calling target_link_libraries() to add PRIVATE dependencies to a static library created in another directory (under policy CMP0079 NEW behavior) would incorrectly propagate usage requirements of those dependencies to dependents that link the static library. This has been fixed. The bug also existed in 3.13.0 through 3.13.4 and is fixed in 3.13.5." Change-Id: Ic9db9050bec45d33d56ee53e3692276494f306de Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc D util/crossgcc/sum/cmake-3.14.2.tar.gz.cksum A util/crossgcc/sum/cmake-3.14.4.tar.gz.cksum 3 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/33053/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index fd5ce43..e99e1d3 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -60,7 +60,7 @@ # CLANG version number CLANG_VERSION=8.0.0 MAKE_VERSION=4.2.1 -CMAKE_VERSION=3.14.2 +CMAKE_VERSION=3.14.4 # GCC toolchain archive locations # These are sanitized by the jenkins toolchain test builder, so if diff --git a/util/crossgcc/sum/cmake-3.14.2.tar.gz.cksum b/util/crossgcc/sum/cmake-3.14.2.tar.gz.cksum deleted file mode 100644 index 6369ac3..0000000 --- a/util/crossgcc/sum/cmake-3.14.2.tar.gz.cksum +++ /dev/null @@ -1 +0,0 @@ -94ef8e36fa93edaf6f194e0ce0065ea769b3e57c tarballs/cmake-3.14.2.tar.gz diff --git a/util/crossgcc/sum/cmake-3.14.4.tar.gz.cksum b/util/crossgcc/sum/cmake-3.14.4.tar.gz.cksum new file mode 100644 index 0000000..c292411 --- /dev/null +++ b/util/crossgcc/sum/cmake-3.14.4.tar.gz.cksum @@ -0,0 +1 @@ +c4a25807bf80ccd4219aeb75de9a822c4d07f5b8 tarballs/cmake-3.14.4.tar.gz -- To view, visit https://review.coreboot.org/c/coreboot/+/33053 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9db9050bec45d33d56ee53e3692276494f306de Gerrit-Change-Number: 33053 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 6

Change in ...coreboot[master]: crossgcc: Upgrade Python to version 3.7.3
by HAOUAS Elyes (Code Review) 25 Jul '19

25 Jul '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32077 Change subject: crossgcc: Upgrade Python to version 3.7.3 ...................................................................... crossgcc: Upgrade Python to version 3.7.3 Change-Id: I2d4a93fa43cf662685d4c439bcff04e338d51375 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc D util/crossgcc/sum/Python-3.7.2.tar.xz.cksum A util/crossgcc/sum/Python-3.7.3.tar.xz.cksum 3 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/32077/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index e901c37..1b94c33 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -55,7 +55,7 @@ BINUTILS_VERSION=2.32 GDB_VERSION=8.2.1 IASL_VERSION=20190215 -PYTHON_VERSION=3.7.2 +PYTHON_VERSION=3.7.3 EXPAT_VERSION=2.2.6 # CLANG version number CLANG_VERSION=7.0.1 diff --git a/util/crossgcc/sum/Python-3.7.2.tar.xz.cksum b/util/crossgcc/sum/Python-3.7.2.tar.xz.cksum deleted file mode 100644 index 4519f88..0000000 --- a/util/crossgcc/sum/Python-3.7.2.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -c3dc6928516bcb934cf4740461044c79c7c35494 tarballs/Python-3.7.2.tar.xz \ No newline at end of file diff --git a/util/crossgcc/sum/Python-3.7.3.tar.xz.cksum b/util/crossgcc/sum/Python-3.7.3.tar.xz.cksum new file mode 100644 index 0000000..10679ac --- /dev/null +++ b/util/crossgcc/sum/Python-3.7.3.tar.xz.cksum @@ -0,0 +1 @@ +e3584650a06ae2765da0678176deae9d133f1b3d tarballs/Python-3.7.3.tar.xz -- To view, visit https://review.coreboot.org/c/coreboot/+/32077 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d4a93fa43cf662685d4c439bcff04e338d51375 Gerrit-Change-Number: 32077 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 10

Change in ...coreboot[master]: crossgcc: Upgrade GDB to version 8.3
by HAOUAS Elyes (Code Review) 25 Jul '19

25 Jul '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32754 Change subject: crossgcc: Upgrade GDB to version 8.3 ...................................................................... crossgcc: Upgrade GDB to version 8.3 Change-Id: I7a85ad171fa259e0dcb0019941d735ef41511737 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc D util/crossgcc/patches/gdb-8.2.1_amd64.patch A util/crossgcc/patches/gdb-8.3_amd64.patch R util/crossgcc/patches/gdb-8.3_no-doc.patch R util/crossgcc/patches/gdb-8.3_pythonhome.patch D util/crossgcc/sum/gdb-8.2.1.tar.xz.cksum A util/crossgcc/sum/gdb-8.3.tar.xz.cksum 7 files changed, 16 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/32754/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 0951fb6..f2cce88 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -53,7 +53,7 @@ GCC_VERSION=8.3.0 GCC_AUTOCONF_VERSION=2.69 BINUTILS_VERSION=2.32 -GDB_VERSION=8.2.1 +GDB_VERSION=8.3 IASL_VERSION=20190215 PYTHON_VERSION=3.7.2 EXPAT_VERSION=2.2.6 diff --git a/util/crossgcc/patches/gdb-8.2.1_amd64.patch b/util/crossgcc/patches/gdb-8.2.1_amd64.patch deleted file mode 100644 index 978fa26..0000000 --- a/util/crossgcc/patches/gdb-8.2.1_amd64.patch +++ /dev/null @@ -1,14 +0,0 @@ -diff -urN gdb-8.2.1.orig/gdb/configure.tgt gdb-8.2.1/gdb/configure.tgt ---- gdb-8.2.1.orig/gdb/configure.tgt 2019-01-04 12:34:10.301072023 +0100 -+++ gdb-8.2.1/gdb/configure.tgt 2019-01-04 12:35:21.948388220 +0100 -@@ -732,6 +732,10 @@ - x86_64-*-rtems*) - gdb_target_obs="${amd64_tobjs} ${i386_tobjs} i386-bsd-tdep.o" - ;; -+x86_64-*-*) -+ # Target: amd64 -+ gdb_target_obs="amd64-tdep.o i386-tdep.o i387-tdep.o" -+ ;; - xtensa*-*-linux*) - # Target: GNU/Linux Xtensa - gdb_target_obs="xtensa-linux-tdep.o symfile-mem.o linux-tdep.o" diff --git a/util/crossgcc/patches/gdb-8.3_amd64.patch b/util/crossgcc/patches/gdb-8.3_amd64.patch new file mode 100644 index 0000000..47d9a72 --- /dev/null +++ b/util/crossgcc/patches/gdb-8.3_amd64.patch @@ -0,0 +1,14 @@ +diff -urN gdb-3.orig/gdb/configure.tgt gdb-8.3/gdb/configure.tgt +--- gdb-8.3.orig/gdb/configure.tgt 2019-02-27 05:51:48.000000000 +0100 ++++ gdb-8.3/gdb/configure.tgt 2019-05-12 08:07:45.624984535 +0200 +@@ -772,6 +772,10 @@ + x86_64-*-rtems*) + gdb_target_obs="${amd64_tobjs} ${i386_tobjs} i386-bsd-tdep.o" + ;; ++x86_64-*-*) ++ # Target: amd6 ++ gdb_target_obs="amd64-tdep.o i386-tdep.o i387-tdep.o" ++ ;; + xtensa*-*-*linux*) + # Target: GNU/Linux Xtensa + gdb_target_obs="xtensa-linux-tdep.o symfile-mem.o linux-tdep.o" diff --git a/util/crossgcc/patches/gdb-8.2.1_no-doc.patch b/util/crossgcc/patches/gdb-8.3_no-doc.patch similarity index 100% rename from util/crossgcc/patches/gdb-8.2.1_no-doc.patch rename to util/crossgcc/patches/gdb-8.3_no-doc.patch diff --git a/util/crossgcc/patches/gdb-8.2.1_pythonhome.patch b/util/crossgcc/patches/gdb-8.3_pythonhome.patch similarity index 100% rename from util/crossgcc/patches/gdb-8.2.1_pythonhome.patch rename to util/crossgcc/patches/gdb-8.3_pythonhome.patch diff --git a/util/crossgcc/sum/gdb-8.2.1.tar.xz.cksum b/util/crossgcc/sum/gdb-8.2.1.tar.xz.cksum deleted file mode 100644 index a976106..0000000 --- a/util/crossgcc/sum/gdb-8.2.1.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -023556a6d6effa1ffaadf0007cc4458cbe8dde3d tarballs/gdb-8.2.1.tar.xz diff --git a/util/crossgcc/sum/gdb-8.3.tar.xz.cksum b/util/crossgcc/sum/gdb-8.3.tar.xz.cksum new file mode 100644 index 0000000..bc82f51 --- /dev/null +++ b/util/crossgcc/sum/gdb-8.3.tar.xz.cksum @@ -0,0 +1 @@ +f45de6af561f0fa0241f0d5085198556fcfd1e5e tarballs/gdb-8.3.tar.xz -- To view, visit https://review.coreboot.org/c/coreboot/+/32754 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a85ad171fa259e0dcb0019941d735ef41511737 Gerrit-Change-Number: 32754 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 4

Change in ...coreboot[master]: coreboot: add md power off flow
by Yanjie Jiang (Code Review) 23 Jul '19

23 Jul '19

Yanjie Jiang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32666 Change subject: coreboot: add md power off flow ...................................................................... coreboot: add md power off flow Change-Id: Ib6e11faeb6936a1dd6bbe8b1a8b612446bf51082 --- M src/soc/mediatek/mt8183/Makefile.inc A src/soc/mediatek/mt8183/include/soc/md_ctrl.h A src/soc/mediatek/mt8183/md_ctrl.c M src/soc/mediatek/mt8183/mt8183.c 4 files changed, 67 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/32666/1 diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc old mode 100644 new mode 100755 index 5392a9e..ca7d521 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -9,6 +9,7 @@ bootblock-y += ../common/timer.c bootblock-y += ../common/uart.c bootblock-y += ../common/wdt.c +bootblock-y += md_ctrl.c decompressor-y += decompressor.c decompressor-y += ../common/mmu_operations.c @@ -21,6 +22,7 @@ verstage-y += ../common/timer.c verstage-y += ../common/uart.c verstage-y += ../common/wdt.c +verstage-y += md_ctrl.c romstage-y += auxadc.c romstage-y += ../common/cbmem.c emi.c @@ -39,6 +41,7 @@ romstage-y += ../common/timer.c romstage-y += ../common/uart.c romstage-y += ../common/wdt.c +romstage-y += md_ctrl.c ramstage-y += auxadc.c ramstage-y += ../common/cbmem.c emi.c diff --git a/src/soc/mediatek/mt8183/include/soc/md_ctrl.h b/src/soc/mediatek/mt8183/include/soc/md_ctrl.h new file mode 100755 index 0000000..534de9b --- /dev/null +++ b/src/soc/mediatek/mt8183/include/soc/md_ctrl.h @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2019 MediaTek Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_MEDIATEK_MD_POWER_H__ +#define __SOC_MEDIATEK_MD_POWER_H__ + +void mtk_md_early_init(void); + +#endif \ No newline at end of file diff --git a/src/soc/mediatek/mt8183/md_ctrl.c b/src/soc/mediatek/mt8183/md_ctrl.c new file mode 100755 index 0000000..c8acb1f --- /dev/null +++ b/src/soc/mediatek/mt8183/md_ctrl.c @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2019 MediaTek Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/mmio.h> +#include <console/console.h> +#include <soc/addressmap.h> +#include <soc/infracfg.h> +#include <soc/pll.h> +#include <soc/md_ctrl.h> + +static void internal_md1_power_down(void) +{ + unsigned int reg_value; + + /* 1. md clock setting: gating */ + reg_value = read32(&mtk_topckgen->clk_mode); + reg_value |= ((1<<8)|(1<<9)); + write32(&mtk_topckgen->clk_mode, reg_value); + + /* 2. mixedsys topsm init, for release srcclkena in kernel */ + reg_value = read32(&mt8183_infracfg->infra_misc2); + reg_value &= ~0xFF; + write32(&mt8183_infracfg->infra_misc2, reg_value); + + printk(BIOS_INFO, "[ccci-off]src clk ena = 0x%X\n", + read32(&mt8183_infracfg->infra_misc2)); +} + +void mtk_md_early_init(void) +{ + internal_md1_power_down(); +} + diff --git a/src/soc/mediatek/mt8183/mt8183.c b/src/soc/mediatek/mt8183/mt8183.c old mode 100644 new mode 100755 index c441980..66038e3 --- a/src/soc/mediatek/mt8183/mt8183.c +++ b/src/soc/mediatek/mt8183/mt8183.c @@ -15,8 +15,10 @@ #include <soc/mt8183.h> #include <soc/wdt.h> +#include <soc/md_ctrl.h> void mt8183_early_init(void) { mtk_wdt_init(); + mtk_md_early_init(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/32666 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib6e11faeb6936a1dd6bbe8b1a8b612446bf51082 Gerrit-Change-Number: 32666 Gerrit-PatchSet: 1 Gerrit-Owner: Yanjie Jiang <yanjie.jiang(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newchange

7 19

Change in ...coreboot[master]: google/kukui: boot up sspm
by Erin Lo (Code Review) 22 Jul '19

22 Jul '19

Erin Lo has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31516 Change subject: google/kukui: boot up sspm ...................................................................... google/kukui: boot up sspm Load sspm firmware form cbfs and bring up it. BUG=b:80501386 BRANCH=none Test=Boots correctly on Kukui. Change-Id: I4ae6034454326f5115cd3948819adc448b67fb1c Signed-off-by: Erin Lo <erin.lo(a)mediatek.com> --- M src/mainboard/google/kukui/Kconfig M src/mainboard/google/kukui/Makefile.inc M src/mainboard/google/kukui/mainboard.c M src/soc/mediatek/mt8183/Makefile.inc M src/soc/mediatek/mt8183/include/soc/addressmap.h A src/soc/mediatek/mt8183/include/soc/sspm.h A src/soc/mediatek/mt8183/sspm.c 7 files changed, 94 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/31516/1 diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig index 9f477e5..0dcdb20 100644 --- a/src/mainboard/google/kukui/Kconfig +++ b/src/mainboard/google/kukui/Kconfig @@ -65,4 +65,8 @@ default "KUKUI TEST 9847" if BOARD_GOOGLE_KUKUI default "FLAPJACK TEST 4147" if BOARD_GOOGLE_FLAPJACK +config SSPM_BIN_FILE + string "SSPM BIN FILE" + default "" + endif diff --git a/src/mainboard/google/kukui/Makefile.inc b/src/mainboard/google/kukui/Makefile.inc index a0556c1..565c3f7 100644 --- a/src/mainboard/google/kukui/Makefile.inc +++ b/src/mainboard/google/kukui/Makefile.inc @@ -25,3 +25,8 @@ ramstage-y += mainboard.c ramstage-y += memlayout.ld ramstage-y += reset.c + +cbfs-files-y += sspm +sspm-file := $(call strip_quotes,$(CONFIG_SSPM_BIN_FILE)) +sspm-type := raw +sspm-compression :=$(CBFS_COMPRESS_FLAG) diff --git a/src/mainboard/google/kukui/mainboard.c b/src/mainboard/google/kukui/mainboard.c index e1d8f5f..5aaab8b 100644 --- a/src/mainboard/google/kukui/mainboard.c +++ b/src/mainboard/google/kukui/mainboard.c @@ -13,10 +13,13 @@ * GNU General Public License for more details. */ +#include <console/console.h> +#include <cbfs.h> #include <device/device.h> #include <soc/gpio.h> #include <soc/mmu_operations.h> #include <soc/usb.h> +#include <soc/sspm.h> static void configure_emmc(void) { @@ -37,10 +40,29 @@ setup_usb_host(); } +#define BUF_SIZE (64 * KiB) +unsigned char buf[BUF_SIZE]; + +static void sspm_boot(void) +{ + size_t fw_size = cbfs_boot_load_file("sspm", buf, sizeof(buf), + CBFS_TYPE_RAW); + + if (fw_size == 0) + printk(BIOS_DEBUG, "no sspm\n"); + else + printk(BIOS_DEBUG, "sspm[0]=%#x, [%zd]=%#x\n", + buf[0], fw_size - 1, buf[fw_size - 1]); + + sspm_init(buf, BUF_SIZE); + +} + static void mainboard_init(struct device *dev) { configure_emmc(); configure_usb(); + sspm_boot(); } static void mainboard_enable(struct device *dev) diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index 5770a83..199b22d 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -49,6 +49,7 @@ ramstage-y += ../common/uart.c ramstage-y += ../common/usb.c ramstage-y += ../common/wdt.c +ramstage-y += sspm.c CPPFLAGS_common += -Isrc/soc/mediatek/mt8183/include CPPFLAGS_common += -Isrc/soc/mediatek/common/include diff --git a/src/soc/mediatek/mt8183/include/soc/addressmap.h b/src/soc/mediatek/mt8183/include/soc/addressmap.h index d41b2b9..f812224 100644 --- a/src/soc/mediatek/mt8183/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8183/include/soc/addressmap.h @@ -34,6 +34,7 @@ EMI_BASE = IO_PHYS + 0x00219000, EMI_MPU_BASE = IO_PHYS + 0x00226000, DRAMC_CH_BASE = IO_PHYS + 0x00228000, + SSPM_BASE = IO_PHYS + 0x00440000, AUXADC_BASE = IO_PHYS + 0x01001000, UART0_BASE = IO_PHYS + 0x01002000, SPI0_BASE = IO_PHYS + 0x0100A000, diff --git a/src/soc/mediatek/mt8183/include/soc/sspm.h b/src/soc/mediatek/mt8183/include/soc/sspm.h new file mode 100644 index 0000000..f006ca2 --- /dev/null +++ b/src/soc/mediatek/mt8183/include/soc/sspm.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_MEDIATEK_MT8183_SSPM_H +#define SOC_MEDIATEK_MT8183_SSPM_H + +#include <soc/addressmap.h> +#include <types.h> + +struct mt8183_sspm_regs { + u32 sw_rstn; +}; +static struct mt8183_sspm_regs *const mt8183_sspm = (void *)SSPM_BASE; +#define CFG_SSPM_SRAM 0x10400000 +s32 sspm_init(unsigned char *buf, int len); +#endif /* SOC_MEDIATEK_MT8183_SSPM_H */ diff --git a/src/soc/mediatek/mt8183/sspm.c b/src/soc/mediatek/mt8183/sspm.c new file mode 100644 index 0000000..a42a0f5 --- /dev/null +++ b/src/soc/mediatek/mt8183/sspm.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/barrier.h> +#include <arch/io.h> +#include <soc/gpio.h> +#include <soc/sspm.h> +#include <string.h> + +#define SSPM_UART 1 +s32 sspm_init(unsigned char *buf, int len) +{ + memcpy((void*)CFG_SSPM_SRAM, buf, len); +#if SSPM_UART + gpio_set_mode(GPIO(EINT4), PAD_EINT4_FUNC_SSPM_UTXD_AO); + gpio_set_mode(GPIO(EINT5), PAD_EINT5_FUNC_SSPM_URXD_AO); +#endif + mb(); + write32(&mt8183_sspm->sw_rstn, 0x1); + return 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/31516 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ae6034454326f5115cd3948819adc448b67fb1c Gerrit-Change-Number: 31516 Gerrit-PatchSet: 1 Gerrit-Owner: Erin Lo <erin.lo(a)mediatek.com> Gerrit-MessageType: newchange

9 67

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit May 2019