coreboot-gerrit May 2019

coreboot-gerrit@coreboot.org

1 participants
1485 discussions

Change in ...coreboot[master]: sb/intel/bd82x6x/early_pch.c: Remove variable set but not used
by HAOUAS Elyes (Code Review) 21 Jun '19

21 Jun '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32943 Change subject: sb/intel/bd82x6x/early_pch.c: Remove variable set but not used ...................................................................... sb/intel/bd82x6x/early_pch.c: Remove variable set but not used Change-Id: If359eaa010949427dbff1e3a83528c0ad399dc9d Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/bd82x6x/early_pch.c 1 file changed, 15 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/32943/1 diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index e74c304..883a4aa 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -40,7 +40,6 @@ static u32 read_iobp(u32 address) { - volatile u32 tmp; u32 ret; RCBA32(IOBPIRI) = address; @@ -48,14 +47,13 @@ wait_iobp(); ret = RCBA32(IOBPD); wait_iobp(); - tmp = RCBA8(IOBPS); // call wait_iobp() instead here? + RCBA8(IOBPS); // call wait_iobp() instead here? return ret; } static void write_iobp(u32 address, u32 val) { - volatile u32 tmp; /* this function was probably pch_iobp_update with the andvalue * being 0. So either the IOBP read can be removed or this function * and the pch_iobp_update function in ramstage could be merged */ @@ -67,7 +65,7 @@ wait_iobp(); RCBA16(IOBPS) = (RCBA16(IOBPS) & 0x1ff) | 0x600; - tmp = RCBA8(IOBPS); // call wait_iobp() instead here? + RCBA8(IOBPS); // call wait_iobp() instead here? } void early_pch_init_native_dmi_pre(void) @@ -84,14 +82,12 @@ void early_pch_init_native_dmi_post(void) { - volatile u32 tmp; - - tmp = RCBA32(0x0050); // !!! = 0x01200654 + RCBA32(0x0050); // !!! = 0x01200654 RCBA32(0x0050) = 0x01200654; - tmp = RCBA32(0x0050); // !!! = 0x01200654 + RCBA32(0x0050); // !!! = 0x01200654 RCBA32(0x0050) = 0x012a0654; - tmp = RCBA32(0x0050); // !!! = 0x012a0654 - tmp = RCBA8(0x1114); // !!! = 0x00 + RCBA32(0x0050); // !!! = 0x012a0654 + RCBA8(0x1114); // !!! = 0x00 RCBA8(0x1114) = 0x05; /* @@ -118,7 +114,7 @@ */ RCBA32(0x2020) = (1 << 31) | (1 << 24) | (0x11 << 1); /* Read back register */ - tmp = RCBA32(0x2020); + RCBA32(0x2020); /* Virtual Channel private Resource Control Register. * Enable channel. @@ -127,7 +123,7 @@ */ RCBA32(0x2030) = (1 << 31) | (2 << 24) | (0x22 << 1); /* Read back register */ - tmp = RCBA32(0x2030); + RCBA32(0x2030); /* Virtual Channel ME Resource Control Register. * Enable channel. @@ -139,7 +135,7 @@ /* Lock Virtual Channel Resource control register. */ RCBA32(0x0050) |= 0x80000000; /* Read back register */ - tmp = RCBA32(0x0050); + RCBA32(0x0050); /* Wait for virtual channels negotiation pending */ while (RCBA16(0x201a) & VCNEGPND) @@ -155,24 +151,23 @@ void early_pch_init_native (void) { - volatile u32 tmp; pci_write_config8 (SOUTHBRIDGE, 0xa6, pci_read_config8 (SOUTHBRIDGE, 0xa6) | 2); RCBA32(0x2088) = 0x00109000; - tmp = RCBA32(0x20ac); // !!! = 0x00000000 + RCBA32(0x20ac); // !!! = 0x00000000 RCBA32(0x20ac) = 0x40000000; RCBA32(0x100c) = 0x01110000; RCBA8(0x2340) = 0x1b; - tmp = RCBA32(0x2314); // !!! = 0x0a080000 + RCBA32(0x2314); // !!! = 0x0a080000 RCBA32(0x2314) = 0x0a280000; - tmp = RCBA32(0x2310); // !!! = 0xc809605b + RCBA32(0x2310); // !!! = 0xc809605b RCBA32(0x2310) = 0xa809605b; RCBA32(0x2324) = 0x00854c74; - tmp = RCBA8(0x0400); // !!! = 0x00 - tmp = RCBA32(0x2310); // !!! = 0xa809605b + RCBA8(0x0400); // !!! = 0x00 + RCBA32(0x2310); // !!! = 0xa809605b RCBA32(0x2310) = 0xa809605b; - tmp = RCBA32(0x2310); // !!! = 0xa809605b + RCBA32(0x2310); // !!! = 0xa809605b RCBA32(0x2310) = 0xa809605b; write_iobp(0xea007f62, 0x00590133); -- To view, visit https://review.coreboot.org/c/coreboot/+/32943 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If359eaa010949427dbff1e3a83528c0ad399dc9d Gerrit-Change-Number: 32943 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 5

Change in ...coreboot[master]: nb/intel/nehalem/raminit.c: Remove variable set but not used
by HAOUAS Elyes (Code Review) 21 Jun '19

21 Jun '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33004 Change subject: nb/intel/nehalem/raminit.c: Remove variable set but not used ...................................................................... nb/intel/nehalem/raminit.c: Remove variable set but not used Change-Id: I5d3a04970fa57f07ca7dd748f114ac0cd6955522 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/nehalem/raminit.c 1 file changed, 3 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/33004/1 diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 5b6077f..59a4ea3 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -2235,26 +2235,11 @@ u8 lower_usable[8]; u8 upper_usable[8]; unsigned short num_successfully_checked[8]; - u8 secondary_total_rank; u8 reg1b3; + int i; - if (info->populated_ranks_mask[1]) { - if (channel == 1) - secondary_total_rank = - info->populated_ranks[1][0][0] + - info->populated_ranks[1][0][1] - + info->populated_ranks[1][1][0] + - info->populated_ranks[1][1][1]; - else - secondary_total_rank = 0; - } else - secondary_total_rank = total_rank; - - { - int i; - for (i = 0; i < 8; i++) - state[i] = BEFORE_USABLE; - } + for (i = 0; i < 8; i++) + state[i] = BEFORE_USABLE; if (!first_run) { int is_all_ok = 1; -- To view, visit https://review.coreboot.org/c/coreboot/+/33004 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d3a04970fa57f07ca7dd748f114ac0cd6955522 Gerrit-Change-Number: 33004 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 6

Change in ...coreboot[master]: cpu/intel/{haswell,model_206ax}: Use MSR_CORE_THREAD_COUNT for msr at...
by HAOUAS Elyes (Code Review) 21 Jun '19

21 Jun '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33015 Change subject: cpu/intel/{haswell,model_206ax}: Use MSR_CORE_THREAD_COUNT for msr at 0x35 ...................................................................... cpu/intel/{haswell,model_206ax}: Use MSR_CORE_THREAD_COUNT for msr at 0x35 Regarding 64 and IA-32 Architectures Software Developer’s Manual, the register name of the msr at 0x35 is MSR_CORE_THREAD_COUNT. Change-Id: I5134619dc3a42187ddd5f46c85873c4278229e27 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/intel/haswell/haswell.h M src/cpu/intel/haswell/haswell_init.c M src/cpu/intel/model_206ax/model_206ax.h M src/cpu/intel/model_206ax/model_206ax_init.c 4 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/33015/1 diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 3dfdd8d..4ebbe18 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -34,7 +34,7 @@ /* Haswell bus clock is fixed at 100MHz */ #define HASWELL_BCLK 100 -#define CORE_THREAD_COUNT_MSR 0x35 +#define MSR_CORE_THREAD_COUNT 0x35 #define MSR_FEATURE_CONFIG 0x13c #define MSR_FLEX_RATIO 0x194 #define FLEX_RATIO_LOCK (1 << 20) diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 25cf243..95d719c 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -732,7 +732,7 @@ int num_threads; int num_cores; - msr = rdmsr(CORE_THREAD_COUNT_MSR); + msr = rdmsr(MSR_CORE_THREAD_COUNT); num_threads = (msr.lo >> 0) & 0xffff; num_cores = (msr.lo >> 16) & 0xffff; printk(BIOS_DEBUG, "CPU has %u cores, %u threads enabled.\n", diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h index f4c5d93..c0d2434 100644 --- a/src/cpu/intel/model_206ax/model_206ax.h +++ b/src/cpu/intel/model_206ax/model_206ax.h @@ -22,7 +22,7 @@ /* SandyBridge/IvyBridge bus clock is fixed at 100MHz */ #define SANDYBRIDGE_BCLK 100 -#define CORE_THREAD_COUNT_MSR 0x35 +#define MSR_CORE_THREAD_COUNT 0x35 #define MSR_FEATURE_CONFIG 0x13c #define MSR_FLEX_RATIO 0x194 #define FLEX_RATIO_LOCK (1 << 20) diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 524e49c..80d85f3 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -513,7 +513,7 @@ int num_threads; int num_cores; - msr = rdmsr(CORE_THREAD_COUNT_MSR); + msr = rdmsr(MSR_CORE_THREAD_COUNT); num_threads = (msr.lo >> 0) & 0xffff; num_cores = (msr.lo >> 16) & 0xffff; printk(BIOS_DEBUG, "CPU has %u cores, %u threads enabled.\n", -- To view, visit https://review.coreboot.org/c/coreboot/+/33015 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5134619dc3a42187ddd5f46c85873c4278229e27 Gerrit-Change-Number: 33015 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 10

Change in ...coreboot[master]: cpu/x86/msr: Move IA32_MISC_ENABLE bits to common place
by HAOUAS Elyes (Code Review) 21 Jun '19

21 Jun '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31193 Change subject: cpu/x86/msr: Move IA32_MISC_ENABLE bits to common place ...................................................................... cpu/x86/msr: Move IA32_MISC_ENABLE bits to common place Change-Id: I51aa300358013cb0e76704feb2115d2a7e260f8a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/include/cpu/x86/msr.h M src/soc/intel/denverton_ns/include/soc/msr.h 2 files changed, 2 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/31193/1 diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index 31c921d..733205a 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -37,6 +37,8 @@ #define IA32_PERF_CTL 0x199 #define IA32_THERM_INTERRUPT 0x19b #define IA32_MISC_ENABLE 0x1a0 +#define FAST_STRINGS_ENABLE_BIT (1 << 0) +#define SPEED_STEP_ENABLE_BIT (1 << 16) #define IA32_ENERGY_PERF_BIAS 0x1b0 #define ENERGY_POLICY_PERFORMANCE 0 #define ENERGY_POLICY_NORMAL 6 diff --git a/src/soc/intel/denverton_ns/include/soc/msr.h b/src/soc/intel/denverton_ns/include/soc/msr.h index 1b27eef..0d469c4 100644 --- a/src/soc/intel/denverton_ns/include/soc/msr.h +++ b/src/soc/intel/denverton_ns/include/soc/msr.h @@ -96,10 +96,6 @@ #define SMRR_SUPPORTED (1 << 11) #define PRMRR_SUPPORTED (1 << 12) -/* IA32_MISC_ENABLE bits */ -#define FAST_STRINGS_ENABLE_BIT (1 << 0) -#define SPEED_STEP_ENABLE_BIT (1 << 16) - /* Read BCLK from MSR */ unsigned int bus_freq_khz(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/31193 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51aa300358013cb0e76704feb2115d2a7e260f8a Gerrit-Change-Number: 31193 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

5 8

Change in ...coreboot[master]: x86/smmstub: Fix compiling with external toolchains
by Arthur Heymans (Code Review) 21 Jun '19

21 Jun '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30504 Change subject: x86/smmstub: Fix compiling with external toolchains ...................................................................... x86/smmstub: Fix compiling with external toolchains Change-Id: I298d24d54b8fb27da96257ccda65b7fbee988ebb Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/smm/Makefile.inc 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/30504/1 diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index 32f5ea7..e6add1d 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -47,8 +47,8 @@ # SMM Stub Module. The stub is used as a trampoline for relocation and normal # SMM handling. -$(obj)/smmstub/smmstub.o: $$(smmstub-objs) - $(CC_smmstub) $(CFLAGS_smmstub) -nostdlib -r -o $@ $^ +$(obj)/smmstub/smmstub.o: $$(smmstub-objs) $(COMPILER_RT_smmstub) + $(LD_smmstub) -nostdlib -r -o $@ $(COMPILER_RT_FLAGS_smmstub) --whole-archive --start-group $(smmstub-objs) --no-whole-archive $(COMPILER_RT_smmstub) --end-group # Link the SMM stub module with a 0-byte heap. ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) -- To view, visit https://review.coreboot.org/c/coreboot/+/30504 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I298d24d54b8fb27da96257ccda65b7fbee988ebb Gerrit-Change-Number: 30504 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 3

Change in ...coreboot[master]: mb/*/{x201,packardbell}: Remove unused C-state generation functions
by Arthur Heymans (Code Review) 21 Jun '19

21 Jun '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33140 Change subject: mb/*/{x201,packardbell}: Remove unused C-state generation functions ...................................................................... mb/*/{x201,packardbell}: Remove unused C-state generation functions Those are copied from Lenovo X60 code, but are unused. NOTE: No ACPI C-state are generated on this platform but Linux has a separate driver for that. Change-Id: Ie9b49f5451d8cde9c36672cac1f0f14cb3f0095e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/x201/mainboard.c M src/mainboard/packardbell/ms2290/mainboard.c 2 files changed, 0 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/33140/1 diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index b8129ad..54acca3 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -29,19 +29,6 @@ #include <cpu/x86/lapic.h> #include <device/pci.h> #include <drivers/lenovo/lenovo.h> -#include <arch/acpigen.h> - -static acpi_cstate_t cst_entries[] = { - {1, 1, 1000, {0x7f, 1, 2, 0, 1, 0} }, - {2, 1, 500, {0x01, 8, 0, 0, DEFAULT_PMBASE + LV2, 0} }, - {2, 17, 250, {0x01, 8, 0, 0, DEFAULT_PMBASE + LV3, 0} }, -}; - -int get_cst_entries(acpi_cstate_t **entries) -{ - *entries = cst_entries; - return ARRAY_SIZE(cst_entries); -} static void mainboard_init(struct device *dev) { diff --git a/src/mainboard/packardbell/ms2290/mainboard.c b/src/mainboard/packardbell/ms2290/mainboard.c index 09310ae..28d3bb0 100644 --- a/src/mainboard/packardbell/ms2290/mainboard.c +++ b/src/mainboard/packardbell/ms2290/mainboard.c @@ -24,7 +24,6 @@ #include <northbridge/intel/nehalem/nehalem.h> #include <southbridge/intel/bd82x6x/pch.h> #include <ec/acpi/ec.h> -#include <arch/acpigen.h> #include <drivers/intel/gma/int15.h> #include <arch/interrupt.h> #include <pc80/keyboard.h> @@ -32,20 +31,6 @@ #include <device/pci.h> #include <smbios.h> -static acpi_cstate_t cst_entries[] = { - {1, 1, 1000, {0x7f, 1, 2, 0, 1, 0} }, - {2, 1, 500, {0x01, 8, 0, 0, DEFAULT_PMBASE + LV2, 0} }, - {2, 17, 250, {0x01, 8, 0, 0, DEFAULT_PMBASE + LV3, 0} }, -}; - -int get_cst_entries(acpi_cstate_t ** entries) -{ - *entries = cst_entries; - return ARRAY_SIZE(cst_entries); -} - - - static void mainboard_enable(struct device *dev) { u16 pmbase; -- To view, visit https://review.coreboot.org/c/coreboot/+/33140 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9b49f5451d8cde9c36672cac1f0f14cb3f0095e Gerrit-Change-Number: 33140 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 3

Change in ...coreboot[master]: sb/intel/ibexpeak/smihandler: Move finalizing to a common location
by Arthur Heymans (Code Review) 21 Jun '19

21 Jun '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33139 Change subject: sb/intel/ibexpeak/smihandler: Move finalizing to a common location ...................................................................... sb/intel/ibexpeak/smihandler: Move finalizing to a common location TODO: There is no reason to do this in SMM. Change-Id: I8bbb2f65bbe674bd1bc4ae8a4086bd1f5e9a79fa Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/x201/smihandler.c M src/mainboard/packardbell/ms2290/smihandler.c M src/southbridge/intel/ibexpeak/smihandler.c 3 files changed, 7 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/33139/1 diff --git a/src/mainboard/lenovo/x201/smihandler.c b/src/mainboard/lenovo/x201/smihandler.c index fc6a0e9..9043f8e 100644 --- a/src/mainboard/lenovo/x201/smihandler.c +++ b/src/mainboard/lenovo/x201/smihandler.c @@ -20,10 +20,7 @@ #include <cpu/x86/smm.h> #include <southbridge/intel/ibexpeak/nvs.h> #include <southbridge/intel/common/pmutil.h> -#include <southbridge/intel/ibexpeak/me.h> -#include <southbridge/intel/common/finalize.h> #include <northbridge/intel/nehalem/nehalem.h> -#include <cpu/intel/model_2065x/model_2065x.h> #include <ec/acpi/ec.h> #include <ec/lenovo/h8/h8.h> #include <delay.h> @@ -135,25 +132,9 @@ mainboard_smi_handle_ec_sci(); } -static int mainboard_finalized = 0; - int mainboard_smi_apmc(u8 data) { switch (data) { - case APM_CNT_FINALIZE: - printk(BIOS_DEBUG, "APMC: FINALIZE\n"); - if (mainboard_finalized) { - printk(BIOS_DEBUG, "APMC#: Already finalized\n"); - return 0; - } - - intel_me_finalize_smm(); - intel_pch_finalize_smm(); - intel_nehalem_finalize_smm(); - intel_model_2065x_finalize_smm(); - - mainboard_finalized = 1; - break; case APM_CNT_ACPI_ENABLE: /* use 0x1600/0x1604 to prevent races with userspace */ ec_set_ports(0x1604, 0x1600); diff --git a/src/mainboard/packardbell/ms2290/smihandler.c b/src/mainboard/packardbell/ms2290/smihandler.c index 83562be..dfc66f9 100644 --- a/src/mainboard/packardbell/ms2290/smihandler.c +++ b/src/mainboard/packardbell/ms2290/smihandler.c @@ -18,11 +18,8 @@ #include <cpu/x86/smm.h> #include <device/pci_ops.h> #include <southbridge/intel/ibexpeak/nvs.h> -#include <southbridge/intel/ibexpeak/me.h> -#include <southbridge/intel/common/finalize.h> #include <southbridge/intel/common/pmutil.h> #include <northbridge/intel/nehalem/nehalem.h> -#include <cpu/intel/model_2065x/model_2065x.h> #include <ec/acpi/ec.h> static void mainboard_smm_init(void) @@ -54,26 +51,10 @@ { } -static int mainboard_finalized = 0; - int mainboard_smi_apmc(u8 data) { u8 tmp; switch (data) { - case APM_CNT_FINALIZE: - printk(BIOS_DEBUG, "APMC: FINALIZE\n"); - if (mainboard_finalized) { - printk(BIOS_DEBUG, "APMC#: Already finalized\n"); - return 0; - } - - intel_me_finalize_smm(); - intel_pch_finalize_smm(); - intel_nehalem_finalize_smm(); - intel_model_2065x_finalize_smm(); - - mainboard_finalized = 1; - break; case APM_CNT_ACPI_ENABLE: tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); tmp &= ~0x03; diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index dbc412c..208075b 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -24,7 +24,10 @@ #include <elog.h> #include <halt.h> #include <pc80/mc146818rtc.h> +#include <cpu/intel/model_2065x/model_2065x.h> +#include <southbridge/intel/common/finalize.h> #include <southbridge/intel/common/pmbase.h> +#include <southbridge/intel/ibexpeak/me.h> #include "pch.h" #include "nvs.h" @@ -182,4 +185,8 @@ void southbridge_finalize_all(void) { + intel_me_finalize_smm(); + intel_pch_finalize_smm(); + intel_nehalem_finalize_smm(); + intel_model_2065x_finalize_smm(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/33139 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8bbb2f65bbe674bd1bc4ae8a4086bd1f5e9a79fa Gerrit-Change-Number: 33139 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

5 5

Change in ...coreboot[master]: WIP: mediatek/mt8183: Add infra group DCM setting
by Weiyi Lu (Code Review) 21 Jun '19

21 Jun '19

Hello Weiyi Lu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31977 to review the following change. Change subject: WIP: mediatek/mt8183: Add infra group DCM setting ...................................................................... WIP: mediatek/mt8183: Add infra group DCM setting Add infra group DCM setting BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui. Change-Id: I4741dfb7b984deb92171f370e5fb2593829d74c2 Signed-off-by: Weiyi Lu <weiyi.lu(a)mediatek.com> --- M src/soc/mediatek/mt8183/include/soc/pll.h M src/soc/mediatek/mt8183/pll.c 2 files changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/31977/1 diff --git a/src/soc/mediatek/mt8183/include/soc/pll.h b/src/soc/mediatek/mt8183/include/soc/pll.h index 5a5f58d..d1c7cd1 100644 --- a/src/soc/mediatek/mt8183/include/soc/pll.h +++ b/src/soc/mediatek/mt8183/include/soc/pll.h @@ -270,4 +270,13 @@ SPI_HZ = MAINPLL_D5_D2_HZ, }; +enum { + DCM_INFRA_BUS_MASK = 0x40907ffb, + DCM_INFRA_BUS_ON = 0x40900843, + DCM_INFRA_MEM_ON = 0x1 << 27, + DCM_INFRA_P2PRX_MASK = 0xf, + DCM_INFRA_PERI_MASK = 0xf03ffffb, + DCM_INFRA_PERI_ON = 0xf03f83e3, +}; + #endif /* SOC_MEDIATEK_MT8183_PLL_H */ diff --git a/src/soc/mediatek/mt8183/pll.c b/src/soc/mediatek/mt8183/pll.c index 61aa2de..4157c1d 100644 --- a/src/soc/mediatek/mt8183/pll.c +++ b/src/soc/mediatek/mt8183/pll.c @@ -344,6 +344,12 @@ /* enable infrasys DCM */ setbits_le32(&mt8183_infracfg->infra_bus_dcm_ctrl, 0x3 << 21); + clrsetbits_le32(&mt8183_infracfg->infra_bus_dcm_ctrl, DCM_INFRA_BUS_MASK, + DCM_INFRA_BUS_ON); + setbits_le32(&mt8183_infracfg->mem_dcm_ctrl, DCM_INFRA_MEM_ON); + clrbits_le32(&mt8183_infracfg->p2p_rx_clk_on, DCM_INFRA_P2PRX_MASK); + clrsetbits_le32(&mt8183_infracfg->peri_bus_dcm_ctrl, DCM_INFRA_PERI_MASK, + DCM_INFRA_PERI_ON); /* enable [11] for change i2c module source clock to TOPCKGEN */ setbits_le32(&mt8183_infracfg->module_clk_sel, 0x1 << 11); -- To view, visit https://review.coreboot.org/c/coreboot/+/31977 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4741dfb7b984deb92171f370e5fb2593829d74c2 Gerrit-Change-Number: 31977 Gerrit-PatchSet: 1 Gerrit-Owner: Weiyi Lu <weiyi.lu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Weiyi Lu <weiyi.lu(a)mediatek.com> Gerrit-MessageType: newchange

7 13

Change in ...coreboot[master]: google/kukui: Modify SPI speed and tick_dly
by Mengqi Zhang (Code Review) 21 Jun '19

21 Jun '19

Mengqi Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32462 Change subject: google/kukui: Modify SPI speed and tick_dly ...................................................................... google/kukui: Modify SPI speed and tick_dly To support high-speed boot process, speed up spi and set suitable tick_dly BUG=b:80501386 BRANCH=none TEST=emerge-kukui coreboot; emerge-elm coreboot Change-Id: I8f44883b4f4a198146330caf5420dc39d5592a0a Signed-off-by: Mengqi Zhang <Mengqi.Zhang(a)mediatek.com> --- M src/mainboard/google/kukui/bootblock.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/32462/1 diff --git a/src/mainboard/google/kukui/bootblock.c b/src/mainboard/google/kukui/bootblock.c index 1efbc7a..232e17b 100644 --- a/src/mainboard/google/kukui/bootblock.c +++ b/src/mainboard/google/kukui/bootblock.c @@ -20,6 +20,6 @@ { mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 6 * MHz, 0); - mtk_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, SPI_PAD0_MASK, 26 * MHz, - 0); + mtk_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, SPI_PAD0_MASK, 56 * MHz, + 2); } -- To view, visit https://review.coreboot.org/c/coreboot/+/32462 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f44883b4f4a198146330caf5420dc39d5592a0a Gerrit-Change-Number: 32462 Gerrit-PatchSet: 1 Gerrit-Owner: Mengqi Zhang <Mengqi.Zhang(a)mediatek.com> Gerrit-MessageType: newchange

6 14

Change in ...coreboot[master]: mediatek: Add SPI tick_dly setting
by Mengqi Zhang (Code Review) 21 Jun '19

21 Jun '19

Mengqi Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32461 Change subject: mediatek: Add SPI tick_dly setting ...................................................................... mediatek: Add SPI tick_dly setting Add spi tick_dly setting for high-speed spi xfer. BUG=b:80501386 BRANCH=none TEST=emerge-kukui coreboot; emerge-elm coreboot Change-Id: Ie49fc3efe2a4a6dcdf2a2fc4c91b47e35d4f086e Signed-off-by: Mengqi Zhang <Mengqi.Zhang(a)mediatek.com> --- M src/mainboard/google/kukui/bootblock.c M src/mainboard/google/kukui/early_init.c M src/mainboard/google/oak/bootblock.c M src/soc/mediatek/common/include/soc/spi_common.h M src/soc/mediatek/common/spi.c M src/soc/mediatek/mt8173/include/soc/spi.h M src/soc/mediatek/mt8173/spi.c M src/soc/mediatek/mt8183/include/soc/spi.h M src/soc/mediatek/mt8183/spi.c 9 files changed, 33 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/32461/1 diff --git a/src/mainboard/google/kukui/bootblock.c b/src/mainboard/google/kukui/bootblock.c index 9d6c38b..1efbc7a 100644 --- a/src/mainboard/google/kukui/bootblock.c +++ b/src/mainboard/google/kukui/bootblock.c @@ -18,6 +18,8 @@ void bootblock_mainboard_init(void) { - mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 6 * MHz); - mtk_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, SPI_PAD0_MASK, 26 * MHz); + mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 6 * MHz, + 0); + mtk_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, SPI_PAD0_MASK, 26 * MHz, + 0); } diff --git a/src/mainboard/google/kukui/early_init.c b/src/mainboard/google/kukui/early_init.c index 1193bb3..7eee080 100644 --- a/src/mainboard/google/kukui/early_init.c +++ b/src/mainboard/google/kukui/early_init.c @@ -34,6 +34,6 @@ gpio_set_mode(AP_IN_SLEEP_L, PAD_SRCLKENA0_FUNC_SRCLKENA0); - mtk_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, SPI_PAD0_MASK, 1 * MHz); + mtk_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, SPI_PAD0_MASK, 1 * MHz, 0); gpio_eint_configure(CR50_IRQ, IRQ_TYPE_EDGE_RISING); } diff --git a/src/mainboard/google/oak/bootblock.c b/src/mainboard/google/oak/bootblock.c index 3c50389..89169ef 100644 --- a/src/mainboard/google/oak/bootblock.c +++ b/src/mainboard/google/oak/bootblock.c @@ -89,7 +89,8 @@ if (CONFIG(OAK_HAS_TPM2)) gpio_eint_configure(CR50_IRQ, IRQ_TYPE_EDGE_RISING); - mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD1_MASK, 6*MHz); + mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD1_MASK, 6*MHz, + 0); setup_chromeos_gpios(); diff --git a/src/soc/mediatek/common/include/soc/spi_common.h b/src/soc/mediatek/common/include/soc/spi_common.h index 162db59..81a9098 100644 --- a/src/soc/mediatek/common/include/soc/spi_common.h +++ b/src/soc/mediatek/common/include/soc/spi_common.h @@ -84,8 +84,9 @@ void mtk_spi_set_gpio_pinmux(unsigned int bus, enum spi_pad_mask pad_select); -void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks); +void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks, + unsigned int tick_dly); void mtk_spi_init(unsigned int bus, enum spi_pad_mask pad_select, - unsigned int speed_hz); + unsigned int speed_hz, unsigned int tick_dly); #endif diff --git a/src/soc/mediatek/common/spi.c b/src/soc/mediatek/common/spi.c index 71ed95a..1af6f10 100644 --- a/src/soc/mediatek/common/spi.c +++ b/src/soc/mediatek/common/spi.c @@ -53,7 +53,7 @@ } void mtk_spi_init(unsigned int bus, enum spi_pad_mask pad_select, - unsigned int speed_hz) + unsigned int speed_hz, unsigned int tick_dly) { u32 div, sck_ticks, cs_ticks; @@ -73,7 +73,7 @@ printk(BIOS_DEBUG, "SPI%u(PAD%u) initialized at %u Hz\n", bus, pad_select, SPI_HZ / (sck_ticks * 2)); - mtk_spi_set_timing(regs, sck_ticks, cs_ticks); + mtk_spi_set_timing(regs, sck_ticks, cs_ticks, tick_dly); clrsetbits_le32(&regs->spi_cmd_reg, (SPI_CMD_CPHA_EN | SPI_CMD_CPOL_EN | diff --git a/src/soc/mediatek/mt8173/include/soc/spi.h b/src/soc/mediatek/mt8173/include/soc/spi.h index aaef3aa..525f160 100644 --- a/src/soc/mediatek/mt8173/include/soc/spi.h +++ b/src/soc/mediatek/mt8173/include/soc/spi.h @@ -43,4 +43,10 @@ SPI_CFG0_CS_SETUP_SHIFT = 24, }; +enum { + SPI_CFG1_TICK_DLY_SHIFT = 30, + + SPI_CFG1_TICK_DLY_MASK = 0x3 << SPI_CFG1_TICK_DLY_SHIFT, +}; + #endif diff --git a/src/soc/mediatek/mt8173/spi.c b/src/soc/mediatek/mt8173/spi.c index 0cc8377..d009441 100644 --- a/src/soc/mediatek/mt8173/spi.c +++ b/src/soc/mediatek/mt8173/spi.c @@ -38,14 +38,17 @@ gpio_set_mode(GPIO(MSDC2_CMD), PAD_MSDC2_CMD_FUNC_SPI_CS_1); } -void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks) +void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks, + unsigned int tick_dly) { write32(&regs->spi_cfg0_reg, ((sck_ticks - 1) << SPI_CFG0_SCK_HIGH_SHIFT) | ((sck_ticks - 1) << SPI_CFG0_SCK_LOW_SHIFT) | ((cs_ticks - 1) << SPI_CFG0_CS_HOLD_SHIFT) | ((cs_ticks - 1) << SPI_CFG0_CS_SETUP_SHIFT)); - clrsetbits_le32(&regs->spi_cfg1_reg, SPI_CFG1_CS_IDLE_MASK, + clrsetbits_le32(&regs->spi_cfg1_reg, SPI_CFG1_CS_IDLE_MASK | + SPI_CFG1_TICK_DLY_MASK, + (tick_dly << SPI_CFG1_TICK_DLY_SHIFT) | ((cs_ticks - 1) << SPI_CFG1_CS_IDLE_SHIFT)); } diff --git a/src/soc/mediatek/mt8183/include/soc/spi.h b/src/soc/mediatek/mt8183/include/soc/spi.h index 9bc7121..dd63e91 100644 --- a/src/soc/mediatek/mt8183/include/soc/spi.h +++ b/src/soc/mediatek/mt8183/include/soc/spi.h @@ -49,5 +49,11 @@ SPI_CFG2_SCK_HIGH_SHIFT = 16, }; +enum { + SPI_CFG1_TICK_DLY_SHIFT = 29, + + SPI_CFG1_TICK_DLY_MASK = 0x7 << SPI_CFG1_TICK_DLY_SHIFT, + +}; #endif diff --git a/src/soc/mediatek/mt8183/spi.c b/src/soc/mediatek/mt8183/spi.c index a79dafb..c57e60f 100644 --- a/src/soc/mediatek/mt8183/spi.c +++ b/src/soc/mediatek/mt8183/spi.c @@ -109,7 +109,8 @@ gpio_set_mode((gpio_t){.id = ptr[i].pin_id}, ptr[i].func); } -void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks) +void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks, + unsigned int tick_dly) { write32(&regs->spi_cfg0_reg, ((cs_ticks - 1) << SPI_CFG0_CS_HOLD_SHIFT) | @@ -119,6 +120,8 @@ ((sck_ticks - 1) << SPI_CFG2_SCK_HIGH_SHIFT) | ((sck_ticks - 1) << SPI_CFG2_SCK_LOW_SHIFT)); + clrsetbits_le32(&regs->spi_cfg1_reg, SPI_CFG1_TICK_DLY_MASK, + tick_dly << SPI_CFG1_TICK_DLY_SHIFT); clrsetbits_le32(&regs->spi_cfg1_reg, SPI_CFG1_CS_IDLE_MASK, ((cs_ticks - 1) << SPI_CFG1_CS_IDLE_SHIFT)); } -- To view, visit https://review.coreboot.org/c/coreboot/+/32461 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie49fc3efe2a4a6dcdf2a2fc4c91b47e35d4f086e Gerrit-Change-Number: 32461 Gerrit-PatchSet: 1 Gerrit-Owner: Mengqi Zhang <Mengqi.Zhang(a)mediatek.com> Gerrit-MessageType: newchange

4 9

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit May 2019