coreboot-gerrit May 2019

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Change in ...coreboot[master]: qcom: Add i2c driver
by Nitheesh Sekar (Code Review) 12 Jun '19

12 Jun '19

Nitheesh Sekar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32546 Change subject: qcom: Add i2c driver ...................................................................... qcom: Add i2c driver Add i2c driver in coreboot. Change-Id: I3d39d0325718fc5dd60da42eb2b87dcc4429bfc2 Signed-off-by: Prudhvi Yarlagadda <pyarlaga(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/soc/qualcomm/qcs405/Makefile.inc A src/soc/qualcomm/qcs405/blsp.c A src/soc/qualcomm/qcs405/i2c.c A src/soc/qualcomm/qcs405/qup.c 4 files changed, 866 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/32546/1 diff --git a/src/soc/qualcomm/qcs405/Makefile.inc b/src/soc/qualcomm/qcs405/Makefile.inc index c64e5bc..0ebfcae 100644 --- a/src/soc/qualcomm/qcs405/Makefile.inc +++ b/src/soc/qualcomm/qcs405/Makefile.inc @@ -8,6 +8,9 @@ bootblock-y += mmu.c bootblock-y += gpio.c bootblock-y += clock.c +bootblock-y += i2c.c +bootblock-y += qup.c +bootblock-y += blsp.c bootblock-$(CONFIG_DRIVERS_UART) += uart.c ################################################################################ @@ -15,6 +18,9 @@ verstage-y += spi.c verstage-y += gpio.c verstage-y += clock.c +verstage-y += i2c.c +verstage-y += qup.c +verstage-y += blsp.c verstage-$(CONFIG_DRIVERS_UART) += uart.c ################################################################################ @@ -25,6 +31,9 @@ romstage-y += clock.c romstage-y += usb.c romstage-$(CONFIG_DRIVERS_UART) += uart.c +romstage-y += i2c.c +romstage-y += qup.c +romstage-y += blsp.c ################################################################################ ramstage-y += soc.c @@ -33,6 +42,9 @@ ramstage-y += cbmem.c ramstage-y += gpio.c ramstage-y += clock.c +ramstage-y += i2c.c +ramstage-y += qup.c +ramstage-y += blsp.c ramstage-y += usb.c ramstage-$(CONFIG_DRIVERS_UART) += uart.c diff --git a/src/soc/qualcomm/qcs405/blsp.c b/src/soc/qualcomm/qcs405/blsp.c new file mode 100644 index 0000000..eb27ce2 --- /dev/null +++ b/src/soc/qualcomm/qcs405/blsp.c @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 - 2016, 2019 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include <device/mmio.h> +#include <soc/blsp.h> +#include <soc/gpio.h> +#include <soc/iomap.h> +#include <soc/clock.h> + +blsp_return_t blsp_i2c_init(blsp_qup_id_t id) +{ + void *base = blsp_qup_base(id); + + if (!base) + return BLSP_ID_ERROR; + + clock_configure_i2c(19200000); + clock_enable_i2c(); + + switch (id) { + case BLSP_QUP_ID_1: + gpio_configure + (GPIO(24), 2, GPIO_PULL_UP, GPIO_2MA, GPIO_OUTPUT); + gpio_configure + (GPIO(25), 2, GPIO_PULL_UP, GPIO_2MA, GPIO_OUTPUT); + break; + default: + return 1; + } + + /* Configure Mini core to I2C core */ + clrsetbits_le32(base, BLSP_MINI_CORE_MASK, BLSP_MINI_CORE_I2C); + + return BLSP_SUCCESS; +} diff --git a/src/soc/qualcomm/qcs405/i2c.c b/src/soc/qualcomm/qcs405/i2c.c new file mode 100644 index 0000000..4e5f215 --- /dev/null +++ b/src/soc/qualcomm/qcs405/i2c.c @@ -0,0 +1,181 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 - 2015, 2019 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include <assert.h> +#include <console/console.h> +#include <delay.h> +#include <device/i2c_simple.h> +#include <stdlib.h> +#include <string.h> +#include <soc/blsp.h> +#include <soc/qup.h> +#include <soc/gpio.h> + +static qup_config_t blsp1_qup0_config = { + QUP_MINICORE_I2C_MASTER, + 400000, + 19200000, + QUP_MODE_BLOCK, + 0 +}; + +static qup_config_t blsp1_qup1_config = { + QUP_MINICORE_I2C_MASTER, + 400000, + 19200000, + QUP_MODE_BLOCK, + 0 +}; + +static qup_config_t blsp1_qup2_config = { + QUP_MINICORE_I2C_MASTER, + 400000, + 19200000, + QUP_MODE_BLOCK, + 0 +}; + +static qup_config_t blsp1_qup3_config = { + QUP_MINICORE_I2C_MASTER, + 400000, + 19200000, + QUP_MODE_BLOCK, + 0 +}; + +static int i2c_read(uint32_t gsbi_id, uint8_t slave, + uint8_t *data, int data_len) +{ + qup_data_t obj; + qup_return_t qup_ret = 0; + + memset(&obj, 0, sizeof(obj)); + obj.protocol = QUP_MINICORE_I2C_MASTER; + obj.p.iic.addr = slave; + obj.p.iic.data_len = data_len; + obj.p.iic.data = data; + qup_ret = qup_recv_data(gsbi_id, &obj); + + if (QUP_SUCCESS != qup_ret) + return 1; + else + return 0; +} + +static int i2c_write(uint32_t gsbi_id, uint8_t slave, + uint8_t *data, int data_len, uint8_t stop_seq) +{ + qup_data_t obj; + qup_return_t qup_ret = 0; + + memset(&obj, 0, sizeof(obj)); + obj.protocol = QUP_MINICORE_I2C_MASTER; + obj.p.iic.addr = slave; + obj.p.iic.data_len = data_len; + obj.p.iic.data = data; + qup_ret = qup_send_data(gsbi_id, &obj, stop_seq); + + if (QUP_SUCCESS != qup_ret) + return 1; + else + return 0; +} + +static int i2c_init(blsp_qup_id_t id) +{ + qup_config_t *qup_config; + + switch (id) { + case BLSP_QUP_ID_0: + qup_config = &blsp1_qup0_config; + break; + case BLSP_QUP_ID_1: + qup_config = &blsp1_qup1_config; + break; + case BLSP_QUP_ID_2: + qup_config = &blsp1_qup2_config; + break; + case BLSP_QUP_ID_3: + qup_config = &blsp1_qup3_config; + break; + default: + printk(BIOS_ERR, "QUP configuration not defined for BLSP%d.\n", + id); + return 1; + } + + if (qup_config->initialized) + return 0; + + if (blsp_i2c_init(id)) { + printk(BIOS_ERR, "failed to initialize blsp\n"); + return 1; + } + + if (qup_init(id, qup_config)) { + printk(BIOS_ERR, "failed to initialize qup\n"); + return 1; + } + + if (qup_reset_i2c_master_status(id)) { + printk(BIOS_ERR, "failed to reset i2c master status\n"); + return 1; + } + + qup_config->initialized = 1; + return 0; +} + +int platform_i2c_transfer(unsigned bus, struct i2c_msg *segments, + int seg_count) +{ + struct i2c_msg *seg = segments; + int ret = 0; + + if (i2c_init(bus)) + return 1; + + while (!ret && seg_count--) { + if (seg->flags & I2C_M_RD) + ret = i2c_read(bus, seg->slave, seg->buf, seg->len); + else + ret = i2c_write(bus, seg->slave, seg->buf, seg->len, + (seg_count ? 0 : 1)); + seg++; + } + + if (ret) { + qup_set_state(bus, QUP_STATE_RESET); + return 1; + } + + return 0; +} diff --git a/src/soc/qualcomm/qcs405/qup.c b/src/soc/qualcomm/qcs405/qup.c new file mode 100644 index 0000000..e2aab06 --- /dev/null +++ b/src/soc/qualcomm/qcs405/qup.c @@ -0,0 +1,610 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 - 2015, 2019 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include <device/mmio.h> +#include <console/console.h> +#include <delay.h> +#include <soc/gpio.h> +#include <soc/iomap.h> +#include <stdlib.h> +#include <soc/qup.h> + +#define TIMEOUT_CNT 100 + +#define QUP_ADDR(id, reg) (blsp_qup_base(id) + (reg)) + +#define QUP_DEBUG 0 + +#define QUPDBG BIOS_ERR, "\t-> " + +#if QUP_DEBUG +#define qup_write32(a, v) do { \ + write32(a, v); \ + printk(QUPDBG "%s(%d): write32(0x%p, 0x%x)\n", \ + __func__, __LINE__, a, v); \ +} while (0) +#else +#define qup_write32 write32 +#endif + +struct i2c_clk_div_fld { + u32 clk_freq_out; + u8 fs_div; + u8 ht_div; +}; + +static struct i2c_clk_div_fld i2c_clk_div_map[] = { + {100000, 124, 62}, + {400000, 28, 14}, + {1000000, 8, 5}, +}; + +static void i2c_set_mstr_clk_ctl(unsigned id, unsigned hz) +{ + int i; + struct i2c_clk_div_fld *itr = i2c_clk_div_map; + u8 fs_div = 0; + u8 ht_div = 0; + u32 mstr_clk_ctl; + + for (i = 0; i < ARRAY_SIZE(i2c_clk_div_map); ++i, ++itr) { + if (hz == itr->clk_freq_out) { + if (!fs_div) + fs_div = itr->fs_div; + if (!ht_div) + ht_div = itr->ht_div; + break; + } + } + + /* format values in clk-ctl cache */ + mstr_clk_ctl = ((ht_div & 0xff) << 16) |(fs_div & 0xff); + + qup_write32(QUP_ADDR(id, QUP_I2C_MASTER_CLK_CTL), mstr_clk_ctl); +} + + +static qup_return_t qup_i2c_master_status(blsp_qup_id_t id) +{ + uint32_t reg_val = read32(QUP_ADDR(id, QUP_I2C_MASTER_STATUS)); + + if (read32(QUP_ADDR(id, QUP_ERROR_FLAGS))) + return QUP_ERR_XFER_FAIL; + +#if QUP_DEBUG + printk(QUPDBG "%s: 0x%x\n", __func__, reg_val); +#endif + + if (reg_val & QUP_I2C_INVALID_READ_ADDR) + return QUP_ERR_I2C_INVALID_SLAVE_ADDR; + if (reg_val & QUP_I2C_FAILED_MASK) + return QUP_ERR_I2C_FAILED; + if (reg_val & QUP_I2C_ARB_LOST) + return QUP_ERR_I2C_ARB_LOST; + if (reg_val & QUP_I2C_BUS_ERROR) + return QUP_ERR_I2C_BUS_ERROR; + if (reg_val & QUP_I2C_INVALID_WRITE) + return QUP_ERR_I2C_INVALID_WRITE; + if (reg_val & QUP_I2C_PACKET_NACK) + return QUP_ERR_I2C_NACK; + if (reg_val & QUP_I2C_INVALID_TAG) + return QUP_ERR_I2C_INVALID_TAG; + + return QUP_SUCCESS; +} + +static int check_bit_state(uint32_t *reg, int wait_for) +{ + unsigned int count = TIMEOUT_CNT; + + while ((read32(reg) & (QUP_STATE_VALID_MASK | QUP_STATE_MASK)) != + (QUP_STATE_VALID | wait_for)) { + if (count == 0) + return QUP_ERR_TIMEOUT; + count--; + } + + return QUP_SUCCESS; +} + +/* + * Check whether GSBIn_QUP State is valid + */ +static qup_return_t qup_wait_for_state(blsp_qup_id_t id, unsigned wait_for) +{ + return check_bit_state(QUP_ADDR(id, QUP_STATE), wait_for); +} + +qup_return_t qup_reset_i2c_master_status(blsp_qup_id_t id) +{ + /* + * The I2C_STATUS is a status register. + * Writing any value clears the status bits. + */ + qup_write32(QUP_ADDR(id, QUP_I2C_MASTER_STATUS), 0); + return QUP_SUCCESS; +} + +static qup_return_t qup_reset_master_status(blsp_qup_id_t id) +{ + qup_write32(QUP_ADDR(id, QUP_ERROR_FLAGS), 0x3C); + qup_write32(QUP_ADDR(id, QUP_ERROR_FLAGS_EN), 0x3C); + qup_reset_i2c_master_status(id); + return QUP_SUCCESS; +} + +static qup_return_t qup_fifo_wait_for(blsp_qup_id_t id, uint32_t status) +{ + qup_return_t ret = QUP_ERR_UNDEFINED; + unsigned int count = TIMEOUT_CNT; + + while (!(read32(QUP_ADDR(id, QUP_OPERATIONAL)) & status)) { + ret = qup_i2c_master_status(id); + if (ret) + return ret; + if (count == 0) + return QUP_ERR_TIMEOUT; + count--; + } + + return QUP_SUCCESS; +} + +static qup_return_t qup_fifo_wait_while(blsp_qup_id_t id, uint32_t status) +{ + qup_return_t ret = QUP_ERR_UNDEFINED; + unsigned int count = TIMEOUT_CNT; + + while (read32(QUP_ADDR(id, QUP_OPERATIONAL)) & status) { + ret = qup_i2c_master_status(id); + if (ret) + return ret; + if (count == 0) + return QUP_ERR_TIMEOUT; + count--; + } + + return QUP_SUCCESS; +} + +static inline uint32_t qup_i2c_create_output_tag(int stop, u8 data) +{ + uint32_t tag; + + if (stop) + tag = QUP_I2C_STOP_SEQ | QUP_I2C_DATA(data); + else + tag = QUP_I2C_DATA_SEQ | QUP_I2C_DATA(data); + + return tag; +} + +static inline qup_return_t qup_i2c_write_fifo_flush(blsp_qup_id_t id) +{ + qup_return_t ret = QUP_ERR_UNDEFINED; + + qup_write32(QUP_ADDR(id, QUP_OPERATIONAL), OUTPUT_SERVICE_FLAG); + + mdelay(4); /* TPM seems to need this */ + + ret = qup_fifo_wait_while(id, OUTPUT_FIFO_NOT_EMPTY); + if (ret) + return ret; + + ret = qup_i2c_master_status(id); + + if (ret) + printk(BIOS_DEBUG, "%s: error\n", __func__); + + return ret; +} + +static qup_return_t qup_i2c_write_fifo(blsp_qup_id_t id, qup_data_t *p_tx_obj, + uint8_t stop_seq) +{ + qup_return_t ret = QUP_ERR_UNDEFINED; + uint8_t addr = p_tx_obj->p.iic.addr; + uint8_t *data_ptr = p_tx_obj->p.iic.data; + unsigned data_len = p_tx_obj->p.iic.data_len; + unsigned idx = 0; + uint32_t tag, *fifo = QUP_ADDR(id, QUP_OUTPUT_FIFO); + + qup_reset_master_status(id); + + qup_write32(QUP_ADDR(id, QUP_MX_OUTPUT_COUNT), data_len + 1); + + qup_set_state(id, QUP_STATE_RUN); + + /* + * Since UNPACK enable is set in io mode register, populate 2 tags + * for each fifo register. + * + * Create the first tag as follows, with the start tag and first byte + * of the data to be written + * +--------+--------+--------+--------+ + * | STOP / | data | START | ADDR | + * |DATA tag| byte | tag | << 1 | + * +--------+--------+--------+--------+ + * rest will be created in the following while loop. + */ + tag = qup_i2c_create_output_tag(data_len == 1 && stop_seq, + data_ptr[idx]); + tag = ((tag << 16) & 0xffff0000) | + (QUP_I2C_START_SEQ | QUP_I2C_ADDR(addr)); + data_len--; + idx++; + + qup_write32(fifo, tag); + + while (data_len) { + + tag = qup_i2c_create_output_tag(data_len == 1 && stop_seq, + data_ptr[idx]); + data_len--; + idx++; + + if (data_len) { + tag |= qup_i2c_create_output_tag( + data_len == 1 && stop_seq, + data_ptr[idx]) << 16; + data_len--; + idx++; + } + + qup_write32(fifo, tag); + + ret = qup_i2c_write_fifo_flush(id); + + if (ret) { + printk(QUPDBG "%s: error\n", __func__); + return ret; + } + } + + ret = qup_i2c_write_fifo_flush(id); + + qup_set_state(id, QUP_STATE_RESET); + + return ret; +} + +static qup_return_t qup_i2c_write(blsp_qup_id_t id, uint8_t mode, + qup_data_t *p_tx_obj, uint8_t stop_seq) +{ + qup_return_t ret = QUP_ERR_UNDEFINED; + + switch (mode) { + case QUP_MODE_FIFO: + case QUP_MODE_BLOCK: + ret = qup_i2c_write_fifo(id, p_tx_obj, stop_seq); + break; + default: + ret = QUP_ERR_UNSUPPORTED; + } + + if (ret) { + qup_set_state(id, QUP_STATE_RESET); + printk(QUPDBG "%s() failed (%d)\n", __func__, ret); + } + + return ret; +} + +static int qup_i2c_parse_tag(uint32_t data, uint8_t *data_ptr, uint32_t len) +{ + int i, idx = 0; + int max = (len > 2) ? 2 : len; + + for (i = 0; i < max; i++) { + switch (QUP_I2C_MI_TAG(data)) { + case QUP_I2C_MIDATA_SEQ: + data_ptr[idx] = QUP_I2C_DATA(data); + idx++; + break; + case QUP_I2C_MISTOP_SEQ: + data_ptr[idx] = QUP_I2C_DATA(data); + idx++; + return idx; + default: + printk(QUPDBG "%s: Unexpected tag (0x%x)\n", __func__, + QUP_I2C_MI_TAG(data)); + return -1; + } + + data = (data >> 16); + } + + return idx; +} + +static qup_return_t qup_i2c_read_fifo(blsp_qup_id_t id, qup_data_t *p_tx_obj) +{ + qup_return_t ret = QUP_ERR_UNDEFINED; + uint8_t addr = p_tx_obj->p.iic.addr; + uint8_t *data_ptr = p_tx_obj->p.iic.data; + unsigned data_len = p_tx_obj->p.iic.data_len; + unsigned idx = 0; + uint32_t *fifo = QUP_ADDR(id, QUP_OUTPUT_FIFO); + + qup_reset_master_status(id); + + qup_write32(QUP_ADDR(id, QUP_IO_MODES), + QUP_UNPACK_EN | QUP_PACK_EN | + ((QUP_MODE_BLOCK & QUP_MODE_MASK) << + QUP_OUTPUT_MODE_SHFT) | + ((QUP_MODE_BLOCK & QUP_MODE_MASK) << + QUP_INPUT_MODE_SHFT)); + + qup_write32(QUP_ADDR(id, QUP_MX_INPUT_COUNT), data_len); + + qup_set_state(id, QUP_STATE_RUN); + + qup_write32(fifo, (QUP_I2C_START_SEQ | + (QUP_I2C_ADDR(addr) | QUP_I2C_SLAVE_READ)) | + ((QUP_I2C_RECV_SEQ | data_len) << 16)); + + ret = qup_i2c_write_fifo_flush(id); + if (ret) { + printk(QUPDBG "%s: OUTPUT_FIFO_NOT_EMPTY\n", __func__); + return ret; + } + + ret = qup_fifo_wait_for(id, INPUT_SERVICE_FLAG); + if (ret) { + printk(QUPDBG "%s: INPUT_SERVICE_FLAG\n", __func__); + return ret; + } + + fifo = QUP_ADDR(id, QUP_INPUT_FIFO); + + while (data_len) { + uint32_t data; + int count; + + data = read32(fifo); + mdelay(1); + + count = qup_i2c_parse_tag(data, data_ptr + idx, data_len); + + if (count < 0) { + printk(QUPDBG "%s: Cannot parse tag 0x%x\n", + __func__, data); + qup_set_state(id, QUP_STATE_PAUSE); + + return QUP_ERR_I2C_INVALID_TAG; + } + + idx += count; + data_len -= count; + + qup_write32(QUP_ADDR(id, QUP_OPERATIONAL), INPUT_SERVICE_FLAG); + } + + p_tx_obj->p.iic.data_len = idx; + + qup_write32(QUP_ADDR(id, QUP_MX_READ_COUNT), 0); + + qup_set_state(id, QUP_STATE_RESET); + + return QUP_SUCCESS; +} + +static qup_return_t qup_i2c_read(blsp_qup_id_t id, uint8_t mode, + qup_data_t *p_tx_obj) +{ + qup_return_t ret = QUP_ERR_UNDEFINED; + + qup_set_state(id, QUP_STATE_RESET); + + switch (mode) { + case QUP_MODE_FIFO: + case QUP_MODE_BLOCK: + ret = qup_i2c_read_fifo(id, p_tx_obj); + break; + default: + ret = QUP_ERR_UNSUPPORTED; + } + + if (ret) { + qup_set_state(id, QUP_STATE_RESET); + printk(QUPDBG "%s() failed (%d)\n", __func__, ret); + } + + return ret; +} + +qup_return_t qup_init(blsp_qup_id_t id, const qup_config_t *config_ptr) +{ + qup_return_t ret = QUP_ERR_UNDEFINED; + uint32_t reg_val; + + /* Reset the QUP core.*/ + qup_write32(QUP_ADDR(id, QUP_SW_RESET), 0x1); + + /* Wait till the reset takes effect */ + ret = qup_wait_for_state(id, QUP_STATE_RESET); + if (ret) + goto bailout; + + /* Reset the config */ + qup_write32(QUP_ADDR(id, QUP_CONFIG), 0); + + /* Program the config register */ + /* Set N value */ + reg_val = 0x0F; + /* Set protocol */ + switch (config_ptr->protocol) { + case QUP_MINICORE_I2C_MASTER: + reg_val |= ((config_ptr->protocol & + QUP_MINI_CORE_PROTO_MASK) << + QUP_MINI_CORE_PROTO_SHFT); + break; + default: + ret = QUP_ERR_UNSUPPORTED; + goto bailout; + } + reg_val |= QUP_APP_CLK_ON_EN | QUP_CORE_CLK_ON_EN; + qup_write32(QUP_ADDR(id, QUP_CONFIG), reg_val); + + /* Choose version 1 tag */ + qup_write32(QUP_ADDR(id, QUP_I2C_MASTER_CONFIG), 0); + + /* Reset i2c clk cntl register */ + qup_write32(QUP_ADDR(id, QUP_I2C_MASTER_CLK_CTL), 0); + + /* Set QUP IO Mode */ + switch (config_ptr->mode) { + case QUP_MODE_FIFO: + case QUP_MODE_BLOCK: + reg_val = QUP_UNPACK_EN | QUP_PACK_EN | + ((config_ptr->mode & QUP_MODE_MASK) << + QUP_OUTPUT_MODE_SHFT) | + ((config_ptr->mode & QUP_MODE_MASK) << + QUP_INPUT_MODE_SHFT); + break; + default: + ret = QUP_ERR_UNSUPPORTED; + goto bailout; + } + qup_write32(QUP_ADDR(id, QUP_IO_MODES), reg_val); + + /*Set i2c clk cntl*/ + i2c_set_mstr_clk_ctl(id, 400000); + + qup_set_state(id, QUP_STATE_RESET); +bailout: + if (ret) + printk(QUPDBG "failed to init qup (%d)\n", ret); + + return ret; +} + +qup_return_t qup_set_state(blsp_qup_id_t id, uint32_t state) +{ + qup_return_t ret = QUP_ERR_UNDEFINED; + unsigned curr_state = read32(QUP_ADDR(id, QUP_STATE)); + + if ((state >= QUP_STATE_RESET && state <= QUP_STATE_PAUSE) + && (curr_state & QUP_STATE_VALID_MASK)) { + /* + * For PAUSE_STATE to RESET_STATE transition, + * two writes of 10[binary]) are required for the + * transition to complete. + */ + if (QUP_STATE_PAUSE == curr_state && QUP_STATE_RESET == state) { + qup_write32(QUP_ADDR(id, QUP_STATE), 0x2); + qup_write32(QUP_ADDR(id, QUP_STATE), 0x2); + } else { + qup_write32(QUP_ADDR(id, QUP_STATE), state); + } + ret = qup_wait_for_state(id, state); + } + + return ret; +} + +static qup_return_t qup_i2c_send_data(blsp_qup_id_t id, qup_data_t *p_tx_obj, + uint8_t stop_seq) +{ + qup_return_t ret = QUP_ERR_UNDEFINED; + uint8_t mode = (read32(QUP_ADDR(id, QUP_IO_MODES)) >> + QUP_OUTPUT_MODE_SHFT) & QUP_MODE_MASK; + + ret = qup_i2c_write(id, mode, p_tx_obj, stop_seq); + if (QUP_DEBUG) { + int i; + + printk(BIOS_DEBUG, "i2c tx bus %d device %2.2x:", + id, p_tx_obj->p.iic.addr); + for (i = 0; i < p_tx_obj->p.iic.data_len; i++) + printk(BIOS_DEBUG, " %2.2x", p_tx_obj->p.iic.data[i]); + printk(BIOS_DEBUG, "\n"); + } + + return ret; +} + +qup_return_t qup_send_data(blsp_qup_id_t id, qup_data_t *p_tx_obj, + uint8_t stop_seq) +{ + qup_return_t ret = QUP_ERR_UNDEFINED; + + if (p_tx_obj->protocol == ((read32(QUP_ADDR(id, QUP_CONFIG)) >> + QUP_MINI_CORE_PROTO_SHFT) & QUP_MINI_CORE_PROTO_MASK)) { + switch (p_tx_obj->protocol) { + case QUP_MINICORE_I2C_MASTER: + ret = qup_i2c_send_data(id, p_tx_obj, stop_seq); + break; + default: + ret = QUP_ERR_UNSUPPORTED; + } + } + + return ret; +} + +static qup_return_t qup_i2c_recv_data(blsp_qup_id_t id, qup_data_t *p_rx_obj) +{ + qup_return_t ret = QUP_ERR_UNDEFINED; + uint8_t mode = (read32(QUP_ADDR(id, QUP_IO_MODES)) >> + QUP_INPUT_MODE_SHFT) & QUP_MODE_MASK; + + ret = qup_i2c_read(id, mode, p_rx_obj); + if (QUP_DEBUG) { + int i; + + printk(BIOS_DEBUG, "i2c rxed on bus %d device %2.2x:", + id, p_rx_obj->p.iic.addr); + for (i = 0; i < p_rx_obj->p.iic.data_len; i++) + printk(BIOS_DEBUG, " %2.2x", p_rx_obj->p.iic.data[i]); + printk(BIOS_DEBUG, "\n"); + } + + return ret; +} + +qup_return_t qup_recv_data(blsp_qup_id_t id, qup_data_t *p_rx_obj) +{ + qup_return_t ret = QUP_ERR_UNDEFINED; + + if (p_rx_obj->protocol == ((read32(QUP_ADDR(id, QUP_CONFIG)) >> + QUP_MINI_CORE_PROTO_SHFT) & QUP_MINI_CORE_PROTO_MASK)) { + switch (p_rx_obj->protocol) { + case QUP_MINICORE_I2C_MASTER: + ret = qup_i2c_recv_data(id, p_rx_obj); + break; + default: + ret = QUP_ERR_UNSUPPORTED; + } + } + + return ret; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/32546 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d39d0325718fc5dd60da42eb2b87dcc4429bfc2 Gerrit-Change-Number: 32546 Gerrit-PatchSet: 1 Gerrit-Owner: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-MessageType: newchange

5 17

Change in ...coreboot[master]: postcarpayload: Boot to payload from postcar stage directly [WIP]
by Subrata Banik (Code Review) 12 Jun '19

12 Jun '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30985 Change subject: postcarpayload: Boot to payload from postcar stage directly [WIP] ...................................................................... postcarpayload: Boot to payload from postcar stage directly [WIP] Changes: 1. Make only required changes to load generic payload [payload_init.c] 2. Compile required functions in postcar stage 3. Call postcar_payload_init() from postcar stage 4. soc and mainboard related changes TEST=Able to boot iclrvp and dragonegg to chrome os with limited FW changes. Change-Id: I27479187461ceb078167f2d726f40839865a9233 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/arch/x86/Makefile.inc M src/arch/x86/acpi.c M src/arch/x86/c_start.S M src/arch/x86/cpu.c M src/arch/x86/include/arch/acpi.h M src/arch/x86/include/arch/cpu.h M src/arch/x86/postcar.c M src/commonlib/Makefile.inc M src/console/post.c M src/cpu/intel/microcode/Makefile.inc M src/cpu/intel/turbo/Makefile.inc M src/cpu/x86/Makefile.inc M src/cpu/x86/lapic/Makefile.inc M src/cpu/x86/mp_init.c M src/cpu/x86/mtrr/Makefile.inc M src/cpu/x86/name/Makefile.inc M src/cpu/x86/smm/Makefile.inc M src/device/Makefile.inc M src/device/pci_early.c M src/drivers/elog/Makefile.inc M src/drivers/intel/fsp2_0/Makefile.inc M src/drivers/intel/fsp2_0/silicon_init.c M src/drivers/intel/gma/Makefile.inc M src/drivers/mrc_cache/Makefile.inc M src/drivers/mrc_cache/mrc_cache.c M src/drivers/pc80/pc/Makefile.inc M src/drivers/uart/uart8250io.c M src/drivers/uart/uart8250mem.c M src/ec/google/chromeec/Makefile.inc M src/include/memlayout.h M src/include/mrc_cache.h M src/include/rules.h M src/include/stddef.h M src/lib/Makefile.inc M src/lib/bootmode.c M src/lib/imd_cbmem.c M src/lib/memrange.c M src/lib/prog_loaders.c M src/lib/program.ld M src/mainboard/google/dragonegg/Kconfig M src/mainboard/google/dragonegg/Makefile.inc M src/mainboard/google/dragonegg/chromeos.c M src/mainboard/google/dragonegg/variants/baseboard/Makefile.inc M src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb M src/mainboard/intel/icelake_rvp/Kconfig M src/security/vboot/Makefile.inc M src/soc/intel/common/Makefile.inc M src/soc/intel/common/block/acpi/Makefile.inc M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/common/block/cpu/Makefile.inc M src/soc/intel/common/block/gpio/Makefile.inc M src/soc/intel/common/block/graphics/Makefile.inc M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/include/intelblocks/acpi.h M src/soc/intel/common/block/include/intelblocks/systemagent.h M src/soc/intel/common/block/itss/Makefile.inc M src/soc/intel/common/block/lpc/Makefile.inc M src/soc/intel/common/block/pcr/Makefile.inc M src/soc/intel/common/block/systemagent/Makefile.inc M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/common/block/systemagent/systemagent_early.c M src/soc/intel/icelake/Makefile.inc M src/soc/intel/icelake/acpi.c A src/soc/intel/icelake/include/soc/payload_init.h A src/soc/intel/icelake/payload_init.c M src/southbridge/intel/common/Makefile.inc M src/vendorcode/google/chromeos/Makefile.inc 67 files changed, 477 insertions(+), 57 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/30985/1 diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 8dafac8..2ee4921 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -260,6 +260,11 @@ $(eval $(call create_class_compiler,postcar,x86_32)) postcar-generic-ccopts += -D__POSTCAR__ +postcar-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c +postcar-$(CONFIG_HAVE_ACPI_TABLES) += acpigen.c +postcar-$(CONFIG_HAVE_ACPI_TABLES) += acpigen_dsm.c +postcar-$(CONFIG_HAVE_ACPI_TABLES) += acpi_device.c +postcar-$(CONFIG_HAVE_ACPI_TABLES) += acpi_pld.c postcar-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c postcar-y += boot.c postcar-y += gdt_init.S @@ -270,6 +275,7 @@ postcar-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c postcar-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S postcar-y += exit_car.S +postcar-y += c_start.S postcar-y += memcpy.c postcar-y += memmove.c postcar-y += memset.c @@ -310,11 +316,13 @@ ramstage-y += c_start.S ramstage-y += cbmem.c ramstage-y += cpu.c +postcar-y += cpu.c ramstage-y += cpu_common.c ramstage-y += ebda.c ramstage-y += exception.c ramstage-y += idt.S ramstage-y += gdt.c +postcar-$(CONFIG_IOAPIC) += ioapic.c ramstage-$(CONFIG_IOAPIC) += ioapic.c ramstage-y += memcpy.c ramstage-y += memlayout.ld @@ -327,10 +335,13 @@ ramstage-$(CONFIG_GENERATE_PIRQ_TABLE) += pirq_routing.c ramstage-y += rdrand.c ramstage-$(CONFIG_GENERATE_SMBIOS_TABLES) += smbios.c +postcar-$(CONFIG_GENERATE_SMBIOS_TABLES) += smbios.c ramstage-y += tables.c +postcar-y += tables.c ramstage-$(CONFIG_COOP_MULTITASKING) += thread.c ramstage-$(CONFIG_COOP_MULTITASKING) += thread_switch.S ramstage-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c +postcar-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.S ramstage-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.S smm-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 3b33f1b..e8c7cb4 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -48,6 +48,9 @@ #include <cpu/cpu.h> #include <cbfs.h> +#include <soc/pci_devs.h> +#include <intelblocks/graphics.h> + u8 acpi_checksum(u8 *table, u32 length) { u8 ret = 0; @@ -1264,6 +1267,7 @@ printk(BIOS_DEBUG, "current = %lx\n", current); +#if 0 // TODO: Bad hack to enable GFX for (dev = all_devices; dev; dev = dev->next) { if (dev->ops && dev->ops->write_acpi_tables) { current = dev->ops->write_acpi_tables(dev, current, @@ -1271,6 +1275,9 @@ current = acpi_align_current(current); } } +#endif + graphics_soc_write_acpi_opregion(SA_DEV_IGD, current, rsdp); + current = acpi_align_current(current); printk(BIOS_INFO, "ACPI: done.\n"); return current; diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S index 86147ec..5bb3cfd 100644 --- a/src/arch/x86/c_start.S +++ b/src/arch/x86/c_start.S @@ -37,8 +37,8 @@ #else .code32 #endif - .globl _start -_start: + .globl _start1 +_start1: cli lgdt %cs:gdtaddr #ifndef __x86_64__ diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c index 018ce9e..d9d0762 100644 --- a/src/arch/x86/cpu.c +++ b/src/arch/x86/cpu.c @@ -227,15 +227,11 @@ * from secondary cpus to a minimum, when debugging is * disabled. */ - struct device *cpu; - struct cpu_info *info; + struct device *cpu = dev_find_path(NULL, DEVICE_PATH_CPU_CLUSTER); struct cpuinfo_x86 c; - info = cpu_info(); - printk(BIOS_INFO, "Initializing CPU #%d\n", index); - cpu = info->cpu; if (!cpu) die("CPU: missing CPU device structure"); diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index a061a27..7ddda19 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -837,7 +837,7 @@ unsigned long (*acpi_fill_ivrs)(acpi_ivrs_t *ivrs_struct, unsigned long current)); -#if ENV_RAMSTAGE && !defined(__SIMPLE_DEVICE__) +#if (ENV_RAMSTAGE || ENV_POSTCAR) && !defined(__SIMPLE_DEVICE__) void acpi_create_hpet(acpi_hpet_t *hpet); unsigned long acpi_write_hpet(struct device *device, unsigned long start, acpi_rsdp_t *rsdp); diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 3ee5cea..b10b984 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -210,7 +210,7 @@ ); return ci; } - +#if !ENV_POSTCAR static inline unsigned long cpu_index(void) { struct cpu_info *ci; @@ -218,6 +218,7 @@ return ci->index; } #endif +#endif #ifndef __ROMCC__ // romcc is segfaulting in some cases struct cpuinfo_x86 { diff --git a/src/arch/x86/postcar.c b/src/arch/x86/postcar.c index ea05824..da02d6b 100644 --- a/src/arch/x86/postcar.c +++ b/src/arch/x86/postcar.c @@ -19,6 +19,7 @@ #include <cpu/x86/mtrr.h> #include <main_decl.h> #include <program_loading.h> +#include <soc/payload_init.h> /* * Systems without a native coreboot cache-as-ram teardown may implement @@ -37,6 +38,8 @@ display_mtrrs(); + postcar_payload_init(); + /* Load and run ramstage. */ run_ramstage(); } diff --git a/src/commonlib/Makefile.inc b/src/commonlib/Makefile.inc index 4d89c48..3d68cb4 100644 --- a/src/commonlib/Makefile.inc +++ b/src/commonlib/Makefile.inc @@ -23,6 +23,8 @@ ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp_relocate.c ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp_relocate.c +postcar-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp_relocate.c + bootblock-y += cbfs.c verstage-y += cbfs.c romstage-y += cbfs.c diff --git a/src/console/post.c b/src/console/post.c index 4c37535..50c84df 100644 --- a/src/console/post.c +++ b/src/console/post.c @@ -41,7 +41,7 @@ DECLARE_SPIN_LOCK(cmos_post_lock) -#if ENV_RAMSTAGE +#if ENV_RAMSTAGE || ENV_POSTCAR void cmos_post_log(void) { u8 code = 0; diff --git a/src/cpu/intel/microcode/Makefile.inc b/src/cpu/intel/microcode/Makefile.inc index 2df1d5e..cdef0e0 100644 --- a/src/cpu/intel/microcode/Makefile.inc +++ b/src/cpu/intel/microcode/Makefile.inc @@ -3,3 +3,4 @@ ramstage-$(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS) += microcode.c romstage-$(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS) += microcode.c +postcar-$(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS) += microcode.c diff --git a/src/cpu/intel/turbo/Makefile.inc b/src/cpu/intel/turbo/Makefile.inc index 48ec55d..6a62f59 100644 --- a/src/cpu/intel/turbo/Makefile.inc +++ b/src/cpu/intel/turbo/Makefile.inc @@ -1 +1,2 @@ +postcar-y += turbo.c ramstage-y += turbo.c diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc index 3e8a664..639d1f8 100644 --- a/src/cpu/x86/Makefile.inc +++ b/src/cpu/x86/Makefile.inc @@ -6,9 +6,11 @@ subdirs-y += pae subdirs-$(CONFIG_PARALLEL_MP) += name +postcar-$(CONFIG_PARALLEL_MP) += mp_init.c ramstage-$(CONFIG_PARALLEL_MP) += mp_init.c ramstage-$(CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING) += mirror_payload.c ramstage-y += backup_default_smm.c +postcar-y += backup_default_smm.c additional-dirs += $(obj)/cpu/x86 @@ -19,6 +21,7 @@ ifeq ($(CONFIG_PARALLEL_MP),y) ramstage-srcs += $(SIPI_BIN).manual +postcar-srcs += $(SIPI_BIN).manual endif rmodules_$(ARCH-ramstage-y)-$(CONFIG_PARALLEL_MP) += sipi_vector.S @@ -37,3 +40,22 @@ $(call src-to-obj,ramstage,$(SIPI_BIN).manual): $(SIPI_BIN) @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" cd $(dir $<); $(OBJCOPY_rmodules_$(ARCH-ramstage-y)) -I binary $(notdir $<) $(target-objcopy) $(abspath $@) + + +rmodules_$(ARCH-postcar-y)-$(CONFIG_PARALLEL_MP) += sipi_vector.S + +$(SIPI_DOTO): $(call src-to-obj,rmodules_$(ARCH-postcar-y),src/cpu/x86/sipi_vector.S) + $(CC_rmodules_$(ARCH-postcar-y)) $(CFLAGS_rmodules_$(ARCH-postcar-y)) -nostdlib -r -o $@ $^ + +ifeq ($(CONFIG_ARCH_POSTCAR_X86_32),y) +$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_DOTO), 0,x86_32)) +else +$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_DOTO), 0,x86_64)) +endif + +$(SIPI_BIN): $(SIPI_RMOD) + $(OBJCOPY_postcar) -O binary $< $@ + +$(call src-to-obj,postcar,$(SIPI_BIN).manual): $(SIPI_BIN) + @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" + cd $(dir $<); $(OBJCOPY_rmodules_$(ARCH-postcar-y)) -I binary $(notdir $<) $(target-objcopy) $(abspath $@) diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc index 9454f8f..3381d04 100644 --- a/src/cpu/x86/lapic/Makefile.inc +++ b/src/cpu/x86/lapic/Makefile.inc @@ -1,4 +1,5 @@ ramstage-y += lapic.c +postcar-y += lapic.c ramstage-y += lapic_cpu_init.c ramstage-$(CONFIG_SMP) += secondary.S romstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 3889c7d..0042f49 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -194,6 +194,19 @@ } } +#if ENV_POSTCAR +static inline unsigned long cpu_index(void) +{ + int i; + + for (i=0; i < CONFIG_MAX_CPUS; i++) { + if (mp_get_apic_id(i) == lapicid()) + return i; + } + return 0; +} +#endif + static void park_this_cpu(void *unused) { stop_this_cpu(); @@ -203,12 +216,11 @@ * been loaded. */ static void asmlinkage ap_init(unsigned int cpu) { - struct cpu_info *info; + static struct cpu_info *info; /* Ensure the local APIC is enabled */ enable_lapic(); - info = cpu_info(); info->index = cpu; info->cpu = cpus[cpu].dev; @@ -399,7 +411,7 @@ /* Assuming linear APIC space allocation. AP will set its own APIC id in the ap_init() path above. */ - cpu_path.apic.apic_id = info->cpu->path.apic.apic_id + i; + cpu_path.apic.apic_id = lapicid() + i; /* Allocate the new CPU device structure */ new = alloc_find_dev(cpu_bus, &cpu_path); @@ -565,7 +577,7 @@ static void init_bsp(struct bus *cpu_bus) { struct device_path cpu_path; - struct cpu_info *info; + static struct cpu_info *info; /* Print processor name */ fill_processor_name(processor_name); @@ -579,9 +591,9 @@ cpu_path.apic.apic_id = lapicid(); /* Find the device structure for the boot CPU. */ - info = cpu_info(); info->cpu = alloc_find_dev(cpu_bus, &cpu_path); info->cpu->name = processor_name; + info->index = cpu_index(); if (info->index != 0) printk(BIOS_CRIT, "BSP index(%d) != 0!\n", info->index); @@ -661,8 +673,7 @@ static void mp_initialize_cpu(void) { /* Call back into driver infrastructure for the AP initialization. */ - struct cpu_info *info = cpu_info(); - cpu_initialize(info->index); + cpu_initialize(cpu_index()); } /* Returns APIC id for coreboot CPU number or < 0 on failure. */ diff --git a/src/cpu/x86/mtrr/Makefile.inc b/src/cpu/x86/mtrr/Makefile.inc index caa6e9c..15ee4e1 100644 --- a/src/cpu/x86/mtrr/Makefile.inc +++ b/src/cpu/x86/mtrr/Makefile.inc @@ -1,4 +1,5 @@ ramstage-y += mtrr.c +postcar-y += mtrr.c romstage-y += earlymtrr.c bootblock-y += earlymtrr.c diff --git a/src/cpu/x86/name/Makefile.inc b/src/cpu/x86/name/Makefile.inc index 5dba1a2..6c62814 100644 --- a/src/cpu/x86/name/Makefile.inc +++ b/src/cpu/x86/name/Makefile.inc @@ -14,3 +14,4 @@ ## ramstage-y += name.c +postcar-y += name.c diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index 32f5ea7..83b7ff8 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -14,6 +14,7 @@ ## ramstage-y += smm_module_loader.c +postcar-y += smm_module_loader.c ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) $(eval $(call create_class_compiler,smm,x86_32)) @@ -23,6 +24,14 @@ $(eval $(call create_class_compiler,smmstub,x86_64)) endif +ifeq ($(CONFIG_ARCH_POSTCAR_X86_32),y) +$(eval $(call create_class_compiler,smm,x86_32)) +$(eval $(call create_class_compiler,smmstub,x86_32)) +else +$(eval $(call create_class_compiler,smm,x86_64)) +$(eval $(call create_class_compiler,smmstub,x86_64)) +endif + smmstub-generic-ccopts += -D__SMM__ smm-generic-ccopts += -D__SMM__ smm-c-deps:=$$(OPTION_TABLE_H) @@ -36,6 +45,10 @@ @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" cd $(dir $<); $(OBJCOPY_smm) -I binary $(notdir $<) $(target-objcopy) $(abspath $@) +$(call src-to-obj,postcar,$(obj)/cpu/x86/smm/smm.manual): $(obj)/smm/smm + @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" + cd $(dir $<); $(OBJCOPY_smm) -I binary $(notdir $<) $(target-objcopy) $(abspath $@) + ifeq ($(CONFIG_SMM_TSEG),y) smmstub-y += smm_stub.S @@ -45,6 +58,9 @@ ramstage-srcs += $(obj)/cpu/x86/smm/smm.manual ramstage-srcs += $(obj)/cpu/x86/smm/smmstub.manual +postcar-srcs += $(obj)/cpu/x86/smm/smm.manual +postcar-srcs += $(obj)/cpu/x86/smm/smmstub.manual + # SMM Stub Module. The stub is used as a trampoline for relocation and normal # SMM handling. $(obj)/smmstub/smmstub.o: $$(smmstub-objs) @@ -57,6 +73,13 @@ $(eval $(call rmodule_link,$(obj)/smmstub/smmstub.elf, $(obj)/smmstub/smmstub.o, 0,x86_64)) endif +ifeq ($(CONFIG_ARCH_POSTCAR_X86_32),y) +$(eval $(call rmodule_link,$(obj)/smmstub/smmstub.elf, $(obj)/smmstub/smmstub.o, 0,x86_32)) +else +$(eval $(call rmodule_link,$(obj)/smmstub/smmstub.elf, $(obj)/smmstub/smmstub.o, 0,x86_64)) +endif + + $(obj)/smmstub/smmstub: $(obj)/smmstub/smmstub.elf.rmod $(OBJCOPY_smmstub) -O binary $< $@ @@ -64,6 +87,10 @@ @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" cd $(dir $<); $(OBJCOPY_smmstub) -I binary $(notdir $<) $(target-objcopy) $(abspath $@) +$(call src-to-obj,postcar,$(obj)/cpu/x86/smm/smmstub.manual): $(obj)/smmstub/smmstub + @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" + cd $(dir $<); $(OBJCOPY_smmstub) -I binary $(notdir $<) $(target-objcopy) $(abspath $@) + # C-based SMM handler. ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) @@ -72,6 +99,12 @@ $(eval $(call rmodule_link,$(obj)/smm/smm.elf, $(obj)/smm/smm.o, $(CONFIG_SMM_MODULE_HEAP_SIZE),x86_64)) endif +ifeq ($(CONFIG_ARCH_POSTCAR_X86_32),y) +$(eval $(call rmodule_link,$(obj)/smm/smm.elf, $(obj)/smm/smm.o, $(CONFIG_SMM_MODULE_HEAP_SIZE),x86_32)) +else +$(eval $(call rmodule_link,$(obj)/smm/smm.elf, $(obj)/smm/smm.o, $(CONFIG_SMM_MODULE_HEAP_SIZE),x86_64)) +endif + $(obj)/smm/smm: $(obj)/smm/smm.elf.rmod $(OBJCOPY_smm) -O binary $< $@ @@ -84,6 +117,7 @@ ifeq ($(CONFIG_HAVE_SMI_HANDLER),y) ramstage-srcs += $(obj)/cpu/x86/smm/smm.manual +postcar-srcs += $(obj)/cpu/x86/smm/smm.manual endif smm-y += smmhandler.S diff --git a/src/device/Makefile.inc b/src/device/Makefile.inc index bed0f71..3a2636c 100644 --- a/src/device/Makefile.inc +++ b/src/device/Makefile.inc @@ -1,9 +1,14 @@ ramstage-y += device.c +postcar-y += device.c ramstage-y += root_device.c +postcar-y += root_device.c ramstage-y += cpu_device.c +postcar-y += cpu_device.c ramstage-y += device_util.c +postcar-y += device_util.c ramstage-$(CONFIG_PCI) += pci_class.c ramstage-$(CONFIG_PCI) += pci_device.c +postcar-$(CONFIG_PCI) += pci_device.c ramstage-$(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT) += hypertransport.c ramstage-$(CONFIG_PCIX_PLUGIN_SUPPORT) += pcix_device.c ramstage-$(CONFIG_PCIEXP_PLUGIN_SUPPORT) += pciexp_device.c @@ -12,9 +17,13 @@ ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_32) += pnp_device.c ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_64) += pnp_device.c ramstage-$(CONFIG_PCI) += pci_ops.c +postcar-$(CONFIG_PCI) += pci_ops.c +postcar-$(CONFIG_MMCONF_SUPPORT) += pci_ops_mmconf.c ramstage-$(CONFIG_MMCONF_SUPPORT) += pci_ops_mmconf.c +postcar-$(CONFIG_PCI) += pci_early.c ramstage-$(CONFIG_PCI) += pci_early.c ramstage-$(CONFIG_PCI) += pci_rom.c +postcar-$(CONFIG_PCI) += pci_rom.c ramstage-y += smbus_ops.c ifeq ($(CONFIG_AZALIA_PLUGIN_SUPPORT),y) diff --git a/src/device/pci_early.c b/src/device/pci_early.c index 4cf8c7e..568b517 100644 --- a/src/device/pci_early.c +++ b/src/device/pci_early.c @@ -20,7 +20,7 @@ #include <device/pci_def.h> #include <delay.h> -#if !ENV_RAMSTAGE +#if !ENV_RAMSTAGE && !ENV_POSTCAR unsigned pci_find_next_capability(pci_devfn_t dev, unsigned cap, unsigned last) { unsigned pos = 0; diff --git a/src/drivers/elog/Makefile.inc b/src/drivers/elog/Makefile.inc index cce1c3d..191a89a 100644 --- a/src/drivers/elog/Makefile.inc +++ b/src/drivers/elog/Makefile.inc @@ -1,7 +1,7 @@ bootblock-$(CONFIG_ELOG_PRERAM) += elog.c verstage-$(CONFIG_ELOG_PRERAM) += elog.c romstage-$(CONFIG_ELOG_PRERAM) += elog.c -postcar-$(CONFIG_ELOG_PRERAM) += elog.c +postcar-$(CONFIG_ELOG) += elog.c ramstage-$(CONFIG_ELOG) += elog.c smm-$(CONFIG_ELOG_GSMI) += elog.c gsmi.c diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index 79fe5f8..efe6208 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -28,6 +28,7 @@ ramstage-y += debug.c ramstage-$(CONFIG_RUN_FSP_GOP) += graphics.c +postcar-$(CONFIG_RUN_FSP_GOP) += graphics.c ramstage-y += hand_off_block.c ramstage-$(CONFIG_DISPLAY_FSP_HEADER) += header_display.c ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c @@ -39,6 +40,10 @@ ramstage-y += util.c ramstage-$(CONFIG_MMA) += mma_core.c +postcar-y += silicon_init.c +postcar-y += util.c +postcar-y += debug.c + postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c postcar-$(CONFIG_FSP_CAR) += temp_ram_exit.c postcar-$(CONFIG_FSP_CAR) += util.c diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index 0670663..834dbb0 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -54,13 +54,14 @@ post_code(POST_FSP_SILICON_EXIT); fsp_debug_after_silicon_init(status); - +#if 0 // TODO: bad hack /* Handle any errors returned by FspSiliconInit */ fsp_handle_reset(status); if (status != FSP_SUCCESS) { printk(BIOS_SPEW, "FspSiliconInit returned 0x%08x\n", status); die("FspSiliconINit returned an error!\n"); } +#endif } void fsps_load(bool s3wake) diff --git a/src/drivers/intel/gma/Makefile.inc b/src/drivers/intel/gma/Makefile.inc index 274955a..c9dbb13 100644 --- a/src/drivers/intel/gma/Makefile.inc +++ b/src/drivers/intel/gma/Makefile.inc @@ -20,7 +20,7 @@ endif ramstage-$(CONFIG_INTEL_GMA_ACPI) += acpi.c ramstage-$(CONFIG_INTEL_GMA_ACPI) += opregion.c - +postcar-$(CONFIG_INTEL_GMA_ACPI) += opregion.c # add_vbt_to_cbfs, first argument is the filename in cbfs, the second one # is the filename in the coreboot tree. add_vbt_to_cbfs= \ diff --git a/src/drivers/mrc_cache/Makefile.inc b/src/drivers/mrc_cache/Makefile.inc index 0d226fe..f3a6dd9 100644 --- a/src/drivers/mrc_cache/Makefile.inc +++ b/src/drivers/mrc_cache/Makefile.inc @@ -1,2 +1,3 @@ romstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c +postcar-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c diff --git a/src/drivers/mrc_cache/mrc_cache.c b/src/drivers/mrc_cache/mrc_cache.c index 4dd0dbc..549470a 100644 --- a/src/drivers/mrc_cache/mrc_cache.c +++ b/src/drivers/mrc_cache/mrc_cache.c @@ -542,7 +542,7 @@ printk(BIOS_ERR, "MRC: invalidation failed for '%s'.\n", name); } -static void update_mrc_cache(void *unused) +void update_mrc_cache(void *unused) { update_mrc_cache_by_type(MRC_TRAINING_DATA); diff --git a/src/drivers/pc80/pc/Makefile.inc b/src/drivers/pc80/pc/Makefile.inc index 8c348e3..70cc516 100644 --- a/src/drivers/pc80/pc/Makefile.inc +++ b/src/drivers/pc80/pc/Makefile.inc @@ -1,5 +1,6 @@ ifeq ($(CONFIG_ARCH_X86),y) +postcar-y += isa-dma.c ramstage-y += isa-dma.c ramstage-y += i8254.c ramstage-y += i8259.c diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c index 9b5f57c..62f315f 100644 --- a/src/drivers/uart/uart8250io.c +++ b/src/drivers/uart/uart8250io.c @@ -124,7 +124,7 @@ uart8250_tx_flush(uart_platform_base(idx)); } -#if ENV_RAMSTAGE +#if ENV_RAMSTAGE || ENV_POSTCAR void uart_fill_lb(void *data) { struct lb_serial serial; diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c index 94a7fc9..2db824a 100644 --- a/src/drivers/uart/uart8250mem.c +++ b/src/drivers/uart/uart8250mem.c @@ -147,7 +147,7 @@ uart8250_mem_tx_flush(base); } -#if ENV_RAMSTAGE +#if ENV_RAMSTAGE || ENV_POSTCAR void uart_fill_lb(void *data) { struct lb_serial serial; diff --git a/src/ec/google/chromeec/Makefile.inc b/src/ec/google/chromeec/Makefile.inc index 85e2599..949525f 100644 --- a/src/ec/google/chromeec/Makefile.inc +++ b/src/ec/google/chromeec/Makefile.inc @@ -6,7 +6,9 @@ smm-$(CONFIG_EC_GOOGLE_CHROMEEC_BOARDID) += ec_boardid.c bootblock-y += ec.c +postcar-y += ec.c bootblock-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c +postcar-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c ramstage-y += ec.c crosec_proto.c vstore.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c @@ -31,6 +33,7 @@ verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SWITCHES) += switches.c romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SWITCHES) += switches.c +postcar-$(CONFIG_EC_GOOGLE_CHROMEEC_SWITCHES) += switches.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SWITCHES) += switches.c CHROMEEC_SOURCE ?= $(top)/3rdparty/chromeec diff --git a/src/include/memlayout.h b/src/include/memlayout.h index a8b3a60..7d65fbd 100644 --- a/src/include/memlayout.h +++ b/src/include/memlayout.h @@ -40,7 +40,7 @@ /* Default is that currently ramstage, smm, and rmodules have a heap. */ #ifndef ARCH_STAGE_HAS_HEAP_SECTION -#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM || ENV_RMODULE) +#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM || ENV_RMODULE || ENV_POSTCAR) #endif #define STR(x) #x diff --git a/src/include/mrc_cache.h b/src/include/mrc_cache.h index 498ecbf..6ecb132 100644 --- a/src/include/mrc_cache.h +++ b/src/include/mrc_cache.h @@ -41,4 +41,6 @@ int mrc_cache_stash_data(int type, uint32_t version, const void *data, size_t size); +void update_mrc_cache(void *unused); + #endif /* _COMMON_MRC_CACHE_H_ */ diff --git a/src/include/rules.h b/src/include/rules.h index deea50b..424fa39 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -270,7 +270,7 @@ * For now only x86 is supported. */ -#if ENV_X86 && (defined(__PRE_RAM__) || ENV_SMM || ENV_POSTCAR) +#if ENV_X86 && (defined(__PRE_RAM__) || ENV_SMM) #define __SIMPLE_DEVICE__ #endif diff --git a/src/include/stddef.h b/src/include/stddef.h index a82a68d..865ab12 100644 --- a/src/include/stddef.h +++ b/src/include/stddef.h @@ -23,10 +23,10 @@ /* The devicetree data structures are only mutable in ramstage. All other stages have a constant devicetree. */ -#if !ENV_RAMSTAGE -#define DEVTREE_EARLY 1 -#else +#if ENV_RAMSTAGE || ENV_POSTCAR #define DEVTREE_EARLY 0 +#else +#define DEVTREE_EARLY 1 #endif #if DEVTREE_EARLY diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 2fd4e4c..4be2fc9 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -86,6 +86,7 @@ romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c romstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c ramstage-y += region_file.c +postcar-y += region_file.c romstage-y += region_file.c ramstage-y += romstage_handoff.c romstage-y += romstage_handoff.c @@ -113,20 +114,27 @@ ramstage-y += prog_ops.c ramstage-y += hardwaremain.c ramstage-y += selfboot.c +postcar-y += selfboot.c ramstage-y += coreboot_table.c +postcar-y += coreboot_table.c ramstage-y += bootmem.c +postcar-y += bootmem.c ramstage-y += fmap.c ramstage-y += memchr.c ramstage-y += memcmp.c ramstage-y += malloc.c +postcar-y += malloc.c smm-$(CONFIG_SMM_TSEG) += malloc.c ramstage-y += dimm_info_util.c ramstage-y += delay.c ramstage-y += fallback_boot.c +postcar-y += fallback_boot.c ramstage-y += compute_ip_checksum.c +postcar-y += compute_ip_checksum.c ramstage-y += cbfs.c ramstage-y += lzma.c lzmadecode.c ramstage-y += stack.c +postcar-y += stack.c ramstage-y += hexstrtobin.c ramstage-y += wrdd.c ramstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c @@ -139,6 +147,7 @@ ramstage-y += edid_fill_fb.c endif ramstage-y += memrange.c +postcar-y += memrange.c ramstage-$(CONFIG_COOP_MULTITASKING) += thread.c ramstage-$(CONFIG_TIMER_QUEUE) += timer_queue.c ramstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c diff --git a/src/lib/bootmode.c b/src/lib/bootmode.c index 29682eb..3b1b4c3 100644 --- a/src/lib/bootmode.c +++ b/src/lib/bootmode.c @@ -16,7 +16,7 @@ #include <bootmode.h> #include <vendorcode/google/chromeos/chromeos.h> -#if ENV_RAMSTAGE +#if ENV_RAMSTAGE || ENV_POSTCAR static int gfx_init_done = -1; int gfx_get_init_done(void) diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index ff1cb95..ae1b416 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -303,8 +303,8 @@ imd_region_used(cbmem_get_imd(), baseptr, size); } -#if ENV_RAMSTAGE || (IS_ENABLED(CONFIG_EARLY_CBMEM_LIST) \ - && (ENV_POSTCAR || ENV_ROMSTAGE)) +#if ENV_RAMSTAGE || ENV_POSTCAR || (IS_ENABLED(CONFIG_EARLY_CBMEM_LIST) \ + && (ENV_ROMSTAGE)) /* * -fdata-sections doesn't work so well on read only strings. They all * get put in the same section even though those strings may never be diff --git a/src/lib/memrange.c b/src/lib/memrange.c index 96d7524..a32f284 100644 --- a/src/lib/memrange.c +++ b/src/lib/memrange.c @@ -47,7 +47,7 @@ range_entry_unlink(&ranges->free_list, r); return r; } - if (ENV_RAMSTAGE) + if (ENV_RAMSTAGE || ENV_POSTCAR) return malloc(sizeof(struct range_entry)); return NULL; } diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index ac80a62..a9a6681 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -160,7 +160,7 @@ die("Ramstage was not loaded!\n"); } -#ifdef __RAMSTAGE__ // gc-sections should take care of this +#if ENV_RAMSTAGE || ENV_POSTCAR // gc-sections should take care of this static struct prog global_payload = PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/payload"); @@ -213,10 +213,12 @@ timestamp_add_now(TS_SELFBOOT_JUMP); +#if ENV_RAMSTAGE /* Before we go off to run the payload, see if * we stayed within our bounds. */ checkstack(_estack, 0); +#endif prog_run(payload); } diff --git a/src/lib/program.ld b/src/lib/program.ld index 156b862..5694e72 100644 --- a/src/lib/program.ld +++ b/src/lib/program.ld @@ -55,7 +55,7 @@ KEEP(*(.rsbe_init)); _ersbe_init_begin = .; -#if ENV_RAMSTAGE +#if ENV_RAMSTAGE || ENV_POSTCAR . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _pci_drivers = .; KEEP(*(.rodata.pci_driver)); diff --git a/src/mainboard/google/dragonegg/Kconfig b/src/mainboard/google/dragonegg/Kconfig index 39228f4..2b51841 100644 --- a/src/mainboard/google/dragonegg/Kconfig +++ b/src/mainboard/google/dragonegg/Kconfig @@ -28,15 +28,15 @@ default 512 # Select this option to enable use of cr50 SPI TPM on dragon egg. -config DRAGONEGG_USE_SPI_TPM - bool - default y - select MAINBOARD_HAS_SPI_TPM_CR50 - select MAINBOARD_HAS_TPM2 +#config DRAGONEGG_USE_SPI_TPM +# bool +# default y +# select MAINBOARD_HAS_SPI_TPM_CR50 +# select MAINBOARD_HAS_TPM2 -config DRIVER_TPM_SPI_BUS - depends on DRAGONEGG_USE_SPI_TPM - default 0x1 +#config DRIVER_TPM_SPI_BUS +# depends on DRAGONEGG_USE_SPI_TPM +# default 0x1 config GBB_HWID string @@ -78,6 +78,7 @@ config VBOOT select VBOOT_LID_SWITCH select EC_GOOGLE_CHROMEEC_SWITCHES + select VBOOT_MOCK_SECDATA select HAS_RECOVERY_MRC_CACHE select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN diff --git a/src/mainboard/google/dragonegg/Makefile.inc b/src/mainboard/google/dragonegg/Makefile.inc index 39e94d0..0388de3 100644 --- a/src/mainboard/google/dragonegg/Makefile.inc +++ b/src/mainboard/google/dragonegg/Makefile.inc @@ -21,10 +21,12 @@ romstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-y += romstage_fsp_params.c +postcar-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c ramstage-y += mainboard.c ramstage-y += ramstage.c +postcar-y += ramstage.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c diff --git a/src/mainboard/google/dragonegg/chromeos.c b/src/mainboard/google/dragonegg/chromeos.c index 657320c..ac26a7d 100644 --- a/src/mainboard/google/dragonegg/chromeos.c +++ b/src/mainboard/google/dragonegg/chromeos.c @@ -21,7 +21,7 @@ #include <variant/gpio.h> -#if ENV_RAMSTAGE +#if ENV_RAMSTAGE || ENV_POSTCAR #include <boot/coreboot_tables.h> void fill_lb_gpios(struct lb_gpios *gpios) diff --git a/src/mainboard/google/dragonegg/variants/baseboard/Makefile.inc b/src/mainboard/google/dragonegg/variants/baseboard/Makefile.inc index 22736b9..f86ac87 100644 --- a/src/mainboard/google/dragonegg/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/dragonegg/variants/baseboard/Makefile.inc @@ -18,3 +18,5 @@ romstage-y += memory.c ramstage-y += gpio.c + +postcar-y += gpio.c diff --git a/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb b/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb index 257ad1d..722956e 100644 --- a/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb @@ -12,14 +12,14 @@ device lapic 0 on end end - register "PchHdaDspEnable" = "1" - register "PchHdaAudioLinkSsp0" = "1" - register "PchHdaAudioLinkSsp1" = "1" + register "PchHdaDspEnable" = "0" + register "PchHdaAudioLinkSsp0" = "0" + register "PchHdaAudioLinkSsp1" = "0" # FSP configuration register "SaGv" = "SaGv_Enabled" register "SmbusEnable" = "1" - register "ScsEmmcHs400Enabled" = "1" + register "ScsEmmcHs400Enabled" = "0" register "usb2_ports[0]" = "USB2_PORT_LONG(OC2)" # Type-C Port 1 register "usb2_ports[1]" = "USB2_PORT_LONG(OC2)" # Type-C Port 2 @@ -278,7 +278,7 @@ device pci 19.0 on end # I2C #4 device pci 19.1 off end # I2C #5 device pci 19.2 on end # UART #2 - device pci 1a.0 on end # eMMC + device pci 1a.0 off end # eMMC device pci 1c.0 on chip drivers/intel/wifi register "wake" = "GPE0_DW0_06" @@ -311,7 +311,7 @@ device pci 1f.0 on end # LPC Interface device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA + device pci 1f.3 off end # Intel HDA device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI device pci 1f.6 off end # GbE diff --git a/src/mainboard/intel/icelake_rvp/Kconfig b/src/mainboard/intel/icelake_rvp/Kconfig index 7cc4e53..0e1b69d 100644 --- a/src/mainboard/intel/icelake_rvp/Kconfig +++ b/src/mainboard/intel/icelake_rvp/Kconfig @@ -15,7 +15,7 @@ select SOC_INTEL_ICELAKE select MAINBOARD_USES_IFD_EC_REGION select INTEL_LPSS_UART_FOR_CONSOLE - + select EC_ACPI config MAINBOARD_DIR string default "intel/icelake_rvp" diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index ae80a02..570e47f 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -29,16 +29,19 @@ bootblock-y += vbnv.c verstage-y += vbnv.c romstage-y += vbnv.c +postcar-y += vbnv.c ramstage-y += vbnv.c bootblock-$(CONFIG_VBOOT_VBNV_CMOS) += vbnv_cmos.c verstage-$(CONFIG_VBOOT_VBNV_CMOS) += vbnv_cmos.c romstage-$(CONFIG_VBOOT_VBNV_CMOS) += vbnv_cmos.c +postcar-$(CONFIG_VBOOT_VBNV_CMOS) += vbnv_cmos.c ramstage-$(CONFIG_VBOOT_VBNV_CMOS) += vbnv_cmos.c bootblock-$(CONFIG_VBOOT_VBNV_CMOS_BACKUP_TO_FLASH) += vbnv_flash.c verstage-$(CONFIG_VBOOT_VBNV_CMOS_BACKUP_TO_FLASH) += vbnv_flash.c romstage-$(CONFIG_VBOOT_VBNV_CMOS_BACKUP_TO_FLASH) += vbnv_flash.c +postcar-$(CONFIG_VBOOT_VBNV_CMOS_BACKUP_TO_FLASH) += vbnv_flash.c ramstage-$(CONFIG_VBOOT_VBNV_CMOS_BACKUP_TO_FLASH) += vbnv_flash.c bootblock-$(CONFIG_VBOOT_VBNV_EC) += vbnv_ec.c diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index 22d350c..f55e41a 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -18,7 +18,9 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c ramstage-$(CONFIG_MMA) += mma.c ramstage-$(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) += acpi_wake_source.c +postcar-$(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) += acpi_wake_source.c ramstage-y += vbt.c +postcar-y += vbt.c ramstage-$(CONFIG_SOC_INTEL_COMMON_NHLT) += nhlt.c bootblock-$(CONFIG_TPM_CR50) += tpm_tis.c diff --git a/src/soc/intel/common/block/acpi/Makefile.inc b/src/soc/intel/common/block/acpi/Makefile.inc index c6bdac5..d792111 100644 --- a/src/soc/intel/common/block/acpi/Makefile.inc +++ b/src/soc/intel/common/block/acpi/Makefile.inc @@ -1 +1,2 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI) += acpi.c +postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI) += acpi.c diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 0ea6cb9..247e9e4 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -446,7 +446,7 @@ #if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) /* Save wake source data for ACPI _SWS methods in NVS */ -static void acpi_save_wake_source(void *unused) +void acpi_save_wake_source(void *unused) { global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); uint32_t pm1, *gpe0; diff --git a/src/soc/intel/common/block/cpu/Makefile.inc b/src/soc/intel/common/block/cpu/Makefile.inc index 5207227..57f1386 100644 --- a/src/soc/intel/common/block/cpu/Makefile.inc +++ b/src/soc/intel/common/block/cpu/Makefile.inc @@ -7,6 +7,8 @@ postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CAR) += car/exit_car.S postcar-$(CONFIG_FSP_CAR) += car/exit_car_fsp.S +postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c +postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT) += mp_init.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT) += mp_init.c diff --git a/src/soc/intel/common/block/gpio/Makefile.inc b/src/soc/intel/common/block/gpio/Makefile.inc index b0ffee3..8db62fd 100644 --- a/src/soc/intel/common/block/gpio/Makefile.inc +++ b/src/soc/intel/common/block/gpio/Makefile.inc @@ -1,4 +1,5 @@ bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO) += gpio.c +postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO) += gpio.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO) += gpio.c romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO) += gpio.c smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO) += gpio.c diff --git a/src/soc/intel/common/block/graphics/Makefile.inc b/src/soc/intel/common/block/graphics/Makefile.inc index 44dfc7e..f58b3e7 100644 --- a/src/soc/intel/common/block/graphics/Makefile.inc +++ b/src/soc/intel/common/block/graphics/Makefile.inc @@ -1 +1,2 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GRAPHICS) += graphics.c +postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GRAPHICS) += graphics.c diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c index f72adfc..a6df4ee 100644 --- a/src/soc/intel/common/block/i2c/i2c.c +++ b/src/soc/intel/common/block/i2c/i2c.c @@ -47,7 +47,7 @@ return EARLY_I2C_BASE(bus); } -#if !ENV_RAMSTAGE +#if !ENV_RAMSTAGE && !ENV_POSTCAR static int lpss_i2c_early_init_bus(unsigned int bus) { const struct dw_i2c_bus_config *config; diff --git a/src/soc/intel/common/block/include/intelblocks/acpi.h b/src/soc/intel/common/block/include/intelblocks/acpi.h index 6b1b9bd..cfbdf15 100644 --- a/src/soc/intel/common/block/include/intelblocks/acpi.h +++ b/src/soc/intel/common/block/include/intelblocks/acpi.h @@ -91,4 +91,6 @@ */ void soc_power_states_generation(int core_id, int cores_per_package); +void acpi_save_wake_source(void *unused); + #endif /* _SOC_INTEL_COMMON_BLOCK_ACPI_H_ */ diff --git a/src/soc/intel/common/block/include/intelblocks/systemagent.h b/src/soc/intel/common/block/include/intelblocks/systemagent.h index babf9ce..329051f 100644 --- a/src/soc/intel/common/block/include/intelblocks/systemagent.h +++ b/src/soc/intel/common/block/include/intelblocks/systemagent.h @@ -64,6 +64,8 @@ */ void sa_add_fixed_mmio_resources(struct device *dev, int *resource_cnt, const struct sa_mmio_descriptor *sa_fixed_resources, size_t count); + +void systemagent_read_resources(struct device *dev); /* * API to set BIOS Reset CPL through MCHBAR * SoC to provide BIOS_RESET_CPL register offset through soc/systemagent.h diff --git a/src/soc/intel/common/block/itss/Makefile.inc b/src/soc/intel/common/block/itss/Makefile.inc index bc0e97a..ba3bcb9 100644 --- a/src/soc/intel/common/block/itss/Makefile.inc +++ b/src/soc/intel/common/block/itss/Makefile.inc @@ -1,3 +1,4 @@ bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_ITSS) += itss.c romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_ITSS) += itss.c +postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_ITSS) += itss.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_ITSS) += itss.c diff --git a/src/soc/intel/common/block/lpc/Makefile.inc b/src/soc/intel/common/block/lpc/Makefile.inc index 428ade9..400dfe4 100644 --- a/src/soc/intel/common/block/lpc/Makefile.inc +++ b/src/soc/intel/common/block/lpc/Makefile.inc @@ -1,6 +1,7 @@ bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPC) += lpc_lib.c romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPC) += lpc_lib.c +postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPC) += lpc_lib.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPC) += lpc_lib.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPC) += lpc.c diff --git a/src/soc/intel/common/block/pcr/Makefile.inc b/src/soc/intel/common/block/pcr/Makefile.inc index 0577e0a..3da14ea 100644 --- a/src/soc/intel/common/block/pcr/Makefile.inc +++ b/src/soc/intel/common/block/pcr/Makefile.inc @@ -1,5 +1,6 @@ bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCR) += pcr.c romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCR) += pcr.c +postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCR) += pcr.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCR) += pcr.c smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCR) += pcr.c verstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCR) += pcr.c diff --git a/src/soc/intel/common/block/systemagent/Makefile.inc b/src/soc/intel/common/block/systemagent/Makefile.inc index 0c29636..e4d4b0b 100644 --- a/src/soc/intel/common/block/systemagent/Makefile.inc +++ b/src/soc/intel/common/block/systemagent/Makefile.inc @@ -3,3 +3,4 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA) += systemagent_early.c postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA) += systemagent_early.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA) += systemagent.c +postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA) += systemagent.c diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 9608359..cfbbbe9 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -250,7 +250,7 @@ *resource_cnt = index; } -static void systemagent_read_resources(struct device *dev) +void systemagent_read_resources(struct device *dev) { int index = 0; diff --git a/src/soc/intel/common/block/systemagent/systemagent_early.c b/src/soc/intel/common/block/systemagent/systemagent_early.c index c1cef5d..7884961 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_early.c +++ b/src/soc/intel/common/block/systemagent/systemagent_early.c @@ -24,7 +24,7 @@ #include "systemagent_def.h" #include <timer.h> -#if !ENV_RAMSTAGE +#if !ENV_RAMSTAGE && !ENV_POSTCAR void bootblock_systemagent_early_init(void) { uint32_t reg; diff --git a/src/soc/intel/icelake/Makefile.inc b/src/soc/intel/icelake/Makefile.inc index 74c9182..84458aa 100644 --- a/src/soc/intel/icelake/Makefile.inc +++ b/src/soc/intel/icelake/Makefile.inc @@ -33,12 +33,15 @@ romstage-y += uart.c ramstage-y += acpi.c +postcar-y += acpi.c ramstage-y += chip.c ramstage-y += cpu.c +postcar-y += cpu.c ramstage-y += finalize.c ramstage-y += fsp_params.c ramstage-y += gpio.c ramstage-y += graphics.c +postcar-y += graphics.c ramstage-y += gspi.c ramstage-y += gpio.c ramstage-y += i2c.c @@ -50,17 +53,22 @@ ramstage-y += pmutil.c ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c ramstage-y += smmrelocate.c +postcar-y += smmrelocate.c ramstage-y += spi.c ramstage-y += systemagent.c ramstage-y += uart.c ramstage-y += sd.c +ramstage-y += payload_init.c + smm-y += gpio.c smm-y += p2sb.c smm-y += pmutil.c smm-y += smihandler.c smm-y += uart.c - +postcar-y += fsp_params.c +postcar-y += gpio.c +postcar-y += payload_init.c postcar-y += memmap.c postcar-y += pmutil.c postcar-y += i2c.c diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c index 39ec58a..c147692 100644 --- a/src/soc/intel/icelake/acpi.c +++ b/src/soc/intel/icelake/acpi.c @@ -220,7 +220,7 @@ gnvs->dpte = config->dptf_enable; /* Fill in the Wifi Region id */ - gnvs->cid1 = wifi_regulatory_domain(); +// gnvs->cid1 = wifi_regulatory_domain(); // TODO: bad hack /* Set USB2/USB3 wake enable bitmaps. */ gnvs->u2we = config->usb2_wake_enable_bitmap; diff --git a/src/soc/intel/icelake/include/soc/payload_init.h b/src/soc/intel/icelake/include/soc/payload_init.h new file mode 100644 index 0000000..4e838cd --- /dev/null +++ b/src/soc/intel/icelake/include/soc/payload_init.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#ifndef _PAYLOAD_INIT_H_ +#define _PAYLOAD_INIT_H_ + +#include <stdint.h> + +void postcar_payload_init(void); +#endif diff --git a/src/soc/intel/icelake/payload_init.c b/src/soc/intel/icelake/payload_init.c new file mode 100644 index 0000000..20fe90c --- /dev/null +++ b/src/soc/intel/icelake/payload_init.c @@ -0,0 +1,237 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootstate.h> +#include <boot/tables.h> +#include <console/console.h> +#include <cpu/cpu.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mp.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <intelblocks/systemagent.h> +#include <fsp/api.h> +#include <fsp/util.h> +#include <romstage_handoff.h> +#include <soc/pci_devs.h> +#include <string.h> +#include <program_loading.h> +#include <soc/payload_init.h> + +#include <cpu/intel/microcode.h> +#include <intelblocks/cpulib.h> +#include <intelblocks/mp_init.h> +#include <intelblocks/msr.h> +#include <intelblocks/acpi.h> +#include <soc/cpu.h> +#include <vendorcode/google/chromeos/chromeos.h> + +#include "mrc_cache.h" +#include <soc/intel/common/acpi.h> + +#define XHCI_FIXED_BAR 0xb2310000 +#define XHCI_BAR_SIZE 0x10000 + +#define IGD_FIXED_BAR 0xb0000000 +#define IGD_BAR_SIZE 0x1000000 +#define IGD_FIXED_BAR_2 0xa0000000 +#define IGD_BAR_SIZE_2 0x10000000 + +static void pch_set_bar(struct device *dev, uintptr_t tempbar, + uintptr_t tempbar_1, uintptr_t tempbar_2) +{ + uint8_t pcireg; + + /* Assign Resources to Thermal Device */ + /* Clear BIT 1-2 of Command Register */ + pcireg = pci_read_config8(dev, PCI_COMMAND); + pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + pci_write_config8(dev, PCI_COMMAND, pcireg); + + /* Program Temporary BAR for Thermal Device */ + pci_write_config32(dev, PCI_BASE_ADDRESS_0, tempbar); + pci_write_config32(dev, PCI_BASE_ADDRESS_1, tempbar_1); + pci_write_config32(dev, PCI_BASE_ADDRESS_2, tempbar_2); + + /* Enable Bus Master and MMIO Space */ + pcireg = pci_read_config8(dev, PCI_COMMAND); + pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config8(dev, PCI_COMMAND, pcireg); +} + +static void allocate_device_resource(struct device *dev, int offset, + uint32_t base, uint32_t size) +{ + struct resource *res; + + res = new_resource(dev, offset); + res->base = base; + res->size = size; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | + IORESOURCE_FIXED; +} + +static void set_device_resource(struct device *dev, int offset, + uint32_t base) +{ + struct resource *res; + + res = find_resource(dev, offset); + dev->command |= 2; + res->flags = IORESOURCE_STORED; + report_resource_stored(dev, res, "Device BAR 0"); + + pci_dev_enable_resources(dev); +} + +static void enable_xhci_device(void) +{ + struct device *dev = PCH_DEV_XHCI; + + allocate_device_resource(dev, PCI_BASE_ADDRESS_0, + XHCI_FIXED_BAR, XHCI_BAR_SIZE); + set_device_resource(dev, PCI_BASE_ADDRESS_0, + XHCI_FIXED_BAR); + + pch_set_bar(dev, XHCI_FIXED_BAR, 0, 0); +} + +static void enable_igd_device(void) +{ + struct device *dev = SA_DEV_IGD; + + allocate_device_resource(dev, PCI_BASE_ADDRESS_0, + IGD_FIXED_BAR, IGD_BAR_SIZE); + set_device_resource(dev, PCI_BASE_ADDRESS_0, + IGD_FIXED_BAR); + + allocate_device_resource(dev, PCI_BASE_ADDRESS_2, + IGD_FIXED_BAR_2, IGD_BAR_SIZE_2); + set_device_resource(dev, PCI_BASE_ADDRESS_2, + IGD_FIXED_BAR_2); + + pch_set_bar(dev, IGD_FIXED_BAR, 0, IGD_FIXED_BAR_2); +} + +static void wrapper_x86_core_init(void *unused) +{ + struct device *dev = dev_find_path(NULL, DEVICE_PATH_CPU_CLUSTER); + + soc_core_init(dev); +} + +static void init_cpus(void) +{ + struct device *dev = dev_find_path(NULL, DEVICE_PATH_CPU_CLUSTER); + static const void *microcode_patch; + + intel_microcode_load_unlocked(microcode_patch); + + if (dev && dev->link_list) + soc_init_cpus(dev->link_list); + + if (mp_run_on_all_cpus(&wrapper_x86_core_init, NULL, 5000) < 0) + printk(BIOS_ERR, "CPU Init failure\n"); +} + +static void wrapper_x86_setup_mtrrs(void *unused) +{ + x86_setup_mtrrs_with_detect(); +} + +/* Ensure to re-program all MTRRs based on DRAM resource settings */ +static void post_cpus_init(void) +{ + if (mp_run_on_all_cpus(&wrapper_x86_setup_mtrrs, NULL, 5000) < 0) + printk(BIOS_ERR, "MTRR programming failure\n"); + + x86_mtrr_check(); +} + +static void wake_from_s3(void) +{ +#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) + void *wake_vector; + + wake_vector = acpi_find_wakeup_vector(); + + if (wake_vector != NULL) { + acpi_save_wake_source(NULL); + arch_bootstate_coreboot_exit(); + acpi_resume(wake_vector); + } +#endif +} + +static void finaize_smm(void) +{ + printk(BIOS_DEBUG, "Finalizing SMM.\n"); + outb(0xcb, 0xb2); +} + +void postcar_payload_init(void) +{ + struct device *dev = SA_DEV_ROOT; + int is_s3_resume = romstage_handoff_is_resume(); + + /* Initialize CPU cores */ + init_cpus(); + + /* Perform silicon specific init. */ + fsp_silicon_init(is_s3_resume); + + /* Save MRC cache into SPI*/ + update_mrc_cache(NULL); + + /* Read Resources for Root Device 0:0:0 */ + systemagent_read_resources(dev); + pci_dev_set_resources(dev); + pci_dev_enable_resources(dev); + + /* Make IGD Enable */ + enable_igd_device(); + + /* Make USB bootable */ + enable_xhci_device(); + + /* Add S3 Resume logic */ + if (is_s3_resume) { + finaize_smm(); + wake_from_s3(); + } + + acpi_prepare_resume_backup(); + + /* DSDT generation */ + southbridge_inject_dsdt(dev); + mainboard_chromeos_acpi_generate(); + + /* Post MP Init to program MTRR on APs */ + post_cpus_init(); + + /* Create coreboot tables */ + write_tables(); + + /* Load Payload */ + payload_load(); + + finaize_smm(); + + /* Run Payload */ + payload_run(); +} diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index 3224e1f..bc43da6 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -34,6 +34,7 @@ ramstage-$(CONFIG_USBDEBUG) += usb_debug.c romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c +postcar-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index 000d056..28abd2e 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -13,10 +13,13 @@ ## GNU General Public License for more details. ## +postcar-$(CONFIG_HAVE_ACPI_TABLES) += gnvs.c ramstage-$(CONFIG_ELOG) += elog.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += gnvs.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c +postcar-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-$(CONFIG_CHROMEOS_RAMOOPS) += ramoops.c +postcar-$(CONFIG_CHROMEOS_RAMOOPS) += ramoops.c ramstage-y += vpd_mac.c vpd_serialno.c vpd_calibration.c ramstage-$(CONFIG_CHROMEOS_DISABLE_PLATFORM_HIERARCHY_ON_RESUME) += tpm2.c ramstage-$(CONFIG_HAVE_REGULATORY_DOMAIN) += wrdd.c -- To view, visit https://review.coreboot.org/c/coreboot/+/30985 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27479187461ceb078167f2d726f40839865a9233 Gerrit-Change-Number: 30985 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

3 10

Change in ...coreboot[master]: console: Make die() and friends variadic
by Jacob Garber (Code Review) 11 Jun '19

11 Jun '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33153 Change subject: console: Make die() and friends variadic ...................................................................... console: Make die() and friends variadic die() currently only accepts a fixed message string, which is rather inconvenient when there is extra information that would be helpful to print in the error message. This currently requires an extra call to printk(), which is somewhat awkward: printk(BIOS_EMERG, "Bad table, opcode %d at %d", id, i); die(""); // what do I say here? die() already has a printk() inside it to print the error message, so let's just make it variadic to combine the two. die("Bad table, opcode %d at %d", id, i); // much better Forwarding variadic arguments from one function to another is rather tricky, so die_with_post_code() is redefined as a variadic macro instead. Change-Id: I28b9eac32899a1aa89e086e0d3889b75459581aa Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> --- M src/console/die.c M src/include/console/console.h 2 files changed, 10 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/33153/1 diff --git a/src/console/die.c b/src/console/die.c index 513d1c4..3a17126 100644 --- a/src/console/die.c +++ b/src/console/die.c @@ -30,17 +30,15 @@ } /* Report a fatal error */ -void __noreturn die(const char *msg) +void __noreturn die(const char *fmt, ...) { - printk(BIOS_EMERG, "%s", msg); + va_list args; + + va_start(args, fmt); + vprintk(BIOS_EMERG, fmt, args); + va_end(args); + die_notify(); halt(); } - -/* Report a fatal error with a post code */ -void __noreturn die_with_post_code(uint8_t value, const char *msg) -{ - post_code(value); - die(msg); -} #endif diff --git a/src/include/console/console.h b/src/include/console/console.h index 082ba29..369ce5b 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -42,8 +42,9 @@ #endif /* this function is weak and can be overridden by a mainboard function. */ void mainboard_post(u8 value); -void __noreturn die(const char *msg); -void __noreturn die_with_post_code(uint8_t value, const char *msg); +void __noreturn die(const char *fmt, ...); +#define die_with_post_code(value, fmt, ...) \ + do { post_code(value); die(fmt, ##__VA_ARGS__); } while (0) /* * This function is weak and can be overridden to provide additional -- To view, visit https://review.coreboot.org/c/coreboot/+/33153 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28b9eac32899a1aa89e086e0d3889b75459581aa Gerrit-Change-Number: 33153 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

4 3

Change in ...coreboot[master]: Kconfig: Create coreboot separate stage kconfigs
by Subrata Banik (Code Review) 11 Jun '19

11 Jun '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33142 Change subject: Kconfig: Create coreboot separate stage kconfigs ...................................................................... Kconfig: Create coreboot separate stage kconfigs This patch creates seperate stage configs as below 1. STAGE_BOOTBLOCK 2. STAGE_VERSTAGE 3. STAGE_ROMSTAGE 4. STAGE_RAMSTAGE A stage can only be enabled if soc has selected its supported architecture(example: arm, ppc, riscv, x86) Change-Id: I0f7e4174619016c5a54c28bedd52699df417a5b7 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/Kconfig 1 file changed, 32 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/33142/1 diff --git a/src/Kconfig b/src/Kconfig index d30aa99..4c1fe32 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -18,6 +18,38 @@ menu "General setup" +config STAGE_BOOTBLOCK + bool "Enable bootblock stage" + default y if ARCH_BOOTBLOCK_PPC64 || ARCH_BOOTBLOCK_ARMV8_64 || ARCH_BOOTBLOCK_ARM64 || ARCH_BOOTBLOCK_ARMV7 || ARCH_BOOTBLOCK_ARMV7_M || ARCH_BOOTBLOCK_ARMV7_R || ARCH_BOOTBLOCK_ARM || ARCH_BOOTBLOCK_ARMV4 || ARCH_BOOTBLOCK_RISCV || ARCH_BOOTBLOCK_X86_32 || ARCH_BOOTBLOCK_X86_64 || ARCH_BOOTBLOCK_MIPS + default n + help + This option is enabled if soc has selected any of supported + bootblock architecture (example: arm, ppc, riscv, x86). + +config STAGE_VERSTAGE + bool "Enable verstage stage" + default y if ARCH_VERSTAGE_PPC64 || ARCH_VERSTAGE_ARMV8_64 || ARCH_VERSTAGE_ARM64 || ARCH_VERSTAGE_ARMV7 || ARCH_VERSTAGE_ARMV7_M || ARCH_VERSTAGE_ARMV7_R || ARCH_VERSTAGE_ARM || ARCH_VERSTAGE_ARMV4 || ARCH_VERSTAGE_RISCV || ARCH_VERSTAGE_X86_32 || ARCH_VERSTAGE_X86_64 || ARCH_VERSTAGE_MIPS + default n + help + This option is enabled if soc has selected any of supported + verstage architecture (example: arm, ppc, riscv, x86). + +config STAGE_ROMSTAGE + bool "Enable romstage stage" + default y if ARCH_ROMSTAGE_PPC64 || ARCH_ROMSTAGE_ARMV8_64 || ARCH_ROMSTAGE_ARM64 || ARCH_ROMSTAGE_ARMV7 || ARCH_ROMSTAGE_ARMV7_R || ARCH_ROMSTAGE_ARM || ARCH_ROMSTAGE_ARMV4 || ARCH_ROMSTAGE_RISCV || ARCH_ROMSTAGE_X86_32 || ARCH_ROMSTAGE_X86_64 || ARCH_ROMSTAGE_MIPS + default n + help + This option is enabled if soc has selected any of supported + romstage architecture (example: arm, ppc, riscv, x86). + +config STAGE_RAMSTAGE + bool "Enable ramstage stage" + default y if ARCH_RAMSTAGE_PPC64 || ARCH_RAMSTAGE_ARMV8_64 || ARCH_RAMSTAGE_ARM64 || ARCH_RAMSTAGE_ARMV7 || ARCH_RAMSTAGE_ARMV7_R || ARCH_RAMSTAGE_ARM || ARCH_RAMSTAGE_ARMV4 || ARCH_RAMSTAGE_RISCV || ARCH_RAMSTAGE_X86_32 || ARCH_RAMSTAGE_X86_64 || ARCH_RAMSTAGE_MIPS + default n + help + This option is enabled if soc has selected any of supported + ramstage architecture (example: arm, ppc, riscv, x86). + config COREBOOT_BUILD bool default y -- To view, visit https://review.coreboot.org/c/coreboot/+/33142 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f7e4174619016c5a54c28bedd52699df417a5b7 Gerrit-Change-Number: 33142 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

6 38

Change in ...coreboot[master]: soc/amd/common: Add errors for invalid AcpiMmio access
by Marshall Dawson (Code Review) 11 Jun '19

11 Jun '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32934 Change subject: soc/amd/common: Add errors for invalid AcpiMmio access ...................................................................... soc/amd/common: Add errors for invalid AcpiMmio access Print an error when accessing a reserved or unexpected AcpiMmio register block. At a minimum, require the soc to indicate in its iomap.h file which register blocks it allows coreboot to use. It may optionally indicate all that are supported/documented or may treat unused blocks as reserved. This patch attempts to dissuade accessing unsupported blocks without requiring the complexity of structures or reinitializing at the beginning of a new stage. TEST=inspect grunt build with objdump with supported and unsupported blocks BUG=b:131682806 Change-Id: I2121df108fd3caf07e5588bc3201bcdd8dcaaa00 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/block/acpimmio/mmio_util.c M src/soc/amd/common/block/include/amdblocks/acpimmio.h M src/soc/amd/stoneyridge/include/soc/iomap.h 3 files changed, 185 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/32934/1 diff --git a/src/soc/amd/common/block/acpimmio/mmio_util.c b/src/soc/amd/common/block/acpimmio/mmio_util.c index c8c6988..89edf396 100644 --- a/src/soc/amd/common/block/acpimmio/mmio_util.c +++ b/src/soc/amd/common/block/acpimmio/mmio_util.c @@ -16,6 +16,7 @@ #include <types.h> #include <arch/io.h> #include <device/mmio.h> +#include <console/console.h> #include <amdblocks/acpimmio_map.h> #include <amdblocks/acpimmio.h> @@ -65,37 +66,55 @@ pm_io_write16(reg + sizeof(uint16_t), value & 0xffff); } +static void print_error(uintptr_t base, uint8_t reg) +{ + printk(BIOS_ERR, "Error: attempting to access offset 0x%x of unsupported AcpiMmio at 0x%lx\n", + reg, base); +} + /* smbus pci read/write - access registers at 0xfed80000 - currently unused */ /* smi read/write - access registers at 0xfed80200 */ uint8_t smi_read8(uint8_t reg) { + if (!SUPPORTS_ACPIMMIO_SMI_BASE) + print_error(ACPIMMIO_SMI_BASE, reg); return read8((void *)(ACPIMMIO_SMI_BASE + reg)); } uint16_t smi_read16(uint8_t reg) { + if (!SUPPORTS_ACPIMMIO_SMI_BASE) + print_error(ACPIMMIO_SMI_BASE, reg); return read16((void *)(ACPIMMIO_SMI_BASE + reg)); } uint32_t smi_read32(uint8_t reg) { + if (!SUPPORTS_ACPIMMIO_SMI_BASE) + print_error(ACPIMMIO_SMI_BASE, reg); return read32((void *)(ACPIMMIO_SMI_BASE + reg)); } void smi_write8(uint8_t reg, uint8_t value) { + if (!SUPPORTS_ACPIMMIO_SMI_BASE) + print_error(ACPIMMIO_SMI_BASE, reg); write8((void *)(ACPIMMIO_SMI_BASE + reg), value); } void smi_write16(uint8_t reg, uint16_t value) { + if (!SUPPORTS_ACPIMMIO_SMI_BASE) + print_error(ACPIMMIO_SMI_BASE, reg); write16((void *)(ACPIMMIO_SMI_BASE + reg), value); } void smi_write32(uint8_t reg, uint32_t value) { + if (!SUPPORTS_ACPIMMIO_SMI_BASE) + print_error(ACPIMMIO_SMI_BASE, reg); write32((void *)(ACPIMMIO_SMI_BASE + reg), value); } @@ -103,31 +122,43 @@ u8 pm_read8(u8 reg) { + if (!SUPPORTS_ACPIMMIO_PMIO_BASE) + print_error(ACPIMMIO_PMIO_BASE, reg); return read8((void *)(ACPIMMIO_PMIO_BASE + reg)); } u16 pm_read16(u8 reg) { + if (!SUPPORTS_ACPIMMIO_PMIO_BASE) + print_error(ACPIMMIO_PMIO_BASE, reg); return read16((void *)(ACPIMMIO_PMIO_BASE + reg)); } u32 pm_read32(u8 reg) { + if (!SUPPORTS_ACPIMMIO_PMIO_BASE) + print_error(ACPIMMIO_PMIO_BASE, reg); return read32((void *)(ACPIMMIO_PMIO_BASE + reg)); } void pm_write8(u8 reg, u8 value) { + if (!SUPPORTS_ACPIMMIO_PMIO_BASE) + print_error(ACPIMMIO_PMIO_BASE, reg); write8((void *)(ACPIMMIO_PMIO_BASE + reg), value); } void pm_write16(u8 reg, u16 value) { + if (!SUPPORTS_ACPIMMIO_PMIO_BASE) + print_error(ACPIMMIO_PMIO_BASE, reg); write16((void *)(ACPIMMIO_PMIO_BASE + reg), value); } void pm_write32(u8 reg, u32 value) { + if (!SUPPORTS_ACPIMMIO_PMIO_BASE) + print_error(ACPIMMIO_PMIO_BASE, reg); write32((void *)(ACPIMMIO_PMIO_BASE + reg), value); } @@ -137,6 +168,8 @@ uint8_t biosram_read8(uint8_t reg) { + if (!SUPPORTS_ACPIMMIO_BIOSRAM_BASE) + print_error(ACPIMMIO_BIOSRAM_BASE, reg); /* could see 1/2/4x */ return read8((void *)(ACPIMMIO_BIOSRAM_BASE + reg)); } @@ -153,6 +186,8 @@ void biosram_write8(uint8_t reg, uint8_t value) { + if (!SUPPORTS_ACPIMMIO_BIOSRAM_BASE) + print_error(ACPIMMIO_BIOSRAM_BASE, reg); /* could see 1/2/4x */ write8((void *)(ACPIMMIO_BIOSRAM_BASE + reg), value); } @@ -178,31 +213,43 @@ u8 acpi_read8(u8 reg) { + if (!SUPPORTS_ACPIMMIO_ACPI_BASE) + print_error(ACPIMMIO_ACPI_BASE, reg); return read8((void *)(ACPIMMIO_ACPI_BASE + reg)); } u16 acpi_read16(u8 reg) { + if (!SUPPORTS_ACPIMMIO_ACPI_BASE) + print_error(ACPIMMIO_ACPI_BASE, reg); return read16((void *)(ACPIMMIO_ACPI_BASE + reg)); } u32 acpi_read32(u8 reg) { + if (!SUPPORTS_ACPIMMIO_ACPI_BASE) + print_error(ACPIMMIO_ACPI_BASE, reg); return read32((void *)(ACPIMMIO_ACPI_BASE + reg)); } void acpi_write8(u8 reg, u8 value) { + if (!SUPPORTS_ACPIMMIO_ACPI_BASE) + print_error(ACPIMMIO_ACPI_BASE, reg); write8((void *)(ACPIMMIO_ACPI_BASE + reg), value); } void acpi_write16(u8 reg, u16 value) { + if (!SUPPORTS_ACPIMMIO_ACPI_BASE) + print_error(ACPIMMIO_ACPI_BASE, reg); write16((void *)(ACPIMMIO_ACPI_BASE + reg), value); } void acpi_write32(u8 reg, u32 value) { + if (!SUPPORTS_ACPIMMIO_ACPI_BASE) + print_error(ACPIMMIO_ACPI_BASE, reg); write32((void *)(ACPIMMIO_ACPI_BASE + reg), value); } @@ -210,21 +257,29 @@ u8 asf_read8(u8 reg) { + if (!SUPPORTS_ACPIMMIO_ASF_BASE) + print_error(ACPIMMIO_ASF_BASE, reg); return read8((void *)(ACPIMMIO_ASF_BASE + reg)); } u16 asf_read16(u8 reg) { + if (!SUPPORTS_ACPIMMIO_ASF_BASE) + print_error(ACPIMMIO_ASF_BASE, reg); return read16((void *)(ACPIMMIO_ASF_BASE + reg)); } void asf_write8(u8 reg, u8 value) { + if (!SUPPORTS_ACPIMMIO_ASF_BASE) + print_error(ACPIMMIO_ASF_BASE, reg); write8((void *)(ACPIMMIO_ASF_BASE + reg), value); } void asf_write16(u8 reg, u16 value) { + if (!SUPPORTS_ACPIMMIO_ASF_BASE) + print_error(ACPIMMIO_ASF_BASE, reg); write16((void *)(ACPIMMIO_ASF_BASE + reg), value); } @@ -232,21 +287,29 @@ u8 smbus_read8(u8 reg) { + if (!SUPPORTS_ACPIMMIO_SMBUS_BASE) + print_error(ACPIMMIO_SMBUS_BASE, reg); return read8((void *)(ACPIMMIO_SMBUS_BASE + reg)); } u16 smbus_read16(u8 reg) { + if (!SUPPORTS_ACPIMMIO_SMBUS_BASE) + print_error(ACPIMMIO_SMBUS_BASE, reg); return read16((void *)(ACPIMMIO_SMBUS_BASE + reg)); } void smbus_write8(u8 reg, u8 value) { + if (!SUPPORTS_ACPIMMIO_SMBUS_BASE) + print_error(ACPIMMIO_SMBUS_BASE, reg); write8((void *)(ACPIMMIO_SMBUS_BASE + reg), value); } void smbus_write16(u8 reg, u16 value) { + if (!SUPPORTS_ACPIMMIO_SMBUS_BASE) + print_error(ACPIMMIO_SMBUS_BASE, reg); write16((void *)(ACPIMMIO_SMBUS_BASE + reg), value); } @@ -258,31 +321,43 @@ u8 iomux_read8(u8 reg) { + if (!SUPPORTS_ACPIMMIO_IOMUX_BASE) + print_error(ACPIMMIO_IOMUX_BASE, reg); return read8((void *)(ACPIMMIO_IOMUX_BASE + reg)); } u16 iomux_read16(u8 reg) { + if (!SUPPORTS_ACPIMMIO_IOMUX_BASE) + print_error(ACPIMMIO_IOMUX_BASE, reg); return read16((void *)(ACPIMMIO_IOMUX_BASE + reg)); } u32 iomux_read32(u8 reg) { + if (!SUPPORTS_ACPIMMIO_IOMUX_BASE) + print_error(ACPIMMIO_IOMUX_BASE, reg); return read32((void *)(ACPIMMIO_IOMUX_BASE + reg)); } void iomux_write8(u8 reg, u8 value) { + if (!SUPPORTS_ACPIMMIO_IOMUX_BASE) + print_error(ACPIMMIO_IOMUX_BASE, reg); write8((void *)(ACPIMMIO_IOMUX_BASE + reg), value); } void iomux_write16(u8 reg, u16 value) { + if (!SUPPORTS_ACPIMMIO_IOMUX_BASE) + print_error(ACPIMMIO_IOMUX_BASE, reg); write16((void *)(ACPIMMIO_IOMUX_BASE + reg), value); } void iomux_write32(u8 reg, u32 value) { + if (!SUPPORTS_ACPIMMIO_IOMUX_BASE) + print_error(ACPIMMIO_IOMUX_BASE, reg); write32((void *)(ACPIMMIO_IOMUX_BASE + reg), value); } @@ -290,31 +365,43 @@ u8 misc_read8(u8 reg) { + if (!SUPPORTS_ACPIMMIO_MISC_BASE) + print_error(ACPIMMIO_MISC_BASE, reg); return read8((void *)(ACPIMMIO_MISC_BASE + reg)); } u16 misc_read16(u8 reg) { + if (!SUPPORTS_ACPIMMIO_MISC_BASE) + print_error(ACPIMMIO_MISC_BASE, reg); return read16((void *)(ACPIMMIO_MISC_BASE + reg)); } u32 misc_read32(u8 reg) { + if (!SUPPORTS_ACPIMMIO_MISC_BASE) + print_error(ACPIMMIO_MISC_BASE, reg); return read32((void *)(ACPIMMIO_MISC_BASE + reg)); } void misc_write8(u8 reg, u8 value) { + if (!SUPPORTS_ACPIMMIO_MISC_BASE) + print_error(ACPIMMIO_MISC_BASE, reg); write8((void *)(ACPIMMIO_MISC_BASE + reg), value); } void misc_write16(u8 reg, u16 value) { + if (!SUPPORTS_ACPIMMIO_MISC_BASE) + print_error(ACPIMMIO_MISC_BASE, reg); write16((void *)(ACPIMMIO_MISC_BASE + reg), value); } void misc_write32(u8 reg, u32 value) { + if (!SUPPORTS_ACPIMMIO_MISC_BASE) + print_error(ACPIMMIO_MISC_BASE, reg); write32((void *)(ACPIMMIO_MISC_BASE + reg), value); } @@ -328,31 +415,43 @@ uint8_t xhci_pm_read8(uint8_t reg) { + if (!SUPPORTS_ACPIMMIO_XHCIPM_BASE) + print_error(ACPIMMIO_XHCIPM_BASE, reg); return read8((void *)(ACPIMMIO_XHCIPM_BASE + reg)); } uint16_t xhci_pm_read16(uint8_t reg) { + if (!SUPPORTS_ACPIMMIO_XHCIPM_BASE) + print_error(ACPIMMIO_XHCIPM_BASE, reg); return read16((void *)(ACPIMMIO_XHCIPM_BASE + reg)); } uint32_t xhci_pm_read32(uint8_t reg) { + if (!SUPPORTS_ACPIMMIO_XHCIPM_BASE) + print_error(ACPIMMIO_XHCIPM_BASE, reg); return read32((void *)(ACPIMMIO_XHCIPM_BASE + reg)); } void xhci_pm_write8(uint8_t reg, uint8_t value) { + if (!SUPPORTS_ACPIMMIO_XHCIPM_BASE) + print_error(ACPIMMIO_XHCIPM_BASE, reg); write8((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); } void xhci_pm_write16(uint8_t reg, uint16_t value) { + if (!SUPPORTS_ACPIMMIO_XHCIPM_BASE) + print_error(ACPIMMIO_XHCIPM_BASE, reg); write16((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); } void xhci_pm_write32(uint8_t reg, uint32_t value) { + if (!SUPPORTS_ACPIMMIO_XHCIPM_BASE) + print_error(ACPIMMIO_XHCIPM_BASE, reg); write32((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); } @@ -362,10 +461,14 @@ u8 aoac_read8(u8 reg) { + if (!SUPPORTS_ACPIMMIO_AOAC_BASE) + print_error(ACPIMMIO_AOAC_BASE, reg); return read8((void *)(ACPIMMIO_AOAC_BASE + reg)); } void aoac_write8(u8 reg, u8 value) { + if (!SUPPORTS_ACPIMMIO_AOAC_BASE) + print_error(ACPIMMIO_AOAC_BASE, reg); write8((void *)(ACPIMMIO_AOAC_BASE + reg), value); } diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h index 6be856b..32da867 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -18,6 +18,69 @@ #ifndef __AMDBLOCKS_ACPIMMIO_H__ #define __AMDBLOCKS_ACPIMMIO_H__ +/* iomap.h must indicate if the device uses a block, optional if unused. */ +#include <soc/iomap.h> +#ifndef SUPPORTS_ACPIMMIO_SMI_BASE + #define SUPPORTS_ACPIMMIO_SMI_BASE 0 +#endif +#ifndef SUPPORTS_ACPIMMIO_PMIO_BASE + #define SUPPORTS_ACPIMMIO_PMIO_BASE 0 +#endif +#ifndef SUPPORTS_ACPIMMIO_PMIO2_BASE + #define SUPPORTS_ACPIMMIO_PMIO2_BASE 0 +#endif +#ifndef SUPPORTS_ACPIMMIO_BIOSRAM_BASE + #define SUPPORTS_ACPIMMIO_BIOSRAM_BASE 0 +#endif +#ifndef SUPPORTS_ACPIMMIO_CMOSRAM_BASE + #define SUPPORTS_ACPIMMIO_CMOSRAM_BASE 0 +#endif +#ifndef SUPPORTS_ACPIMMIO_CMOS_BASE + #define SUPPORTS_ACPIMMIO_CMOS_BASE 0 +#endif +#ifndef SUPPORTS_ACPIMMIO_ACPI_BASE + #define SUPPORTS_ACPIMMIO_ACPI_BASE 0 +#endif +#ifndef SUPPORTS_ACPIMMIO_ASF_BASE + #define SUPPORTS_ACPIMMIO_ASF_BASE 0 +#endif +#ifndef SUPPORTS_ACPIMMIO_SMBUS_BASE + #define SUPPORTS_ACPIMMIO_SMBUS_BASE 0 +#endif +#ifndef SUPPORTS_ACPIMMIO_WDT_BASE + #define SUPPORTS_ACPIMMIO_WDT_BASE 0 +#endif +#ifndef SUPPORTS_ACPIMMIO_HPET_BASE + #define SUPPORTS_ACPIMMIO_HPET_BASE 0 +#endif +#ifndef SUPPORTS_ACPIMMIO_IOMUX_BASE + #define SUPPORTS_ACPIMMIO_IOMUX_BASE 0 +#endif +#ifndef SUPPORTS_ACPIMMIO_MISC_BASE + #define SUPPORTS_ACPIMMIO_MISC_BASE 0 +#endif +#ifndef SUPPORTS_ACPIMMIO_DPVGA_BASE + #define SUPPORTS_ACPIMMIO_DPVGA_BASE 0 +#endif +#ifndef SUPPORTS_ACPIMMIO_GPIO0_BASE + #define SUPPORTS_ACPIMMIO_GPIO0_BASE 0 +#endif +#ifndef SUPPORTS_ACPIMMIO_GPIO1_BASE + #define SUPPORTS_ACPIMMIO_GPIO1_BASE 0 +#endif +#ifndef SUPPORTS_ACPIMMIO_GPIO2_BASE + #define SUPPORTS_ACPIMMIO_GPIO2_BASE 0 +#endif +#ifndef SUPPORTS_ACPIMMIO_XHCIPM_BASE + #define SUPPORTS_ACPIMMIO_XHCIPM_BASE 0 +#endif +#ifndef SUPPORTS_ACPIMMIO_ACDCTMR_BASE + #define SUPPORTS_ACPIMMIO_ACDCTMR_BASE 0 +#endif +#ifndef SUPPORTS_ACPIMMIO_AOAC_BASE + #define SUPPORTS_ACPIMMIO_AOAC_BASE 0 +#endif + /* * The following AcpiMmio register block mapping represents definitions * that have been documented in AMD publications. All blocks aren't diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h index 3856a22..da8906a 100644 --- a/src/soc/amd/stoneyridge/include/soc/iomap.h +++ b/src/soc/amd/stoneyridge/include/soc/iomap.h @@ -22,8 +22,26 @@ #define SPI_BASE_ADDRESS 0xfec10000 #define IO_APIC2_ADDR 0xfec20000 -/* AcpiMmio blocks are at fixed offsets from FED8_0000h, enabled in PMx04[1] */ +/* + * AcpiMmio blocks are at fixed offsets from FED8_0000h, enabled in PMx04[1]. + * All ranges not specified as supported below may, or may not, be listed in + * any documentation but should be considered reserved through FED8_1FFFh. + */ #include <amdblocks/acpimmio_map.h> +#define SUPPORTS_ACPIMMIO_SMI_BASE 1 /* 0xfed80100 */ +#define SUPPORTS_ACPIMMIO_PMIO_BASE 1 /* 0xfed80300 */ +#define SUPPORTS_ACPIMMIO_PMIO2_BASE 1 /* 0xfed80400 */ +#define SUPPORTS_ACPIMMIO_BIOSRAM_BASE 1 /* 0xfed80500 */ +#define SUPPORTS_ACPIMMIO_ACPI_BASE 1 /* 0xfed80800 */ +#define SUPPORTS_ACPIMMIO_ASF_BASE 1 /* 0xfed80900 */ +#define SUPPORTS_ACPIMMIO_SMBUS_BASE 1 /* 0xfed80a00 */ +#define SUPPORTS_ACPIMMIO_IOMUX_BASE 1 /* 0xfed80d00 */ +#define SUPPORTS_ACPIMMIO_MISC_BASE 1 /* 0xfed80e00 */ +#define SUPPORTS_ACPIMMIO_GPIO0_BASE 1 /* 0xfed81500 */ +#define SUPPORTS_ACPIMMIO_GPIO1_BASE 1 /* 0xfed81800 */ +#define SUPPORTS_ACPIMMIO_GPIO2_BASE 1 /* 0xfed81700 */ +#define SUPPORTS_ACPIMMIO_XHCIPM_BASE 1 /* 0xfed81c00 */ +#define SUPPORTS_ACPIMMIO_AOAC_BASE 1 /* 0xfed81e00 */ #define ALINK_AHB_ADDRESS 0xfedc0000 -- To view, visit https://review.coreboot.org/c/coreboot/+/32934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2121df108fd3caf07e5588bc3201bcdd8dcaaa00 Gerrit-Change-Number: 32934 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/mediatek/mt8173/i2c.c: Remove variable set but not used
by HAOUAS Elyes (Code Review) 10 Jun '19

10 Jun '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33062 Change subject: soc/mediatek/mt8173/i2c.c: Remove variable set but not used ...................................................................... soc/mediatek/mt8173/i2c.c: Remove variable set but not used Change-Id: I52d841aed31ce6d447280c75c1a1e7a08d8e0ca2 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/mediatek/mt8173/i2c.c 1 file changed, 15 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/33062/1 diff --git a/src/soc/mediatek/mt8173/i2c.c b/src/soc/mediatek/mt8173/i2c.c index 3395539..c09eeb1 100644 --- a/src/soc/mediatek/mt8173/i2c.c +++ b/src/soc/mediatek/mt8173/i2c.c @@ -111,30 +111,26 @@ static inline void mtk_i2c_dump_info(uint8_t bus) { - struct mt8173_i2c_regs *regs; - - regs = i2c[bus].i2c_regs; - I2CLOG("I2C register:\nSLAVE_ADDR %x\nINTR_MASK %x\nINTR_STAT %x\n" "CONTROL %x\nTRANSFER_LEN %x\nTRANSAC_LEN %x\nDELAY_LEN %x\n" "TIMING %x\nSTART %x\nFIFO_STAT %x\nIO_CONFIG %x\nHS %x\n" "DEBUGSTAT %x\nEXT_CONF %x\n", - (read32(&regs->salve_addr)), - (read32(&regs->intr_mask)), - (read32(&regs->intr_stat)), - (read32(&regs->control)), - (read32(&regs->transfer_len)), - (read32(&regs->transac_len)), - (read32(&regs->delay_len)), - (read32(&regs->timing)), - (read32(&regs->start)), - (read32(&regs->fifo_stat)), - (read32(&regs->io_config)), - (read32(&regs->hs)), - (read32(&regs->debug_stat)), - (read32(&regs->ext_conf))); + (read32(&i2c[bus].i2c_regs->salve_addr)), + (read32(&i2c[bus].i2c_regs->intr_mask)), + (read32(&i2c[bus].i2c_regs->intr_stat)), + (read32(&i2c[bus].i2c_regs->control)), + (read32(&i2c[bus].i2c_regs->transfer_len)), + (read32(&i2c[bus].i2c_regs->transac_len)), + (read32(&i2c[bus].i2c_regs->delay_len)), + (read32(&i2c[bus].i2c_regs->timing)), + (read32(&i2c[bus].i2c_regs->start)), + (read32(&i2c[bus].i2c_regs->fifo_stat)), + (read32(&i2c[bus].i2c_regs->io_config)), + (read32(&i2c[bus].i2c_regs->hs)), + (read32(&i2c[bus].i2c_regs->debug_stat)), + (read32(&i2c[bus].i2c_regs->ext_conf))); - I2CLOG("addr address %x\n", (uint32_t)regs); + I2CLOG("addr address %x\n", (uint32_t)i2c[bus].i2c_regs); } static uint32_t mtk_i2c_transfer(uint8_t bus, struct i2c_msg *seg, -- To view, visit https://review.coreboot.org/c/coreboot/+/33062 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52d841aed31ce6d447280c75c1a1e7a08d8e0ca2 Gerrit-Change-Number: 33062 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 2

Change in ...coreboot[master]: acpigen: Add support for IndexField
by Patrick Rudolph (Code Review) 09 Jun '19

09 Jun '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33032 Change subject: acpigen: Add support for IndexField ...................................................................... acpigen: Add support for IndexField Add support for generating IndexField, which is similar to Field. Change-Id: If66a627e64953696b0b68488256bd5c141e4c205 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/arch/x86/acpigen.c M src/arch/x86/include/arch/acpigen.h 2 files changed, 63 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/33032/1 diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c index e283f4d..74cd25a 100644 --- a/src/arch/x86/acpigen.c +++ b/src/arch/x86/acpigen.c @@ -514,6 +514,63 @@ acpigen_pop_len(); } +/* + * Generate ACPI AML code for IndexField + * Arg0: region name + * Arg1: Pointer to struct fieldlist. + * Arg2: no. of entries in Arg1 + * Arg3: flags which indicate filed access type, lock rule & update rule. + * Example with fieldlist + * struct fieldlist l[] = { + * FIELDLIST_OFFSET(0x84), + * FIELDLIST_NAMESTR("PMCS", 2), + * }; + * acpigen_write_field("IDX", "DATA" l, ARRAY_SIZE(l), FIELD_ANYACC | + * FIELD_NOLOCK | + * FIELD_PRESERVE); + * Output: + * IndexField (IDX, DATA, AnyAcc, NoLock, Preserve) + * { + * Offset (0x84), + * PMCS, 2 + * } + */ +void acpigen_write_indexfield(const char *idx, const char *data, + struct fieldlist *l, size_t count, uint8_t flags) +{ + uint16_t i; + uint32_t current_bit_pos = 0; + + /* FieldOp */ + acpigen_emit_ext_op(INDEX_FIELD_OP); + /* Package Length */ + acpigen_write_len_f(); + /* NameString 4 chars only */ + acpigen_emit_simple_namestring(idx); + /* NameString 4 chars only */ + acpigen_emit_simple_namestring(data); + /* Field Flag */ + acpigen_emit_byte(flags); + + for (i = 0; i < count; i++) { + switch (l[i].type) { + case NAME_STRING: + acpigen_write_field_name(l[i].name, l[i].bits); + current_bit_pos += l[i].bits; + break; + case OFFSET: + acpigen_write_field_offset(l[i].bits, current_bit_pos); + current_bit_pos = l[i].bits; + break; + default: + printk(BIOS_ERR, "%s: Invalid field type 0x%X\n" + , __func__, l[i].type); + break; + } + } + acpigen_pop_len(); +} + void acpigen_write_empty_PCT(void) { /* diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h index 6114667..db003fe 100644 --- a/src/arch/x86/include/arch/acpigen.h +++ b/src/arch/x86/include/arch/acpigen.h @@ -420,6 +420,12 @@ */ void acpigen_write_field(const char *name, struct fieldlist *l, size_t count, uint8_t flags); +/* + * Generate ACPI AML code for IndexField + * This function takes input index name, data name, fieldlist, count & flags. + */ +void acpigen_write_indexfield(const char *idx, const char *data, + struct fieldlist *l, size_t count, uint8_t flags); int get_cst_entries(acpi_cstate_t **); -- To view, visit https://review.coreboot.org/c/coreboot/+/33032 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If66a627e64953696b0b68488256bd5c141e4c205 Gerrit-Change-Number: 33032 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

2 4

Change in ...coreboot[master]: autoport: Generate a libgfxinit template
by Iru Cai (vimacs) (Code Review) 09 Jun '19

09 Jun '19

Hello Iru Cai, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/30912 to review the following change. Change subject: autoport: Generate a libgfxinit template ...................................................................... autoport: Generate a libgfxinit template Change-Id: I213628e525cc11c502de7d538bd60f49f3a930b9 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- M util/autoport/main.go 1 file changed, 42 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/30912/1 diff --git a/util/autoport/main.go b/util/autoport/main.go index 05a829b..c1a7907 100644 --- a/util/autoport/main.go +++ b/util/autoport/main.go @@ -748,6 +748,10 @@ ScanRoot(ctx) + KconfigBool["MAINBOARD_HAS_LIBGFXINIT"] = true + KconfigComment["MAINBOARD_HAS_LIBGFXINIT"] = "FIXME: check this" + AddRAMStageFile("gma-mainboard.ads", "CONFIG_MAINBOARD_USE_LIBGFXINIT") + if len(ROMStageFiles) > 0 || len(RAMStageFiles) > 0 || len(SMMFiles) > 0 { mf := Create(ctx, "Makefile.inc") defer mf.Close() @@ -882,4 +886,42 @@ } `) + gma := Create(ctx, "gma-mainboard.ads") + defer gma.Close() + + gma.WriteString(`-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + Internal, + others => Disabled); + +end GMA.Mainboard; +`) } -- To view, visit https://review.coreboot.org/c/coreboot/+/30912 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I213628e525cc11c502de7d538bd60f49f3a930b9 Gerrit-Change-Number: 30912 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-MessageType: newchange

3 5

Change in ...coreboot[master]: mainboard/Kconfig: add option for a 6144 KB(6 MB) ROM size
by Kacper Słomiński (Code Review) 09 Jun '19

09 Jun '19

Kacper Słomiński has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30980 Change subject: mainboard/Kconfig: add option for a 6144 KB(6 MB) ROM size ...................................................................... mainboard/Kconfig: add option for a 6144 KB(6 MB) ROM size Signed-off-by: Kacper Słomiński <kacper.slominski72(a)gmail.com> Change-Id: I7a1949c3512528b6b73955d907efc21728eed739 --- M src/mainboard/Kconfig 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/30980/1 diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index 363df55..c88d317 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -24,6 +24,8 @@ bool config BOARD_ROMSIZE_KB_4096 bool +config BOARD_ROMSIZE_KB_6144 + bool config BOARD_ROMSIZE_KB_8192 bool config BOARD_ROMSIZE_KB_10240 @@ -47,6 +49,7 @@ default COREBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024 default COREBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048 default COREBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096 + default COREBOOT_ROMSIZE_KB_6144 if BOARD_ROMSIZE_KB_6144 default COREBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192 default COREBOOT_ROMSIZE_KB_10240 if BOARD_ROMSIZE_KB_10240 default COREBOOT_ROMSIZE_KB_12288 if BOARD_ROMSIZE_KB_12288 @@ -94,6 +97,11 @@ help Choose this option if you have a 4096 KB (4 MB) ROM chip. +config COREBOOT_ROMSIZE_KB_6144 + bool "6144 KB (6 MB)" + help + Choose this option if you have a 6144 KB (6 MB) ROM chip. + config COREBOOT_ROMSIZE_KB_8192 bool "8192 KB (8 MB)" help @@ -136,6 +144,7 @@ default 1024 if COREBOOT_ROMSIZE_KB_1024 default 2048 if COREBOOT_ROMSIZE_KB_2048 default 4096 if COREBOOT_ROMSIZE_KB_4096 + default 6144 if COREBOOT_ROMSIZE_KB_6144 default 8192 if COREBOOT_ROMSIZE_KB_8192 default 10240 if COREBOOT_ROMSIZE_KB_10240 default 12288 if COREBOOT_ROMSIZE_KB_12288 @@ -153,6 +162,7 @@ default 0x100000 if COREBOOT_ROMSIZE_KB_1024 default 0x200000 if COREBOOT_ROMSIZE_KB_2048 default 0x400000 if COREBOOT_ROMSIZE_KB_4096 + default 0x600000 if COREBOOT_ROMSIZE_KB_6144 default 0x800000 if COREBOOT_ROMSIZE_KB_8192 default 0xa00000 if COREBOOT_ROMSIZE_KB_10240 default 0xc00000 if COREBOOT_ROMSIZE_KB_12288 -- To view, visit https://review.coreboot.org/c/coreboot/+/30980 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a1949c3512528b6b73955d907efc21728eed739 Gerrit-Change-Number: 30980 Gerrit-PatchSet: 1 Gerrit-Owner: Kacper Słomiński <kacper.slominski72(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [TESTME]soc/intel/braswell: Implement and use open source CAR
by Arthur Heymans (Code Review) 08 Jun '19

08 Jun '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30778 Change subject: [TESTME]soc/intel/braswell: Implement and use open source CAR ...................................................................... [TESTME]soc/intel/braswell: Implement and use open source CAR Copied from baytrail. Change-Id: I29eabb8960b5e98a9b50f7c7082b9e148a42fde2 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/intel/fsp1_1/car.c M src/drivers/intel/fsp1_1/include/fsp/car.h M src/soc/intel/braswell/Kconfig M src/soc/intel/braswell/Makefile.inc M src/soc/intel/braswell/romstage/Makefile.inc A src/soc/intel/braswell/romstage/cache_as_ram.inc 6 files changed, 242 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/30778/1 diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c index 6409ad5..10e3c60 100644 --- a/src/drivers/intel/fsp1_1/car.c +++ b/src/drivers/intel/fsp1_1/car.c @@ -21,36 +21,38 @@ #include <program_loading.h> #include <timestamp.h> -asmlinkage void cache_as_ram_main(struct cache_as_ram_params *car_params) +asmlinkage void cache_as_ram_main(unsigned long bist, uint64_t tsc) { + /* Need to locate the current FSP_INFO_HEADER. The cache-as-ram + * is still enabled. We can directly access work buffer here. */ + FSP_INFO_HEADER *fih; + struct prog fsp = PROG_INIT(PROG_REFCODE, "fsp.bin"); + /* Initialize timestamp book keeping only once. */ - timestamp_init(car_params->tsc); + timestamp_init(tsc); /* Call into pre-console init code then initialize console. */ car_soc_pre_console_init(); car_mainboard_pre_console_init(); console_init(); - printk(BIOS_DEBUG, "FSP TempRamInit successful\n"); + printk(BIOS_SPEW, "bist: 0x%08lx\n", bist); + printk(BIOS_SPEW, "tsc: 0x%016llx\n", tsc); - printk(BIOS_SPEW, "bist: 0x%08x\n", car_params->bist); - printk(BIOS_SPEW, "tsc: 0x%016llx\n", car_params->tsc); - - if (car_params->bootloader_car_start != CONFIG_DCACHE_RAM_BASE || - car_params->bootloader_car_end != - (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)) { - printk(BIOS_INFO, "CAR mismatch: %08x--%08x vs %08lx--%08lx\n", - CONFIG_DCACHE_RAM_BASE, - CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE, - (long)car_params->bootloader_car_start, - (long)car_params->bootloader_car_end); + if (prog_locate(&fsp)) { + fih = NULL; + printk(BIOS_ERR, "Unable to locate %s\n", prog_name(&fsp)); + } else { + /* This leaks a mapping which this code assumes is benign as + * the flash is memory mapped CPU's address space. */ + fih = find_fsp((uintptr_t)rdev_mmap_full(prog_rdev(&fsp))); } car_soc_post_console_init(); car_mainboard_post_console_init(); /* Return new stack value in RAM back to assembly stub. */ - cache_as_ram_stage_main(car_params->fih); + cache_as_ram_stage_main(fih); } /* Entry point taken when romstage is called after a separate verstage. */ diff --git a/src/drivers/intel/fsp1_1/include/fsp/car.h b/src/drivers/intel/fsp1_1/include/fsp/car.h index df5e0da..96c9cf9 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/car.h +++ b/src/drivers/intel/fsp1_1/include/fsp/car.h @@ -30,7 +30,7 @@ }; /* Entry points from the cache-as-ram assembly code. */ -asmlinkage void cache_as_ram_main(struct cache_as_ram_params *car_params); +asmlinkage void cache_as_ram_main(unsigned long bist, uint64_t tsc); asmlinkage void after_cache_as_ram(void *chipset_context); asmlinkage void romstage_c_entry(void); /* Per stage calls from the above two functions. The void * return from diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index d0a250a..b780038 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -39,7 +39,8 @@ select TSC_MONOTONIC_TIMER select TSC_SYNC_MFENCE select UDELAY_TSC - select USE_GENERIC_FSP_CAR_INC +# select USE_GENERIC_FSP_CAR_INC + select SKIP_FSP_CAR select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SPI_CONSOLE_SUPPORT select HAVE_FSP_GOP diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc index 3296331..1a5addb 100644 --- a/src/soc/intel/braswell/Makefile.inc +++ b/src/soc/intel/braswell/Makefile.inc @@ -18,6 +18,7 @@ postcar-y += memmap.c postcar-y += iosf.c +postcar-y += ../../../cpu/intel/car/non-evict/exit_car.S ramstage-y += acpi.c ramstage-y += chip.c diff --git a/src/soc/intel/braswell/romstage/Makefile.inc b/src/soc/intel/braswell/romstage/Makefile.inc index c3ed415..1ab1b45 100644 --- a/src/soc/intel/braswell/romstage/Makefile.inc +++ b/src/soc/intel/braswell/romstage/Makefile.inc @@ -1,3 +1,5 @@ romstage-y += early_spi.c romstage-y += pmc.c romstage-y += romstage.c + +cpu_incs-y += $(src)/soc/intel/braswell/romstage/cache_as_ram.inc diff --git a/src/soc/intel/braswell/romstage/cache_as_ram.inc b/src/soc/intel/braswell/romstage/cache_as_ram.inc new file mode 100644 index 0000000..9db7f85 --- /dev/null +++ b/src/soc/intel/braswell/romstage/cache_as_ram.inc @@ -0,0 +1,219 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich(a)gmail.com> + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/x86/mtrr.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/post_code.h> +#include <cpu/x86/msr.h> + +#include "fmap_config.h" + +/* The full cache-as-ram size includes the cache-as-ram portion from coreboot + * and the space used by the reference code. These 2 values combined should + * be a power of 2 because the MTRR setup assumes that. */ +#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE +#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE + +/* Cache all of CBFS just below 4GiB as Write-Protect type. */ +#define CODE_CACHE_SIZE _ALIGN_UP_POW2(___FMAP__COREBOOT_SIZE) +#define CODE_CACHE_BASE (-CODE_CACHE_SIZE) +#define CODE_CACHE_MASK (~(CODE_CACHE_SIZE - 1)) + +#define NoEvictMod_MSR 0x2e0 +#define BBL_CR_CTL3_MSR 0x11e + + /* Save the BIST result. */ + movl %eax, %ebp + +cache_as_ram: + post_code(0x20) + + /* Send INIT IPI to all excluding ourself. */ + movl $0x000C4500, %eax + movl $0xFEE00300, %esi + movl %eax, (%esi) + + /* All CPUs need to be in Wait for SIPI state */ +wait_for_sipi: + movl (%esi), %eax + bt $12, %eax + jc wait_for_sipi + + post_code(0x21) + /* Configure the default memory type to uncacheable as well as disable + * fixed and variable range mtrrs. */ + movl $MTRR_DEF_TYPE_MSR, %ecx + rdmsr + andl $(~0x00000cff), %eax + wrmsr + + post_code(0x22) + /* Zero the variable MTRRs. */ + movl $IA32_MCG_CAP, %ecx + rdmsr + movzx %al, %ebx + /* First variable MTRR. */ + movl $MTRR_PHYS_BASE(0), %ecx + xorl %eax, %eax + xorl %edx, %edx +1: + wrmsr + inc %ecx + dec %ebx + jnz 1b + + /* Clear/disable fixed MTRRs */ + mov $fixed_mtrr_list_size, %ebx + xor %eax, %eax + xor %edx, %edx + +clear_fixed_mtrr: + add $-2, %ebx + movzwl fixed_mtrr_list(%ebx), %ecx + wrmsr + jnz clear_fixed_mtrr + + /* Determine CPU_ADDR_BITS and load PHYSMASK high word to %edx. */ + movl $0x80000008, %eax + cpuid + movb %al, %cl + sub $32, %cl + movl $1, %edx + shl %cl, %edx + subl $1, %edx + + /* Preload high word of address mask (in %edx) for Variable + * MTRRs 0 and 1. + */ +addrsize_set_high: + xorl %eax, %eax + movl $MTRR_PHYS_MASK(0), %ecx + wrmsr + movl $MTRR_PHYS_MASK(1), %ecx + wrmsr + + + post_code(0x23) + /* Set Cache-as-RAM base address. */ + movl $(MTRR_PHYS_BASE(0)), %ecx + movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax + xorl %edx, %edx + wrmsr + + post_code(0x24) + /* Set Cache-as-RAM mask. */ + movl $(MTRR_PHYS_MASK(0)), %ecx + rdmsr + movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax + wrmsr + + post_code(0x25) + /* Set code caching up for romstage. */ + movl $(MTRR_PHYS_BASE(1)), %ecx + movl $(CODE_CACHE_BASE | MTRR_TYPE_WRPROT), %eax + xorl %edx, %edx + wrmsr + + movl $MTRR_PHYS_MASK(1), %ecx + rdmsr + movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax + wrmsr + + /* Enable MTRR. */ + movl $MTRR_DEF_TYPE_MSR, %ecx + rdmsr + orl $MTRR_DEF_TYPE_EN, %eax + wrmsr + + post_code(0x26) + + /* Enable the L2 cache. */ + movl $BBL_CR_CTL3_MSR, %ecx + rdmsr + orl $0x100, %eax + wrmsr + + post_code(0x27) + + /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ + movl %cr0, %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax + invd + movl %eax, %cr0 + + /* enable the 'no eviction' mode */ + movl $NoEvictMod_MSR, %ecx + rdmsr + orl $1, %eax + wrmsr + + post_code(0x28) + + /* Clear the cache memory region. This will also fill up the cache */ + movl $CACHE_AS_RAM_BASE, %esi + movl %esi, %edi + movl $(CACHE_AS_RAM_SIZE >> 2), %ecx + xorl %eax, %eax + rep stosl + + /* enable no evict mode */ + movl $NoEvictMod_MSR, %ecx + rdmsr + orl $2, %eax + wrmsr + + post_code(0x29) + + /* Setup the stack. */ + movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax + movl %eax, %esp + + /* Push the initial TSC value from boot block. The low 32 bits are + * in mm0, and the high 32 bits are in mm1. */ + movd %mm1, %eax + pushl %eax + movd %mm0, %eax + pushl %eax + /* Restore the BIST result. */ + movl %ebp, %eax + movl %esp, %ebp + pushl %eax + +before_romstage: + post_code(0x2a) + /* Call car.c main function. */ + call cache_as_ram_main + + /* Should never see this postcode */ + post_code(POST_DEAD_CODE) + +.Lhlt: + hlt + jmp .Lhlt + +fixed_mtrr_list: + .word MTRR_FIX_64K_00000 + .word MTRR_FIX_16K_80000 + .word MTRR_FIX_16K_A0000 + .word MTRR_FIX_4K_C0000 + .word MTRR_FIX_4K_C8000 + .word MTRR_FIX_4K_D0000 + .word MTRR_FIX_4K_D8000 + .word MTRR_FIX_4K_E0000 + .word MTRR_FIX_4K_E8000 + .word MTRR_FIX_4K_F0000 + .word MTRR_FIX_4K_F8000 +fixed_mtrr_list_size = . - fixed_mtrr_list -- To view, visit https://review.coreboot.org/c/coreboot/+/30778 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29eabb8960b5e98a9b50f7c7082b9e148a42fde2 Gerrit-Change-Number: 30778 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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coreboot-gerrit May 2019