coreboot-gerrit May 2019

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Change in ...coreboot[master]: sb/intel/i82801gx: Use common code to lock down SPI
by Arthur Heymans (Code Review) 18 Jun '19

18 Jun '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33043 Change subject: sb/intel/i82801gx: Use common code to lock down SPI ...................................................................... sb/intel/i82801gx: Use common code to lock down SPI Change-Id: Ie5ae18e576b7cf7450ab7aa2c12244a92a452d62 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/i82801gx/lpc.c 1 file changed, 1 insertion(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/33043/1 diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index b226b23..33cf941 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -611,9 +611,6 @@ } } -#define SPIBAR16(x) RCBA16(0x3020 + x) -#define SPIBAR32(x) RCBA32(0x3020 + x) - static void lpc_final(struct device *dev) { u16 tco1_cnt; @@ -623,8 +620,7 @@ spi_finalize_ops(); - /* Lock SPIBAR */ - SPIBAR16(0) = SPIBAR16(0) | (1 << 15); + spi_lock_down(); /* BIOS Interface Lockdown */ RCBA32(0x3410) |= 1 << 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/33043 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie5ae18e576b7cf7450ab7aa2c12244a92a452d62 Gerrit-Change-Number: 33043 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

2 2

Change in ...coreboot[master]: sb/intel/common: Add a function to cleanly lock down the SPI config
by Arthur Heymans (Code Review) 18 Jun '19

18 Jun '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33042 Change subject: sb/intel/common: Add a function to cleanly lock down the SPI config ...................................................................... sb/intel/common: Add a function to cleanly lock down the SPI config Currently SPI gets locked in ramstage/smm with updating the g_ichspi_lock global variable. Some southbridges worked around it by reinitializing SPI by calling spi_init(); Change-Id: Idc2340c74b95644c38ea88997d7dc6f2ec32e7e3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/common/spi.c M src/southbridge/intel/common/spi.h 2 files changed, 27 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/33042/1 diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index c8e953e..2935d6b 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -1082,6 +1082,32 @@ { } +void spi_lock_down(void) +{ + uint8_t *rcrb; /* Root Complex Register Block */ + uint32_t rcba; /* Root Complex Base Address */ + ich9_spi_regs *ich9_spi; + ich7_spi_regs *ich7_spi; + +#ifdef __SIMPLE_DEVICE__ + pci_devfn_t dev = PCI_DEV(0, 31, 0); +#else + struct device *dev = pcidev_on_root(31, 0); +#endif + + rcba = pci_read_config32(dev, 0xf0); + /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */ + rcrb = (uint8_t *)(rcba & 0xffffc000); + if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) { + ich7_spi = (ich7_spi_regs *)(rcrb + 0x3020); + writew_(readw_(&ich7_spi->spis) | HSFS_FLOCKDN, &ich7_spi->spis); + } else { + ich9_spi = (ich9_spi_regs *)(rcrb + 0x3800); + writew_(readw_(&ich9_spi->hsfs) | HSFS_FLOCKDN, &ich9_spi->hsfs) ; + } + g_ichspi_lock = 1; +} + static const struct spi_ctrlr spi_ctrlr = { .xfer_vector = xfer_vectors, .max_xfer_size = member_size(ich9_spi_regs, fdata), diff --git a/src/southbridge/intel/common/spi.h b/src/southbridge/intel/common/spi.h index fcc5cd8..5dbd723 100644 --- a/src/southbridge/intel/common/spi.h +++ b/src/southbridge/intel/common/spi.h @@ -34,5 +34,6 @@ void spi_finalize_ops(void); void intel_southbridge_override_spi(struct intel_spi_config *spi_config); +void spi_lock_down(void); #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/33042 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc2340c74b95644c38ea88997d7dc6f2ec32e7e3 Gerrit-Change-Number: 33042 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

2 5

Change in ...coreboot[master]: commonlib: define cbtable tags as enum to identify conflicts
by Patrick Georgi (Code Review) 18 Jun '19

18 Jun '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32958 Change subject: commonlib: define cbtable tags as enum to identify conflicts ...................................................................... commonlib: define cbtable tags as enum to identify conflicts We had a value that was overloaded thrice. By moving them in a common structure and ordering them by value such issues are hopefully avoided in the future. Also add a few values to libpayload that were only defined in commonlib. Change-Id: I227d078eebee2d92488454707d4dab8ecc24a4d8 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M payloads/libpayload/include/coreboot_tables.h M src/commonlib/include/commonlib/coreboot_tables.h 2 files changed, 55 insertions(+), 50 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/32958/1 diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index c12db03..03febde 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -63,6 +63,7 @@ CB_TAG_RAM_OOPS = 0x0023, CB_TAG_ACPI_GNVS = 0x0024, CB_TAG_BOARD_ID = 0x0025, + CB_TAG_VERSION_TIMESTAMP = 0x0026, CB_TAG_WIFI_CALIBRATION = 0x0027, CB_TAG_RAM_CODE = 0x0028, CB_TAG_SERIALNO = 0x002a, @@ -71,10 +72,12 @@ CB_TAG_VPD = 0x002c, CB_TAG_SKU_ID = 0x002d, CB_TAG_BOOT_MEDIA_PARAMS = 0x0030, + CB_TAG_CBMEM_ENTRY = 0x0031, CB_TAG_TSC_INFO = 0x0032, CB_TAG_MAC_ADDRS = 0x0033, CB_TAG_VBOOT_WORKBUF = 0x0034, CB_TAG_MMC_INFO = 0x0035, + CB_TAG_TCPA_LOG = 0x0036, CB_TAG_CMOS_OPTION_TABLE = 0x00c8, CB_TAG_OPTION = 0x00c9, CB_TAG_OPTION_ENUM = 0x00ca, diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index 277b746..d583e16 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -44,6 +44,58 @@ * table entries and be backwards compatible, but it is not required. */ +enum { + LB_TAG_UNUSED = 0x0000, + LB_TAG_MEMORY = 0x0001, + LB_TAG_HWRPB = 0x0002, + LB_TAG_MAINBOARD = 0x0003, + LB_TAG_VERSION = 0x0004, + LB_TAG_EXTRA_VERSION = 0x0005, + LB_TAG_BUILD = 0x0006, + LB_TAG_COMPILE_TIME = 0x0007, + LB_TAG_COMPILE_BY = 0x0008, + LB_TAG_COMPILE_HOST = 0x0009, + LB_TAG_COMPILE_DOMAIN = 0x000a, + LB_TAG_COMPILER = 0x000b, + LB_TAG_LINKER = 0x000c, + LB_TAG_ASSEMBLER = 0x000d, + LB_TAG_SERIAL = 0x000f, + LB_TAG_CONSOLE = 0x0010, + LB_TAG_FORWARD = 0x0011, + LB_TAG_FRAMEBUFFER = 0x0012, + LB_TAG_GPIO = 0x0013, + LB_TAG_TIMESTAMPS = 0x0016, + LB_TAG_CBMEM_CONSOLE = 0x0017, + LB_TAG_MRC_CACHE = 0x0018, + LB_TAG_VBNV = 0x0019, + LB_TAG_VBOOT_HANDOFF = 0x0020, + LB_TAG_X86_ROM_MTRR = 0x0021, + LB_TAG_DMA = 0x0022, + LB_TAG_RAM_OOPS = 0x0023, + LB_TAG_ACPI_GNVS = 0x0024, + LB_TAG_BOARD_ID = 0x0025, + LB_TAG_VERSION_TIMESTAMP = 0x0026, + LB_TAG_WIFI_CALIBRATION = 0x0027, + LB_TAG_RAM_CODE = 0x0028, + LB_TAG_SERIALNO = 0x002a, + LB_TAG_SPI_FLASH = 0x0029, + LB_TAG_MTC = 0x002b, + LB_TAG_VPD = 0x002c, + LB_TAG_SKU_ID = 0x002d, + LB_TAG_BOOT_MEDIA_PARAMS = 0x0030, + LB_TAG_CBMEM_ENTRY = 0x0031, + LB_TAG_TSC_INFO = 0x0032, + LB_TAG_MAC_ADDRS = 0x0033, + LB_TAG_VBOOT_WORKBUF = 0x0034, + LB_TAG_MMC_INFO = 0x0035, + LB_TAG_TCPA_LOG = 0x0036, + LB_TAG_CMOS_OPTION_TABLE = 0x00c8, + LB_TAG_OPTION = 0x00c9, + LB_TAG_OPTION_ENUM = 0x00ca, + LB_TAG_OPTION_DEFAULTS = 0x00cb, + LB_TAG_OPTION_CHECKSUM = 0x00cc, +}; + /* Since coreboot is usually compiled 32bit, gcc will align 64bit * types to 32bit boundaries. If the coreboot table is dumped on a * 64bit system, a uint64_t would be aligned to 64bit boundaries, @@ -97,9 +149,6 @@ uint32_t size; /* size of record (in bytes) */ }; -#define LB_TAG_UNUSED 0x0000 - -#define LB_TAG_MEMORY 0x0001 struct lb_memory_range { struct lb_uint64 start; @@ -120,14 +169,12 @@ struct lb_memory_range map[0]; }; -#define LB_TAG_HWRPB 0x0002 struct lb_hwrpb { uint32_t tag; uint32_t size; uint64_t hwrpb; }; -#define LB_TAG_MAINBOARD 0x0003 struct lb_mainboard { uint32_t tag; uint32_t size; @@ -136,23 +183,12 @@ uint8_t strings[0]; }; -#define LB_TAG_VERSION 0x0004 -#define LB_TAG_EXTRA_VERSION 0x0005 -#define LB_TAG_BUILD 0x0006 -#define LB_TAG_COMPILE_TIME 0x0007 -#define LB_TAG_COMPILE_BY 0x0008 -#define LB_TAG_COMPILE_HOST 0x0009 -#define LB_TAG_COMPILE_DOMAIN 0x000a -#define LB_TAG_COMPILER 0x000b -#define LB_TAG_LINKER 0x000c -#define LB_TAG_ASSEMBLER 0x000d struct lb_string { uint32_t tag; uint32_t size; uint8_t string[0]; }; -#define LB_TAG_VERSION_TIMESTAMP 0x0026 struct lb_timestamp { uint32_t tag; uint32_t size; @@ -162,7 +198,6 @@ /* 0xe is taken by v3 */ -#define LB_TAG_SERIAL 0x000f struct lb_serial { uint32_t tag; uint32_t size; @@ -189,7 +224,6 @@ uint32_t uart_pci_addr; }; -#define LB_TAG_CONSOLE 0x0010 struct lb_console { uint32_t tag; uint32_t size; @@ -204,7 +238,6 @@ #define LB_TAG_CONSOLE_EHCI 5 #define LB_TAG_CONSOLE_SERIAL8250MEM 6 -#define LB_TAG_FORWARD 0x0011 struct lb_forward { uint32_t tag; uint32_t size; @@ -250,7 +283,6 @@ * fields described above. It may, however, only implement a subset * of the possible color formats. */ -#define LB_TAG_FRAMEBUFFER 0x0012 struct lb_framebuffer { uint32_t tag; uint32_t size; @@ -270,7 +302,6 @@ uint8_t reserved_mask_size; }; -#define LB_TAG_GPIO 0x0013 struct lb_gpio { uint32_t port; @@ -290,12 +321,6 @@ struct lb_gpio gpios[0]; }; -#define LB_TAG_VBNV 0x0019 -#define LB_TAG_VBOOT_HANDOFF 0x0020 -#define LB_TAG_VBOOT_WORKBUF 0x0034 -#define LB_TAG_DMA 0x0022 -#define LB_TAG_RAM_OOPS 0x0023 -#define LB_TAG_MTC 0x002b struct lb_range { uint32_t tag; uint32_t size; @@ -306,13 +331,6 @@ void lb_ramoops(struct lb_header *header); -#define LB_TAG_TIMESTAMPS 0x0016 -#define LB_TAG_CBMEM_CONSOLE 0x0017 -#define LB_TAG_MRC_CACHE 0x0018 -#define LB_TAG_ACPI_GNVS 0x0024 -#define LB_TAG_TCPA_LOG 0x0036 -#define LB_TAG_WIFI_CALIBRATION 0x0027 -#define LB_TAG_VPD 0x002c struct lb_cbmem_ref { uint32_t tag; uint32_t size; @@ -320,7 +338,6 @@ uint64_t cbmem_addr; }; -#define LB_TAG_X86_ROM_MTRR 0x0021 struct lb_x86_rom_mtrr { uint32_t tag; uint32_t size; @@ -328,9 +345,6 @@ uint32_t index; }; -#define LB_TAG_BOARD_ID 0x0025 -#define LB_TAG_RAM_CODE 0x0028 -#define LB_TAG_SKU_ID 0x002d struct lb_strapping_id { uint32_t tag; @@ -338,7 +352,6 @@ uint32_t id_code; }; -#define LB_TAG_SPI_FLASH 0x0029 struct lb_spi_flash { uint32_t tag; uint32_t size; @@ -347,7 +360,6 @@ uint32_t erase_cmd; }; -#define LB_TAG_BOOT_MEDIA_PARAMS 0x0030 struct lb_boot_media_params { uint32_t tag; uint32_t size; @@ -361,7 +373,6 @@ /* * There can be more than one of these records as there is one per cbmem entry. */ -#define LB_TAG_CBMEM_ENTRY 0x0031 struct lb_cbmem_entry { uint32_t tag; uint32_t size; @@ -371,7 +382,6 @@ uint32_t id; }; -#define LB_TAG_TSC_INFO 0x0032 struct lb_tsc_info { uint32_t tag; uint32_t size; @@ -379,13 +389,11 @@ uint32_t freq_khz; }; -#define LB_TAG_MAC_ADDRS 0x0033 struct mac_address { uint8_t mac_addr[6]; uint8_t pad[2]; /* Pad it to 8 bytes to keep it simple. */ }; -#define LB_TAG_MMC_INFO 0x0035 struct lb_mmc_info { uint32_t tag; uint32_t size; @@ -407,11 +415,9 @@ struct mac_address mac_addrs[0]; }; -#define LB_TAG_SERIALNO 0x002a #define MAX_SERIALNO_LENGTH 32 /* The following structures are for the cmos definitions table */ -#define LB_TAG_CMOS_OPTION_TABLE 200 /* cmos header record */ struct cmos_option_table { uint32_t tag; /* CMOS definitions table type */ @@ -426,7 +432,6 @@ * starts at the beginning of the byte and the length is * fills complete bytes. */ -#define LB_TAG_OPTION 201 struct cmos_entries { uint32_t tag; /* entry type */ uint32_t size; /* length of this record */ @@ -444,7 +449,6 @@ * This record is variable length. The text field may be * shorter than CMOS_MAX_TEXT_LENGTH. */ -#define LB_TAG_OPTION_ENUM 202 struct cmos_enums { uint32_t tag; /* enumeration type */ uint32_t size; /* length of this record */ @@ -458,7 +462,6 @@ /* cmos defaults record * This record contains default settings for the cmos ram. */ -#define LB_TAG_OPTION_DEFAULTS 203 struct cmos_defaults { uint32_t tag; /* default type */ uint32_t size; /* length of this record */ @@ -468,7 +471,6 @@ uint8_t default_set[CMOS_IMAGE_BUFFER_SIZE]; /* default settings */ }; -#define LB_TAG_OPTION_CHECKSUM 204 struct cmos_checksum { uint32_t tag; uint32_t size; -- To view, visit https://review.coreboot.org/c/coreboot/+/32958 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I227d078eebee2d92488454707d4dab8ecc24a4d8 Gerrit-Change-Number: 32958 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 8

Change in ...coreboot[master]: libpayload: define cbtable tags as enum to identify conflicts
by Patrick Georgi (Code Review) 18 Jun '19

18 Jun '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32957 Change subject: libpayload: define cbtable tags as enum to identify conflicts ...................................................................... libpayload: define cbtable tags as enum to identify conflicts We had a value that was overloaded thrice. By moving them in a common structure and ordering them by value such issues are hopefully avoided in the future. Change-Id: I0c7762601d7620413989b458fa634d7606accc9d Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M payloads/libpayload/include/coreboot_tables.h 1 file changed, 49 insertions(+), 55 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/32957/1 diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index 8e5cec0..c12db03 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -33,6 +33,55 @@ #include <arch/types.h> #include <ipchksum.h> +enum { + CB_TAG_UNUSED = 0x0000, + CB_TAG_MEMORY = 0x0001, + CB_TAG_HWRPB = 0x0002, + CB_TAG_MAINBOARD = 0x0003, + CB_TAG_VERSION = 0x0004, + CB_TAG_EXTRA_VERSION = 0x0005, + CB_TAG_BUILD = 0x0006, + CB_TAG_COMPILE_TIME = 0x0007, + CB_TAG_COMPILE_BY = 0x0008, + CB_TAG_COMPILE_HOST = 0x0009, + CB_TAG_COMPILE_DOMAIN = 0x000a, + CB_TAG_COMPILER = 0x000b, + CB_TAG_LINKER = 0x000c, + CB_TAG_ASSEMBLER = 0x000d, + CB_TAG_SERIAL = 0x000f, + CB_TAG_CONSOLE = 0x0010, + CB_TAG_FORWARD = 0x0011, + CB_TAG_FRAMEBUFFER = 0x0012, + CB_TAG_GPIO = 0x0013, + CB_TAG_TIMESTAMPS = 0x0016, + CB_TAG_CBMEM_CONSOLE = 0x0017, + CB_TAG_MRC_CACHE = 0x0018, + CB_TAG_VBNV = 0x0019, + CB_TAG_VBOOT_HANDOFF = 0x0020, + CB_TAG_X86_ROM_MTRR = 0x0021, + CB_TAG_DMA = 0x0022, + CB_TAG_RAM_OOPS = 0x0023, + CB_TAG_ACPI_GNVS = 0x0024, + CB_TAG_BOARD_ID = 0x0025, + CB_TAG_WIFI_CALIBRATION = 0x0027, + CB_TAG_RAM_CODE = 0x0028, + CB_TAG_SERIALNO = 0x002a, + CB_TAG_SPI_FLASH = 0x0029, + CB_TAG_MTC = 0x002b, + CB_TAG_VPD = 0x002c, + CB_TAG_SKU_ID = 0x002d, + CB_TAG_BOOT_MEDIA_PARAMS = 0x0030, + CB_TAG_TSC_INFO = 0x0032, + CB_TAG_MAC_ADDRS = 0x0033, + CB_TAG_VBOOT_WORKBUF = 0x0034, + CB_TAG_MMC_INFO = 0x0035, + CB_TAG_CMOS_OPTION_TABLE = 0x00c8, + CB_TAG_OPTION = 0x00c9, + CB_TAG_OPTION_ENUM = 0x00ca, + CB_TAG_OPTION_DEFAULTS = 0x00cb, + CB_TAG_OPTION_CHECKSUM = 0x00cc, +}; + struct cbuint64 { u32 lo; u32 hi; @@ -52,9 +101,6 @@ u32 size; }; -#define CB_TAG_UNUSED 0x0000 -#define CB_TAG_MEMORY 0x0001 - struct cb_memory_range { struct cbuint64 start; struct cbuint64 size; @@ -75,16 +121,12 @@ struct cb_memory_range map[0]; }; -#define CB_TAG_HWRPB 0x0002 - struct cb_hwrpb { u32 tag; u32 size; u64 hwrpb; }; -#define CB_TAG_MAINBOARD 0x0003 - struct cb_mainboard { u32 tag; u32 size; @@ -93,25 +135,12 @@ u8 strings[0]; }; -#define CB_TAG_VERSION 0x0004 -#define CB_TAG_EXTRA_VERSION 0x0005 -#define CB_TAG_BUILD 0x0006 -#define CB_TAG_COMPILE_TIME 0x0007 -#define CB_TAG_COMPILE_BY 0x0008 -#define CB_TAG_COMPILE_HOST 0x0009 -#define CB_TAG_COMPILE_DOMAIN 0x000a -#define CB_TAG_COMPILER 0x000b -#define CB_TAG_LINKER 0x000c -#define CB_TAG_ASSEMBLER 0x000d - struct cb_string { u32 tag; u32 size; u8 string[0]; }; -#define CB_TAG_SERIAL 0x000f - struct cb_serial { u32 tag; u32 size; @@ -138,8 +167,6 @@ u32 uart_pci_addr; }; -#define CB_TAG_CONSOLE 0x00010 - struct cb_console { u32 tag; u32 size; @@ -153,15 +180,12 @@ #define CB_TAG_CONSOLE_SROM 4 // OBSOLETE #define CB_TAG_CONSOLE_EHCI 5 -#define CB_TAG_FORWARD 0x00011 - struct cb_forward { u32 tag; u32 size; u64 forward; }; -#define CB_TAG_FRAMEBUFFER 0x0012 struct cb_framebuffer { u32 tag; u32 size; @@ -181,7 +205,6 @@ u8 reserved_mask_size; }; -#define CB_TAG_GPIO 0x0013 #define CB_GPIO_ACTIVE_LOW 0 #define CB_GPIO_ACTIVE_HIGH 1 #define CB_GPIO_MAX_NAME_LENGTH 16 @@ -200,13 +223,6 @@ struct cb_gpio gpios[0]; }; -#define CB_TAG_VBNV 0x0019 -#define CB_TAG_VBOOT_HANDOFF 0x0020 -#define CB_TAG_VBOOT_WORKBUF 0x0034 -#define CB_TAG_DMA 0x0022 -#define CB_TAG_RAM_OOPS 0x0023 -#define CB_TAG_MTC 0x002b -#define CB_TAG_VPD 0x002c struct lb_range { uint32_t tag; uint32_t size; @@ -214,18 +230,12 @@ uint32_t range_size; }; -#define CB_TAG_TIMESTAMPS 0x0016 -#define CB_TAG_CBMEM_CONSOLE 0x0017 -#define CB_TAG_MRC_CACHE 0x0018 -#define CB_TAG_ACPI_GNVS 0x0024 -#define CB_TAG_WIFI_CALIBRATION 0x0027 struct cb_cbmem_tab { uint32_t tag; uint32_t size; uint64_t cbmem_tab; }; -#define CB_TAG_X86_ROM_MTRR 0x0021 struct cb_x86_rom_mtrr { uint32_t tag; uint32_t size; @@ -236,17 +246,12 @@ uint32_t index; }; - -#define CB_TAG_BOARD_ID 0x0025 -#define CB_TAG_RAM_CODE 0x0028 -#define CB_TAG_SKU_ID 0x002d struct cb_strapping_id { uint32_t tag; uint32_t size; uint32_t id_code; }; -#define CB_TAG_SPI_FLASH 0x0029 struct cb_spi_flash { uint32_t tag; uint32_t size; @@ -255,7 +260,6 @@ uint32_t erase_cmd; }; -#define CB_TAG_BOOT_MEDIA_PARAMS 0x0030 struct cb_boot_media_params { uint32_t tag; uint32_t size; @@ -266,7 +270,6 @@ uint64_t boot_media_size; }; -#define CB_TAG_TSC_INFO 0x0032 struct cb_tsc_info { uint32_t tag; uint32_t size; @@ -274,7 +277,6 @@ uint32_t freq_khz; }; -#define CB_TAG_MAC_ADDRS 0x0033 struct mac_address { uint8_t mac_addr[6]; uint8_t pad[2]; /* Pad it to 8 bytes to keep it simple. */ @@ -287,7 +289,6 @@ struct mac_address mac_addrs[0]; }; -#define CB_TAG_MMC_INFO 0x0035 struct cb_mmc_info { uint32_t tag; uint32_t size; @@ -302,17 +303,14 @@ int32_t early_cmd1_status; }; -#define CB_TAG_SERIALNO 0x002a #define CB_MAX_SERIALNO_LENGTH 32 -#define CB_TAG_CMOS_OPTION_TABLE 0x00c8 struct cb_cmos_option_table { u32 tag; u32 size; u32 header_length; }; -#define CB_TAG_OPTION 0x00c9 #define CB_CMOS_MAX_NAME_LENGTH 32 struct cb_cmos_entries { u32 tag; @@ -324,8 +322,6 @@ u8 name[CB_CMOS_MAX_NAME_LENGTH]; }; - -#define CB_TAG_OPTION_ENUM 0x00ca #define CB_CMOS_MAX_TEXT_LENGTH 32 struct cb_cmos_enums { u32 tag; @@ -335,7 +331,6 @@ u8 text[CB_CMOS_MAX_TEXT_LENGTH]; }; -#define CB_TAG_OPTION_DEFAULTS 0x00cb #define CB_CMOS_IMAGE_BUFFER_SIZE 128 struct cb_cmos_defaults { u32 tag; @@ -345,7 +340,6 @@ u8 default_set[CB_CMOS_IMAGE_BUFFER_SIZE]; }; -#define CB_TAG_OPTION_CHECKSUM 0x00cc #define CB_CHECKSUM_NONE 0 #define CB_CHECKSUM_PCBIOS 1 struct cb_cmos_checksum { -- To view, visit https://review.coreboot.org/c/coreboot/+/32957 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c7762601d7620413989b458fa634d7606accc9d Gerrit-Change-Number: 32957 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 5

Change in ...coreboot[master]: mb/{i945}: Move CHANNEL_XOR_RANDOMIZATION selection to northbridge
by HAOUAS Elyes (Code Review) 14 Jun '19

14 Jun '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32928 Change subject: mb/{i945}: Move CHANNEL_XOR_RANDOMIZATION selection to northbridge ...................................................................... mb/{i945}: Move CHANNEL_XOR_RANDOMIZATION selection to northbridge Change-Id: I31e6ed6cb040dcba756cbfd2247d90753d372915 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/apple/macbook21/Kconfig M src/mainboard/asus/p5gc-mx/Kconfig M src/mainboard/getac/p470/Kconfig M src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig M src/mainboard/ibase/mb899/Kconfig M src/mainboard/intel/d945gclf/Kconfig M src/mainboard/kontron/986lcd-m/Kconfig M src/mainboard/lenovo/t60/Kconfig M src/mainboard/lenovo/x60/Kconfig M src/mainboard/lenovo/z61t/Kconfig M src/mainboard/roda/rk886ex/Kconfig M src/northbridge/intel/i945/Kconfig 12 files changed, 1 insertion(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/32928/1 diff --git a/src/mainboard/apple/macbook21/Kconfig b/src/mainboard/apple/macbook21/Kconfig index 6535f8f..84c00cf 100644 --- a/src/mainboard/apple/macbook21/Kconfig +++ b/src/mainboard/apple/macbook21/Kconfig @@ -13,7 +13,6 @@ select HAVE_CMOS_DEFAULT select HAVE_MP_TABLE select BOARD_ROMSIZE_KB_2048 - select CHANNEL_XOR_RANDOMIZATION select INTEL_INT15 select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME diff --git a/src/mainboard/asus/p5gc-mx/Kconfig b/src/mainboard/asus/p5gc-mx/Kconfig index 21e57bb..193364a 100644 --- a/src/mainboard/asus/p5gc-mx/Kconfig +++ b/src/mainboard/asus/p5gc-mx/Kconfig @@ -29,7 +29,6 @@ select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME select BOARD_ROMSIZE_KB_512 - select CHANNEL_XOR_RANDOMIZATION select MAINBOARD_HAS_NATIVE_VGA_INIT select INTEL_GMA_HAVE_VBT diff --git a/src/mainboard/getac/p470/Kconfig b/src/mainboard/getac/p470/Kconfig index a5eed1a..9fe40bc 100644 --- a/src/mainboard/getac/p470/Kconfig +++ b/src/mainboard/getac/p470/Kconfig @@ -32,7 +32,6 @@ select HAVE_ACPI_RESUME select UDELAY_LAPIC select BOARD_ROMSIZE_KB_1024 - select CHANNEL_XOR_RANDOMIZATION select INTEL_INT15 select I945_LVDS diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig b/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig index ea3142a..e9ed54d 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig @@ -29,7 +29,6 @@ select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME select BOARD_ROMSIZE_KB_512 - select CHANNEL_XOR_RANDOMIZATION select MAINBOARD_HAS_NATIVE_VGA_INIT select REALTEK_8168_RESET if BOARD_GIGABYTE_GA_945GCM_S2L select INTEL_GMA_HAVE_VBT diff --git a/src/mainboard/ibase/mb899/Kconfig b/src/mainboard/ibase/mb899/Kconfig index 621395d..fcc2e38 100644 --- a/src/mainboard/ibase/mb899/Kconfig +++ b/src/mainboard/ibase/mb899/Kconfig @@ -14,7 +14,6 @@ select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME select BOARD_ROMSIZE_KB_512 - select CHANNEL_XOR_RANDOMIZATION select INTEL_INT15 config MAINBOARD_DIR diff --git a/src/mainboard/intel/d945gclf/Kconfig b/src/mainboard/intel/d945gclf/Kconfig index 70fa848..46d82ec 100644 --- a/src/mainboard/intel/d945gclf/Kconfig +++ b/src/mainboard/intel/d945gclf/Kconfig @@ -28,7 +28,6 @@ select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME select BOARD_ROMSIZE_KB_512 - select CHANNEL_XOR_RANDOMIZATION select MAINBOARD_HAS_NATIVE_VGA_INIT select INTEL_GMA_HAVE_VBT diff --git a/src/mainboard/kontron/986lcd-m/Kconfig b/src/mainboard/kontron/986lcd-m/Kconfig index 43bdf14..9dadd55 100644 --- a/src/mainboard/kontron/986lcd-m/Kconfig +++ b/src/mainboard/kontron/986lcd-m/Kconfig @@ -14,7 +14,6 @@ select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME select BOARD_ROMSIZE_KB_1024 - select CHANNEL_XOR_RANDOMIZATION select INTEL_INT15 select OVERRIDE_CLOCK_DISABLE diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig index a6a88b3..e4e87c9 100644 --- a/src/mainboard/lenovo/t60/Kconfig +++ b/src/mainboard/lenovo/t60/Kconfig @@ -17,7 +17,6 @@ select INTEL_INT15 select HAVE_MP_TABLE select BOARD_ROMSIZE_KB_2048 - select CHANNEL_XOR_RANDOMIZATION select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME select H8_DOCK_EARLY_INIT diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index 6db7f11..e3aabf3 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -19,7 +19,6 @@ select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select BOARD_ROMSIZE_KB_2048 - select CHANNEL_XOR_RANDOMIZATION select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME select USE_OPTION_TABLE diff --git a/src/mainboard/lenovo/z61t/Kconfig b/src/mainboard/lenovo/z61t/Kconfig index a223077..de48d95 100644 --- a/src/mainboard/lenovo/z61t/Kconfig +++ b/src/mainboard/lenovo/z61t/Kconfig @@ -17,7 +17,6 @@ select INTEL_INT15 select HAVE_MP_TABLE select BOARD_ROMSIZE_KB_2048 - select CHANNEL_XOR_RANDOMIZATION select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME select H8_DOCK_EARLY_INIT diff --git a/src/mainboard/roda/rk886ex/Kconfig b/src/mainboard/roda/rk886ex/Kconfig index 821a9a1..9e97529 100644 --- a/src/mainboard/roda/rk886ex/Kconfig +++ b/src/mainboard/roda/rk886ex/Kconfig @@ -17,7 +17,6 @@ select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME select BOARD_ROMSIZE_KB_1024 - select CHANNEL_XOR_RANDOMIZATION select INTEL_INT15 config MAINBOARD_DIR diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index 2c21420..c004224 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -32,6 +32,7 @@ select SMM_TSEG select PARALLEL_MP select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM + select CHANNEL_XOR_RANDOMIZATION config NORTHBRIDGE_INTEL_SUBTYPE_I945GC def_bool n -- To view, visit https://review.coreboot.org/c/coreboot/+/32928 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31e6ed6cb040dcba756cbfd2247d90753d372915 Gerrit-Change-Number: 32928 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 11

Change in ...coreboot[master]: mainboard/google/hatch: Update Helios device tree
by Tim Wawrzynczak (Code Review) 14 Jun '19

14 Jun '19

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33050 Change subject: mainboard/google/hatch: Update Helios device tree ...................................................................... mainboard/google/hatch: Update Helios device tree Update Helios device tree override to match schematics. BUG=b:133182138 BRANCH=none TEST=Compiles Change-Id: I3d15fc43651a289d16ffb3cfadaea8f786e858fc Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/hatch/variants/helios/overridetree.cb 1 file changed, 88 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/33050/1 diff --git a/src/mainboard/google/hatch/variants/helios/overridetree.cb b/src/mainboard/google/hatch/variants/helios/overridetree.cb index 84f0e29..4fecab3 100644 --- a/src/mainboard/google/hatch/variants/helios/overridetree.cb +++ b/src/mainboard/google/hatch/variants/helios/overridetree.cb @@ -14,6 +14,9 @@ [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" + # No PCIe WiFi + register "PcieRpEnable[13]" = "0" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | @@ -42,5 +45,89 @@ }, }" - device domain 0 on end + device domain 0 on + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + # No Type-A port + device usb 2.2 off end + end + chip drivers/usb/acpi + # No Type-A Port + device usb 2.3 off end + end + chip drivers/usb/acpi + # No WWAN + device usb 2.5 off end + end + chip drivers/usb/acpi + # No WWAN + device usb 3.4 off end + end + end + end + end + + # Native SD Card interface unused + device pci 14.5 off end + + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A20_IRQ)" + register "wake" = "GPE0_DW0_21" + device i2c 15 on end + end + end + + device pci 15.1 on + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "generic.reset_delay_ms" = "10" + register "generic.reset_off_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 5d on end + end + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + register "gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A8)" + register "key.wake" = "GPE0_DW0_08" + register "key.wakeup_event_action" = "EV_ACT_ASSERTED" + register "key.dev_name" = ""EJCT"" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + device generic 0 on end + end + end # I2C 1 + + # I2C #2 unused + device pci 15.2 off end + + # I2C #3 unused + device pci 15.3 off end + + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" + register "property_count" = "1" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end #I2C #4 + end end -- To view, visit https://review.coreboot.org/c/coreboot/+/33050 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d15fc43651a289d16ffb3cfadaea8f786e858fc Gerrit-Change-Number: 33050 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

5 15

Change in ...coreboot[master]: Set ENV_PAYLOAD_LOADER to ENV_POSTCAR when CONFIG_RAMPAYLOAD is enable
by Subrata Banik (Code Review) 13 Jun '19

13 Jun '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32751 Change subject: Set ENV_PAYLOAD_LOADER to ENV_POSTCAR when CONFIG_RAMPAYLOAD is enable ...................................................................... Set ENV_PAYLOAD_LOADER to ENV_POSTCAR when CONFIG_RAMPAYLOAD is enable Change-Id: I416c74ea83ee68370bbeb53834054bcb18e631e1 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/include/rules.h 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/32751/1 diff --git a/src/include/rules.h b/src/include/rules.h index 801a7fe..5ee535b 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -257,9 +257,14 @@ #endif +#if CONFIG(RAMPAYLOAD) +/* ENV_PAYLOAD_LOADER is set to ENV_POSTCAR when CONFIG_RAMPAYLOAD is enable */ +#define ENV_PAYLOAD_LOADER ENV_POSTCAR +#else /* ENV_PAYLOAD_LOADER is set when you are in a stage that loads the payload. * For now, that is the ramstage. */ #define ENV_PAYLOAD_LOADER ENV_RAMSTAGE +#endif /** * For pre-DRAM stages and post-CAR always build with simple device model, ie. -- To view, visit https://review.coreboot.org/c/coreboot/+/32751 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I416c74ea83ee68370bbeb53834054bcb18e631e1 Gerrit-Change-Number: 32751 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

3 19

Change in ...coreboot[master]: vendorcode/intel/fsp/fsp2_0/cometlake: Update FSP-M/S header files as...
by Aamir Bohra (Code Review) 13 Jun '19

13 Jun '19

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32844 Change subject: vendorcode/intel/fsp/fsp2_0/cometlake: Update FSP-M/S header files as per v1155 ...................................................................... vendorcode/intel/fsp/fsp2_0/cometlake: Update FSP-M/S header files as per v1155 Update FSP-M and FSP-S header files as per FSP release version 1155. Change-Id: I6d412424f9f5c5d2d56b789c2fef4bdb817a3019 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/vendorcode/intel/fsp/fsp2_0/cometlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/cometlake/FspsUpd.h 2 files changed, 960 insertions(+), 857 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/32844/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspmUpd.h index 85dbe70..92663f0 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspmUpd.h @@ -1421,799 +1421,830 @@ **/ UINT8 PcdDebugInterfaceFlags; -/** Offset 0x044C - PcdSerialIoUartNumber - Select SerialIo Uart Controller for debug. +/** Offset 0x044C - Serial Io Uart Debug Controller Number + Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT + Core interface, it cannot be used for debug purpose. 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 **/ - UINT8 PcdSerialIoUartNumber; + UINT8 SerialIoUartDebugControllerNumber; -/** Offset 0x044D - ReservedPchPreMem +/** Offset 0x044D - Serial Io Uart Debug Auto Flow + Enables UART hardware flow control, CTS and RTS lines. + $EN_DIS +**/ + UINT8 SerialIoUartDebugAutoFlow; + +/** Offset 0x044E +**/ + UINT8 UnusedUpdSpace7[2]; + +/** Offset 0x0450 - Serial Io Uart Debug BaudRate + Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600, + 19200, 57600, 115200, 460800, 921600, 1500000, 1843200, 3000000, 3686400, 6000000 +**/ + UINT32 SerialIoUartDebugBaudRate; + +/** Offset 0x0454 - Serial Io Uart Debug Parity + Set default Parity. + 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity +**/ + UINT8 SerialIoUartDebugParity; + +/** Offset 0x0455 - Serial Io Uart Debug Stop Bits + Set default stop bits. + 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits +**/ + UINT8 SerialIoUartDebugStopBits; + +/** Offset 0x0456 - Serial Io Uart Debug Data Bits + Set default word length. 0: Default, 5,6,7,8 + 5:5BITS, 6:6BITS, 7:7BITS, 8:8BITS +**/ + UINT8 SerialIoUartDebugDataBits; + +/** Offset 0x0457 - ReservedPchPreMem Reserved for Pch Pre-Mem $EN_DIS **/ UINT8 ReservedPchPreMem[16]; -/** Offset 0x045D - ISA Serial Base selection +/** Offset 0x0467 - ISA Serial Base selection Select ISA Serial Base address. Default is 0x3F8. 0:0x3F8, 1:0x2F8 **/ UINT8 PcdIsaSerialUartBase; -/** Offset 0x045E - GT PLL voltage offset +/** Offset 0x0468 - GT PLL voltage offset Core PLL voltage offset. 0: No offset. Range 0-63 **/ UINT8 GtPllVoltageOffset; -/** Offset 0x045F - Ring PLL voltage offset +/** Offset 0x0469 - Ring PLL voltage offset Core PLL voltage offset. 0: No offset. Range 0-63 **/ UINT8 RingPllVoltageOffset; -/** Offset 0x0460 - System Agent PLL voltage offset +/** Offset 0x046A - System Agent PLL voltage offset Core PLL voltage offset. 0: No offset. Range 0-63 **/ UINT8 SaPllVoltageOffset; -/** Offset 0x0461 - Memory Controller PLL voltage offset +/** Offset 0x046B - Memory Controller PLL voltage offset Core PLL voltage offset. 0: No offset. Range 0-63 **/ UINT8 McPllVoltageOffset; -/** Offset 0x0462 - MRC Safe Config +/** Offset 0x046C - MRC Safe Config Enables/Disable MRC Safe Config $EN_DIS **/ UINT8 MrcSafeConfig; -/** Offset 0x0463 - PcdSerialDebugBaudRate +/** Offset 0x046D - PcdSerialDebugBaudRate Baud Rate for Serial Debug Messages. 3:9600, 4:19200, 6:56700, 7:115200. 3:9600, 4:19200, 6:56700, 7:115200 **/ UINT8 PcdSerialDebugBaudRate; -/** Offset 0x0464 - HobBufferSize +/** Offset 0x046E - HobBufferSize Size to set HOB Buffer. 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value(assuming 63KB total HOB size). 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value **/ UINT8 HobBufferSize; -/** Offset 0x0465 - Early Command Training +/** Offset 0x046F - Early Command Training Enables/Disable Early Command Training $EN_DIS **/ UINT8 ECT; -/** Offset 0x0466 - SenseAmp Offset Training +/** Offset 0x0470 - SenseAmp Offset Training Enables/Disable SenseAmp Offset Training $EN_DIS **/ UINT8 SOT; -/** Offset 0x0467 - Early ReadMPR Timing Centering 2D +/** Offset 0x0471 - Early ReadMPR Timing Centering 2D Enables/Disable Early ReadMPR Timing Centering 2D $EN_DIS **/ UINT8 ERDMPRTC2D; -/** Offset 0x0468 - Read MPR Training +/** Offset 0x0472 - Read MPR Training Enables/Disable Read MPR Training $EN_DIS **/ UINT8 RDMPRT; -/** Offset 0x0469 - Receive Enable Training +/** Offset 0x0473 - Receive Enable Training Enables/Disable Receive Enable Training $EN_DIS **/ UINT8 RCVET; -/** Offset 0x046A - Jedec Write Leveling +/** Offset 0x0474 - Jedec Write Leveling Enables/Disable Jedec Write Leveling $EN_DIS **/ UINT8 JWRL; -/** Offset 0x046B - Early Write Time Centering 2D +/** Offset 0x0475 - Early Write Time Centering 2D Enables/Disable Early Write Time Centering 2D $EN_DIS **/ UINT8 EWRTC2D; -/** Offset 0x046C - Early Read Time Centering 2D +/** Offset 0x0476 - Early Read Time Centering 2D Enables/Disable Early Read Time Centering 2D $EN_DIS **/ UINT8 ERDTC2D; -/** Offset 0x046D - Write Timing Centering 1D +/** Offset 0x0477 - Write Timing Centering 1D Enables/Disable Write Timing Centering 1D $EN_DIS **/ UINT8 WRTC1D; -/** Offset 0x046E - Write Voltage Centering 1D +/** Offset 0x0478 - Write Voltage Centering 1D Enables/Disable Write Voltage Centering 1D $EN_DIS **/ UINT8 WRVC1D; -/** Offset 0x046F - Read Timing Centering 1D +/** Offset 0x0479 - Read Timing Centering 1D Enables/Disable Read Timing Centering 1D $EN_DIS **/ UINT8 RDTC1D; -/** Offset 0x0470 - Dimm ODT Training +/** Offset 0x047A - Dimm ODT Training Enables/Disable Dimm ODT Training $EN_DIS **/ UINT8 DIMMODTT; -/** Offset 0x0471 - DIMM RON Training +/** Offset 0x047B - DIMM RON Training Enables/Disable DIMM RON Training $EN_DIS **/ UINT8 DIMMRONT; -/** Offset 0x0472 - Write Drive Strength/Equalization 2D +/** Offset 0x047C - Write Drive Strength/Equalization 2D Enables/Disable Write Drive Strength/Equalization 2D $EN_DIS **/ UINT8 WRDSEQT; -/** Offset 0x0473 - Write Slew Rate Training +/** Offset 0x047D - Write Slew Rate Training Enables/Disable Write Slew Rate Training $EN_DIS **/ UINT8 WRSRT; -/** Offset 0x0474 - Read ODT Training +/** Offset 0x047E - Read ODT Training Enables/Disable Read ODT Training $EN_DIS **/ UINT8 RDODTT; -/** Offset 0x0475 - Read Equalization Training +/** Offset 0x047F - Read Equalization Training Enables/Disable Read Equalization Training $EN_DIS **/ UINT8 RDEQT; -/** Offset 0x0476 - Read Amplifier Training +/** Offset 0x0480 - Read Amplifier Training Enables/Disable Read Amplifier Training $EN_DIS **/ UINT8 RDAPT; -/** Offset 0x0477 - Write Timing Centering 2D +/** Offset 0x0481 - Write Timing Centering 2D Enables/Disable Write Timing Centering 2D $EN_DIS **/ UINT8 WRTC2D; -/** Offset 0x0478 - Read Timing Centering 2D +/** Offset 0x0482 - Read Timing Centering 2D Enables/Disable Read Timing Centering 2D $EN_DIS **/ UINT8 RDTC2D; -/** Offset 0x0479 - Write Voltage Centering 2D +/** Offset 0x0483 - Write Voltage Centering 2D Enables/Disable Write Voltage Centering 2D $EN_DIS **/ UINT8 WRVC2D; -/** Offset 0x047A - Read Voltage Centering 2D +/** Offset 0x0484 - Read Voltage Centering 2D Enables/Disable Read Voltage Centering 2D $EN_DIS **/ UINT8 RDVC2D; -/** Offset 0x047B - Command Voltage Centering +/** Offset 0x0485 - Command Voltage Centering Enables/Disable Command Voltage Centering $EN_DIS **/ UINT8 CMDVC; -/** Offset 0x047C - Late Command Training +/** Offset 0x0486 - Late Command Training Enables/Disable Late Command Training $EN_DIS **/ UINT8 LCT; -/** Offset 0x047D - Round Trip Latency Training +/** Offset 0x0487 - Round Trip Latency Training Enables/Disable Round Trip Latency Training $EN_DIS **/ UINT8 RTL; -/** Offset 0x047E - Turn Around Timing Training +/** Offset 0x0488 - Turn Around Timing Training Enables/Disable Turn Around Timing Training $EN_DIS **/ UINT8 TAT; -/** Offset 0x047F - Memory Test +/** Offset 0x0489 - Memory Test Enables/Disable Memory Test $EN_DIS **/ UINT8 MEMTST; -/** Offset 0x0480 - DIMM SPD Alias Test +/** Offset 0x048A - DIMM SPD Alias Test Enables/Disable DIMM SPD Alias Test $EN_DIS **/ UINT8 ALIASCHK; -/** Offset 0x0481 - Receive Enable Centering 1D +/** Offset 0x048B - Receive Enable Centering 1D Enables/Disable Receive Enable Centering 1D $EN_DIS **/ UINT8 RCVENC1D; -/** Offset 0x0482 - Retrain Margin Check +/** Offset 0x048C - Retrain Margin Check Enables/Disable Retrain Margin Check $EN_DIS **/ UINT8 RMC; -/** Offset 0x0483 - Write Drive Strength Up/Dn independently +/** Offset 0x048D - Write Drive Strength Up/Dn independently Enables/Disable Write Drive Strength Up/Dn independently $EN_DIS **/ UINT8 WRDSUDT; -/** Offset 0x0484 - ECC Support +/** Offset 0x048E - ECC Support Enables/Disable ECC Support $EN_DIS **/ UINT8 EccSupport; -/** Offset 0x0485 - Memory Remap +/** Offset 0x048F - Memory Remap Enables/Disable Memory Remap $EN_DIS **/ UINT8 RemapEnable; -/** Offset 0x0486 - Rank Interleave support +/** Offset 0x0490 - Rank Interleave support Enables/Disable Rank Interleave support. NOTE: RI and HORI can not be enabled at the same time. $EN_DIS **/ UINT8 RankInterleave; -/** Offset 0x0487 - Enhanced Interleave support +/** Offset 0x0491 - Enhanced Interleave support Enables/Disable Enhanced Interleave support $EN_DIS **/ UINT8 EnhancedInterleave; -/** Offset 0x0488 - Memory Trace +/** Offset 0x0492 - Memory Trace Enable Memory Trace of Ch 0 to Ch 1 using Stacked Mode. Both channels must be of equal size. This option may change TOLUD and REMAP values as needed. $EN_DIS **/ UINT8 MemoryTrace; -/** Offset 0x0489 - Ch Hash Support +/** Offset 0x0493 - Ch Hash Support Enable/Disable Channel Hash Support. NOTE: ONLY if Memory interleaved Mode $EN_DIS **/ UINT8 ChHashEnable; -/** Offset 0x048A - Extern Therm Status +/** Offset 0x0494 - Extern Therm Status Enables/Disable Extern Therm Status $EN_DIS **/ UINT8 EnableExtts; -/** Offset 0x048B - Closed Loop Therm Manage +/** Offset 0x0495 - Closed Loop Therm Manage Enables/Disable Closed Loop Therm Manage $EN_DIS **/ UINT8 EnableCltm; -/** Offset 0x048C - Open Loop Therm Manage +/** Offset 0x0496 - Open Loop Therm Manage Enables/Disable Open Loop Therm Manage $EN_DIS **/ UINT8 EnableOltm; -/** Offset 0x048D - DDR PowerDown and idle counter +/** Offset 0x0497 - DDR PowerDown and idle counter Enables/Disable DDR PowerDown and idle counter $EN_DIS **/ UINT8 EnablePwrDn; -/** Offset 0x048E - DDR PowerDown and idle counter - LPDDR +/** Offset 0x0498 - DDR PowerDown and idle counter - LPDDR Enables/Disable DDR PowerDown and idle counter(For LPDDR Only) $EN_DIS **/ UINT8 EnablePwrDnLpddr; -/** Offset 0x048F - Use user provided power weights, scale factor, and channel power floor values +/** Offset 0x0499 - Use user provided power weights, scale factor, and channel power floor values Enables/Disable Use user provided power weights, scale factor, and channel power floor values $EN_DIS **/ UINT8 UserPowerWeightsEn; -/** Offset 0x0490 - RAPL PL Lock +/** Offset 0x049A - RAPL PL Lock Enables/Disable RAPL PL Lock $EN_DIS **/ UINT8 RaplLim2Lock; -/** Offset 0x0491 - RAPL PL 2 enable +/** Offset 0x049B - RAPL PL 2 enable Enables/Disable RAPL PL 2 enable $EN_DIS **/ UINT8 RaplLim2Ena; -/** Offset 0x0492 - RAPL PL 1 enable +/** Offset 0x049C - RAPL PL 1 enable Enables/Disable RAPL PL 1 enable $EN_DIS **/ UINT8 RaplLim1Ena; -/** Offset 0x0493 - SelfRefresh Enable +/** Offset 0x049D - SelfRefresh Enable Enables/Disable SelfRefresh Enable $EN_DIS **/ UINT8 SrefCfgEna; -/** Offset 0x0494 - Throttler CKEMin Defeature - LPDDR +/** Offset 0x049E - Throttler CKEMin Defeature - LPDDR Enables/Disable Throttler CKEMin Defeature(For LPDDR Only) $EN_DIS **/ UINT8 ThrtCkeMinDefeatLpddr; -/** Offset 0x0495 - Throttler CKEMin Defeature +/** Offset 0x049F - Throttler CKEMin Defeature Enables/Disable Throttler CKEMin Defeature $EN_DIS **/ UINT8 ThrtCkeMinDefeat; -/** Offset 0x0496 - Enable RH Prevention +/** Offset 0x04A0 - Enable RH Prevention Enables/Disable RH Prevention $EN_DIS **/ UINT8 RhPrevention; -/** Offset 0x0497 - Exit On Failure (MRC) +/** Offset 0x04A1 - Exit On Failure (MRC) Enables/Disable Exit On Failure (MRC) $EN_DIS **/ UINT8 ExitOnFailure; -/** Offset 0x0498 - LPDDR Thermal Sensor +/** Offset 0x04A2 - LPDDR Thermal Sensor Enables/Disable LPDDR Thermal Sensor $EN_DIS **/ UINT8 DdrThermalSensor; -/** Offset 0x0499 - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP +/** Offset 0x04A3 - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP $EN_DIS **/ UINT8 Ddr4DdpSharedClock; -/** Offset 0x049A - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP +/** Offset 0x04A4 - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP ESelect if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP $EN_DIS **/ UINT8 Ddr4DdpSharedZq; -/** Offset 0x049B +/** Offset 0x04A5 **/ - UINT8 UnusedUpdSpace7; + UINT8 UnusedUpdSpace8; -/** Offset 0x049C - Ch Hash Mask +/** Offset 0x04A6 - Ch Hash Mask Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to BITS [19:6 **/ UINT16 ChHashMask; -/** Offset 0x049E -**/ - UINT8 UnusedUpdSpace8[2]; - -/** Offset 0x04A0 - Base reference clock value +/** Offset 0x04A8 - Base reference clock value Base reference clock value, in Hertz(Default is 125Hz) 100000000:100Hz, 125000000:125Hz, 167000000:167Hz, 250000000:250Hz **/ UINT32 BClkFrequency; -/** Offset 0x04A4 - Ch Hash Interleaved Bit +/** Offset 0x04AC - Ch Hash Interleaved Bit Select the BIT to be used for Channel Interleaved mode. NOTE: BIT7 will interlave the channels at a 2 cacheline granularity, BIT8 at 4 and BIT9 at 8. Default is BIT8 0:BIT6, 1:BIT7, 2:BIT8, 3:BIT9, 4:BIT10, 5:BIT11, 6:BIT12, 7:BIT13 **/ UINT8 ChHashInterleaveBit; -/** Offset 0x04A5 - Energy Scale Factor +/** Offset 0x04AD - Energy Scale Factor Energy Scale Factor, Default is 4 **/ UINT8 EnergyScaleFact; -/** Offset 0x04A6 - EPG DIMM Idd3N +/** Offset 0x04AE - EPG DIMM Idd3N Active standby current (Idd3N) in milliamps from datasheet. Must be calculated on a per DIMM basis. Default is 26 **/ UINT16 Idd3n; -/** Offset 0x04A8 - EPG DIMM Idd3P +/** Offset 0x04B0 - EPG DIMM Idd3P Active power-down current (Idd3P) in milliamps from datasheet. Must be calculated on a per DIMM basis. Default is 11 **/ UINT16 Idd3p; -/** Offset 0x04AA - CMD Slew Rate Training +/** Offset 0x04B2 - CMD Slew Rate Training Enable/Disable CMD Slew Rate Training $EN_DIS **/ UINT8 CMDSR; -/** Offset 0x04AB - CMD Drive Strength and Tx Equalization +/** Offset 0x04B3 - CMD Drive Strength and Tx Equalization Enable/Disable CMD Drive Strength and Tx Equalization $EN_DIS **/ UINT8 CMDDSEQ; -/** Offset 0x04AC - CMD Normalization +/** Offset 0x04B4 - CMD Normalization Enable/Disable CMD Normalization $EN_DIS **/ UINT8 CMDNORM; -/** Offset 0x04AD - Early DQ Write Drive Strength and Equalization Training +/** Offset 0x04B5 - Early DQ Write Drive Strength and Equalization Training Enable/Disable Early DQ Write Drive Strength and Equalization Training $EN_DIS **/ UINT8 EWRDSEQ; -/** Offset 0x04AE - RH Activation Probability +/** Offset 0x04B6 - RH Activation Probability RH Activation Probability, Probability value is 1/2^(inputvalue) **/ UINT8 RhActProbability; -/** Offset 0x04AF - RAPL PL 2 WindowX +/** Offset 0x04B7 - RAPL PL 2 WindowX Power PL 2 time window X value, (1/1024)*(1+(x/4))*(2^y) (1=Def) **/ UINT8 RaplLim2WindX; -/** Offset 0x04B0 - RAPL PL 2 WindowY +/** Offset 0x04B8 - RAPL PL 2 WindowY Power PL 2 time window Y value, (1/1024)*(1+(x/4))*(2^y) (1=Def) **/ UINT8 RaplLim2WindY; -/** Offset 0x04B1 - RAPL PL 1 WindowX +/** Offset 0x04B9 - RAPL PL 1 WindowX Power PL 1 time window X value, (1/1024)*(1+(x/4))*(2^y) (0=Def) **/ UINT8 RaplLim1WindX; -/** Offset 0x04B2 - RAPL PL 1 WindowY +/** Offset 0x04BA - RAPL PL 1 WindowY Power PL 1 time window Y value, (1/1024)*(1+(x/4))*(2^y) (0=Def) **/ UINT8 RaplLim1WindY; -/** Offset 0x04B3 +/** Offset 0x04BB **/ UINT8 UnusedUpdSpace9; -/** Offset 0x04B4 - RAPL PL 2 Power +/** Offset 0x04BC - RAPL PL 2 Power range[0;2^14-1]= [2047.875;0]in W, (222= Def) **/ UINT16 RaplLim2Pwr; -/** Offset 0x04B6 - RAPL PL 1 Power +/** Offset 0x04BE - RAPL PL 1 Power range[0;2^14-1]= [2047.875;0]in W, (0= Def) **/ UINT16 RaplLim1Pwr; -/** Offset 0x04B8 - Warm Threshold Ch0 Dimm0 +/** Offset 0x04C0 - Warm Threshold Ch0 Dimm0 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 **/ UINT8 WarmThresholdCh0Dimm0; -/** Offset 0x04B9 - Warm Threshold Ch0 Dimm1 +/** Offset 0x04C1 - Warm Threshold Ch0 Dimm1 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 **/ UINT8 WarmThresholdCh0Dimm1; -/** Offset 0x04BA - Warm Threshold Ch1 Dimm0 +/** Offset 0x04C2 - Warm Threshold Ch1 Dimm0 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 **/ UINT8 WarmThresholdCh1Dimm0; -/** Offset 0x04BB - Warm Threshold Ch1 Dimm1 +/** Offset 0x04C3 - Warm Threshold Ch1 Dimm1 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 **/ UINT8 WarmThresholdCh1Dimm1; -/** Offset 0x04BC - Hot Threshold Ch0 Dimm0 +/** Offset 0x04C4 - Hot Threshold Ch0 Dimm0 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 **/ UINT8 HotThresholdCh0Dimm0; -/** Offset 0x04BD - Hot Threshold Ch0 Dimm1 +/** Offset 0x04C5 - Hot Threshold Ch0 Dimm1 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 **/ UINT8 HotThresholdCh0Dimm1; -/** Offset 0x04BE - Hot Threshold Ch1 Dimm0 +/** Offset 0x04C6 - Hot Threshold Ch1 Dimm0 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 **/ UINT8 HotThresholdCh1Dimm0; -/** Offset 0x04BF - Hot Threshold Ch1 Dimm1 +/** Offset 0x04C7 - Hot Threshold Ch1 Dimm1 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 **/ UINT8 HotThresholdCh1Dimm1; -/** Offset 0x04C0 - Warm Budget Ch0 Dimm0 +/** Offset 0x04C8 - Warm Budget Ch0 Dimm0 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM **/ UINT8 WarmBudgetCh0Dimm0; -/** Offset 0x04C1 - Warm Budget Ch0 Dimm1 +/** Offset 0x04C9 - Warm Budget Ch0 Dimm1 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM **/ UINT8 WarmBudgetCh0Dimm1; -/** Offset 0x04C2 - Warm Budget Ch1 Dimm0 +/** Offset 0x04CA - Warm Budget Ch1 Dimm0 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM **/ UINT8 WarmBudgetCh1Dimm0; -/** Offset 0x04C3 - Warm Budget Ch1 Dimm1 +/** Offset 0x04CB - Warm Budget Ch1 Dimm1 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM **/ UINT8 WarmBudgetCh1Dimm1; -/** Offset 0x04C4 - Hot Budget Ch0 Dimm0 +/** Offset 0x04CC - Hot Budget Ch0 Dimm0 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM **/ UINT8 HotBudgetCh0Dimm0; -/** Offset 0x04C5 - Hot Budget Ch0 Dimm1 +/** Offset 0x04CD - Hot Budget Ch0 Dimm1 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM **/ UINT8 HotBudgetCh0Dimm1; -/** Offset 0x04C6 - Hot Budget Ch1 Dimm0 +/** Offset 0x04CE - Hot Budget Ch1 Dimm0 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM **/ UINT8 HotBudgetCh1Dimm0; -/** Offset 0x04C7 - Hot Budget Ch1 Dimm1 +/** Offset 0x04CF - Hot Budget Ch1 Dimm1 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM **/ UINT8 HotBudgetCh1Dimm1; -/** Offset 0x04C8 - Idle Energy Ch0Dimm0 +/** Offset 0x04D0 - Idle Energy Ch0Dimm0 Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) **/ UINT8 IdleEnergyCh0Dimm0; -/** Offset 0x04C9 - Idle Energy Ch0Dimm1 +/** Offset 0x04D1 - Idle Energy Ch0Dimm1 Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) **/ UINT8 IdleEnergyCh0Dimm1; -/** Offset 0x04CA - Idle Energy Ch1Dimm0 +/** Offset 0x04D2 - Idle Energy Ch1Dimm0 Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) **/ UINT8 IdleEnergyCh1Dimm0; -/** Offset 0x04CB - Idle Energy Ch1Dimm1 +/** Offset 0x04D3 - Idle Energy Ch1Dimm1 Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) **/ UINT8 IdleEnergyCh1Dimm1; -/** Offset 0x04CC - PowerDown Energy Ch0Dimm0 +/** Offset 0x04D4 - PowerDown Energy Ch0Dimm0 PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def) **/ UINT8 PdEnergyCh0Dimm0; -/** Offset 0x04CD - PowerDown Energy Ch0Dimm1 +/** Offset 0x04D5 - PowerDown Energy Ch0Dimm1 PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def) **/ UINT8 PdEnergyCh0Dimm1; -/** Offset 0x04CE - PowerDown Energy Ch1Dimm0 +/** Offset 0x04D6 - PowerDown Energy Ch1Dimm0 PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def) **/ UINT8 PdEnergyCh1Dimm0; -/** Offset 0x04CF - PowerDown Energy Ch1Dimm1 +/** Offset 0x04D7 - PowerDown Energy Ch1Dimm1 PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def) **/ UINT8 PdEnergyCh1Dimm1; -/** Offset 0x04D0 - Activate Energy Ch0Dimm0 +/** Offset 0x04D8 - Activate Energy Ch0Dimm0 Activate Energy Contribution, range[255;0],(172= Def) **/ UINT8 ActEnergyCh0Dimm0; -/** Offset 0x04D1 - Activate Energy Ch0Dimm1 +/** Offset 0x04D9 - Activate Energy Ch0Dimm1 Activate Energy Contribution, range[255;0],(172= Def) **/ UINT8 ActEnergyCh0Dimm1; -/** Offset 0x04D2 - Activate Energy Ch1Dimm0 +/** Offset 0x04DA - Activate Energy Ch1Dimm0 Activate Energy Contribution, range[255;0],(172= Def) **/ UINT8 ActEnergyCh1Dimm0; -/** Offset 0x04D3 - Activate Energy Ch1Dimm1 +/** Offset 0x04DB - Activate Energy Ch1Dimm1 Activate Energy Contribution, range[255;0],(172= Def) **/ UINT8 ActEnergyCh1Dimm1; -/** Offset 0x04D4 - Read Energy Ch0Dimm0 +/** Offset 0x04DC - Read Energy Ch0Dimm0 Read Energy Contribution, range[255;0],(212= Def) **/ UINT8 RdEnergyCh0Dimm0; -/** Offset 0x04D5 - Read Energy Ch0Dimm1 +/** Offset 0x04DD - Read Energy Ch0Dimm1 Read Energy Contribution, range[255;0],(212= Def) **/ UINT8 RdEnergyCh0Dimm1; -/** Offset 0x04D6 - Read Energy Ch1Dimm0 +/** Offset 0x04DE - Read Energy Ch1Dimm0 Read Energy Contribution, range[255;0],(212= Def) **/ UINT8 RdEnergyCh1Dimm0; -/** Offset 0x04D7 - Read Energy Ch1Dimm1 +/** Offset 0x04DF - Read Energy Ch1Dimm1 Read Energy Contribution, range[255;0],(212= Def) **/ UINT8 RdEnergyCh1Dimm1; -/** Offset 0x04D8 - Write Energy Ch0Dimm0 +/** Offset 0x04E0 - Write Energy Ch0Dimm0 Write Energy Contribution, range[255;0],(221= Def) **/ UINT8 WrEnergyCh0Dimm0; -/** Offset 0x04D9 - Write Energy Ch0Dimm1 +/** Offset 0x04E1 - Write Energy Ch0Dimm1 Write Energy Contribution, range[255;0],(221= Def) **/ UINT8 WrEnergyCh0Dimm1; -/** Offset 0x04DA - Write Energy Ch1Dimm0 +/** Offset 0x04E2 - Write Energy Ch1Dimm0 Write Energy Contribution, range[255;0],(221= Def) **/ UINT8 WrEnergyCh1Dimm0; -/** Offset 0x04DB - Write Energy Ch1Dimm1 +/** Offset 0x04E3 - Write Energy Ch1Dimm1 Write Energy Contribution, range[255;0],(221= Def) **/ UINT8 WrEnergyCh1Dimm1; -/** Offset 0x04DC - Throttler CKEMin Timer +/** Offset 0x04E4 - Throttler CKEMin Timer Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4). Default is 0x30 **/ UINT8 ThrtCkeMinTmr; -/** Offset 0x04DD - Cke Rank Mapping +/** Offset 0x04E5 - Cke Rank Mapping Bits [7:4] - Channel 1, bits [3:0] - Channel 0. 0xAA=Default Bit [i] specifies which rank CKE[i] goes to. **/ UINT8 CkeRankMapping; -/** Offset 0x04DE - Rapl Power Floor Ch0 +/** Offset 0x04E6 - Rapl Power Floor Ch0 Power budget ,range[255;0],(0= 5.3W Def) **/ UINT8 RaplPwrFlCh0; -/** Offset 0x04DF - Rapl Power Floor Ch1 +/** Offset 0x04E7 - Rapl Power Floor Ch1 Power budget ,range[255;0],(0= 5.3W Def) **/ UINT8 RaplPwrFlCh1; -/** Offset 0x04E0 - Command Rate Support +/** Offset 0x04E8 - Command Rate Support CMD Rate and Limit Support Option. NOTE: ONLY supported in 1N Mode, Default is 3 CMDs 0:Disable, 1:1 CMD, 2:2 CMDS, 3:3 CMDS, 4:4 CMDS, 5:5 CMDS, 6:6 CMDS, 7:7 CMDS **/ UINT8 EnCmdRate; -/** Offset 0x04E1 - REFRESH_2X_MODE +/** Offset 0x04E9 - REFRESH_2X_MODE 0- (Default)Disabled 1-iMC enables 2xRef when Warm and Hot 2- iMC enables 2xRef when Hot 0:Disable, 1:Enabled for WARM or HOT, 2:Enabled HOT only **/ UINT8 Refresh2X; -/** Offset 0x04E2 - Energy Performance Gain +/** Offset 0x04EA - Energy Performance Gain Enable/disable(default) Energy Performance Gain. $EN_DIS **/ UINT8 EpgEnable; -/** Offset 0x04E3 - Row Hammer Solution +/** Offset 0x04EB - Row Hammer Solution Type of method used to prevent Row Hammer. Default is Hardware RHP 0:Hardware RHP, 1:2x Refresh **/ UINT8 RhSolution; -/** Offset 0x04E4 - User Manual Threshold +/** Offset 0x04EC - User Manual Threshold Disabled: Predefined threshold will be used.\n Enabled: User Input will be used. $EN_DIS **/ UINT8 UserThresholdEnable; -/** Offset 0x04E5 - User Manual Budget +/** Offset 0x04ED - User Manual Budget Disabled: Configuration of memories will defined the Budget value.\n Enabled: User Input will be used. $EN_DIS **/ UINT8 UserBudgetEnable; -/** Offset 0x04E6 - TcritMax +/** Offset 0x04EE - TcritMax Maximum Critical Temperature in Centigrade of the On-DIMM Thermal Sensor. TCRITMax has to be greater than THIGHMax .\n Critical temperature will be TcritMax **/ UINT8 TsodTcritMax; -/** Offset 0x04E7 - Event mode +/** Offset 0x04EF - Event mode Disable:Comparator mode.\n Enable:Interrupt mode $EN_DIS **/ UINT8 TsodEventMode; -/** Offset 0x04E8 - EVENT polarity +/** Offset 0x04F0 - EVENT polarity Disable:Active LOW.\n Enable:Active HIGH $EN_DIS **/ UINT8 TsodEventPolarity; -/** Offset 0x04E9 - Critical event only +/** Offset 0x04F1 - Critical event only Disable:Trips on alarm or critical.\n Enable:Trips only if criticaal temperature is reached $EN_DIS **/ UINT8 TsodCriticalEventOnly; -/** Offset 0x04EA - Event output control +/** Offset 0x04F2 - Event output control Disable:Event output disable.\n Enable:Event output enabled $EN_DIS **/ UINT8 TsodEventOutputControl; -/** Offset 0x04EB - Alarm window lock bit +/** Offset 0x04F3 - Alarm window lock bit Disable:Alarm trips are not locked and can be changed.\n Enable:Alarm trips are locked and cannot be changed $EN_DIS **/ UINT8 TsodAlarmwindowLockBit; -/** Offset 0x04EC - Critical trip lock bit +/** Offset 0x04F4 - Critical trip lock bit Disable:Critical trip is not locked and can be changed.\n Enable:Critical trip is locked and cannot be changed $EN_DIS **/ UINT8 TsodCriticaltripLockBit; -/** Offset 0x04ED - Shutdown mode +/** Offset 0x04F5 - Shutdown mode Disable:Temperature sensor enable.\n Enable:Temperature sensor disable $EN_DIS **/ UINT8 TsodShutdownMode; -/** Offset 0x04EE - ThighMax +/** Offset 0x04F6 - ThighMax Thigh = ThighMax (Default is 93) **/ UINT8 TsodThigMax; -/** Offset 0x04EF - User Manual Thig and Tcrit +/** Offset 0x04F7 - User Manual Thig and Tcrit Disabled(Default): Temperature will be given by the configuration of memories and 1x or 2xrefresh rate.\n Enabled: User Input will define for Thigh and Tcrit. @@ -2221,32 +2252,32 @@ **/ UINT8 TsodManualEnable; -/** Offset 0x04F0 - Force OLTM or 2X Refresh when needed +/** Offset 0x04F8 - Force OLTM or 2X Refresh when needed Disabled(Default): = Force OLTM.\n Enabled: = Force 2x Refresh. $EN_DIS **/ UINT8 ForceOltmOrRefresh2x; -/** Offset 0x04F1 - Pwr Down Idle Timer +/** Offset 0x04F9 - Pwr Down Idle Timer The minimum value should = to the worst case Roundtrip delay + Burst_Length. 0 means AUTO: 64 for ULX/ULT, 128 for DT/Halo **/ UINT8 PwdwnIdleCounter; -/** Offset 0x04F2 - Bitmask of ranks that have CA bus terminated +/** Offset 0x04FA - Bitmask of ranks that have CA bus terminated Offset 225 LPDDR4: Bitmask of ranks that have CA bus terminated. 0x01=Default, Rank0 is terminating and Rank1 is non-terminating **/ UINT8 CmdRanksTerminated; -/** Offset 0x04F3 - GDXC MOT enable +/** Offset 0x04FB - GDXC MOT enable GDXC MOT enable. $EN_DIS **/ UINT8 GdxcEnable; -/** Offset 0x04F4 - PcdSerialDebugLevel +/** Offset 0x04FC - PcdSerialDebugLevel Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, Info & Verbose. @@ -2255,148 +2286,154 @@ **/ UINT8 PcdSerialDebugLevel; -/** Offset 0x04F5 - Fivr Faults +/** Offset 0x04FD - Fivr Faults Fivr Faults; 0: Disabled; 1: Enabled. $EN_DIS **/ UINT8 FivrFaults; -/** Offset 0x04F6 - Fivr Efficiency +/** Offset 0x04FE - Fivr Efficiency Fivr Efficiency Management; 0: Disabled; 1: Enabled. $EN_DIS **/ UINT8 FivrEfficiency; -/** Offset 0x04F7 - Safe Mode Support +/** Offset 0x04FF - Safe Mode Support This option configures the varous items in the IO and MC to be more conservative.(def=Disable) $EN_DIS **/ UINT8 SafeMode; -/** Offset 0x04F8 - Ask MRC to clear memory content +/** Offset 0x0500 - Ask MRC to clear memory content Ask MRC to clear memory content 0: Do not Clear Memory; 1: Clear Memory. $EN_DIS **/ UINT8 CleanMemory; -/** Offset 0x04F9 - LpDdrDqDqsReTraining +/** Offset 0x0501 - LpDdrDqDqsReTraining Enables/Disable LpDdrDqDqsReTraining $EN_DIS **/ UINT8 LpDdrDqDqsReTraining; -/** Offset 0x04FA - Post Code Output Port +/** Offset 0x0502 - Post Code Output Port This option configures Post Code Output Port **/ UINT16 PostCodeOutputPort; -/** Offset 0x04FC - RMTLoopCount +/** Offset 0x0504 - RMTLoopCount Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO **/ UINT8 RMTLoopCount; -/** Offset 0x04FD - BER Support +/** Offset 0x0505 - BER Support Enable/Disable the Rank Margin Tool interpolation/extrapolation. 0:Disable, 1:Enable **/ UINT8 EnBER; -/** Offset 0x04FE - Dual Dimm Per-Channel Board Type +/** Offset 0x0506 - Dual Dimm Per-Channel Board Type Option to indicate if Board Layout includes One/Two DIMMs per channel. This is used to limit maximum frequency for some SKUs. 0:1DPC, 1:2DPC **/ UINT8 DualDimmPerChannelBoardType; -/** Offset 0x04FF - DDR4 Mixed U-DIMM 2DPC Limitation +/** Offset 0x0507 - DDR4 Mixed U-DIMM 2DPC Limitation Enable/Disable 2667 Frequency Limitation for DDR4 U-DIMM Mixed Dimm 2DPC population. Disable=0, Enable(Default)=1 $EN_DIS **/ UINT8 Ddr4MixedUDimm2DpcLimit; -/** Offset 0x0500 - CFL Reserved +/** Offset 0x0508 - CFL Reserved Reserved FspmConfig CFL $EN_DIS **/ UINT8 ReservedFspmUpdCfl[2]; -/** Offset 0x0502 - Memory Test on Warm Boot +/** Offset 0x050A - Memory Test on Warm Boot Run Base Memory Test on Warm Boot 0:Disable, 1:Enable **/ UINT8 MemTestOnWarmBoot; -/** Offset 0x0503 - Throttler CKEMin Timer - LPDDR +/** Offset 0x050B - Throttler CKEMin Timer - LPDDR Timer value for CKEMin (For LPDDR Only), range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4). Default is 0x40 **/ UINT8 ThrtCkeMinTmrLpddr; -/** Offset 0x0504 - State of X2APIC_OPT_OUT bit in the DMAR table +/** Offset 0x050C - State of X2APIC_OPT_OUT bit in the DMAR table 0=Disable/Clear, 1=Enable/Set $EN_DIS **/ UINT8 X2ApicOptOut; -/** Offset 0x0505 +/** Offset 0x050D - MRC Force training on Warm + Enables/Disable the MRC training on warm boot + $EN_DIS +**/ + UINT8 MrcTrainOnWarm; + +/** Offset 0x050E **/ UINT8 UnusedUpdSpace10[2]; -/** Offset 0x0507 +/** Offset 0x0510 **/ - UINT8 ReservedFspmUpd[9]; + UINT8 ReservedFspmUpd[8]; } FSP_M_CONFIG; /** Fsp M Test Configuration **/ typedef struct { -/** Offset 0x0510 +/** Offset 0x0518 **/ UINT32 Signature; -/** Offset 0x0514 - Skip external display device scanning +/** Offset 0x051C - Skip external display device scanning Enable: Do not scan for external display device, Disable (Default): Scan external display devices $EN_DIS **/ UINT8 SkipExtGfxScan; -/** Offset 0x0515 - Generate BIOS Data ACPI Table +/** Offset 0x051D - Generate BIOS Data ACPI Table Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it $EN_DIS **/ UINT8 BdatEnable; -/** Offset 0x0516 - Detect External Graphics device for LegacyOpROM +/** Offset 0x051E - Detect External Graphics device for LegacyOpROM Detect and report if external graphics device only support LegacyOpROM or not (to support CSM auto-enable). Enable(Default)=1, Disable=0 $EN_DIS **/ UINT8 ScanExtGfxForLegacyOpRom; -/** Offset 0x0517 - Lock PCU Thermal Management registers +/** Offset 0x051F - Lock PCU Thermal Management registers Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0 $EN_DIS **/ UINT8 LockPTMregs; -/** Offset 0x0518 - DMI Max Link Speed +/** Offset 0x0520 - DMI Max Link Speed Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 **/ UINT8 DmiMaxLinkSpeed; -/** Offset 0x0519 - DMI Equalization Phase 2 +/** Offset 0x0521 - DMI Equalization Phase 2 DMI Equalization Phase 2. (0x0): Disable phase 2, (0x1): Enable phase 2, (0x2)(Default): AUTO - Use the current default method 0:Disable phase2, 1:Enable phase2, 2:Auto **/ UINT8 DmiGen3EqPh2Enable; -/** Offset 0x051A - DMI Gen3 Equalization Phase3 +/** Offset 0x0522 - DMI Gen3 Equalization Phase3 DMI Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static @@ -2406,35 +2443,35 @@ **/ UINT8 DmiGen3EqPh3Method; -/** Offset 0x051B - Phase2 EQ enable on the PEG 0:1:0. +/** Offset 0x0523 - Phase2 EQ enable on the PEG 0:1:0. Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): Enable phase 2, Auto(0x2)(Default): Use the current default method 0:Disable, 1:Enable, 2:Auto **/ UINT8 Peg0Gen3EqPh2Enable; -/** Offset 0x051C - Phase2 EQ enable on the PEG 0:1:1. +/** Offset 0x0524 - Phase2 EQ enable on the PEG 0:1:1. Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): Enable phase 2, Auto(0x2)(Default): Use the current default method 0:Disable, 1:Enable, 2:Auto **/ UINT8 Peg1Gen3EqPh2Enable; -/** Offset 0x051D - Phase2 EQ enable on the PEG 0:1:2. +/** Offset 0x0525 - Phase2 EQ enable on the PEG 0:1:2. Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): Enable phase 2, Auto(0x2)(Default): Use the current default method 0:Disable, 1:Enable, 2:Auto **/ UINT8 Peg2Gen3EqPh2Enable; -/** Offset 0x051E - Phase2 EQ enable on the PEG 0:1:3. +/** Offset 0x0526 - Phase2 EQ enable on the PEG 0:1:3. Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): Enable phase 2, Auto(0x2)(Default): Use the current default method 0:Disable, 1:Enable, 2:Auto **/ UINT8 Peg3Gen3EqPh2Enable; -/** Offset 0x051F - Phase3 EQ method on the PEG 0:1:0. +/** Offset 0x0527 - Phase3 EQ method on the PEG 0:1:0. PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static @@ -2444,7 +2481,7 @@ **/ UINT8 Peg0Gen3EqPh3Method; -/** Offset 0x0520 - Phase3 EQ method on the PEG 0:1:1. +/** Offset 0x0528 - Phase3 EQ method on the PEG 0:1:1. PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static @@ -2454,7 +2491,7 @@ **/ UINT8 Peg1Gen3EqPh3Method; -/** Offset 0x0521 - Phase3 EQ method on the PEG 0:1:2. +/** Offset 0x0529 - Phase3 EQ method on the PEG 0:1:2. PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static @@ -2464,7 +2501,7 @@ **/ UINT8 Peg2Gen3EqPh3Method; -/** Offset 0x0522 - Phase3 EQ method on the PEG 0:1:3. +/** Offset 0x052A - Phase3 EQ method on the PEG 0:1:3. PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static @@ -2474,14 +2511,14 @@ **/ UINT8 Peg3Gen3EqPh3Method; -/** Offset 0x0523 - Enable/Disable PEG GEN3 Static EQ Phase1 programming +/** Offset 0x052B - Enable/Disable PEG GEN3 Static EQ Phase1 programming Program PEG Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming $EN_DIS **/ UINT8 PegGen3ProgramStaticEq; -/** Offset 0x0524 - PEG Gen3 SwEq Always Attempt +/** Offset 0x052C - PEG Gen3 SwEq Always Attempt Gen3 Software Equalization will be executed every boot. Disabled(0x0)(Default): Reuse EQ settings saved/restored from NVRAM whenever possible, Enabled(0x1): Re-test and generate new EQ values every boot, not recommended @@ -2489,7 +2526,7 @@ **/ UINT8 Gen3SwEqAlwaysAttempt; -/** Offset 0x0525 - Select number of TxEq presets to test in the PCIe/DMI SwEq +/** Offset 0x052D - Select number of TxEq presets to test in the PCIe/DMI SwEq Select number of TxEq presets to test in the PCIe/DMI SwEq. P7,P3,P5(0x0): Test Presets 7, 3, and 5, P0-P9(0x1): Test Presets 0-9, Auto(0x2)(Default): Use the current default method (Default)Auto will test Presets 7, 3, and 5. It is possible @@ -2499,7 +2536,7 @@ **/ UINT8 Gen3SwEqNumberOfPresets; -/** Offset 0x0526 - Enable use of the Voltage Offset and Centering Test in the PCIe SwEq +/** Offset 0x052E - Enable use of the Voltage Offset and Centering Test in the PCIe SwEq Enable use of the Voltage Offset and Centering Test in the PCIe Software Equalization Algorithm. Disabled(0x0): Disable VOC Test, Enabled(0x1): Enable VOC Test, Auto(0x2)(Default): Use the current default @@ -2507,7 +2544,7 @@ **/ UINT8 Gen3SwEqEnableVocTest; -/** Offset 0x0527 - PCIe Rx Compliance Testing Mode +/** Offset 0x052F - PCIe Rx Compliance Testing Mode Disabled(0x0)(Default): Normal Operation - Disable PCIe Rx Compliance testing, Enabled(0x1): PCIe Rx Compliance Test Mode - PEG controller is in Rx Compliance Testing Mode; it should only be set when doing PCIe compliance testing @@ -2515,12 +2552,12 @@ **/ UINT8 PegRxCemTestingMode; -/** Offset 0x0528 - PCIe Rx Compliance Loopback Lane When PegRxCemTestingMode is Enabled +/** Offset 0x0530 - PCIe Rx Compliance Loopback Lane When PegRxCemTestingMode is Enabled the specificied Lane (0 - 15) will be used for RxCEMLoopback. Default is Lane 0 **/ UINT8 PegRxCemLoopbackLane; -/** Offset 0x0529 - Generate PCIe BDAT Margin Table +/** Offset 0x0531 - Generate PCIe BDAT Margin Table Set this policy to enable the generation and addition of PCIe margin data to the BDAT table. Disabled(0x0)(Default): Normal Operation - Disable PCIe BDAT margin data generation, Enable(0x1): Generate PCIe BDAT margin data @@ -2528,7 +2565,7 @@ **/ UINT8 PegGenerateBdatMarginTable; -/** Offset 0x052A - PCIe Non-Protocol Awareness for Rx Compliance Testing +/** Offset 0x0532 - PCIe Non-Protocol Awareness for Rx Compliance Testing Set this policy to enable the generation and addition of PCIe margin data to the BDAT table. Disabled(0x0)(Default): Normal Operation - Disable non-protocol awareness, Enable(0x1): Non-Protocol Awareness Enabled - Enable non-protocol awareness for @@ -2537,7 +2574,7 @@ **/ UINT8 PegRxCemNonProtocolAwareness; -/** Offset 0x052B - PCIe Override RxCTLE +/** Offset 0x0533 - PCIe Override RxCTLE Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1): Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE peak values unmodified @@ -2545,7 +2582,7 @@ **/ UINT8 PegGen3RxCtleOverride; -/** Offset 0x052C - Rsvd +/** Offset 0x0534 - Rsvd Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1): Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE peak values unmodified @@ -2553,284 +2590,284 @@ **/ UINT8 PegGen3Rsvd; -/** Offset 0x052D - PEG Gen3 Root port preset values per lane +/** Offset 0x0535 - PEG Gen3 Root port preset values per lane Used for programming PEG Gen3 preset values per lane. Range: 0-9, 8 is default for each lane **/ UINT8 PegGen3RootPortPreset[20]; -/** Offset 0x0541 - PEG Gen3 End port preset values per lane +/** Offset 0x0549 - PEG Gen3 End port preset values per lane Used for programming PEG Gen3 preset values per lane. Range: 0-9, 7 is default for each lane **/ UINT8 PegGen3EndPointPreset[20]; -/** Offset 0x0555 - PEG Gen3 End port Hint values per lane +/** Offset 0x055D - PEG Gen3 End port Hint values per lane Used for programming PEG Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane **/ UINT8 PegGen3EndPointHint[20]; -/** Offset 0x0569 +/** Offset 0x0571 **/ UINT8 UnusedUpdSpace11; -/** Offset 0x056A - Jitter Dwell Time for PCIe Gen3 Software Equalization +/** Offset 0x0572 - Jitter Dwell Time for PCIe Gen3 Software Equalization Range: 0-65535, default is 1000. @warning Do not change from the default **/ UINT16 Gen3SwEqJitterDwellTime; -/** Offset 0x056C - Jitter Error Target for PCIe Gen3 Software Equalization +/** Offset 0x0574 - Jitter Error Target for PCIe Gen3 Software Equalization Range: 0-65535, default is 1. @warning Do not change from the default **/ UINT16 Gen3SwEqJitterErrorTarget; -/** Offset 0x056E - VOC Dwell Time for PCIe Gen3 Software Equalization +/** Offset 0x0576 - VOC Dwell Time for PCIe Gen3 Software Equalization Range: 0-65535, default is 10000. @warning Do not change from the default **/ UINT16 Gen3SwEqVocDwellTime; -/** Offset 0x0570 - VOC Error Target for PCIe Gen3 Software Equalization +/** Offset 0x0578 - VOC Error Target for PCIe Gen3 Software Equalization Range: 0-65535, default is 2. @warning Do not change from the default **/ UINT16 Gen3SwEqVocErrorTarget; -/** Offset 0x0572 - Panel Power Enable +/** Offset 0x057A - Panel Power Enable Control for enabling/disabling VDD force bit (Required only for early enabling of eDP panel). 0=Disable, 1(Default)=Enable $EN_DIS **/ UINT8 PanelPowerEnable; -/** Offset 0x0573 - BdatTestType +/** Offset 0x057B - BdatTestType Indicates the type of Memory Training data to populate into the BDAT ACPI table. 0:Rank Margin Tool, 1:Margin2D **/ UINT8 BdatTestType; -/** Offset 0x0574 - Disable VT-d +/** Offset 0x057C - Disable VT-d 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled) $EN_DIS **/ UINT8 VtdDisable; -/** Offset 0x0575 +/** Offset 0x057D **/ UINT8 UnusedUpdSpace12; -/** Offset 0x0576 - Delta T12 Power Cycle Delay required in ms +/** Offset 0x057E - Delta T12 Power Cycle Delay required in ms Select the value for delay required. 0(Default)= No delay, 0xFFFF = Auto calculate T12 Delay to max 500ms 0 : No Delay, 0xFFFF : Auto Calulate T12 Delay **/ UINT16 DeltaT12PowerCycleDelayPreMem; -/** Offset 0x0578 - SaPreMemTestRsvd +/** Offset 0x0580 - SaPreMemTestRsvd Reserved for SA Pre-Mem Test $EN_DIS **/ UINT8 SaPreMemTestRsvd[9]; -/** Offset 0x0581 +/** Offset 0x0589 **/ UINT8 UnusedUpdSpace13; -/** Offset 0x0582 - TotalFlashSize +/** Offset 0x058A - TotalFlashSize Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable **/ UINT16 TotalFlashSize; -/** Offset 0x0584 - BiosSize +/** Offset 0x058C - BiosSize Enable/Disable. 0: Disable, define default value of BiosSize , 1: enable **/ UINT16 BiosSize; -/** Offset 0x0586 - TxtAcheckRequest +/** Offset 0x058E - TxtAcheckRequest Enable/Disable. When Enabled, it will forcing calling TXT Acheck once. $EN_DIS **/ UINT8 TxtAcheckRequest; -/** Offset 0x0587 - SecurityTestRsvd +/** Offset 0x058F - SecurityTestRsvd Reserved for SA Pre-Mem Test $EN_DIS **/ UINT8 SecurityTestRsvd[3]; -/** Offset 0x058A - Smbus dynamic power gating +/** Offset 0x0592 - Smbus dynamic power gating Disable or Enable Smbus dynamic power gating. $EN_DIS **/ UINT8 SmbusDynamicPowerGating; -/** Offset 0x058B - Disable and Lock Watch Dog Register +/** Offset 0x0593 - Disable and Lock Watch Dog Register Set 1 to clear WDT status, then disable and lock WDT registers. $EN_DIS **/ UINT8 WdtDisableAndLock; -/** Offset 0x058C - SMBUS SPD Write Disable +/** Offset 0x0594 - SMBUS SPD Write Disable Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write Disable bit. For security recommendations, SPD write disable bit must be set. $EN_DIS **/ UINT8 SmbusSpdWriteDisable; -/** Offset 0x058D - ReservedPchPreMemTest +/** Offset 0x0595 - ReservedPchPreMemTest Reserved for Pch Pre-Mem Test $EN_DIS **/ UINT8 ReservedPchPreMemTest[16]; -/** Offset 0x059D - Force ME DID Init Status +/** Offset 0x05A5 - Force ME DID Init Status Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set ME DID init stat value $EN_DIS **/ UINT8 DidInitStat; -/** Offset 0x059E - CPU Replaced Polling Disable +/** Offset 0x05A6 - CPU Replaced Polling Disable Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop $EN_DIS **/ UINT8 DisableCpuReplacedPolling; -/** Offset 0x059F - ME DID Message +/** Offset 0x05A7 - ME DID Message Test, 0: disable, 1: enable, Enable/Disable ME DID Message (disable will prevent the DID message from being sent) $EN_DIS **/ UINT8 SendDidMsg; -/** Offset 0x05A0 - Check HECI message before send +/** Offset 0x05A8 - Check HECI message before send Test, 0: disable, 1: enable, Enable/Disable message check. $EN_DIS **/ UINT8 DisableMessageCheck; -/** Offset 0x05A1 - Skip MBP HOB +/** Offset 0x05A9 - Skip MBP HOB Test, 0: disable, 1: enable, Enable/Disable MOB HOB. $EN_DIS **/ UINT8 SkipMbpHob; -/** Offset 0x05A2 - HECI2 Interface Communication +/** Offset 0x05AA - HECI2 Interface Communication Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space. $EN_DIS **/ UINT8 HeciCommunication2; -/** Offset 0x05A3 - Enable KT device +/** Offset 0x05AB - Enable KT device Test, 0: disable, 1: enable, Enable or Disable KT device. $EN_DIS **/ UINT8 KtDeviceEnable; -/** Offset 0x05A4 - tRd2RdSG +/** Offset 0x05AC - tRd2RdSG Delay between Read-to-Read commands in the same Bank Group. 0-Auto, Range 4-54. **/ UINT8 tRd2RdSG; -/** Offset 0x05A5 - tRd2RdDG +/** Offset 0x05AD - tRd2RdDG Delay between Read-to-Read commands in different Bank Group for DDR4. All other DDR technologies should set this equal to SG. 0-Auto, Range 4-54. **/ UINT8 tRd2RdDG; -/** Offset 0x05A6 - tRd2RdDR +/** Offset 0x05AE - tRd2RdDR Delay between Read-to-Read commands in different Ranks. 0-Auto, Range 4-54. **/ UINT8 tRd2RdDR; -/** Offset 0x05A7 - tRd2RdDD +/** Offset 0x05AF - tRd2RdDD Delay between Read-to-Read commands in different DIMMs. 0-Auto, Range 4-54. **/ UINT8 tRd2RdDD; -/** Offset 0x05A8 - tWr2RdSG +/** Offset 0x05B0 - tWr2RdSG Delay between Write-to-Read commands in the same Bank Group. 0-Auto, Range 4-86. **/ UINT8 tWr2RdSG; -/** Offset 0x05A9 - tWr2RdDG +/** Offset 0x05B1 - tWr2RdDG Delay between Write-to-Read commands in different Bank Group for DDR4. All other DDR technologies should set this equal to SG. 0-Auto, Range 4-54. **/ UINT8 tWr2RdDG; -/** Offset 0x05AA - tWr2RdDR +/** Offset 0x05B2 - tWr2RdDR Delay between Write-to-Read commands in different Ranks. 0-Auto, Range 4-54. **/ UINT8 tWr2RdDR; -/** Offset 0x05AB - tWr2RdDD +/** Offset 0x05B3 - tWr2RdDD Delay between Write-to-Read commands in different DIMMs. 0-Auto, Range 4-54. **/ UINT8 tWr2RdDD; -/** Offset 0x05AC - tWr2WrSG +/** Offset 0x05B4 - tWr2WrSG Delay between Write-to-Write commands in the same Bank Group. 0-Auto, Range 4-54. **/ UINT8 tWr2WrSG; -/** Offset 0x05AD - tWr2WrDG +/** Offset 0x05B5 - tWr2WrDG Delay between Write-to-Write commands in different Bank Group for DDR4. All other DDR technologies should set this equal to SG. 0-Auto, Range 4-54. **/ UINT8 tWr2WrDG; -/** Offset 0x05AE - tWr2WrDR +/** Offset 0x05B6 - tWr2WrDR Delay between Write-to-Write commands in different Ranks. 0-Auto, Range 4-54. **/ UINT8 tWr2WrDR; -/** Offset 0x05AF - tWr2WrDD +/** Offset 0x05B7 - tWr2WrDD Delay between Write-to-Write commands in different DIMMs. 0-Auto, Range 4-54. **/ UINT8 tWr2WrDD; -/** Offset 0x05B0 - tRd2WrSG +/** Offset 0x05B8 - tRd2WrSG Delay between Read-to-Write commands in the same Bank Group. 0-Auto, Range 4-54. **/ UINT8 tRd2WrSG; -/** Offset 0x05B1 - tRd2WrDG +/** Offset 0x05B9 - tRd2WrDG Delay between Read-to-Write commands in different Bank Group for DDR4. All other DDR technologies should set this equal to SG. 0-Auto, Range 4-54. **/ UINT8 tRd2WrDG; -/** Offset 0x05B2 - tRd2WrDR +/** Offset 0x05BA - tRd2WrDR Delay between Read-to-Write commands in different Ranks. 0-Auto, Range 4-54. **/ UINT8 tRd2WrDR; -/** Offset 0x05B3 - tRd2WrDD +/** Offset 0x05BB - tRd2WrDD Delay between Read-to-Write commands in different DIMMs. 0-Auto, Range 4-54. **/ UINT8 tRd2WrDD; -/** Offset 0x05B4 - tRRD_L +/** Offset 0x05BC - tRRD_L Min Row Active to Row Active Delay Time for Same Bank Group, DDR4 Only. 0: AUTO, max: 31 **/ UINT8 tRRD_L; -/** Offset 0x05B5 - tRRD_S +/** Offset 0x05BD - tRRD_S Min Row Active to Row Active Delay Time for Different Bank Group, DDR4 Only. 0: AUTO, max: 31 **/ UINT8 tRRD_S; -/** Offset 0x05B6 - tWTR_L +/** Offset 0x05BE - tWTR_L Min Internal Write to Read Command Delay Time for Same Bank Group, DDR4 Only. 0: AUTO, max: 60 **/ UINT8 tWTR_L; -/** Offset 0x05B7 - tWTR_S +/** Offset 0x05BF - tWTR_S Min Internal Write to Read Command Delay Time for Different Bank Group, DDR4 Only. 0: AUTO, max: 28 **/ UINT8 tWTR_S; -/** Offset 0x05B8 +/** Offset 0x05C0 **/ UINT8 ReservedFspmTestUpd[4]; } FSP_M_TEST_CONFIG; @@ -2851,11 +2888,11 @@ **/ FSP_M_CONFIG FspmConfig; -/** Offset 0x0510 +/** Offset 0x0518 **/ FSP_M_TEST_CONFIG FspmTestConfig; -/** Offset 0x05BC +/** Offset 0x05C4 **/ UINT32 UpdTerminator; } FSPM_UPD; diff --git a/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspsUpd.h index c595fd3..4981bb1 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspsUpd.h @@ -139,301 +139,316 @@ **/ UINT8 Heci3Enabled; -/** Offset 0x003B - AMT Switch +/** Offset 0x003B - HECI1 state + Determine if HECI1 is hidden prior to boot to OS. 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 Heci1Disabled; + +/** Offset 0x003C - AMT Switch Enable/Disable. 0: Disable, 1: enable, Enable or disable AMT functionality. $EN_DIS **/ UINT8 AmtEnabled; -/** Offset 0x003C - WatchDog Timer Switch +/** Offset 0x003D - WatchDog Timer Switch Enable/Disable. 0: Disable, 1: enable, Enable or disable WatchDog timer. Setting is invalid if AmtEnabled is 0. $EN_DIS **/ UINT8 WatchDogEnabled; -/** Offset 0x003D - Manageability Mode set by Mebx +/** Offset 0x003E - Manageability Mode set by Mebx Enable/Disable. 0: Disable, 1: enable, Enable or disable Manageability Mode. $EN_DIS **/ UINT8 ManageabilityMode; -/** Offset 0x003E - PET Progress +/** Offset 0x003F - PET Progress Enable/Disable. 0: Disable, 1: enable, Enable/Disable PET Events Progress to receive PET Events. Setting is invalid if AmtEnabled is 0. $EN_DIS **/ UINT8 FwProgress; -/** Offset 0x003F - SOL Switch +/** Offset 0x0040 - SOL Switch Enable/Disable. 0: Disable, 1: enable, Serial Over Lan enable/disable state by Mebx. Setting is invalid if AmtEnabled is 0. $EN_DIS **/ UINT8 AmtSolEnabled; -/** Offset 0x0040 - OS Timer +/** Offset 0x0041 +**/ + UINT8 UnusedUpdSpace1; + +/** Offset 0x0042 - OS Timer 16 bits Value, Set OS watchdog timer. Setting is invalid if AmtEnabled is 0. **/ UINT16 WatchDogTimerOs; -/** Offset 0x0042 - BIOS Timer +/** Offset 0x0044 - BIOS Timer 16 bits Value, Set BIOS watchdog timer. Setting is invalid if AmtEnabled is 0. **/ UINT16 WatchDogTimerBios; -/** Offset 0x0044 - Remote Assistance Trigger Availablilty +/** Offset 0x0046 - Remote Assistance Trigger Availablilty Enable/Disable. 0: Disable, 1: enable, Remote Assistance enable/disable state by Mebx. $EN_DIS **/ UINT8 RemoteAssistance; -/** Offset 0x0045 - KVM Switch +/** Offset 0x0047 - KVM Switch Enable/Disable. 0: Disable, 1: enable, KVM enable/disable state by Mebx. Setting is invalid if AmtEnabled is 0. $EN_DIS **/ UINT8 AmtKvmEnabled; -/** Offset 0x0046 - MEBX execution +/** Offset 0x0048 - MEBX execution Enable/Disable. 0: Disable, 1: enable, Force MEBX execution. $EN_DIS **/ UINT8 ForcMebxSyncUp; -/** Offset 0x0047 - Enable/Disable SA CRID +/** Offset 0x0049 - Enable/Disable SA CRID Enable: SA CRID, Disable (Default): SA CRID $EN_DIS **/ UINT8 CridEnable; -/** Offset 0x0048 - DMI ASPM +/** Offset 0x004A - DMI ASPM 0=Disable, 1:L0s, 2:L1, 3(Default)=L0sL1 0:Disable, 1:L0s, 2:L1, 3:L0sL1 **/ UINT8 DmiAspm; -/** Offset 0x0049 - PCIe DeEmphasis control per root port +/** Offset 0x004B - PCIe DeEmphasis control per root port 0: -6dB, 1(Default): -3.5dB 0:-6dB, 1:-3.5dB **/ UINT8 PegDeEmphasis[4]; -/** Offset 0x004D - PCIe Slot Power Limit value per root port +/** Offset 0x004F - PCIe Slot Power Limit value per root port Slot power limit value per root port **/ UINT8 PegSlotPowerLimitValue[4]; -/** Offset 0x0051 - PCIe Slot Power Limit scale per root port +/** Offset 0x0053 - PCIe Slot Power Limit scale per root port Slot power limit scale per root port 0:1.0x, 1:0.1x, 2:0.01x, 3:0x001x **/ UINT8 PegSlotPowerLimitScale[4]; -/** Offset 0x0055 +/** Offset 0x0057 **/ - UINT8 UnusedUpdSpace1[1]; + UINT8 UnusedUpdSpace2[1]; -/** Offset 0x0056 - PCIe Physical Slot Number per root port +/** Offset 0x0058 - PCIe Physical Slot Number per root port Physical Slot Number per root port **/ UINT16 PegPhysicalSlotNumber[4]; -/** Offset 0x005E - Enable/Disable PavpEnable +/** Offset 0x0060 - Enable/Disable PavpEnable Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable $EN_DIS **/ UINT8 PavpEnable; -/** Offset 0x005F - CdClock Frequency selection +/** Offset 0x0061 - CdClock Frequency selection 0=337.5 Mhz, 1=450 Mhz, 2=540 Mhz, 3(Default)=675 Mhz 0: 337.5 Mhz, 1: 450 Mhz, 2: 540 Mhz, 3: 675 Mhz **/ UINT8 CdClock; -/** Offset 0x0060 - Enable/Disable PeiGraphicsPeimInit +/** Offset 0x0062 - Enable/Disable PeiGraphicsPeimInit Enable: Enable PeiGraphicsPeimInit, Disable(Default): Disable PeiGraphicsPeimInit $EN_DIS **/ UINT8 PeiGraphicsPeimInit; -/** Offset 0x0061 - Enable or disable GNA device +/** Offset 0x0063 - Enable or disable GNA device 0=Disable, 1(Default)=Enable $EN_DIS **/ UINT8 GnaEnable; -/** Offset 0x0062 - State of X2APIC_OPT_OUT bit in the DMAR table +/** Offset 0x0064 - State of X2APIC_OPT_OUT bit in the DMAR table 0=Disable/Clear, 1=Enable/Set $EN_DIS **/ UINT8 X2ApicOptOutDeprecated; -/** Offset 0x0063 +/** Offset 0x0065 **/ - UINT8 UnusedUpdSpace2[1]; + UINT8 UnusedUpdSpace3[3]; -/** Offset 0x0064 - Base addresses for VT-d function MMIO access +/** Offset 0x0068 - Base addresses for VT-d function MMIO access Base addresses for VT-d MMIO access per VT-d engine **/ UINT32 VtdBaseAddressDeprecated[3]; -/** Offset 0x0070 - Enable or disable eDP device +/** Offset 0x0074 - Enable or disable eDP device 0=Disable, 1(Default)=Enable $EN_DIS **/ UINT8 DdiPortEdp; -/** Offset 0x0071 - Enable or disable HPD of DDI port B +/** Offset 0x0075 - Enable or disable HPD of DDI port B 0=Disable, 1(Default)=Enable $EN_DIS **/ UINT8 DdiPortBHpd; -/** Offset 0x0072 - Enable or disable HPD of DDI port C +/** Offset 0x0076 - Enable or disable HPD of DDI port C 0=Disable, 1(Default)=Enable $EN_DIS **/ UINT8 DdiPortCHpd; -/** Offset 0x0073 - Enable or disable HPD of DDI port D +/** Offset 0x0077 - Enable or disable HPD of DDI port D 0=Disable, 1(Default)=Enable $EN_DIS **/ UINT8 DdiPortDHpd; -/** Offset 0x0074 - Enable or disable HPD of DDI port F +/** Offset 0x0078 - Enable or disable HPD of DDI port F 0=Disable, 1(Default)=Enable $EN_DIS **/ UINT8 DdiPortFHpd; -/** Offset 0x0075 - Enable or disable DDC of DDI port B +/** Offset 0x0079 - Enable or disable DDC of DDI port B 0=Disable, 1(Default)=Enable $EN_DIS **/ UINT8 DdiPortBDdc; -/** Offset 0x0076 - Enable or disable DDC of DDI port C +/** Offset 0x007A - Enable or disable DDC of DDI port C 0=Disable, 1(Default)=Enable $EN_DIS **/ UINT8 DdiPortCDdc; -/** Offset 0x0077 - Enable or disable DDC of DDI port D +/** Offset 0x007B - Enable or disable DDC of DDI port D 0=Disable, 1(Default)=Enable $EN_DIS **/ UINT8 DdiPortDDdc; -/** Offset 0x0078 - Enable or disable DDC of DDI port F +/** Offset 0x007C - Enable or disable DDC of DDI port F 0(Default)=Disable, 1=Enable $EN_DIS **/ UINT8 DdiPortFDdc; -/** Offset 0x0079 - Enable/Disable SkipS3CdClockInit +/** Offset 0x007D - Enable/Disable SkipS3CdClockInit Enable: Skip Full CD clock initializaton, Disable(Default): Initialize the full CD clock in S3 resume due to GOP absent $EN_DIS **/ UINT8 SkipS3CdClockInit; -/** Offset 0x007A - Delta T12 Power Cycle Delay required in ms +/** Offset 0x007E - Delta T12 Power Cycle Delay required in ms DEPRECATED 0 : No Delay, 0xFFFF : Auto Calulate T12 Delay **/ UINT16 DeltaT12PowerCycleDelay; -/** Offset 0x007C - Blt Buffer Address +/** Offset 0x0080 - Blt Buffer Address Address of Blt buffer **/ UINT32 BltBufferAddress; -/** Offset 0x0080 - Blt Buffer Size +/** Offset 0x0084 - Blt Buffer Size Size of Blt Buffer, is equal to PixelWidth * PixelHeight * 4 bytes (the size of EFI_GRAPHICS_OUTPUT_BLT_PIXEL) **/ UINT32 BltBufferSize; -/** Offset 0x0084 - SaPostMemProductionRsvd +/** Offset 0x0088 - Program GT Chicken bits + Progarm the GT chicken bits in GTTMMADR + 0xD00 BITS [3:1] +**/ + UINT8 ProgramGtChickenBits; + +/** Offset 0x0089 - SaPostMemProductionRsvd Reserved for SA Post-Mem Production $EN_DIS **/ - UINT8 SaPostMemProductionRsvd[35]; + UINT8 SaPostMemProductionRsvd[34]; -/** Offset 0x00A7 - PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable +/** Offset 0x00AB - PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable Workaround needed for Alpine ridge **/ UINT8 PcieRootPortGen2PllL1CgDisable[24]; -/** Offset 0x00BF - Advanced Encryption Standard (AES) feature +/** Offset 0x00C3 - Advanced Encryption Standard (AES) feature Enable or Disable Advanced Encryption Standard (AES) feature; 0: Disable; 1: Enable $EN_DIS **/ UINT8 AesEnable; -/** Offset 0x00C0 - Power State 3 enable/disable +/** Offset 0x00C4 - Power State 3 enable/disable PCODE MMIO Mailbox: Power State 3 enable/disable; 0: Disable; 1: Enable. For all VR Indexes **/ UINT8 Psi3Enable[5]; -/** Offset 0x00C5 - Power State 4 enable/disable +/** Offset 0x00C9 - Power State 4 enable/disable PCODE MMIO Mailbox: Power State 4 enable/disable; 0: Disable; 1: Enable.For all VR Indexes **/ UINT8 Psi4Enable[5]; -/** Offset 0x00CA - Imon slope correction +/** Offset 0x00CE - Imon slope correction PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values. Range is 0-200. 125 = 1.25. 0: Auto.For all VR Indexes **/ UINT8 ImonSlope[5]; -/** Offset 0x00CF - Imon offset correction +/** Offset 0x00D3 - Imon offset correction DEPRECATED **/ UINT8 ImonOffset[5]; -/** Offset 0x00D4 - Enable/Disable BIOS configuration of VR +/** Offset 0x00D8 - Enable/Disable BIOS configuration of VR Enable/Disable BIOS configuration of VR; 0: Disable; 1: Enable.For all VR Indexes **/ UINT8 VrConfigEnable[5]; -/** Offset 0x00D9 - Thermal Design Current enable/disable +/** Offset 0x00DD - Thermal Design Current enable/disable PCODE MMIO Mailbox: Thermal Design Current enable/disable; 0: Disable; 1: Enable.For all VR Indexes **/ UINT8 TdcEnable[5]; -/** Offset 0x00DE - HECI3 state +/** Offset 0x00E2 - HECI3 state PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds. Valid Values 1 - 1ms , 2 - 2ms , 3 - 3ms , 4 - 4ms , 5 - 5ms , 6 - 6ms , 7 - 7ms , 8 - 8ms , 10 - 10ms.For all VR Indexe **/ UINT8 TdcTimeWindow[5]; -/** Offset 0x00E3 - Thermal Design Current Lock +/** Offset 0x00E7 - Thermal Design Current Lock PCODE MMIO Mailbox: Thermal Design Current Lock; 0: Disable; 1: Enable.For all VR Indexes **/ UINT8 TdcLock[5]; -/** Offset 0x00E8 - Platform Psys slope correction +/** Offset 0x00EC - Platform Psys slope correction PCODE MMIO Mailbox: Platform Psys slope correction. 0 - Auto Specified in 1/100 increment values. Range is 0-200. 125 = 1.25 **/ UINT8 PsysSlope; -/** Offset 0x00E9 - Platform Psys offset correction +/** Offset 0x00ED - Platform Psys offset correction PCODE MMIO Mailbox: Platform Psys offset correction. 0 - Auto Units 1/4, Range 0-255. Value of 100 = 100/4 = 25 offset **/ UINT8 PsysOffset; -/** Offset 0x00EA - Acoustic Noise Mitigation feature +/** Offset 0x00EE - Acoustic Noise Mitigation feature Enable or Disable Acoustic Noise Mitigation feature. This has to be enabled to program slew rate configuration for all VR domains, Pre Wake, Ramp Up and, Ramp Down times.0: Disabled; 1: Enabled @@ -441,96 +456,96 @@ **/ UINT8 AcousticNoiseMitigation; -/** Offset 0x00EB - Disable Fast Slew Rate for Deep Package C States for VR IA domain +/** Offset 0x00EF - Disable Fast Slew Rate for Deep Package C States for VR IA domain Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled. 0: False; 1: True $EN_DIS **/ UINT8 FastPkgCRampDisableIa; -/** Offset 0x00EC - Slew Rate configuration for Deep Package C States for VR IA domain +/** Offset 0x00F0 - Slew Rate configuration for Deep Package C States for VR IA domain Slew Rate configuration for Deep Package C States for VR IA domain based on Acoustic Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16 **/ UINT8 SlowSlewRateForIa; -/** Offset 0x00ED - Slew Rate configuration for Deep Package C States for VR GT domain +/** Offset 0x00F1 - Slew Rate configuration for Deep Package C States for VR GT domain Slew Rate configuration for Deep Package C States for VR GT domain based on Acoustic Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16 **/ UINT8 SlowSlewRateForGt; -/** Offset 0x00EE - Slew Rate configuration for Deep Package C States for VR SA domain +/** Offset 0x00F2 - Slew Rate configuration for Deep Package C States for VR SA domain Slew Rate configuration for Deep Package C States for VR SA domain based on Acoustic Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16 **/ UINT8 SlowSlewRateForSa; -/** Offset 0x00EF +/** Offset 0x00F3 **/ - UINT8 UnusedUpdSpace3[1]; + UINT8 UnusedUpdSpace4[1]; -/** Offset 0x00F0 - Thermal Design Current current limit +/** Offset 0x00F4 - Thermal Design Current current limit PCODE MMIO Mailbox: Thermal Design Current current limit. Specified in 1/8A units. Range is 0-4095. 1000 = 125A. 0: Auto. For all VR Indexes **/ UINT16 TdcPowerLimit[5]; -/** Offset 0x00FA - AcLoadline +/** Offset 0x00FE - AcLoadline PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is 0-6249. Intel Recommended Defaults vary by domain and SKU. **/ UINT16 AcLoadline[5]; -/** Offset 0x0104 - DcLoadline +/** Offset 0x0108 - DcLoadline PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is 0-6249.Intel Recommended Defaults vary by domain and SKU. **/ UINT16 DcLoadline[5]; -/** Offset 0x010E - Power State 1 Threshold current +/** Offset 0x0112 - Power State 1 Threshold current PCODE MMIO Mailbox: Power State 1 current cuttof in 1/4 Amp increments. Range is 0-128A. **/ UINT16 Psi1Threshold[5]; -/** Offset 0x0118 - Power State 2 Threshold current +/** Offset 0x011C - Power State 2 Threshold current PCODE MMIO Mailbox: Power State 2 current cuttof in 1/4 Amp increments. Range is 0-128A. **/ UINT16 Psi2Threshold[5]; -/** Offset 0x0122 - Power State 3 Threshold current +/** Offset 0x0126 - Power State 3 Threshold current PCODE MMIO Mailbox: Power State 3 current cuttof in 1/4 Amp increments. Range is 0-128A. **/ UINT16 Psi3Threshold[5]; -/** Offset 0x012C - Icc Max limit +/** Offset 0x0130 - Icc Max limit PCODE MMIO Mailbox: VR Icc Max limit. 0-255A in 1/4 A units. 400 = 100A **/ UINT16 IccMax[5]; -/** Offset 0x0136 - VR Voltage Limit +/** Offset 0x013A - VR Voltage Limit PCODE MMIO Mailbox: VR Voltage Limit. Range is 0-7999mV. **/ UINT16 VrVoltageLimit[5]; -/** Offset 0x0140 - Disable Fast Slew Rate for Deep Package C States for VR GT domain +/** Offset 0x0144 - Disable Fast Slew Rate for Deep Package C States for VR GT domain Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled. 0: False; 1: True $EN_DIS **/ UINT8 FastPkgCRampDisableGt; -/** Offset 0x0141 - Disable Fast Slew Rate for Deep Package C States for VR SA domain +/** Offset 0x0145 - Disable Fast Slew Rate for Deep Package C States for VR SA domain Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled. 0: False; 1: True $EN_DIS **/ UINT8 FastPkgCRampDisableSa; -/** Offset 0x0142 - Enable VR specific mailbox command +/** Offset 0x0146 - Enable VR specific mailbox command VR specific mailbox commands. 00b - no VR specific command sent. 01b - A VR mailbox command specifically for the MPS IMPV8 VR will be sent. 10b - VR specific command sent for PS4 exit issue. 11b - Reserved. @@ -538,209 +553,209 @@ **/ UINT8 SendVrMbxCmd; -/** Offset 0x0143 - Reserved +/** Offset 0x0147 - Reserved Reserved **/ UINT8 Reserved2; -/** Offset 0x0144 - Enable or Disable TXT +/** Offset 0x0148 - Enable or Disable TXT Enable or Disable TXT; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 TxtEnable; -/** Offset 0x0145 - Deprecated DO NOT USE Skip Multi-Processor Initialization +/** Offset 0x0149 - Deprecated DO NOT USE Skip Multi-Processor Initialization @deprecated SkipMpInit has been moved to FspmUpd $EN_DIS **/ UINT8 SkipMpInitDeprecated; -/** Offset 0x0146 - McIVR RFI Frequency Prefix +/** Offset 0x014A - McIVR RFI Frequency Prefix PCODE MMIO Mailbox: McIVR RFI Frequency Adjustment Prefix. 0: Plus (+); 1: Minus (-). **/ UINT8 McivrRfiFrequencyPrefix; -/** Offset 0x0147 - McIVR RFI Frequency Adjustment +/** Offset 0x014B - McIVR RFI Frequency Adjustment PCODE MMIO Mailbox: Adjust the RFI frequency relative to the nominal frequency in increments of 100KHz. For subtraction, change McivrRfiFrequencyPrefix. 0: Auto. **/ UINT8 McivrRfiFrequencyAdjust; -/** Offset 0x0148 - FIVR RFI Frequency +/** Offset 0x014C - FIVR RFI Frequency PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz. 0: Auto. Range varies based on XTAL clock: 0-1918 (Up to 191.8HMz) for 24MHz clock; 0-1535 (Up to 153.5MHz) for 19MHz clock. **/ UINT16 FivrRfiFrequency; -/** Offset 0x014A - McIVR RFI Spread Spectrum +/** Offset 0x014E - McIVR RFI Spread Spectrum PCODE MMIO Mailbox: McIVR RFI Spread Spectrum. 0: 0%; 1: +/- 0.5%; 2: +/- 1%; 3: +/- 1.5%; 4: +/- 2%; 5: +/- 3%; 6: +/- 4%; 7: +/- 5%; 8: +/- 6%. **/ UINT8 McivrSpreadSpectrum; -/** Offset 0x014B - FIVR RFI Spread Spectrum +/** Offset 0x014F - FIVR RFI Spread Spectrum PCODE MMIO Mailbox: FIVR RFI Spread Spectrum, in 0.1% increments. 0: 0%; Range: 0.0% to 10.0% (0-100). **/ UINT8 FivrSpreadSpectrum; -/** Offset 0x014C - Disable Fast Slew Rate for Deep Package C States for VR FIVR domain +/** Offset 0x0150 - Disable Fast Slew Rate for Deep Package C States for VR FIVR domain Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled. 0: False; 1: True $EN_DIS **/ UINT8 FastPkgCRampDisableFivr; -/** Offset 0x014D - Slew Rate configuration for Deep Package C States for VR FIVR domain +/** Offset 0x0151 - Slew Rate configuration for Deep Package C States for VR FIVR domain Slew Rate configuration for Deep Package C States for VR FIVR domain based on Acoustic Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16 **/ UINT8 SlowSlewRateForFivr; -/** Offset 0x014E +/** Offset 0x0152 **/ - UINT8 UnusedUpdSpace4[2]; + UINT8 UnusedUpdSpace5[2]; -/** Offset 0x0150 - CpuBistData +/** Offset 0x0154 - CpuBistData Pointer CPU BIST Data **/ UINT32 CpuBistData; -/** Offset 0x0154 - Activates VR mailbox command for Intersil VR C-state issues. +/** Offset 0x0158 - Activates VR mailbox command for Intersil VR C-state issues. Intersil VR mailbox command. 0 - no mailbox command sent. 1 - VR mailbox command sent for IA/GT rails only. 2 - VR mailbox command sent for IA/GT/SA rails. **/ UINT8 IslVrCmd; -/** Offset 0x0155 +/** Offset 0x0159 **/ - UINT8 UnusedUpdSpace5[1]; + UINT8 UnusedUpdSpace6[1]; -/** Offset 0x0156 - Imon slope1 correction +/** Offset 0x015A - Imon slope1 correction PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values. Range is 0-200. 125 = 1.25. 0: Auto.For all VR Indexes **/ UINT16 ImonSlope1[5]; -/** Offset 0x0160 - CPU VR Power Delivery Design +/** Offset 0x0164 - CPU VR Power Delivery Design Used to communicate the power delivery design capability of the board. This value is an enum of the available power delivery segments that are defined in the Platform Design Guide. **/ UINT32 VrPowerDeliveryDesign; -/** Offset 0x0164 - Pre Wake Randomization time +/** Offset 0x0168 - Pre Wake Randomization time PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum pre-wake randomization time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled. Range 0-255 0. **/ UINT8 PreWake; -/** Offset 0x0165 - Ramp Up Randomization time +/** Offset 0x0169 - Ramp Up Randomization time PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum Ramp Up randomization time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled.Range 0-255 0. **/ UINT8 RampUp; -/** Offset 0x0166 - Ramp Down Randomization time +/** Offset 0x016A - Ramp Down Randomization time PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum Ramp Down randomization time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled.Range 0-255 0. **/ UINT8 RampDown; -/** Offset 0x0167 +/** Offset 0x016B **/ - UINT8 UnusedUpdSpace6; + UINT8 UnusedUpdSpace7; -/** Offset 0x0168 - CpuMpPpi +/** Offset 0x016C - CpuMpPpi Pointer for CpuMpPpi **/ UINT32 CpuMpPpi; -/** Offset 0x016C - CpuMpHob +/** Offset 0x0170 - CpuMpHob Pointer for CpuMpHob. This is optional data buffer for CpuMpPpi usage. **/ UINT32 CpuMpHob; -/** Offset 0x0170 - Enable or Disable processor debug features +/** Offset 0x0174 - Enable or Disable processor debug features Enable or Disable processor debug features; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 DebugInterfaceEnable; -/** Offset 0x0171 +/** Offset 0x0175 **/ - UINT8 UnusedUpdSpace7[1]; + UINT8 UnusedUpdSpace8[1]; -/** Offset 0x0172 - Imon offset 1 correction +/** Offset 0x0176 - Imon offset 1 correction PCODE MMIO Mailbox: Imon offset correction. Value is a 2's complement signed integer. Units 1/1000, Range 0-63999. For an offset = 12.580, use 12580. 0: Auto **/ UINT16 ImonOffset1[5]; -/** Offset 0x017C - ReservedCpuPostMemProduction +/** Offset 0x0180 - ReservedCpuPostMemProduction Reserved for CPU Post-Mem Production $EN_DIS **/ UINT8 ReservedCpuPostMemProduction[8]; -/** Offset 0x0184 - Enable HD Audio DSP +/** Offset 0x0188 - Enable HD Audio DSP Enable/disable HD Audio DSP feature. $EN_DIS **/ UINT8 PchHdaDspEnable; -/** Offset 0x0185 - SPI0 Chip Select Polarity +/** Offset 0x0189 - SPI0 Chip Select Polarity Sets polarity for each chip Select. Available options: 0:PchSerialIoCsActiveLow, 1:PchSerialIoCsActiveHigh **/ UINT8 SerialIoSpi0CsPolarity[2]; -/** Offset 0x0187 - SPI1 Chip Select Polarity +/** Offset 0x018B - SPI1 Chip Select Polarity Sets polarity for each chip Select. Available options: 0:PchSerialIoCsActiveLow, 1:PchSerialIoCsActiveHigh **/ UINT8 SerialIoSpi1CsPolarity[2]; -/** Offset 0x0189 - SPI2 Chip Select Polarity +/** Offset 0x018D - SPI2 Chip Select Polarity Sets polarity for each chip Select. Available options: 0:PchSerialIoCsActiveLow, 1:PchSerialIoCsActiveHigh **/ UINT8 SerialIoSpi2CsPolarity[2]; -/** Offset 0x018B - SPI0 Chip Select Enable +/** Offset 0x018F - SPI0 Chip Select Enable 0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled **/ UINT8 SerialIoSpi0CsEnable[2]; -/** Offset 0x018D - SPI1 Chip Select Enable +/** Offset 0x0191 - SPI1 Chip Select Enable 0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled **/ UINT8 SerialIoSpi1CsEnable[2]; -/** Offset 0x018F - SPI2 Chip Select Enable +/** Offset 0x0193 - SPI2 Chip Select Enable 0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled **/ UINT8 SerialIoSpi2CsEnable[2]; -/** Offset 0x0191 - SPIn Device Mode +/** Offset 0x0195 - SPIn Device Mode Selects SPI operation mode. N represents controller index: SPI0, SPI1, ... Available modes: 0:SerialIoSpiDisabled, 1:SerialIoSpiPci, 2:SerialIoSpiHidden **/ UINT8 SerialIoSpiMode[3]; -/** Offset 0x0194 - SPIn Default Chip Select Output +/** Offset 0x0198 - SPIn Default Chip Select Output Sets Default CS as Output. N represents controller index: SPI0, SPI1, ... Available options: 0:CS0, 1:CS1 **/ UINT8 SerialIoSpiDefaultCsOutput[3]; -/** Offset 0x0197 - PCH SerialIo I2C Pads Termination +/** Offset 0x019B - PCH SerialIo I2C Pads Termination 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5 pads termination respectively. One byte for each controller, byte0 for I2C0, byte1 @@ -748,1036 +763,1035 @@ **/ UINT8 PchSerialIoI2cPadsTermination[6]; -/** Offset 0x019D - I2Cn Device Mode +/** Offset 0x01A1 - I2Cn Device Mode Selects I2c operation mode. N represents controller index: I2c0, I2c1, ... Available modes: 0:SerialIoI2cDisabled, 1:SerialIoI2cPci, 2:SerialIoI2cHidden **/ UINT8 SerialIoI2cMode[6]; -/** Offset 0x01A3 - UARTn Device Mode +/** Offset 0x01A7 - UARTn Device Mode Selects Uart operation mode. N represents controller index: Uart0, Uart1, ... Available modes: 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, 4:SerialIoUartSkipInit **/ UINT8 SerialIoUartMode[3]; -/** Offset 0x01A6 +/** Offset 0x01AA **/ - UINT8 UnusedUpdSpace8[2]; + UINT8 UnusedUpdSpace9[2]; -/** Offset 0x01A8 - Default BaudRate for each Serial IO UART +/** Offset 0x01AC - Default BaudRate for each Serial IO UART Set default BaudRate Supported from 0 - default to 6000000 **/ UINT32 SerialIoUartBaudRate[3]; -/** Offset 0x01B4 - Default ParityType for each Serial IO UART +/** Offset 0x01B8 - Default ParityType for each Serial IO UART Set default Parity. 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity **/ UINT8 SerialIoUartParity[3]; -/** Offset 0x01B7 - Default DataBits for each Serial IO UART +/** Offset 0x01BB - Default DataBits for each Serial IO UART Set default word length. 0: Default, 5,6,7,8 **/ UINT8 SerialIoUartDataBits[3]; -/** Offset 0x01BA - Default StopBits for each Serial IO UART +/** Offset 0x01BE - Default StopBits for each Serial IO UART Set default stop bits. 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits **/ UINT8 SerialIoUartStopBits[3]; -/** Offset 0x01BD - Power Gating mode for each Serial IO UART that works in COM mode +/** Offset 0x01C1 - Power Gating mode for each Serial IO UART that works in COM mode Set Power Gating. 0: Disabled, 1: Enabled, 2: Auto **/ UINT8 SerialIoUartPowerGating[3]; -/** Offset 0x01C0 - Enable Dma for each Serial IO UART that supports it +/** Offset 0x01C4 - Enable Dma for each Serial IO UART that supports it Set DMA/PIO mode. 0: Disabled, 1: Enabled **/ UINT8 SerialIoUartDmaEnable[3]; -/** Offset 0x01C3 - Enables UART hardware flow control, CTS and RTS lines +/** Offset 0x01C7 - Enables UART hardware flow control, CTS and RTS lines Enables UART hardware flow control, CTS and RTS lines. **/ UINT8 SerialIoUartAutoFlow[3]; -/** Offset 0x01C6 +/** Offset 0x01CA - Serial IO UART Pin Mux + Applies only to UART0 muxed with CNVI 0 = GPIO C8 to C11 1 = GPIO F5 - + F7 (PCH LP) J5 - J7 (PCH H) **/ - UINT8 UnusedUpdSpace9[2]; + UINT8 SerialIoUartPinMux[3]; -/** Offset 0x01C8 - SerialIoUartRxPinMux - Select SerialIo Uart Rx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RX* for - possible values. -**/ - UINT32 SerialIoUartRxPinMux[3]; - -/** Offset 0x01D4 - SerialIoUartTxPinMux - Select SerialIo Uart Tx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_TX* for - possible values. -**/ - UINT32 SerialIoUartTxPinMux[3]; - -/** Offset 0x01E0 - SerialIoUartRtsPinMux - Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS* - for possible values. -**/ - UINT32 SerialIoUartRtsPinMux[3]; - -/** Offset 0x01EC - SerialIoUartCtsPinMux - Select SerialIo Uart Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS* - for possible values. -**/ - UINT32 SerialIoUartCtsPinMux[3]; - -/** Offset 0x01F8 - UART Number For Debug Purpose +/** Offset 0x01CD - UART Number For Debug Purpose UART number for debug purpose. 0:UART0, 1: UART1, 2:UART2. Note: If UART0 is selected as CNVi BT Core interface, it cannot be used for debug purpose. 0:UART0, 1:UART1, 2:UART2 **/ UINT8 SerialIoDebugUartNumber; -/** Offset 0x01F9 - Serial IO UART DBG2 table +/** Offset 0x01CE - Serial IO UART DBG2 table Enable or disable Serial Io UART DBG2 table, default is Disable; 0: Disable; 1: Enable. **/ UINT8 SerialIoUartDbg2[3]; -/** Offset 0x01FC - Enable eMMC Controller +/** Offset 0x01D1 - Enable eMMC Controller Enable/disable eMMC Controller. $EN_DIS **/ UINT8 ScsEmmcEnabled; -/** Offset 0x01FD - Enable eMMC HS400 Mode +/** Offset 0x01D2 - Enable eMMC HS400 Mode Enable eMMC HS400 Mode. $EN_DIS **/ UINT8 ScsEmmcHs400Enabled; -/** Offset 0x01FE - Enable SdCard Controller +/** Offset 0x01D3 - Enable SdCard Controller Enable/disable SD Card Controller. $EN_DIS **/ UINT8 ScsSdCardEnabled; -/** Offset 0x01FF - Show SPI controller +/** Offset 0x01D4 - Show SPI controller Enable/disable to show SPI controller. $EN_DIS **/ UINT8 ShowSpiController; -/** Offset 0x0200 - Enable SATA SALP Support +/** Offset 0x01D5 - Enable SATA SALP Support Enable/disable SATA Aggressive Link Power Management. $EN_DIS **/ UINT8 SataSalpSupport; -/** Offset 0x0201 - Enable SATA ports +/** Offset 0x01D6 - Enable SATA ports Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. **/ UINT8 SataPortsEnable[8]; -/** Offset 0x0209 - Enable SATA DEVSLP Feature +/** Offset 0x01DE - Enable SATA DEVSLP Feature Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each port, byte0 for port0, byte1 for port1, and so on. **/ UINT8 SataPortsDevSlp[8]; -/** Offset 0x0211 - Enable USB2 ports +/** Offset 0x01E6 - Enable USB2 ports Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. **/ UINT8 PortUsb20Enable[16]; -/** Offset 0x0221 - Enable USB3 ports +/** Offset 0x01F6 - Enable USB3 ports Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. **/ UINT8 PortUsb30Enable[10]; -/** Offset 0x022B - Enable xDCI controller +/** Offset 0x0200 - Enable xDCI controller Enable/disable to xDCI controller. $EN_DIS **/ UINT8 XdciEnable; -/** Offset 0x022C - Address of PCH_DEVICE_INTERRUPT_CONFIG table. +/** Offset 0x0201 +**/ + UINT8 UnusedUpdSpace10[3]; + +/** Offset 0x0204 - Address of PCH_DEVICE_INTERRUPT_CONFIG table. The address of the table of PCH_DEVICE_INTERRUPT_CONFIG. **/ UINT32 DevIntConfigPtr; -/** Offset 0x0230 - Number of DevIntConfig Entry +/** Offset 0x0208 - Number of DevIntConfig Entry Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr must not be NULL. **/ UINT8 NumOfDevIntConfig; -/** Offset 0x0231 - PIRQx to IRQx Map Config +/** Offset 0x0209 - PIRQx to IRQx Map Config PIRQx to IRQx mapping. The valid value is 0x00 to 0x0F for each. First byte is for PIRQA, second byte is for PIRQB, and so on. The setting is only available in Legacy 8259 PCI mode. **/ UINT8 PxRcConfig[8]; -/** Offset 0x0239 - Select GPIO IRQ Route +/** Offset 0x0211 - Select GPIO IRQ Route GPIO IRQ Select. The valid value is 14 or 15. **/ UINT8 GpioIrqRoute; -/** Offset 0x023A - Select SciIrqSelect +/** Offset 0x0212 - Select SciIrqSelect SCI IRQ Select. The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only. **/ UINT8 SciIrqSelect; -/** Offset 0x023B - Select TcoIrqSelect +/** Offset 0x0213 - Select TcoIrqSelect TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23. **/ UINT8 TcoIrqSelect; -/** Offset 0x023C - Enable/Disable Tco IRQ +/** Offset 0x0214 - Enable/Disable Tco IRQ Enable/disable TCO IRQ $EN_DIS **/ UINT8 TcoIrqEnable; -/** Offset 0x023D - PCH HDA Verb Table Entry Number +/** Offset 0x0215 - PCH HDA Verb Table Entry Number Number of Entries in Verb Table. **/ UINT8 PchHdaVerbTableEntryNum; -/** Offset 0x023E +/** Offset 0x0216 **/ - UINT8 UnusedUpdSpace10[2]; + UINT8 UnusedUpdSpace11[2]; -/** Offset 0x0240 - PCH HDA Verb Table Pointer +/** Offset 0x0218 - PCH HDA Verb Table Pointer Pointer to Array of pointers to Verb Table. **/ UINT32 PchHdaVerbTablePtr; -/** Offset 0x0244 - PCH HDA Codec Sx Wake Capability +/** Offset 0x021C - PCH HDA Codec Sx Wake Capability Capability to detect wake initiated by a codec in Sx **/ UINT8 PchHdaCodecSxWakeCapability; -/** Offset 0x0245 - Enable SATA +/** Offset 0x021D - Enable SATA Enable/disable SATA controller. $EN_DIS **/ UINT8 SataEnable; -/** Offset 0x0246 - SATA Mode +/** Offset 0x021E - SATA Mode Select SATA controller working mode. 0:AHCI, 1:RAID **/ UINT8 SataMode; -/** Offset 0x0247 - USB Per Port HS Preemphasis Bias +/** Offset 0x021F - USB Per Port HS Preemphasis Bias USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port. **/ UINT8 Usb2AfePetxiset[16]; -/** Offset 0x0257 - USB Per Port HS Transmitter Bias +/** Offset 0x022F - USB Per Port HS Transmitter Bias USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port. **/ UINT8 Usb2AfeTxiset[16]; -/** Offset 0x0267 - USB Per Port HS Transmitter Emphasis +/** Offset 0x023F - USB Per Port HS Transmitter Emphasis USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON, 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port. **/ UINT8 Usb2AfePredeemp[16]; -/** Offset 0x0277 - USB Per Port Half Bit Pre-emphasis +/** Offset 0x024F - USB Per Port Half Bit Pre-emphasis USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis. One byte for each port. **/ UINT8 Usb2AfePehalfbit[16]; -/** Offset 0x0287 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment +/** Offset 0x025F - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value in arrary can be between 0-1. One byte for each port. **/ UINT8 Usb3HsioTxDeEmphEnable[10]; -/** Offset 0x0291 - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting +/** Offset 0x0269 - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16], Default = 29h (approximately -3.5dB De-Emphasis). One byte for each port. **/ UINT8 Usb3HsioTxDeEmph[10]; -/** Offset 0x029B - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment +/** Offset 0x0273 - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value in arrary can be between 0-1. One byte for each port. **/ UINT8 Usb3HsioTxDownscaleAmpEnable[10]; -/** Offset 0x02A5 - USB 3.0 TX Output Downscale Amplitude Adjustment +/** Offset 0x027D - USB 3.0 TX Output Downscale Amplitude Adjustment USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], Default = 00h. One byte for each port. **/ UINT8 Usb3HsioTxDownscaleAmp[10]; -/** Offset 0x02AF - Enable LAN +/** Offset 0x0287 - Enable xHCI LTR override + Enables override of recommended LTR values for xHCI + $EN_DIS +**/ + UINT8 PchUsbLtrOverrideEnable; + +/** Offset 0x0288 - xHCI High Idle Time LTR override + Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting +**/ + UINT32 PchUsbLtrHighIdleTimeOverride; + +/** Offset 0x028C - xHCI Medium Idle Time LTR override + Value used for overriding LTR recommendation for xHCI Medium Idle Time LTR setting +**/ + UINT32 PchUsbLtrMediumIdleTimeOverride; + +/** Offset 0x0290 - xHCI Low Idle Time LTR override + Value used for overriding LTR recommendation for xHCI Low Idle Time LTR setting +**/ + UINT32 PchUsbLtrLowIdleTimeOverride; + +/** Offset 0x0294 - Enable LAN Enable/disable LAN controller. $EN_DIS **/ UINT8 PchLanEnable; -/** Offset 0x02B0 - Enable HD Audio Link +/** Offset 0x0295 - Enable HD Audio Link Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1. $EN_DIS **/ UINT8 PchHdaAudioLinkHda; -/** Offset 0x02B1 - Enable HD Audio DMIC0 Link +/** Offset 0x0296 - Enable HD Audio DMIC0 Link Enable/disable HD Audio DMIC0 link. Muxed with SNDW4. $EN_DIS **/ UINT8 PchHdaAudioLinkDmic0; -/** Offset 0x02B2 - Enable HD Audio DMIC1 Link +/** Offset 0x0297 - Enable HD Audio DMIC1 Link Enable/disable HD Audio DMIC1 link. Muxed with SNDW3. $EN_DIS **/ UINT8 PchHdaAudioLinkDmic1; -/** Offset 0x02B3 - Enable HD Audio SSP0 Link +/** Offset 0x0298 - Enable HD Audio SSP0 Link Enable/disable HD Audio SSP0/I2S link. Muxed with HDA. $EN_DIS **/ UINT8 PchHdaAudioLinkSsp0; -/** Offset 0x02B4 - Enable HD Audio SSP1 Link +/** Offset 0x0299 - Enable HD Audio SSP1 Link Enable/disable HD Audio SSP1/I2S link. Muxed with HDA/SNDW2. $EN_DIS **/ UINT8 PchHdaAudioLinkSsp1; -/** Offset 0x02B5 - Enable HD Audio SSP2 Link +/** Offset 0x029A - Enable HD Audio SSP2 Link Enable/disable HD Audio SSP2/I2S link. $EN_DIS **/ UINT8 PchHdaAudioLinkSsp2; -/** Offset 0x02B6 - Enable HD Audio SoundWire#1 Link +/** Offset 0x029B - Enable HD Audio SoundWire#1 Link Enable/disable HD Audio SNDW1 link. Muxed with HDA. $EN_DIS **/ UINT8 PchHdaAudioLinkSndw1; -/** Offset 0x02B7 - Enable HD Audio SoundWire#2 Link +/** Offset 0x029C - Enable HD Audio SoundWire#2 Link Enable/disable HD Audio SNDW2 link. Muxed with SSP1. $EN_DIS **/ UINT8 PchHdaAudioLinkSndw2; -/** Offset 0x02B8 - Enable HD Audio SoundWire#3 Link +/** Offset 0x029D - Enable HD Audio SoundWire#3 Link Enable/disable HD Audio SNDW3 link. Muxed with DMIC1. $EN_DIS **/ UINT8 PchHdaAudioLinkSndw3; -/** Offset 0x02B9 - Enable HD Audio SoundWire#4 Link +/** Offset 0x029E - Enable HD Audio SoundWire#4 Link Enable/disable HD Audio SNDW4 link. Muxed with DMIC0. $EN_DIS **/ UINT8 PchHdaAudioLinkSndw4; -/** Offset 0x02BA - Soundwire Clock Buffer GPIO RCOMP Setting +/** Offset 0x029F - Soundwire Clock Buffer GPIO RCOMP Setting 0: non-ACT - 50 Ohm driver impedance, 1: ACT - 8 Ohm driver impedance. $EN_DIS **/ UINT8 PchHdaSndwBufferRcomp; -/** Offset 0x02BB -**/ - UINT8 UnusedUpdSpace11; - -/** Offset 0x02BC - PTM for PCIE RP Mask +/** Offset 0x02A0 - PTM for PCIE RP Mask Enable/disable Precision Time Measurement for PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on. **/ UINT32 PcieRpPtmMask; -/** Offset 0x02C0 - DPC for PCIE RP Mask +/** Offset 0x02A4 - DPC for PCIE RP Mask Enable/disable Downstream Port Containment for PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on. **/ UINT32 PcieRpDpcMask; -/** Offset 0x02C4 - DPC Extensions PCIE RP Mask +/** Offset 0x02A8 - DPC Extensions PCIE RP Mask Enable/disable DPC Extensions for PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on. **/ UINT32 PcieRpDpcExtensionsMask; -/** Offset 0x02C8 - USB PDO Programming +/** Offset 0x02AC - USB PDO Programming Enable/disable PDO programming for USB in PEI phase. Disabling will allow for programming during later phase. 1: enable, 0: disable $EN_DIS **/ UINT8 UsbPdoProgramming; -/** Offset 0x02C9 +/** Offset 0x02AD **/ UINT8 UnusedUpdSpace12[3]; -/** Offset 0x02CC - Power button debounce configuration +/** Offset 0x02B0 - Power button debounce configuration Debounce time for PWRBTN in microseconds. For values not supported by HW, they will be rounded down to closest supported on. 0: disable, 250-1024000us: supported range **/ UINT32 PmcPowerButtonDebounce; -/** Offset 0x02D0 - PCH eSPI Master and Slave BME enabled +/** Offset 0x02B4 - PCH eSPI Master and Slave BME enabled PCH eSPI Master and Slave BME enabled $EN_DIS **/ UINT8 PchEspiBmeMasterSlaveEnabled; -/** Offset 0x02D1 - PCH SATA use RST Legacy OROM +/** Offset 0x02B5 - PCH SATA use RST Legacy OROM Use PCH SATA RST Legacy OROM when CSM is Enabled $EN_DIS **/ UINT8 SataRstLegacyOrom; -/** Offset 0x02D2 +/** Offset 0x02B6 **/ UINT8 UnusedUpdSpace13[2]; -/** Offset 0x02D4 - Trace Hub Memory Base +/** Offset 0x02B8 - Trace Hub Memory Base If Trace Hub is enabled and trace to memory is desired, BootLoader needs to allocate trace hub memory as reserved and uncacheable, set the base to ensure Trace Hub memory is configured properly. **/ UINT32 TraceHubMemBase; -/** Offset 0x02D8 - PMC Debug Message Enable +/** Offset 0x02BC - PMC Debug Message Enable When Enabled, PMC HW will send debug messages to trace hub; When Disabled, PMC HW will never send debug meesages to trace hub. Noted: When Enabled, may not enter S0ix $EN_DIS **/ UINT8 PmcDbgMsgEn; -/** Offset 0x02D9 +/** Offset 0x02BD **/ UINT8 UnusedUpdSpace14[3]; -/** Offset 0x02DC - Pointer of ChipsetInit Binary +/** Offset 0x02C0 - Pointer of ChipsetInit Binary ChipsetInit Binary Pointer. **/ UINT32 ChipsetInitBinPtr; -/** Offset 0x02E0 - Length of ChipsetInit Binary +/** Offset 0x02C4 - Length of ChipsetInit Binary ChipsetInit Binary Length. **/ UINT32 ChipsetInitBinLen; -/** Offset 0x02E4 - Enable Ufs Controller +/** Offset 0x02C8 - Enable Ufs Controller Enable/disable Ufs 2.0 Controller. $EN_DIS **/ UINT8 ScsUfsEnabled; -/** Offset 0x02E5 - CNVi Configuration +/** Offset 0x02C9 - CNVi Configuration This option allows for automatic detection of Connectivity Solution. [Auto Detection] assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi. 0:Disable, 1:Auto **/ UINT8 CnviMode; -/** Offset 0x02E6 - CNVi BT Core +/** Offset 0x02CA - CNVi BT Core Enable/Disable CNVi BT Core, Default is ENABLE. 0: DISABLE, 1: ENABLE $EN_DIS **/ UINT8 CnviBtCore; -/** Offset 0x02E7 - CNVi BT Audio Offload +/** Offset 0x02CB - CNVi BT Audio Offload Enable/Disable BT Audio Offload, Default is DISABLE. 0: DISABLE, 1: ENABLE $EN_DIS **/ UINT8 CnviBtAudioOffload; -/** Offset 0x02E8 - SdCard power enable polarity +/** Offset 0x02CC - SdCard power enable polarity Choose SD_PWREN# polarity 0: Active low, 1: Active high **/ UINT8 SdCardPowerEnableActiveHigh; -/** Offset 0x02E9 - PCH USB2 PHY Power Gating enable +/** Offset 0x02CD - PCH USB2 PHY Power Gating enable 1: Will enable USB2 PHY SUS Well Power Gating, 0: Will not enable PG of USB2 PHY Sus Well PG $EN_DIS **/ UINT8 PchUsb2PhySusPgEnable; -/** Offset 0x02EA - PCH USB OverCurrent mapping enable +/** Offset 0x02CE - PCH USB OverCurrent mapping enable 1: Will program USB OC pin mapping in xHCI controller memory, 0: Will clear OC pin mapping allow for NOA usage of OC pins $EN_DIS **/ UINT8 PchUsbOverCurrentEnable; -/** Offset 0x02EB - Espi Lgmr Memory Range decode +/** Offset 0x02CF - Espi Lgmr Memory Range decode This option enables or disables espi lgmr $EN_DIS **/ UINT8 PchEspiLgmrEnable; -/** Offset 0x02EC - PCHHOT# pin +/** Offset 0x02D0 - PCHHOT# pin Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable $EN_DIS **/ UINT8 PchHotEnable; -/** Offset 0x02ED - SATA LED +/** Offset 0x02D1 - SATA LED SATA LED indicating SATA controller activity. 0: disable, 1: enable $EN_DIS **/ UINT8 SataLedEnable; -/** Offset 0x02EE - VRAlert# Pin +/** Offset 0x02D2 - VRAlert# Pin When VRAlert# feature pin is enabled and its state is '0', the PMC requests throttling to a T3 Tstate to the PCH throttling unit.. 0: disable, 1: enable $EN_DIS **/ UINT8 PchPmVrAlert; -/** Offset 0x02EF - SLP_S0 VM Dynamic Control +/** Offset 0x02D3 - SLP_S0 VM Dynamic Control SLP_S0 Voltage Margining Runtime Control Policy. 0: disable, 1: enable $EN_DIS **/ UINT8 PchPmSlpS0VmRuntimeControl; -/** Offset 0x02F0 - SLP_S0 VM 0.70V Support +/** Offset 0x02D4 - SLP_S0 VM 0.70V Support SLP_S0 Voltage Margining 0.70V Support Policy. 0: disable, 1: enable $EN_DIS **/ UINT8 PchPmSlpS0Vm070VSupport; -/** Offset 0x02F1 - SLP_S0 VM 0.75V Support +/** Offset 0x02D5 - SLP_S0 VM 0.75V Support SLP_S0 Voltage Margining 0.75V Support Policy. 0: disable, 1: enable $EN_DIS **/ UINT8 PchPmSlpS0Vm075VSupport; -/** Offset 0x02F2 - PCH PCIe root port connection type +/** Offset 0x02D6 - PCH PCIe root port connection type 0: built-in device, 1:slot **/ UINT8 PcieRpSlotImplemented[24]; -/** Offset 0x030A - Usage type for ClkSrc +/** Offset 0x02EE - Usage type for ClkSrc 0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use (free running), 0xFF: not used **/ UINT8 PcieClkSrcUsage[16]; -/** Offset 0x031A - ClkReq-to-ClkSrc mapping +/** Offset 0x02FE - ClkReq-to-ClkSrc mapping Number of ClkReq signal assigned to ClkSrc **/ UINT8 PcieClkSrcClkReq[16]; -/** Offset 0x032A - PCIE RP Access Control Services Extended Capability +/** Offset 0x030E - PCIE RP Access Control Services Extended Capability Enable/Disable PCIE RP Access Control Services Extended Capability **/ UINT8 PcieRpAcsEnabled[24]; -/** Offset 0x0342 - PCIE RP Clock Power Management +/** Offset 0x0326 - PCIE RP Clock Power Management Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal can still be controlled by L1 PM substates mechanism **/ UINT8 PcieRpEnableCpm[24]; -/** Offset 0x035A - PCIE RP Detect Timeout Ms +/** Offset 0x033E - PCIE RP Detect Timeout Ms The number of milliseconds within 0~65535 in reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port. **/ UINT16 PcieRpDetectTimeoutMs[24]; -/** Offset 0x038A - ModPHY SUS Power Domain Dynamic Gating +/** Offset 0x036E - ModPHY SUS Power Domain Dynamic Gating Enable/Disable ModPHY SUS Power Domain Dynamic Gating. Setting not supported on PCH-H. 0: disable, 1: enable $EN_DIS **/ UINT8 PmcModPhySusPgEnable; -/** Offset 0x038B - SlpS0WithGbeSupport +/** Offset 0x036F - SlpS0WithGbeSupport Enable/Disable SLP_S0 with GBE Support. Default is 0 when paired with WHL V0 stepping CPU and 1 for all other CPUs. 0: Disable, 1: Enable $EN_DIS **/ UINT8 SlpS0WithGbeSupport; -/** Offset 0x038C - Enable Power Optimizer +/** Offset 0x0370 - Enable Power Optimizer Enable DMI Power Optimizer on PCH side. $EN_DIS **/ UINT8 PchPwrOptEnable; -/** Offset 0x038D - PCH Flash Protection Ranges Write Enble +/** Offset 0x0371 - PCH Flash Protection Ranges Write Enble Write or erase is blocked by hardware. **/ UINT8 PchWriteProtectionEnable[5]; -/** Offset 0x0392 - PCH Flash Protection Ranges Read Enble +/** Offset 0x0376 - PCH Flash Protection Ranges Read Enble Read is blocked by hardware. **/ UINT8 PchReadProtectionEnable[5]; -/** Offset 0x0397 +/** Offset 0x037B **/ UINT8 UnusedUpdSpace15[1]; -/** Offset 0x0398 - PCH Protect Range Limit +/** Offset 0x037C - PCH Protect Range Limit Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for limit comparison. **/ UINT16 PchProtectedRangeLimit[5]; -/** Offset 0x03A2 - PCH Protect Range Base +/** Offset 0x0386 - PCH Protect Range Base Left shifted address by 12 bits with address bits 11:0 are assumed to be 0. **/ UINT16 PchProtectedRangeBase[5]; -/** Offset 0x03AC - Enable Pme +/** Offset 0x0390 - Enable Pme Enable Azalia wake-on-ring. $EN_DIS **/ UINT8 PchHdaPme; -/** Offset 0x03AD - VC Type +/** Offset 0x0391 - VC Type Virtual Channel Type Select: 0: VC0, 1: VC1. 0: VC0, 1: VC1 **/ UINT8 PchHdaVcType; -/** Offset 0x03AE - HD Audio Link Frequency +/** Offset 0x0392 - HD Audio Link Frequency HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, 1: 12MHz, 2: 24MHz. 0: 6MHz, 1: 12MHz, 2: 24MHz **/ UINT8 PchHdaLinkFrequency; -/** Offset 0x03AF - iDisp-Link Frequency +/** Offset 0x0393 - iDisp-Link Frequency iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz. 4: 96MHz, 3: 48MHz **/ UINT8 PchHdaIDispLinkFrequency; -/** Offset 0x03B0 - iDisp-Link T-mode +/** Offset 0x0394 - iDisp-Link T-mode iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 1: 1T. 0: 2T, 1: 1T **/ UINT8 PchHdaIDispLinkTmode; -/** Offset 0x03B1 - Universal Audio Architecture compliance for DSP enabled system +/** Offset 0x0395 - Universal Audio Architecture compliance for DSP enabled system 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox driver or SST driver supported). $EN_DIS **/ UINT8 PchHdaDspUaaCompliance; -/** Offset 0x03B2 - iDisplay Audio Codec disconnection +/** Offset 0x0396 - iDisplay Audio Codec disconnection 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable. $EN_DIS **/ UINT8 PchHdaIDispCodecDisconnect; -/** Offset 0x03B3 - USB LFPS Filter selection +/** Offset 0x0397 - USB LFPS Filter selection For each byte bits 2:0 are for p, bits 4:6 are for n. 0h:1.6ns, 1h:2.4ns, 2h:3.2ns, 3h:4.0ns, 4h:4.8ns, 5h:5.6ns, 6h:6.4ns. **/ UINT8 PchUsbHsioFilterSel[10]; -/** Offset 0x03BD - Enable PCH Io Apic Entry 24-119 +/** Offset 0x03A1 - Enable PCH Io Apic Entry 24-119 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PchIoApicEntry24_119; -/** Offset 0x03BE - PCH Io Apic ID +/** Offset 0x03A2 - PCH Io Apic ID This member determines IOAPIC ID. Default is 0x02. **/ UINT8 PchIoApicId; -/** Offset 0x03BF - Enable PCH ISH SPI GPIO pins assigned +/** Offset 0x03A3 - Enable PCH ISH SPI GPIO pins assigned 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PchIshSpiGpioAssign; -/** Offset 0x03C0 - Enable PCH ISH UART0 GPIO pins assigned +/** Offset 0x03A4 - Enable PCH ISH UART0 GPIO pins assigned 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PchIshUart0GpioAssign; -/** Offset 0x03C1 - Enable PCH ISH UART1 GPIO pins assigned +/** Offset 0x03A5 - Enable PCH ISH UART1 GPIO pins assigned 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PchIshUart1GpioAssign; -/** Offset 0x03C2 - Enable PCH ISH I2C0 GPIO pins assigned +/** Offset 0x03A6 - Enable PCH ISH I2C0 GPIO pins assigned 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PchIshI2c0GpioAssign; -/** Offset 0x03C3 - Enable PCH ISH I2C1 GPIO pins assigned +/** Offset 0x03A7 - Enable PCH ISH I2C1 GPIO pins assigned 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PchIshI2c1GpioAssign; -/** Offset 0x03C4 - Enable PCH ISH I2C2 GPIO pins assigned +/** Offset 0x03A8 - Enable PCH ISH I2C2 GPIO pins assigned 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PchIshI2c2GpioAssign; -/** Offset 0x03C5 - Enable PCH ISH GP_0 GPIO pin assigned +/** Offset 0x03A9 - Enable PCH ISH GP_0 GPIO pin assigned 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PchIshGp0GpioAssign; -/** Offset 0x03C6 - Enable PCH ISH GP_1 GPIO pin assigned +/** Offset 0x03AA - Enable PCH ISH GP_1 GPIO pin assigned 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PchIshGp1GpioAssign; -/** Offset 0x03C7 - Enable PCH ISH GP_2 GPIO pin assigned +/** Offset 0x03AB - Enable PCH ISH GP_2 GPIO pin assigned 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PchIshGp2GpioAssign; -/** Offset 0x03C8 - Enable PCH ISH GP_3 GPIO pin assigned +/** Offset 0x03AC - Enable PCH ISH GP_3 GPIO pin assigned 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PchIshGp3GpioAssign; -/** Offset 0x03C9 - Enable PCH ISH GP_4 GPIO pin assigned +/** Offset 0x03AD - Enable PCH ISH GP_4 GPIO pin assigned 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PchIshGp4GpioAssign; -/** Offset 0x03CA - Enable PCH ISH GP_5 GPIO pin assigned +/** Offset 0x03AE - Enable PCH ISH GP_5 GPIO pin assigned 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PchIshGp5GpioAssign; -/** Offset 0x03CB - Enable PCH ISH GP_6 GPIO pin assigned +/** Offset 0x03AF - Enable PCH ISH GP_6 GPIO pin assigned 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PchIshGp6GpioAssign; -/** Offset 0x03CC - Enable PCH ISH GP_7 GPIO pin assigned +/** Offset 0x03B0 - Enable PCH ISH GP_7 GPIO pin assigned 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PchIshGp7GpioAssign; -/** Offset 0x03CD - PCH ISH PDT Unlock Msg +/** Offset 0x03B1 - PCH ISH PDT Unlock Msg 0: False; 1: True. $EN_DIS **/ UINT8 PchIshPdtUnlock; -/** Offset 0x03CE - Enable PCH Lan LTR capabilty of PCH internal LAN +/** Offset 0x03B2 - Enable PCH Lan LTR capabilty of PCH internal LAN 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PchLanLtrEnable; -/** Offset 0x03CF - Enable LOCKDOWN BIOS LOCK +/** Offset 0x03B3 - Enable LOCKDOWN BIOS LOCK Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region protection. $EN_DIS **/ UINT8 PchLockDownBiosLock; -/** Offset 0x03D0 - PCH Compatibility Revision ID +/** Offset 0x03B4 - PCH Compatibility Revision ID This member describes whether or not the CRID feature of PCH should be enabled. $EN_DIS **/ UINT8 PchCrid; -/** Offset 0x03D1 - RTC CMOS MEMORY LOCK +/** Offset 0x03B5 - RTC CMOS MEMORY LOCK Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper and and lower 128-byte bank of RTC RAM. $EN_DIS **/ UINT8 PchLockDownRtcMemoryLock; -/** Offset 0x03D2 - Enable PCIE RP HotPlug +/** Offset 0x03B6 - Enable PCIE RP HotPlug Indicate whether the root port is hot plug available. **/ UINT8 PcieRpHotPlug[24]; -/** Offset 0x03EA - Enable PCIE RP Pm Sci +/** Offset 0x03CE - Enable PCIE RP Pm Sci Indicate whether the root port power manager SCI is enabled. **/ UINT8 PcieRpPmSci[24]; -/** Offset 0x0402 - Enable PCIE RP Ext Sync +/** Offset 0x03E6 - Enable PCIE RP Ext Sync Indicate whether the extended synch is enabled. **/ UINT8 PcieRpExtSync[24]; -/** Offset 0x041A - Enable PCIE RP Transmitter Half Swing +/** Offset 0x03FE - Enable PCIE RP Transmitter Half Swing Indicate whether the Transmitter Half Swing is enabled. **/ UINT8 PcieRpTransmitterHalfSwing[24]; -/** Offset 0x0432 - Enable PCIE RP Clk Req Detect +/** Offset 0x0416 - Enable PCIE RP Clk Req Detect Probe CLKREQ# signal before enabling CLKREQ# based power management. **/ UINT8 PcieRpClkReqDetect[24]; -/** Offset 0x044A - PCIE RP Advanced Error Report +/** Offset 0x042E - PCIE RP Advanced Error Report Indicate whether the Advanced Error Reporting is enabled. **/ UINT8 PcieRpAdvancedErrorReporting[24]; -/** Offset 0x0462 - PCIE RP Unsupported Request Report +/** Offset 0x0446 - PCIE RP Unsupported Request Report Indicate whether the Unsupported Request Report is enabled. **/ UINT8 PcieRpUnsupportedRequestReport[24]; -/** Offset 0x047A - PCIE RP Fatal Error Report +/** Offset 0x045E - PCIE RP Fatal Error Report Indicate whether the Fatal Error Report is enabled. **/ UINT8 PcieRpFatalErrorReport[24]; -/** Offset 0x0492 - PCIE RP No Fatal Error Report +/** Offset 0x0476 - PCIE RP No Fatal Error Report Indicate whether the No Fatal Error Report is enabled. **/ UINT8 PcieRpNoFatalErrorReport[24]; -/** Offset 0x04AA - PCIE RP Correctable Error Report +/** Offset 0x048E - PCIE RP Correctable Error Report Indicate whether the Correctable Error Report is enabled. **/ UINT8 PcieRpCorrectableErrorReport[24]; -/** Offset 0x04C2 - PCIE RP System Error On Fatal Error +/** Offset 0x04A6 - PCIE RP System Error On Fatal Error Indicate whether the System Error on Fatal Error is enabled. **/ UINT8 PcieRpSystemErrorOnFatalError[24]; -/** Offset 0x04DA - PCIE RP System Error On Non Fatal Error +/** Offset 0x04BE - PCIE RP System Error On Non Fatal Error Indicate whether the System Error on Non Fatal Error is enabled. **/ UINT8 PcieRpSystemErrorOnNonFatalError[24]; -/** Offset 0x04F2 - PCIE RP System Error On Correctable Error +/** Offset 0x04D6 - PCIE RP System Error On Correctable Error Indicate whether the System Error on Correctable Error is enabled. **/ UINT8 PcieRpSystemErrorOnCorrectableError[24]; -/** Offset 0x050A - PCIE RP Max Payload +/** Offset 0x04EE - PCIE RP Max Payload Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD. **/ UINT8 PcieRpMaxPayload[24]; -/** Offset 0x0522 - PCH USB3 RX HSIO Tuning parameters +/** Offset 0x0506 - PCH USB3 RX HSIO Tuning parameters Bits 7:3 are for Signed Magnatude number added to the CTLE code, Bits 2:0 are for controlling the input offset **/ UINT8 PchUsbHsioRxTuningParameters[10]; -/** Offset 0x052C - PCH USB3 HSIO Rx Tuning Enable +/** Offset 0x0510 - PCH USB3 HSIO Rx Tuning Enable Mask for enabling tuning of HSIO Rx signals of USB3 ports. Bits: 0 - HsioCtrlAdaptOffsetCfgEnable, 1 - HsioFilterSelNEnable, 2 - HsioFilterSelPEnable, 3 - HsioOlfpsCfgPullUpDwnResEnable **/ UINT8 PchUsbHsioRxTuningEnable[10]; -/** Offset 0x0536 - PCIE RP Pcie Speed +/** Offset 0x051A - PCIE RP Pcie Speed Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see: PCH_PCIE_SPEED). **/ UINT8 PcieRpPcieSpeed[24]; -/** Offset 0x054E - PCIE RP Gen3 Equalization Phase Method +/** Offset 0x0532 - PCIE RP Gen3 Equalization Phase Method PCIe Gen3 Eq Ph3 Method (see PCH_PCIE_EQ_METHOD). 0: DEPRECATED, hardware equalization; 1: hardware equalization; 4: Fixed Coeficients. **/ UINT8 PcieRpGen3EqPh3Method[24]; -/** Offset 0x0566 - PCIE RP Physical Slot Number +/** Offset 0x054A - PCIE RP Physical Slot Number Indicates the slot number for the root port. Default is the value as root port index. **/ UINT8 PcieRpPhysicalSlotNumber[24]; -/** Offset 0x057E - PCIE RP Completion Timeout +/** Offset 0x0562 - PCIE RP Completion Timeout The root port completion timeout(see: PCH_PCIE_COMPLETION_TIMEOUT). Default is PchPcieCompletionTO_Default. **/ UINT8 PcieRpCompletionTimeout[24]; -/** Offset 0x0596 - PCIE RP Aspm +/** Offset 0x057A - PCIE RP Aspm The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is PchPcieAspmAutoConfig. **/ UINT8 PcieRpAspm[24]; -/** Offset 0x05AE - PCIE RP L1 Substates +/** Offset 0x0592 - PCIE RP L1 Substates The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). Default is PchPcieL1SubstatesL1_1_2. **/ UINT8 PcieRpL1Substates[24]; -/** Offset 0x05C6 - PCIE RP Ltr Enable +/** Offset 0x05AA - PCIE RP Ltr Enable Latency Tolerance Reporting Mechanism. **/ UINT8 PcieRpLtrEnable[24]; -/** Offset 0x05DE - PCIE RP Ltr Config Lock +/** Offset 0x05C2 - PCIE RP Ltr Config Lock 0: Disable; 1: Enable. **/ UINT8 PcieRpLtrConfigLock[24]; -/** Offset 0x05F6 - PCIE Eq Ph3 Lane Param Cm +/** Offset 0x05DA - PCIE Eq Ph3 Lane Param Cm PCH_PCIE_EQ_LANE_PARAM. Coefficient C-1. **/ UINT8 PcieEqPh3LaneParamCm[24]; -/** Offset 0x060E - PCIE Eq Ph3 Lane Param Cp +/** Offset 0x05F2 - PCIE Eq Ph3 Lane Param Cp PCH_PCIE_EQ_LANE_PARAM. Coefficient C+1. **/ UINT8 PcieEqPh3LaneParamCp[24]; -/** Offset 0x0626 - PCIE Sw Eq CoeffList Cm +/** Offset 0x060A - PCIE Sw Eq CoeffList Cm PCH_PCIE_EQ_PARAM. Coefficient C-1. **/ UINT8 PcieSwEqCoeffListCm[5]; -/** Offset 0x062B - PCIE Sw Eq CoeffList Cp +/** Offset 0x060F - PCIE Sw Eq CoeffList Cp PCH_PCIE_EQ_PARAM. Coefficient C+1. **/ UINT8 PcieSwEqCoeffListCp[5]; -/** Offset 0x0630 - PCIE Disable RootPort Clock Gating +/** Offset 0x0614 - PCIE Disable RootPort Clock Gating Describes whether the PCI Express Clock Gating for each root port is enabled by platform modules. 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PcieDisableRootPortClockGating; -/** Offset 0x0631 - PCIE Enable Peer Memory Write +/** Offset 0x0615 - PCIE Enable Peer Memory Write This member describes whether Peer Memory Writes are enabled on the platform. $EN_DIS **/ UINT8 PcieEnablePeerMemoryWrite; -/** Offset 0x0632 - PCIE Compliance Test Mode +/** Offset 0x0616 - PCIE Compliance Test Mode Compliance Test Mode shall be enabled when using Compliance Load Board. $EN_DIS **/ UINT8 PcieComplianceTestMode; -/** Offset 0x0633 - PCIE Rp Function Swap +/** Offset 0x0617 - PCIE Rp Function Swap Allows BIOS to use root port function number swapping when root port of function 0 is disabled. $EN_DIS **/ UINT8 PcieRpFunctionSwap; -/** Offset 0x0634 - Teton Glacier Cycle Router +/** Offset 0x0618 - Teton Glacier Cycle Router Specify to which cycle router Teton Glacier is connected, it is valid only when Teton Glacier support is enabled. Default is 0 for CNP-H system and 1 for CNP-LP system **/ UINT8 TetonGlacierCR; -/** Offset 0x0635 - PCH Pm PME_B0_S5_DIS +/** Offset 0x0619 - PCH Pm PME_B0_S5_DIS When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1. $EN_DIS **/ UINT8 PchPmPmeB0S5Dis; -/** Offset 0x0636 - PCIE IMR +/** Offset 0x061A - PCIE IMR Enables Isolated Memory Region for PCIe. $EN_DIS **/ UINT8 PcieRpImrEnabled; -/** Offset 0x0637 - PCIE IMR port number +/** Offset 0x061B - PCIE IMR port number Selects PCIE root port number for IMR feature. **/ UINT8 PcieRpImrSelection; -/** Offset 0x0638 - Teton Glacier Detection and Configuration Mode - Enables support for Teton Glacier hybrid storage device. 0: Disabled; 1: Static - Configuration 2: Dynamic Configuration. Default is 0: Disabled - 0: Disabled, 1: Static Configuration, 2: Dynamic Configuration +/** Offset 0x061C - Teton Glacier Detection and Configuration Mode + Enables support for Teton Glacier hybrid storage device. 0: Disabled; 1: Dynamic + Configuration. Default is 0: Disabled + 0: Disabled, 1: Dynamic Configuration **/ UINT8 TetonGlacierMode; -/** Offset 0x0639 - PCH Pm Wol Enable Override +/** Offset 0x061D - PCH Pm Wol Enable Override Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register. $EN_DIS **/ UINT8 PchPmWolEnableOverride; -/** Offset 0x063A - PCH Pm Pcie Wake From DeepSx +/** Offset 0x061E - PCH Pm Pcie Wake From DeepSx Determine if enable PCIe to wake from deep Sx. $EN_DIS **/ UINT8 PchPmPcieWakeFromDeepSx; -/** Offset 0x063B - PCH Pm WoW lan Enable +/** Offset 0x061F - PCH Pm WoW lan Enable Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register. $EN_DIS **/ UINT8 PchPmWoWlanEnable; -/** Offset 0x063C - PCH Pm WoW lan DeepSx Enable +/** Offset 0x0620 - PCH Pm WoW lan DeepSx Enable Determine if WLAN wake from DeepSx, corresponds to the DSX_WLAN_PP_EN bit in the PWRM_CFG3 register. $EN_DIS **/ UINT8 PchPmWoWlanDeepSxEnable; -/** Offset 0x063D - PCH Pm Lan Wake From DeepSx +/** Offset 0x0621 - PCH Pm Lan Wake From DeepSx Determine if enable LAN to wake from deep Sx. $EN_DIS **/ UINT8 PchPmLanWakeFromDeepSx; -/** Offset 0x063E - PCH Pm Deep Sx Pol +/** Offset 0x0622 - PCH Pm Deep Sx Pol Deep Sx Policy. $EN_DIS **/ UINT8 PchPmDeepSxPol; -/** Offset 0x063F - PCH Pm Slp S3 Min Assert +/** Offset 0x0623 - PCH Pm Slp S3 Min Assert SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms. **/ UINT8 PchPmSlpS3MinAssert; -/** Offset 0x0640 - PCH Pm Slp S4 Min Assert +/** Offset 0x0624 - PCH Pm Slp S4 Min Assert SLP_S4 Minimum Assertion Width Policy. Default is PchSlpS44s. **/ UINT8 PchPmSlpS4MinAssert; -/** Offset 0x0641 - PCH Pm Slp Sus Min Assert +/** Offset 0x0625 - PCH Pm Slp Sus Min Assert SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s. **/ UINT8 PchPmSlpSusMinAssert; -/** Offset 0x0642 - PCH Pm Slp A Min Assert +/** Offset 0x0626 - PCH Pm Slp A Min Assert SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s. **/ UINT8 PchPmSlpAMinAssert; -/** Offset 0x0643 - SLP_S0# Override +/** Offset 0x0627 - SLP_S0# Override Select 'Auto', it will be auto-configured according to probe type. Select 'Enabled' will disable SLP_S0# assertion whereas 'Disabled' will enable SLP_S0# assertion when debug is enabled. \n @@ -1787,7 +1801,7 @@ **/ UINT8 SlpS0Override; -/** Offset 0x0644 - S0ix Override Settings +/** Offset 0x0628 - S0ix Override Settings Select 'Auto', it will be auto-configured according to probe type. 'No Change' will keep PMC default settings. Or select the desired debug probe type for S0ix Override settings.\n @@ -1798,498 +1812,498 @@ **/ UINT8 SlpS0DisQForDebug; -/** Offset 0x0645 - USB Overcurrent Override for DbC +/** Offset 0x0629 - USB Overcurrent Override for DbC This option overrides USB Over Current enablement state that USB OC will be disabled after enabling this option. Enable when DbC is used to avoid signaling conflicts. $EN_DIS **/ UINT8 PchEnableDbcObs; -/** Offset 0x0646 - PCH Legacy IO Low Latency Enable +/** Offset 0x062A - PCH Legacy IO Low Latency Enable Set to enable low latency of legacy IO. 0: Disable, 1: Enable $EN_DIS **/ UINT8 PchLegacyIoLowLatency; -/** Offset 0x0647 - PCH Pm Lpc Clock Run +/** Offset 0x062B - PCH Pm Lpc Clock Run This member describes whether or not the LPC ClockRun feature of PCH should be enabled. Default value is Disabled $EN_DIS **/ UINT8 PchPmLpcClockRun; -/** Offset 0x0648 - PCH Pm Slp Strch Sus Up +/** Offset 0x062C - PCH Pm Slp Strch Sus Up Enable SLP_X Stretching After SUS Well Power Up. $EN_DIS **/ UINT8 PchPmSlpStrchSusUp; -/** Offset 0x0649 - PCH Pm Slp Lan Low Dc +/** Offset 0x062D - PCH Pm Slp Lan Low Dc Enable/Disable SLP_LAN# Low on DC Power. $EN_DIS **/ UINT8 PchPmSlpLanLowDc; -/** Offset 0x064A - PCH Pm Pwr Btn Override Period +/** Offset 0x062E - PCH Pm Pwr Btn Override Period PCH power button override period. 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s. **/ UINT8 PchPmPwrBtnOverridePeriod; -/** Offset 0x064B - PCH Pm Disable Dsx Ac Present Pulldown +/** Offset 0x062F - PCH Pm Disable Dsx Ac Present Pulldown When Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit. $EN_DIS **/ UINT8 PchPmDisableDsxAcPresentPulldown; -/** Offset 0x064C - PCH Pm Disable Native Power Button +/** Offset 0x0630 - PCH Pm Disable Native Power Button Power button native mode disable. $EN_DIS **/ UINT8 PchPmDisableNativePowerButton; -/** Offset 0x064D - PCH Pm Slp S0 Enable +/** Offset 0x0631 - PCH Pm Slp S0 Enable Indicates whether SLP_S0# is to be asserted when PCH reaches idle state. $EN_DIS **/ UINT8 PchPmSlpS0Enable; -/** Offset 0x064E - PCH Pm ME_WAKE_STS +/** Offset 0x0632 - PCH Pm ME_WAKE_STS Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register. $EN_DIS **/ UINT8 PchPmMeWakeSts; -/** Offset 0x064F - PCH Pm WOL_OVR_WK_STS +/** Offset 0x0633 - PCH Pm WOL_OVR_WK_STS Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register. $EN_DIS **/ UINT8 PchPmWolOvrWkSts; -/** Offset 0x0650 - PCH Pm Reset Power Cycle Duration +/** Offset 0x0634 - PCH Pm Reset Power Cycle Duration Could be customized in the unit of second. Please refer to EDS for all support settings. 0 is default, 1 is 1 second, 2 is 2 seconds, ... **/ UINT8 PchPmPwrCycDur; -/** Offset 0x0651 - PCH Pm Pcie Pll Ssc +/** Offset 0x0635 - PCH Pm Pcie Pll Ssc Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No BIOS override. **/ UINT8 PchPmPciePllSsc; -/** Offset 0x0652 - PCH Sata Pwr Opt Enable +/** Offset 0x0636 - PCH Sata Pwr Opt Enable SATA Power Optimizer on PCH side. $EN_DIS **/ UINT8 SataPwrOptEnable; -/** Offset 0x0653 - PCH Sata eSATA Speed Limit +/** Offset 0x0637 - PCH Sata eSATA Speed Limit When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed. $EN_DIS **/ UINT8 EsataSpeedLimit; -/** Offset 0x0654 - PCH Sata Speed Limit +/** Offset 0x0638 - PCH Sata Speed Limit Indicates the maximum speed the SATA controller can support 0h: PchSataSpeedDefault. **/ UINT8 SataSpeedLimit; -/** Offset 0x0655 - Enable SATA Port HotPlug +/** Offset 0x0639 - Enable SATA Port HotPlug Enable SATA Port HotPlug. **/ UINT8 SataPortsHotPlug[8]; -/** Offset 0x065D - Enable SATA Port Interlock Sw +/** Offset 0x0641 - Enable SATA Port Interlock Sw Enable SATA Port Interlock Sw. **/ UINT8 SataPortsInterlockSw[8]; -/** Offset 0x0665 - Enable SATA Port External +/** Offset 0x0649 - Enable SATA Port External Enable SATA Port External. **/ UINT8 SataPortsExternal[8]; -/** Offset 0x066D - Enable SATA Port SpinUp +/** Offset 0x0651 - Enable SATA Port SpinUp Enable the COMRESET initialization Sequence to the device. **/ UINT8 SataPortsSpinUp[8]; -/** Offset 0x0675 - Enable SATA Port Solid State Drive +/** Offset 0x0659 - Enable SATA Port Solid State Drive 0: HDD; 1: SSD. **/ UINT8 SataPortsSolidStateDrive[8]; -/** Offset 0x067D - Enable SATA Port Enable Dito Config +/** Offset 0x0661 - Enable SATA Port Enable Dito Config Enable DEVSLP Idle Timeout settings (DmVal, DitoVal). **/ UINT8 SataPortsEnableDitoConfig[8]; -/** Offset 0x0685 - Enable SATA Port DmVal +/** Offset 0x0669 - Enable SATA Port DmVal DITO multiplier. Default is 15. **/ UINT8 SataPortsDmVal[8]; -/** Offset 0x068D +/** Offset 0x0671 **/ UINT8 UnusedUpdSpace16[1]; -/** Offset 0x068E - Enable SATA Port DmVal +/** Offset 0x0672 - Enable SATA Port DmVal DEVSLP Idle Timeout (DITO), Default is 625. **/ UINT16 SataPortsDitoVal[8]; -/** Offset 0x069E - Enable SATA Port ZpOdd +/** Offset 0x0682 - Enable SATA Port ZpOdd Support zero power ODD. **/ UINT8 SataPortsZpOdd[8]; -/** Offset 0x06A6 - PCH Sata Rst Raid Device Id +/** Offset 0x068A - PCH Sata Rst Raid Device Id Enable RAID Alternate ID. 0:Client, 1:Alternate, 2:Server **/ UINT8 SataRstRaidDeviceId; -/** Offset 0x06A7 - PCH Sata Rst Raid0 +/** Offset 0x068B - PCH Sata Rst Raid0 RAID0. $EN_DIS **/ UINT8 SataRstRaid0; -/** Offset 0x06A8 - PCH Sata Rst Raid1 +/** Offset 0x068C - PCH Sata Rst Raid1 RAID1. $EN_DIS **/ UINT8 SataRstRaid1; -/** Offset 0x06A9 - PCH Sata Rst Raid10 +/** Offset 0x068D - PCH Sata Rst Raid10 RAID10. $EN_DIS **/ UINT8 SataRstRaid10; -/** Offset 0x06AA - PCH Sata Rst Raid5 +/** Offset 0x068E - PCH Sata Rst Raid5 RAID5. $EN_DIS **/ UINT8 SataRstRaid5; -/** Offset 0x06AB - PCH Sata Rst Irrt +/** Offset 0x068F - PCH Sata Rst Irrt Intel Rapid Recovery Technology. $EN_DIS **/ UINT8 SataRstIrrt; -/** Offset 0x06AC - PCH Sata Rst Orom Ui Banner +/** Offset 0x0690 - PCH Sata Rst Orom Ui Banner OROM UI and BANNER. $EN_DIS **/ UINT8 SataRstOromUiBanner; -/** Offset 0x06AD - PCH Sata Rst Orom Ui Delay +/** Offset 0x0691 - PCH Sata Rst Orom Ui Delay 00b: 2 secs; 01b: 4 secs; 10b: 6 secs; 11: 8 secs (see: PCH_SATA_OROM_DELAY). **/ UINT8 SataRstOromUiDelay; -/** Offset 0x06AE - PCH Sata Rst Hdd Unlock +/** Offset 0x0692 - PCH Sata Rst Hdd Unlock Indicates that the HDD password unlock in the OS is enabled. $EN_DIS **/ UINT8 SataRstHddUnlock; -/** Offset 0x06AF - PCH Sata Rst Led Locate +/** Offset 0x0693 - PCH Sata Rst Led Locate Indicates that the LED/SGPIO hardware is attached and ping to locate feature is enabled on the OS. $EN_DIS **/ UINT8 SataRstLedLocate; -/** Offset 0x06B0 - PCH Sata Rst Irrt Only +/** Offset 0x0694 - PCH Sata Rst Irrt Only Allow only IRRT drives to span internal and external ports. $EN_DIS **/ UINT8 SataRstIrrtOnly; -/** Offset 0x06B1 - PCH Sata Rst Smart Storage +/** Offset 0x0695 - PCH Sata Rst Smart Storage RST Smart Storage caching Bit. $EN_DIS **/ UINT8 SataRstSmartStorage; -/** Offset 0x06B2 - PCH Sata Rst Pcie Storage Remap enable +/** Offset 0x0696 - PCH Sata Rst Pcie Storage Remap enable Enable Intel RST for PCIe Storage remapping. **/ UINT8 SataRstPcieEnable[3]; -/** Offset 0x06B5 - PCH Sata Rst Pcie Storage Port +/** Offset 0x0699 - PCH Sata Rst Pcie Storage Port Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect). **/ UINT8 SataRstPcieStoragePort[3]; -/** Offset 0x06B8 - PCH Sata Rst Pcie Device Reset Delay +/** Offset 0x069C - PCH Sata Rst Pcie Device Reset Delay PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms **/ UINT8 SataRstPcieDeviceResetDelay[3]; -/** Offset 0x06BB - Enable eMMC HS400 Training +/** Offset 0x069F - Enable eMMC HS400 Training Deprecated. $EN_DIS **/ UINT8 PchScsEmmcHs400TuningRequired; -/** Offset 0x06BC - Set HS400 Tuning Data Valid +/** Offset 0x06A0 - Set HS400 Tuning Data Valid Set if HS400 Tuning Data Valid. $EN_DIS **/ UINT8 PchScsEmmcHs400DllDataValid; -/** Offset 0x06BD - Rx Strobe Delay Control +/** Offset 0x06A1 - Rx Strobe Delay Control Rx Strobe Delay Control - Rx Strobe Delay DLL 1 (HS400 Mode). **/ UINT8 PchScsEmmcHs400RxStrobeDll1; -/** Offset 0x06BE - Tx Data Delay Control +/** Offset 0x06A2 - Tx Data Delay Control Tx Data Delay Control 1 - Tx Data Delay (HS400 Mode). **/ UINT8 PchScsEmmcHs400TxDataDll; -/** Offset 0x06BF - I/O Driver Strength +/** Offset 0x06A3 - I/O Driver Strength Deprecated. 0:33 Ohm, 1:40 Ohm, 2:50 Ohm **/ UINT8 PchScsEmmcHs400DriverStrength; -/** Offset 0x06C0 - Enable Serial IRQ +/** Offset 0x06A4 - Enable Serial IRQ Determines if enable Serial IRQ. $EN_DIS **/ UINT8 PchSirqEnable; -/** Offset 0x06C1 - Serial IRQ Mode Select +/** Offset 0x06A5 - Serial IRQ Mode Select Serial IRQ Mode Select, 0: quiet mode, 1: continuous mode. $EN_DIS **/ UINT8 PchSirqMode; -/** Offset 0x06C2 - Start Frame Pulse Width +/** Offset 0x06A6 - Start Frame Pulse Width Start Frame Pulse Width, 0: PchSfpw4Clk, 1: PchSfpw6Clk, 2: PchSfpw8Clk. 0: PchSfpw4Clk, 1: PchSfpw6Clk, 2: PchSfpw8Clk **/ UINT8 PchStartFramePulse; -/** Offset 0x06C3 - Reserved +/** Offset 0x06A7 - Reserved Reserved $EN_DIS **/ UINT8 ReservedForFuture1; -/** Offset 0x06C4 - Thermal Device SMI Enable +/** Offset 0x06A8 - Thermal Device SMI Enable This locks down SMI Enable on Alert Thermal Sensor Trip. $EN_DIS **/ UINT8 PchTsmicLock; -/** Offset 0x06C5 +/** Offset 0x06A9 **/ UINT8 UnusedUpdSpace17; -/** Offset 0x06C6 - Thermal Throttling Custimized T0Level Value +/** Offset 0x06AA - Thermal Throttling Custimized T0Level Value Custimized T0Level value. **/ UINT16 PchT0Level; -/** Offset 0x06C8 - Thermal Throttling Custimized T1Level Value +/** Offset 0x06AC - Thermal Throttling Custimized T1Level Value Custimized T1Level value. **/ UINT16 PchT1Level; -/** Offset 0x06CA - Thermal Throttling Custimized T2Level Value +/** Offset 0x06AE - Thermal Throttling Custimized T2Level Value Custimized T2Level value. **/ UINT16 PchT2Level; -/** Offset 0x06CC - Enable The Thermal Throttle +/** Offset 0x06B0 - Enable The Thermal Throttle Enable the thermal throttle function. $EN_DIS **/ UINT8 PchTTEnable; -/** Offset 0x06CD - PMSync State 13 +/** Offset 0x06B1 - PMSync State 13 When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force at least T2 state. $EN_DIS **/ UINT8 PchTTState13Enable; -/** Offset 0x06CE - Thermal Throttle Lock +/** Offset 0x06B2 - Thermal Throttle Lock Thermal Throttle Lock. $EN_DIS **/ UINT8 PchTTLock; -/** Offset 0x06CF - Thermal Throttling Suggested Setting +/** Offset 0x06B3 - Thermal Throttling Suggested Setting Thermal Throttling Suggested Setting. $EN_DIS **/ UINT8 TTSuggestedSetting; -/** Offset 0x06D0 - Enable PCH Cross Throttling +/** Offset 0x06B4 - Enable PCH Cross Throttling Enable/Disable PCH Cross Throttling $EN_DIS **/ UINT8 TTCrossThrottling; -/** Offset 0x06D1 - DMI Thermal Sensor Autonomous Width Enable +/** Offset 0x06B5 - DMI Thermal Sensor Autonomous Width Enable DMI Thermal Sensor Autonomous Width Enable. $EN_DIS **/ UINT8 PchDmiTsawEn; -/** Offset 0x06D2 - DMI Thermal Sensor Suggested Setting +/** Offset 0x06B6 - DMI Thermal Sensor Suggested Setting DMT thermal sensor suggested representative values. $EN_DIS **/ UINT8 DmiSuggestedSetting; -/** Offset 0x06D3 - Thermal Sensor 0 Target Width +/** Offset 0x06B7 - Thermal Sensor 0 Target Width DMT thermal sensor suggested representative values. 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 **/ UINT8 DmiTS0TW; -/** Offset 0x06D4 - Thermal Sensor 1 Target Width +/** Offset 0x06B8 - Thermal Sensor 1 Target Width Thermal Sensor 1 Target Width. 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 **/ UINT8 DmiTS1TW; -/** Offset 0x06D5 - Thermal Sensor 2 Target Width +/** Offset 0x06B9 - Thermal Sensor 2 Target Width Thermal Sensor 2 Target Width. 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 **/ UINT8 DmiTS2TW; -/** Offset 0x06D6 - Thermal Sensor 3 Target Width +/** Offset 0x06BA - Thermal Sensor 3 Target Width Thermal Sensor 3 Target Width. 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 **/ UINT8 DmiTS3TW; -/** Offset 0x06D7 - Port 0 T1 Multipler +/** Offset 0x06BB - Port 0 T1 Multipler Port 0 T1 Multipler. **/ UINT8 SataP0T1M; -/** Offset 0x06D8 - Port 0 T2 Multipler +/** Offset 0x06BC - Port 0 T2 Multipler Port 0 T2 Multipler. **/ UINT8 SataP0T2M; -/** Offset 0x06D9 - Port 0 T3 Multipler +/** Offset 0x06BD - Port 0 T3 Multipler Port 0 T3 Multipler. **/ UINT8 SataP0T3M; -/** Offset 0x06DA - Port 0 Tdispatch +/** Offset 0x06BE - Port 0 Tdispatch Port 0 Tdispatch. **/ UINT8 SataP0TDisp; -/** Offset 0x06DB - Port 1 T1 Multipler +/** Offset 0x06BF - Port 1 T1 Multipler Port 1 T1 Multipler. **/ UINT8 SataP1T1M; -/** Offset 0x06DC - Port 1 T2 Multipler +/** Offset 0x06C0 - Port 1 T2 Multipler Port 1 T2 Multipler. **/ UINT8 SataP1T2M; -/** Offset 0x06DD - Port 1 T3 Multipler +/** Offset 0x06C1 - Port 1 T3 Multipler Port 1 T3 Multipler. **/ UINT8 SataP1T3M; -/** Offset 0x06DE - Port 1 Tdispatch +/** Offset 0x06C2 - Port 1 Tdispatch Port 1 Tdispatch. **/ UINT8 SataP1TDisp; -/** Offset 0x06DF - Port 0 Tinactive +/** Offset 0x06C3 - Port 0 Tinactive Port 0 Tinactive. **/ UINT8 SataP0Tinact; -/** Offset 0x06E0 - Port 0 Alternate Fast Init Tdispatch +/** Offset 0x06C4 - Port 0 Alternate Fast Init Tdispatch Port 0 Alternate Fast Init Tdispatch. $EN_DIS **/ UINT8 SataP0TDispFinit; -/** Offset 0x06E1 - Port 1 Tinactive +/** Offset 0x06C5 - Port 1 Tinactive Port 1 Tinactive. **/ UINT8 SataP1Tinact; -/** Offset 0x06E2 - Port 1 Alternate Fast Init Tdispatch +/** Offset 0x06C6 - Port 1 Alternate Fast Init Tdispatch Port 1 Alternate Fast Init Tdispatch. $EN_DIS **/ UINT8 SataP1TDispFinit; -/** Offset 0x06E3 - Sata Thermal Throttling Suggested Setting +/** Offset 0x06C7 - Sata Thermal Throttling Suggested Setting Sata Thermal Throttling Suggested Setting. $EN_DIS **/ UINT8 SataThermalSuggestedSetting; -/** Offset 0x06E4 - Enable Memory Thermal Throttling +/** Offset 0x06C8 - Enable Memory Thermal Throttling Enable Memory Thermal Throttling. $EN_DIS **/ UINT8 PchMemoryThrottlingEnable; -/** Offset 0x06E5 - Memory Thermal Throttling +/** Offset 0x06C9 - Memory Thermal Throttling Enable Memory Thermal Throttling. **/ UINT8 PchMemoryPmsyncEnable[2]; -/** Offset 0x06E7 - Enable Memory Thermal Throttling +/** Offset 0x06CB - Enable Memory Thermal Throttling Enable Memory Thermal Throttling. **/ UINT8 PchMemoryC0TransmitEnable[2]; -/** Offset 0x06E9 - Enable Memory Thermal Throttling +/** Offset 0x06CD - Enable Memory Thermal Throttling Enable Memory Thermal Throttling. **/ UINT8 PchMemoryPinSelection[2]; -/** Offset 0x06EB +/** Offset 0x06CF **/ UINT8 UnusedUpdSpace18; -/** Offset 0x06EC - Thermal Device Temperature +/** Offset 0x06D0 - Thermal Device Temperature Decides the temperature. **/ UINT16 PchTemperatureHotLevel; -/** Offset 0x06EE - Enable xHCI Compliance Mode +/** Offset 0x06D2 - Enable xHCI Compliance Mode Compliance Mode can be enabled for testing through this option but this is disabled by default. $EN_DIS **/ UINT8 PchEnableComplianceMode; -/** Offset 0x06EF - USB2 Port Over Current Pin +/** Offset 0x06D3 - USB2 Port Over Current Pin Describe the specific over current pin number of USB 2.0 Port N. **/ UINT8 Usb2OverCurrentPin[16]; -/** Offset 0x06FF - USB3 Port Over Current Pin +/** Offset 0x06E3 - USB3 Port Over Current Pin Describe the specific over current pin number of USB 3.0 Port N. **/ UINT8 Usb3OverCurrentPin[10]; -/** Offset 0x0709 - Enable 8254 Static Clock Gating +/** Offset 0x06ED - Enable 8254 Static Clock Gating Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support boot legacy OS using 8254 timer. Also enable this while S0ix is enabled. @@ -2297,19 +2311,19 @@ **/ UINT8 Enable8254ClockGating; -/** Offset 0x070A - PCH Sata Rst Optane Memory +/** Offset 0x06EE - PCH Sata Rst Optane Memory Optane Memory $EN_DIS **/ UINT8 SataRstOptaneMemory; -/** Offset 0x070B - PCH Sata Rst CPU Attached Storage +/** Offset 0x06EF - PCH Sata Rst CPU Attached Storage CPU Attached Storage $EN_DIS **/ UINT8 SataRstCpuAttachedStorage; -/** Offset 0x070C - Enable 8254 Static Clock Gating On S3 +/** Offset 0x06F0 - Enable 8254 Static Clock Gating On S3 This is only applicable when Enable8254ClockGating is disabled. FSP will do the 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This avoids the SMI requirement for the programming. @@ -2317,11 +2331,11 @@ **/ UINT8 Enable8254ClockGatingOnS3; -/** Offset 0x070D +/** Offset 0x06F1 **/ UINT8 UnusedUpdSpace19[3]; -/** Offset 0x0710 - Pch PCIE device override table pointer +/** Offset 0x06F4 - Pch PCIE device override table pointer The PCIe device table is being used to override PCIe device ASPM settings. This is a pointer points to a 32bit address. And it's only used in PostMem phase. Please refer to PCH_PCIE_DEVICE_OVERRIDE structure for the table. Last entry VendorId @@ -2329,7 +2343,7 @@ **/ UINT32 PchPcieDeviceOverrideTablePtr; -/** Offset 0x0714 - Enable TCO timer. +/** Offset 0x06F8 - Enable TCO timer. When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer emulation must be enabled, and WDAT table must not be exposed to the OS. @@ -2337,7 +2351,7 @@ **/ UINT8 EnableTcoTimer; -/** Offset 0x0715 - Enable PS_ON. +/** Offset 0x06F9 - Enable PS_ON. PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power target that will be required by the California Energy Commission (CEC). When FALSE, PS_ON is to be disabled. @@ -2345,107 +2359,159 @@ **/ UINT8 PsOnEnable; -/** Offset 0x0716 - Pmc Cpu C10 Gate Pin Enable +/** Offset 0x06FA - Pmc Cpu C10 Gate Pin Enable Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO and VccSTG rails instead of SLP_S0# pin. $EN_DIS **/ UINT8 PmcCpuC10GatePinEnable; -/** Offset 0x0717 - Pch Dmi Aspm Ctrl +/** Offset 0x06FB - Pch Dmi Aspm Ctrl ASPM configuration on the PCH side of the DMI/OPI Link. Default is PchPcieAspmAutoConfig 0:Disabled, 1:L0s, 2:L1, 3:L0sL1, 4:Auto **/ UINT8 PchDmiAspmCtrl; -/** Offset 0x0718 - ReservedPchPostMem +/** Offset 0x06FC - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3 + Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3, Each + value in array can be between 0-1. One byte for each port. +**/ + UINT8 Usb3HsioTxRate3UniqTranEnable[10]; + +/** Offset 0x0706 - USB 3.0 TX Output Unique Transition Bit Scale for rate 3 + USB 3.0 TX Output Unique Transition Bit Scale for rate 3, HSIO_TX_DWORD9[6:0], Default + = 4Ch. One byte for each port. +**/ + UINT8 Usb3HsioTxRate3UniqTran[10]; + +/** Offset 0x0710 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2 + Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2, Each + value in array can be between 0-1. One byte for each port. +**/ + UINT8 Usb3HsioTxRate2UniqTranEnable[10]; + +/** Offset 0x071A - USB 3.0 TX Output Unique Transition Bit Scale for rate 2 + USB 3.0 TX Output Unique Transition Bit Scale for rate 2, HSIO_TX_DWORD9[14:8], + Default = 4Ch. One byte for each port. +**/ + UINT8 Usb3HsioTxRate2UniqTran[10]; + +/** Offset 0x0724 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1 + Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1, Each + value in array can be between 0-1. One byte for each port. +**/ + UINT8 Usb3HsioTxRate1UniqTranEnable[10]; + +/** Offset 0x072E - USB 3.0 TX Output Unique Transition Bit Scale for rate 1 + USB 3.0 TX Output Unique Transition Bit Scale for rate 1, HSIO_TX_DWORD9[22:16], + Default = 4Ch. One byte for each port. +**/ + UINT8 Usb3HsioTxRate1UniqTran[10]; + +/** Offset 0x0738 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0 + Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0, Each + value in array can be between 0-1. One byte for each port. +**/ + UINT8 Usb3HsioTxRate0UniqTranEnable[10]; + +/** Offset 0x0742 - USB 3.0 TX Output Unique Transition Bit Scale for rate 0 + USB 3.0 TX Output Unique Transition Bit Scale for rate 0, HSIO_TX_DWORD9[30:24], + Default = 4Ch. One byte for each port. +**/ + UINT8 Usb3HsioTxRate0UniqTran[10]; + +/** Offset 0x074C - ReservedPchPostMem Reserved for Pch Post-Mem $EN_DIS **/ UINT8 ReservedPchPostMem[16]; -/** Offset 0x0728 - BgpdtHash[4] +/** Offset 0x075C +**/ + UINT8 UnusedUpdSpace20[4]; + +/** Offset 0x0760 - BgpdtHash[4] BgpdtHash values **/ UINT64 BgpdtHash[4]; -/** Offset 0x0748 - BiosGuardAttr +/** Offset 0x0780 - BiosGuardAttr BiosGuardAttr default values **/ UINT32 BiosGuardAttr; -/** Offset 0x074C +/** Offset 0x0784 **/ - UINT8 UnusedUpdSpace20[4]; + UINT8 UnusedUpdSpace21[4]; -/** Offset 0x0750 - BiosGuardModulePtr +/** Offset 0x0788 - BiosGuardModulePtr BiosGuardModulePtr default values **/ UINT64 BiosGuardModulePtr; -/** Offset 0x0758 - SendEcCmd +/** Offset 0x0790 - SendEcCmd SendEcCmd function pointer. \n @code typedef EFI_STATUS (EFIAPI *PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE EcCmdType, IN UINT8 EcCmd, IN UINT8 SendData, IN OUT UINT8 *ReceiveData); @endcode **/ UINT64 SendEcCmd; -/** Offset 0x0760 - EcCmdProvisionEav +/** Offset 0x0798 - EcCmdProvisionEav Ephemeral Authorization Value default values. Provisions an ephemeral shared secret to the EC **/ UINT8 EcCmdProvisionEav; -/** Offset 0x0761 - EcCmdLock +/** Offset 0x0799 - EcCmdLock EcCmdLock default values. Locks Ephemeral Authorization Value sent previously **/ UINT8 EcCmdLock; -/** Offset 0x0762 +/** Offset 0x079A **/ - UINT8 UnusedUpdSpace21[6]; + UINT8 UnusedUpdSpace22[6]; -/** Offset 0x0768 - SgxEpoch0 +/** Offset 0x07A0 - SgxEpoch0 SgxEpoch0 default values **/ UINT64 SgxEpoch0; -/** Offset 0x0770 - SgxEpoch1 +/** Offset 0x07A8 - SgxEpoch1 SgxEpoch1 default values **/ UINT64 SgxEpoch1; -/** Offset 0x0778 - SgxSinitNvsData +/** Offset 0x07B0 - SgxSinitNvsData SgxSinitNvsData default values **/ UINT8 SgxSinitNvsData; -/** Offset 0x0779 - Si Config CSM Flag. +/** Offset 0x07B1 - Si Config CSM Flag. Platform specific common policies that used by several silicon components. CSM status flag. $EN_DIS **/ UINT8 SiCsmFlag; -/** Offset 0x077A +/** Offset 0x07B2 **/ - UINT8 UnusedUpdSpace22[2]; + UINT8 UnusedUpdSpace23[2]; -/** Offset 0x077C - SVID SDID table Poniter. +/** Offset 0x07B4 - SVID SDID table Poniter. The address of the table of SVID SDID to customize each SVID SDID entry. **/ UINT32 SiSsidTablePtr; -/** Offset 0x0780 - Number of ssid table. +/** Offset 0x07B8 - Number of ssid table. SiNumberOfSsidTableEntry should match the table entries created in SiSsidTablePtr. **/ UINT16 SiNumberOfSsidTableEntry; -/** Offset 0x0782 - SATA RST Interrupt Mode +/** Offset 0x07BA - SATA RST Interrupt Mode Allowes to choose which interrupts will be implemented by SATA controller in RAID mode. 0:Msix, 1:Msi, 2:Legacy **/ UINT8 SataRstInterrupt; -/** Offset 0x0783 - ME Unconfig on RTC clear +/** Offset 0x07BB - ME Unconfig on RTC clear 0: Disable ME Unconfig On Rtc Clear. 1: Enable ME Unconfig On Rtc Clear. 2: Cmos is clear, status unkonwn. 3: Reserved 0: Disable ME Unconfig On Rtc Clear, 1: Enable ME Unconfig On Rtc Clear, 2: Cmos @@ -2453,11 +2519,11 @@ **/ UINT8 MeUnconfigOnRtcClear; -/** Offset 0x0784 +/** Offset 0x07BC **/ - UINT8 UnusedUpdSpace23[3]; + UINT8 UnusedUpdSpace24[3]; -/** Offset 0x0787 +/** Offset 0x07BF **/ UINT8 ReservedFspsUpd[1]; } FSP_S_CONFIG; @@ -2466,74 +2532,74 @@ **/ typedef struct { -/** Offset 0x0788 +/** Offset 0x07C0 **/ UINT32 Signature; -/** Offset 0x078C - Enable/Disable Device 7 +/** Offset 0x07C4 - Enable/Disable Device 7 Enable: Device 7 enabled, Disable (Default): Device 7 disabled $EN_DIS **/ UINT8 ChapDeviceEnable; -/** Offset 0x078D - Skip PAM register lock +/** Offset 0x07C5 - Skip PAM register lock Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): PAM registers will be locked by RC $EN_DIS **/ UINT8 SkipPamLock; -/** Offset 0x078E - EDRAM Test Mode +/** Offset 0x07C6 - EDRAM Test Mode Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): PAM registers will be locked by RC 0: EDRAM SW disable, 1: EDRAM SW Enable, 2: EDRAM HW mode **/ UINT8 EdramTestMode; -/** Offset 0x078F - DMI Extended Sync Control +/** Offset 0x07C7 - DMI Extended Sync Control Enable: Enable DMI Extended Sync Control, Disable(Default): Disable DMI Extended Sync Control $EN_DIS **/ UINT8 DmiExtSync; -/** Offset 0x0790 - DMI IOT Control +/** Offset 0x07C8 - DMI IOT Control Enable: Enable DMI IOT Control, Disable(Default): Disable DMI IOT Control $EN_DIS **/ UINT8 DmiIot; -/** Offset 0x0791 - PEG Max Payload size per root port +/** Offset 0x07C9 - PEG Max Payload size per root port 0xFF(Default):Auto, 0x1: Force 128B, 0x2: Force 256B 0xFF: Auto, 0x1: Force 128B, 0x2: Force 256B **/ UINT8 PegMaxPayload[4]; -/** Offset 0x0795 - Enable/Disable IGFX RenderStandby +/** Offset 0x07CD - Enable/Disable IGFX RenderStandby Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby $EN_DIS **/ UINT8 RenderStandby; -/** Offset 0x0796 - Enable/Disable IGFX PmSupport +/** Offset 0x07CE - Enable/Disable IGFX PmSupport Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport $EN_DIS **/ UINT8 PmSupport; -/** Offset 0x0797 - Enable/Disable CdynmaxClamp +/** Offset 0x07CF - Enable/Disable CdynmaxClamp Enable(Default): Enable CdynmaxClamp, Disable: Disable CdynmaxClamp $EN_DIS **/ UINT8 CdynmaxClampEnable; -/** Offset 0x0798 - Disable VT-d +/** Offset 0x07D0 - Disable VT-d 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled) $EN_DIS **/ UINT8 VtdDisableDeprecated; -/** Offset 0x0799 - GT Frequency Limit +/** Offset 0x07D1 - GT Frequency Limit 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, @@ -2547,19 +2613,19 @@ **/ UINT8 GtFreqMax; -/** Offset 0x079A - Disable Turbo GT +/** Offset 0x07D2 - Disable Turbo GT 0=Disable: GT frequency is not limited, 1=Enable: Disables Turbo GT frequency $EN_DIS **/ UINT8 DisableTurboGt; -/** Offset 0x079B - SaPostMemTestRsvd +/** Offset 0x07D3 - SaPostMemTestRsvd Reserved for SA Post-Mem Test $EN_DIS **/ UINT8 SaPostMemTestRsvd[11]; -/** Offset 0x07A6 - 1-Core Ratio Limit +/** Offset 0x07DE - 1-Core Ratio Limit 1-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 1-Core Ratio Limit Must be greater than or equal to 2-Core Ratio Limit, 3-Core Ratio Limit, 4-Core Ratio Limit, 5-Core Ratio Limit, 6-Core Ratio Limit, 7-Core Ratio Limit, @@ -2567,79 +2633,79 @@ **/ UINT8 OneCoreRatioLimit; -/** Offset 0x07A7 - 2-Core Ratio Limit +/** Offset 0x07DF - 2-Core Ratio Limit 2-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 2-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 **/ UINT8 TwoCoreRatioLimit; -/** Offset 0x07A8 - 3-Core Ratio Limit +/** Offset 0x07E0 - 3-Core Ratio Limit 3-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 3-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 **/ UINT8 ThreeCoreRatioLimit; -/** Offset 0x07A9 - 4-Core Ratio Limit +/** Offset 0x07E1 - 4-Core Ratio Limit 4-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 4-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 **/ UINT8 FourCoreRatioLimit; -/** Offset 0x07AA - Enable or Disable HWP +/** Offset 0x07E2 - Enable or Disable HWP Enable or Disable HWP(Hardware P states) Support. 0: Disable; 1: Enable; 2-3:Reserved $EN_DIS **/ UINT8 Hwp; -/** Offset 0x07AB - Hardware Duty Cycle Control +/** Offset 0x07E3 - Hardware Duty Cycle Control Hardware Duty Cycle Control configuration. 0: Disabled; 1: Enabled 2-3:Reserved $EN_DIS **/ UINT8 HdcControl; -/** Offset 0x07AC - Package Long duration turbo mode time +/** Offset 0x07E4 - Package Long duration turbo mode time Package Long duration turbo mode time window in seconds. 0 = AUTO, uses 28 seconds. Valid values(Unit in seconds) 1 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128 **/ UINT8 PowerLimit1Time; -/** Offset 0x07AD - Short Duration Turbo Mode +/** Offset 0x07E5 - Short Duration Turbo Mode Enable or Disable short duration Turbo Mode. 0 : Disable; 1: Enable $EN_DIS **/ UINT8 PowerLimit2; -/** Offset 0x07AE - Turbo settings Lock +/** Offset 0x07E6 - Turbo settings Lock Lock all Turbo settings Enable/Disable; 0: Disable , 1: Enable $EN_DIS **/ UINT8 TurboPowerLimitLock; -/** Offset 0x07AF - Package PL3 time window +/** Offset 0x07E7 - Package PL3 time window Package PL3 time window range for this policy from 0 to 64ms **/ UINT8 PowerLimit3Time; -/** Offset 0x07B0 - Package PL3 Duty Cycle +/** Offset 0x07E8 - Package PL3 Duty Cycle Package PL3 Duty Cycle; Valid Range is 0 to 100 **/ UINT8 PowerLimit3DutyCycle; -/** Offset 0x07B1 - Package PL3 Lock +/** Offset 0x07E9 - Package PL3 Lock Package PL3 Lock Enable/Disable; 0: Disable ; 1: Enable $EN_DIS **/ UINT8 PowerLimit3Lock; -/** Offset 0x07B2 - Package PL4 Lock +/** Offset 0x07EA - Package PL4 Lock Package PL4 Lock Enable/Disable; 0: Disable ; 1: Enable $EN_DIS **/ UINT8 PowerLimit4Lock; -/** Offset 0x07B3 - TCC Activation Offset +/** Offset 0x07EB - TCC Activation Offset TCC Activation Offset. Offset from factory set TCC activation temperature at which the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation Temperature, in volts.For Y SKU, the recommended default for this policy is 15, @@ -2647,7 +2713,7 @@ **/ UINT8 TccActivationOffset; -/** Offset 0x07B4 - Tcc Offset Clamp Enable/Disable +/** Offset 0x07EC - Tcc Offset Clamp Enable/Disable Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle below P1.For Y SKU, the recommended default for this policy is 1: Enabled, For all other SKUs the recommended default are 0: Disabled. @@ -2655,345 +2721,345 @@ **/ UINT8 TccOffsetClamp; -/** Offset 0x07B5 - Tcc Offset Lock +/** Offset 0x07ED - Tcc Offset Lock Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature target; 0: Disabled; 1: Enabled. $EN_DIS **/ UINT8 TccOffsetLock; -/** Offset 0x07B6 - Custom Ratio State Entries +/** Offset 0x07EE - Custom Ratio State Entries The number of custom ratio state entries, ranges from 0 to 40 for a valid custom ratio table.Sets the number of custom P-states. At least 2 states must be present **/ UINT8 NumberOfEntries; -/** Offset 0x07B7 - Custom Short term Power Limit time window +/** Offset 0x07EF - Custom Short term Power Limit time window Short term Power Limit time window value for custom CTDP level 1. Valid Range 0 to 128, 0 = AUTO **/ UINT8 Custom1PowerLimit1Time; -/** Offset 0x07B8 - Custom Turbo Activation Ratio +/** Offset 0x07F0 - Custom Turbo Activation Ratio Turbo Activation Ratio for custom cTDP level 1. Valid Range 0 to 255 **/ UINT8 Custom1TurboActivationRatio; -/** Offset 0x07B9 - Custom Config Tdp Control +/** Offset 0x07F1 - Custom Config Tdp Control Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2 **/ UINT8 Custom1ConfigTdpControl; -/** Offset 0x07BA - Custom Short term Power Limit time window +/** Offset 0x07F2 - Custom Short term Power Limit time window Short term Power Limit time window value for custom CTDP level 2. Valid Range 0 to 128, 0 = AUTO **/ UINT8 Custom2PowerLimit1Time; -/** Offset 0x07BB - Custom Turbo Activation Ratio +/** Offset 0x07F3 - Custom Turbo Activation Ratio Turbo Activation Ratio for custom cTDP level 2. Valid Range 0 to 255 **/ UINT8 Custom2TurboActivationRatio; -/** Offset 0x07BC - Custom Config Tdp Control +/** Offset 0x07F4 - Custom Config Tdp Control Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2 **/ UINT8 Custom2ConfigTdpControl; -/** Offset 0x07BD - Custom Short term Power Limit time window +/** Offset 0x07F5 - Custom Short term Power Limit time window Short term Power Limit time window value for custom CTDP level 3. Valid Range 0 to 128, 0 = AUTO **/ UINT8 Custom3PowerLimit1Time; -/** Offset 0x07BE - Custom Turbo Activation Ratio +/** Offset 0x07F6 - Custom Turbo Activation Ratio Turbo Activation Ratio for custom cTDP level 3. Valid Range 0 to 255 **/ UINT8 Custom3TurboActivationRatio; -/** Offset 0x07BF - Custom Config Tdp Control +/** Offset 0x07F7 - Custom Config Tdp Control Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2 **/ UINT8 Custom3ConfigTdpControl; -/** Offset 0x07C0 - ConfigTdp mode settings Lock +/** Offset 0x07F8 - ConfigTdp mode settings Lock Lock the ConfigTdp mode settings from runtime changes; 0: Disable; 1: Enable $EN_DIS **/ UINT8 ConfigTdpLock; -/** Offset 0x07C1 - Load Configurable TDP SSDT +/** Offset 0x07F9 - Load Configurable TDP SSDT Configure whether to load Configurable TDP SSDT; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 ConfigTdpBios; -/** Offset 0x07C2 - PL1 Enable value +/** Offset 0x07FA - PL1 Enable value PL1 Enable value to limit average platform power. 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PsysPowerLimit1; -/** Offset 0x07C3 - PL1 timewindow +/** Offset 0x07FB - PL1 timewindow PL1 timewindow in seconds. 0 = AUTO, uses 28 seconds. Valid values(Unit in seconds) 1 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128 **/ UINT8 PsysPowerLimit1Time; -/** Offset 0x07C4 - PL2 Enable Value +/** Offset 0x07FC - PL2 Enable Value PL2 Enable activates the PL2 value to limit average platform power.0: Disable; 1: Enable. $EN_DIS **/ UINT8 PsysPowerLimit2; -/** Offset 0x07C5 - Enable or Disable MLC Streamer Prefetcher +/** Offset 0x07FD - Enable or Disable MLC Streamer Prefetcher Enable or Disable MLC Streamer Prefetcher; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 MlcStreamerPrefetcher; -/** Offset 0x07C6 - Enable or Disable MLC Spatial Prefetcher +/** Offset 0x07FE - Enable or Disable MLC Spatial Prefetcher Enable or Disable MLC Spatial Prefetcher; 0: Disable; 1: Enable $EN_DIS **/ UINT8 MlcSpatialPrefetcher; -/** Offset 0x07C7 - Enable or Disable Monitor /MWAIT instructions +/** Offset 0x07FF - Enable or Disable Monitor /MWAIT instructions Enable or Disable Monitor /MWAIT instructions; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 MonitorMwaitEnable; -/** Offset 0x07C8 - Enable or Disable initialization of machine check registers +/** Offset 0x0800 - Enable or Disable initialization of machine check registers Enable or Disable initialization of machine check registers; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 MachineCheckEnable; -/** Offset 0x07C9 - Deprecated DO NOT USE Enable or Disable processor debug features +/** Offset 0x0801 - Deprecated DO NOT USE Enable or Disable processor debug features @deprecated Enable or Disable processor debug features; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 DebugInterfaceEnable; -/** Offset 0x07CA - Lock or Unlock debug interface features +/** Offset 0x0802 - Lock or Unlock debug interface features Lock or Unlock debug interface features; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 DebugInterfaceLockEnable; -/** Offset 0x07CB - AP Idle Manner of waiting for SIPI +/** Offset 0x0803 - AP Idle Manner of waiting for SIPI AP Idle Manner of waiting for SIPI; 1: HALT loop; 2: MWAIT loop; 3: RUN loop. 1: HALT loop, 2: MWAIT loop, 3: RUN loop **/ UINT8 ApIdleManner; -/** Offset 0x07CC - Control on Processor Trace output scheme +/** Offset 0x0804 - Control on Processor Trace output scheme Control on Processor Trace output scheme; 0: Single Range Output; 1: ToPA Output. 0: Single Range Output, 1: ToPA Output **/ UINT8 ProcessorTraceOutputScheme; -/** Offset 0x07CD - Enable or Disable Processor Trace feature +/** Offset 0x0805 - Enable or Disable Processor Trace feature Enable or Disable Processor Trace feature; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 ProcessorTraceEnable; -/** Offset 0x07CE +/** Offset 0x0806 **/ - UINT8 UnusedUpdSpace24[2]; + UINT8 UnusedUpdSpace25[2]; -/** Offset 0x07D0 - Base of memory region allocated for Processor Trace +/** Offset 0x0808 - Base of memory region allocated for Processor Trace Base address of memory region allocated for Processor Trace. Processor Trace requires 2^N alignment and size in bytes per thread, from 4KB to 128MB. 0: Disable **/ UINT64 ProcessorTraceMemBase; -/** Offset 0x07D8 - Memory region allocation for Processor Trace +/** Offset 0x0810 - Memory region allocation for Processor Trace Length in bytes of memory region allocated for Processor Trace. Processor Trace requires 2^N alignment and size in bytes per thread, from 4KB to 128MB. 0: Disable **/ UINT32 ProcessorTraceMemLength; -/** Offset 0x07DC - Enable or Disable Voltage Optimization feature +/** Offset 0x0814 - Enable or Disable Voltage Optimization feature Enable or Disable Voltage Optimization feature 0: Disable; 1: Enable $EN_DIS **/ UINT8 VoltageOptimization; -/** Offset 0x07DD - Enable or Disable Intel SpeedStep Technology +/** Offset 0x0815 - Enable or Disable Intel SpeedStep Technology Enable or Disable Intel SpeedStep Technology. 0: Disable; 1: Enable $EN_DIS **/ UINT8 Eist; -/** Offset 0x07DE - Enable or Disable Energy Efficient P-state +/** Offset 0x0816 - Enable or Disable Energy Efficient P-state Enable or Disable Energy Efficient P-state will be applied in Turbo mode. Disable; 1: Enable $EN_DIS **/ UINT8 EnergyEfficientPState; -/** Offset 0x07DF - Enable or Disable Energy Efficient Turbo +/** Offset 0x0817 - Enable or Disable Energy Efficient Turbo Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode. Disable; 1: Enable $EN_DIS **/ UINT8 EnergyEfficientTurbo; -/** Offset 0x07E0 - Enable or Disable T states +/** Offset 0x0818 - Enable or Disable T states Enable or Disable T states; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 TStates; -/** Offset 0x07E1 - Enable or Disable Bi-Directional PROCHOT# +/** Offset 0x0819 - Enable or Disable Bi-Directional PROCHOT# Enable or Disable Bi-Directional PROCHOT#; 0: Disable; 1: Enable $EN_DIS **/ UINT8 BiProcHot; -/** Offset 0x07E2 - Enable or Disable PROCHOT# signal being driven externally +/** Offset 0x081A - Enable or Disable PROCHOT# signal being driven externally Enable or Disable PROCHOT# signal being driven externally; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 DisableProcHotOut; -/** Offset 0x07E3 - Enable or Disable PROCHOT# Response +/** Offset 0x081B - Enable or Disable PROCHOT# Response Enable or Disable PROCHOT# Response; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 ProcHotResponse; -/** Offset 0x07E4 - Enable or Disable VR Thermal Alert +/** Offset 0x081C - Enable or Disable VR Thermal Alert Enable or Disable VR Thermal Alert; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 DisableVrThermalAlert; -/** Offset 0x07E5 - Enable or Disable Thermal Reporting +/** Offset 0x081D - Enable or Disable Thermal Reporting Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 AutoThermalReporting; -/** Offset 0x07E6 - Enable or Disable Thermal Monitor +/** Offset 0x081E - Enable or Disable Thermal Monitor Enable or Disable Thermal Monitor; 0: Disable; 1: Enable $EN_DIS **/ UINT8 ThermalMonitor; -/** Offset 0x07E7 - Enable or Disable CPU power states (C-states) +/** Offset 0x081F - Enable or Disable CPU power states (C-states) Enable or Disable CPU power states (C-states). 0: Disable; 1: Enable $EN_DIS **/ UINT8 Cx; -/** Offset 0x07E8 - Configure C-State Configuration Lock +/** Offset 0x0820 - Configure C-State Configuration Lock Configure C-State Configuration Lock; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PmgCstCfgCtrlLock; -/** Offset 0x07E9 - Enable or Disable Enhanced C-states +/** Offset 0x0821 - Enable or Disable Enhanced C-states Enable or Disable Enhanced C-states. 0: Disable; 1: Enable $EN_DIS **/ UINT8 C1e; -/** Offset 0x07EA - Enable or Disable Package Cstate Demotion +/** Offset 0x0822 - Enable or Disable Package Cstate Demotion Enable or Disable Package Cstate Demotion. 0: Disable; 1: Enable $EN_DIS **/ UINT8 PkgCStateDemotion; -/** Offset 0x07EB - Enable or Disable Package Cstate UnDemotion +/** Offset 0x0823 - Enable or Disable Package Cstate UnDemotion Enable or Disable Package Cstate UnDemotion. 0: Disable; 1: Enable $EN_DIS **/ UINT8 PkgCStateUnDemotion; -/** Offset 0x07EC - Enable or Disable CState-Pre wake +/** Offset 0x0824 - Enable or Disable CState-Pre wake Enable or Disable CState-Pre wake. 0: Disable; 1: Enable $EN_DIS **/ UINT8 CStatePreWake; -/** Offset 0x07ED - Enable or Disable TimedMwait Support. +/** Offset 0x0825 - Enable or Disable TimedMwait Support. Enable or Disable TimedMwait Support. 0: Disable; 1: Enable $EN_DIS **/ UINT8 TimedMwait; -/** Offset 0x07EE - Enable or Disable IO to MWAIT redirection +/** Offset 0x0826 - Enable or Disable IO to MWAIT redirection Enable or Disable IO to MWAIT redirection; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 CstCfgCtrIoMwaitRedirection; -/** Offset 0x07EF - Set the Max Pkg Cstate +/** Offset 0x0827 - Set the Max Pkg Cstate Set the Max Pkg Cstate. Default set to Auto which limits the Max Pkg Cstate to deep C-state. Valid values 0 - C0/C1 , 1 - C2 , 2 - C3 , 3 - C6 , 4 - C7 , 5 - C7S , 6 - C8 , 7 - C9 , 8 - C10 , 254 - CPU Default , 255 - Auto **/ UINT8 PkgCStateLimit; -/** Offset 0x07F0 - TimeUnit for C-State Latency Control0 +/** Offset 0x0828 - TimeUnit for C-State Latency Control0 TimeUnit for C-State Latency Control0; Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns **/ UINT8 CstateLatencyControl0TimeUnit; -/** Offset 0x07F1 - TimeUnit for C-State Latency Control1 +/** Offset 0x0829 - TimeUnit for C-State Latency Control1 TimeUnit for C-State Latency Control1;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns **/ UINT8 CstateLatencyControl1TimeUnit; -/** Offset 0x07F2 - TimeUnit for C-State Latency Control2 +/** Offset 0x082A - TimeUnit for C-State Latency Control2 TimeUnit for C-State Latency Control2;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns **/ UINT8 CstateLatencyControl2TimeUnit; -/** Offset 0x07F3 - TimeUnit for C-State Latency Control3 +/** Offset 0x082B - TimeUnit for C-State Latency Control3 TimeUnit for C-State Latency Control3;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns **/ UINT8 CstateLatencyControl3TimeUnit; -/** Offset 0x07F4 - TimeUnit for C-State Latency Control4 +/** Offset 0x082C - TimeUnit for C-State Latency Control4 Time - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns **/ UINT8 CstateLatencyControl4TimeUnit; -/** Offset 0x07F5 - TimeUnit for C-State Latency Control5 +/** Offset 0x082D - TimeUnit for C-State Latency Control5 TimeUnit for C-State Latency Control5;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns **/ UINT8 CstateLatencyControl5TimeUnit; -/** Offset 0x07F6 - Interrupt Redirection Mode Select +/** Offset 0x082E - Interrupt Redirection Mode Select Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;4: PAIR with fixed priority;5: PAIR with round robin;6: PAIR with hash vector;7: No change. **/ UINT8 PpmIrmSetting; -/** Offset 0x07F7 - Lock prochot configuration +/** Offset 0x082F - Lock prochot configuration Lock prochot configuration Enable/Disable; 0: Disable; 1: Enable $EN_DIS **/ UINT8 ProcHotLock; -/** Offset 0x07F8 - Configuration for boot TDP selection +/** Offset 0x0830 - Configuration for boot TDP selection Configuration for boot TDP selection; 0: TDP Nominal; 1: TDP Down; 2: TDP Up;0xFF : Deactivate **/ UINT8 ConfigTdpLevel; -/** Offset 0x07F9 - Race To Halt +/** Offset 0x0831 - Race To Halt Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency in order to enter pkg C-State faster to reduce overall power. (RTH is controlled through MSR 1FC bit 20)Disable; 1: Enable @@ -3001,19 +3067,19 @@ **/ UINT8 RaceToHalt; -/** Offset 0x07FA - Max P-State Ratio +/** Offset 0x0832 - Max P-State Ratio Max P-State Ratio, Valid Range 0 to 0x7F **/ UINT8 MaxRatio; -/** Offset 0x07FB - P-state ratios for custom P-state table +/** Offset 0x0833 - P-state ratios for custom P-state table P-state ratios for custom P-state table. NumberOfEntries has valid range between 0 to 40. For no. of P-States supported(NumberOfEntries) , StateRatio[NumberOfEntries] are configurable. Valid Range of each entry is 0 to 0x7F **/ UINT8 StateRatio[40]; -/** Offset 0x0823 - P-state ratios for max 16 version of custom P-state table +/** Offset 0x085B - P-state ratios for max 16 version of custom P-state table P-state ratios for max 16 version of custom P-state table. This table is used for OS versions limited to a max of 16 P-States. If the first entry of this table is 0, or if Number of Entries is 16 or less, then this table will be ignored, and @@ -3022,391 +3088,391 @@ **/ UINT8 StateRatioMax16[16]; -/** Offset 0x0833 +/** Offset 0x086B **/ - UINT8 UnusedUpdSpace25; + UINT8 UnusedUpdSpace26; -/** Offset 0x0834 - Platform Power Pmax +/** Offset 0x086C - Platform Power Pmax PCODE MMIO Mailbox: Platform Power Pmax. 0 - Auto Specified in 1/8 Watt increments. Range 0-1024 Watts. Value of 800 = 100W **/ UINT16 PsysPmax; -/** Offset 0x0836 - Interrupt Response Time Limit of C-State LatencyContol0 +/** Offset 0x086E - Interrupt Response Time Limit of C-State LatencyContol0 Interrupt Response Time Limit of C-State LatencyContol0.Range of value 0 to 0x3FF **/ UINT16 CstateLatencyControl0Irtl; -/** Offset 0x0838 - Interrupt Response Time Limit of C-State LatencyContol1 +/** Offset 0x0870 - Interrupt Response Time Limit of C-State LatencyContol1 Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF **/ UINT16 CstateLatencyControl1Irtl; -/** Offset 0x083A - Interrupt Response Time Limit of C-State LatencyContol2 +/** Offset 0x0872 - Interrupt Response Time Limit of C-State LatencyContol2 Interrupt Response Time Limit of C-State LatencyContol2.Range of value 0 to 0x3FF **/ UINT16 CstateLatencyControl2Irtl; -/** Offset 0x083C - Interrupt Response Time Limit of C-State LatencyContol3 +/** Offset 0x0874 - Interrupt Response Time Limit of C-State LatencyContol3 Interrupt Response Time Limit of C-State LatencyContol3.Range of value 0 to 0x3FF **/ UINT16 CstateLatencyControl3Irtl; -/** Offset 0x083E - Interrupt Response Time Limit of C-State LatencyContol4 +/** Offset 0x0876 - Interrupt Response Time Limit of C-State LatencyContol4 Interrupt Response Time Limit of C-State LatencyContol4.Range of value 0 to 0x3FF **/ UINT16 CstateLatencyControl4Irtl; -/** Offset 0x0840 - Interrupt Response Time Limit of C-State LatencyContol5 +/** Offset 0x0878 - Interrupt Response Time Limit of C-State LatencyContol5 Interrupt Response Time Limit of C-State LatencyContol5.Range of value 0 to 0x3FF **/ UINT16 CstateLatencyControl5Irtl; -/** Offset 0x0842 +/** Offset 0x087A **/ - UINT8 UnusedUpdSpace26[2]; + UINT8 UnusedUpdSpace27[2]; -/** Offset 0x0844 - Package Long duration turbo mode power limit +/** Offset 0x087C - Package Long duration turbo mode power limit Package Long duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 PowerLimit1; -/** Offset 0x0848 - Package Short duration turbo mode power limit +/** Offset 0x0880 - Package Short duration turbo mode power limit Package Short duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 PowerLimit2Power; -/** Offset 0x084C - Package PL3 power limit +/** Offset 0x0884 - Package PL3 power limit Package PL3 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 PowerLimit3; -/** Offset 0x0850 - Package PL4 power limit +/** Offset 0x0888 - Package PL4 power limit Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 1023875 in Step size of 125 **/ UINT32 PowerLimit4; -/** Offset 0x0854 - Tcc Offset Time Window for RATL +/** Offset 0x088C - Tcc Offset Time Window for RATL Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 1023875 in Step size of 125 **/ UINT32 TccOffsetTimeWindowForRatl; -/** Offset 0x0858 - Short term Power Limit value for custom cTDP level 1 +/** Offset 0x0890 - Short term Power Limit value for custom cTDP level 1 Short term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 Custom1PowerLimit1; -/** Offset 0x085C - Long term Power Limit value for custom cTDP level 1 +/** Offset 0x0894 - Long term Power Limit value for custom cTDP level 1 Long term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 Custom1PowerLimit2; -/** Offset 0x0860 - Short term Power Limit value for custom cTDP level 2 +/** Offset 0x0898 - Short term Power Limit value for custom cTDP level 2 Short term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 Custom2PowerLimit1; -/** Offset 0x0864 - Long term Power Limit value for custom cTDP level 2 +/** Offset 0x089C - Long term Power Limit value for custom cTDP level 2 Long term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 Custom2PowerLimit2; -/** Offset 0x0868 - Short term Power Limit value for custom cTDP level 3 +/** Offset 0x08A0 - Short term Power Limit value for custom cTDP level 3 Short term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 Custom3PowerLimit1; -/** Offset 0x086C - Long term Power Limit value for custom cTDP level 3 +/** Offset 0x08A4 - Long term Power Limit value for custom cTDP level 3 Long term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 Custom3PowerLimit2; -/** Offset 0x0870 - Platform PL1 power +/** Offset 0x08A8 - Platform PL1 power Platform PL1 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 PsysPowerLimit1Power; -/** Offset 0x0874 - Platform PL2 power +/** Offset 0x08AC - Platform PL2 power Platform PL2 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 PsysPowerLimit2Power; -/** Offset 0x0878 - Set Three Strike Counter Disable +/** Offset 0x08B0 - Set Three Strike Counter Disable False (default): Three Strike counter will be incremented and True: Prevents Three Strike counter from incrementing; 0: False; 1: True. 0: False, 1: True **/ UINT8 ThreeStrikeCounterDisable; -/** Offset 0x0879 - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT +/** Offset 0x08B1 - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 HwpInterruptControl; -/** Offset 0x087A - 5-Core Ratio Limit +/** Offset 0x08B2 - 5-Core Ratio Limit 5-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 5-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 0x0:0xFF **/ UINT8 FiveCoreRatioLimit; -/** Offset 0x087B - 6-Core Ratio Limit +/** Offset 0x08B3 - 6-Core Ratio Limit 6-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 6-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 0x0:0xFF **/ UINT8 SixCoreRatioLimit; -/** Offset 0x087C - 7-Core Ratio Limit +/** Offset 0x08B4 - 7-Core Ratio Limit 7-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 7-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 0x0:0xFF **/ UINT8 SevenCoreRatioLimit; -/** Offset 0x087D - 8-Core Ratio Limit +/** Offset 0x08B5 - 8-Core Ratio Limit 8-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 8-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 0x0:0xFF **/ UINT8 EightCoreRatioLimit; -/** Offset 0x087E - Intel Turbo Boost Max Technology 3.0 +/** Offset 0x08B6 - Intel Turbo Boost Max Technology 3.0 Intel Turbo Boost Max Technology 3.0. 0: Disabled; 1: Enabled $EN_DIS **/ UINT8 EnableItbm; -/** Offset 0x087F - Intel Turbo Boost Max Technology 3.0 Driver +/** Offset 0x08B7 - Intel Turbo Boost Max Technology 3.0 Driver Intel Turbo Boost Max Technology 3.0 Driver 0: Disabled; 1: Enabled $EN_DIS **/ UINT8 EnableItbmDriver; -/** Offset 0x0880 - Enable or Disable C1 Cstate Demotion +/** Offset 0x08B8 - Enable or Disable C1 Cstate Demotion Enable or Disable C1 Cstate Demotion. Disable; 1: Enable $EN_DIS **/ UINT8 C1StateAutoDemotion; -/** Offset 0x0881 - Enable or Disable C1 Cstate UnDemotion +/** Offset 0x08B9 - Enable or Disable C1 Cstate UnDemotion Enable or Disable C1 Cstate UnDemotion. Disable; 1: Enable $EN_DIS **/ UINT8 C1StateUnDemotion; -/** Offset 0x0882 - CpuWakeUpTimer +/** Offset 0x08BA - CpuWakeUpTimer Enable long CPU Wakeup Timer. When enabled, the cpu internal wakeup time is increased to 180 seconds. 0: Disable; 1: Enable $EN_DIS **/ UINT8 CpuWakeUpTimer; -/** Offset 0x0883 - Minimum Ring ratio limit override +/** Offset 0x08BB - Minimum Ring ratio limit override Minimum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo ratio limit **/ UINT8 MinRingRatioLimit; -/** Offset 0x0884 - Minimum Ring ratio limit override +/** Offset 0x08BC - Minimum Ring ratio limit override Maximum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo ratio limit **/ UINT8 MaxRingRatioLimit; -/** Offset 0x0885 - Enable or Disable C3 Cstate Demotion +/** Offset 0x08BD - Enable or Disable C3 Cstate Demotion Enable or Disable C3 Cstate Demotion. Disable; 1: Enable $EN_DIS **/ UINT8 C3StateAutoDemotion; -/** Offset 0x0886 - Enable or Disable C3 Cstate UnDemotion +/** Offset 0x08BE - Enable or Disable C3 Cstate UnDemotion Enable or Disable C3 Cstate UnDemotion. Disable; 1: Enable $EN_DIS **/ UINT8 C3StateUnDemotion; -/** Offset 0x0887 - ReservedCpuPostMemTest +/** Offset 0x08BF - ReservedCpuPostMemTest Reserved for CPU Post-Mem Test $EN_DIS **/ UINT8 ReservedCpuPostMemTest[19]; -/** Offset 0x089A - SgxSinitDataFromTpm +/** Offset 0x08D2 - SgxSinitDataFromTpm SgxSinitDataFromTpm default values **/ UINT8 SgxSinitDataFromTpm; -/** Offset 0x089B - End of Post message +/** Offset 0x08D3 - End of Post message Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1): EOP send in PEI, Send in DXE(0x2)(Default): EOP send in PEI 0:Disable, 1:Send in PEI, 2:Send in DXE, 3:Reserved **/ UINT8 EndOfPostMessage; -/** Offset 0x089C - D0I3 Setting for HECI Disable +/** Offset 0x08D4 - D0I3 Setting for HECI Disable Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all HECI devices $EN_DIS **/ UINT8 DisableD0I3SettingForHeci; -/** Offset 0x089D +/** Offset 0x08D5 **/ - UINT8 UnusedUpdSpace27; + UINT8 UnusedUpdSpace28; -/** Offset 0x089E - HD Audio Reset Wait Timer +/** Offset 0x08D6 - HD Audio Reset Wait Timer The delay timer after Azalia reset, the value is number of microseconds. Default is 600. **/ UINT16 PchHdaResetWaitTimer; -/** Offset 0x08A0 - Enable LOCKDOWN SMI +/** Offset 0x08D8 - Enable LOCKDOWN SMI Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. $EN_DIS **/ UINT8 PchLockDownGlobalSmi; -/** Offset 0x08A1 - Enable LOCKDOWN BIOS Interface +/** Offset 0x08D9 - Enable LOCKDOWN BIOS Interface Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register. $EN_DIS **/ UINT8 PchLockDownBiosInterface; -/** Offset 0x08A2 - Unlock all GPIO pads +/** Offset 0x08DA - Unlock all GPIO pads Force all GPIO pads to be unlocked for debug purpose. $EN_DIS **/ UINT8 PchUnlockGpioPads; -/** Offset 0x08A3 - PCH Unlock SideBand access +/** Offset 0x08DB - PCH Unlock SideBand access The SideBand PortID mask for certain end point (e.g. PSFx) will be locked before 3rd party code execution. 0: Lock SideBand access; 1: Unlock SideBand access. $EN_DIS **/ UINT8 PchSbAccessUnlock; -/** Offset 0x08A4 - PCIE RP Ltr Max Snoop Latency +/** Offset 0x08DC - PCIE RP Ltr Max Snoop Latency Latency Tolerance Reporting, Max Snoop Latency. **/ UINT16 PcieRpLtrMaxSnoopLatency[24]; -/** Offset 0x08D4 - PCIE RP Ltr Max No Snoop Latency +/** Offset 0x090C - PCIE RP Ltr Max No Snoop Latency Latency Tolerance Reporting, Max Non-Snoop Latency. **/ UINT16 PcieRpLtrMaxNoSnoopLatency[24]; -/** Offset 0x0904 - PCIE RP Snoop Latency Override Mode +/** Offset 0x093C - PCIE RP Snoop Latency Override Mode Latency Tolerance Reporting, Snoop Latency Override Mode. **/ UINT8 PcieRpSnoopLatencyOverrideMode[24]; -/** Offset 0x091C - PCIE RP Snoop Latency Override Multiplier +/** Offset 0x0954 - PCIE RP Snoop Latency Override Multiplier Latency Tolerance Reporting, Snoop Latency Override Multiplier. **/ UINT8 PcieRpSnoopLatencyOverrideMultiplier[24]; -/** Offset 0x0934 - PCIE RP Snoop Latency Override Value +/** Offset 0x096C - PCIE RP Snoop Latency Override Value Latency Tolerance Reporting, Snoop Latency Override Value. **/ UINT16 PcieRpSnoopLatencyOverrideValue[24]; -/** Offset 0x0964 - PCIE RP Non Snoop Latency Override Mode +/** Offset 0x099C - PCIE RP Non Snoop Latency Override Mode Latency Tolerance Reporting, Non-Snoop Latency Override Mode. **/ UINT8 PcieRpNonSnoopLatencyOverrideMode[24]; -/** Offset 0x097C - PCIE RP Non Snoop Latency Override Multiplier +/** Offset 0x09B4 - PCIE RP Non Snoop Latency Override Multiplier Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier. **/ UINT8 PcieRpNonSnoopLatencyOverrideMultiplier[24]; -/** Offset 0x0994 - PCIE RP Non Snoop Latency Override Value +/** Offset 0x09CC - PCIE RP Non Snoop Latency Override Value Latency Tolerance Reporting, Non-Snoop Latency Override Value. **/ UINT16 PcieRpNonSnoopLatencyOverrideValue[24]; -/** Offset 0x09C4 - PCIE RP Slot Power Limit Scale +/** Offset 0x09FC - PCIE RP Slot Power Limit Scale Specifies scale used for slot power limit value. Leave as 0 to set to default. **/ UINT8 PcieRpSlotPowerLimitScale[24]; -/** Offset 0x09DC - PCIE RP Slot Power Limit Value +/** Offset 0x0A14 - PCIE RP Slot Power Limit Value Specifies upper limit on power supplie by slot. Leave as 0 to set to default. **/ UINT16 PcieRpSlotPowerLimitValue[24]; -/** Offset 0x0A0C - PCIE RP Upstream Port Transmiter Preset +/** Offset 0x0A44 - PCIE RP Upstream Port Transmiter Preset Used during Gen3 Link Equalization. Used for all lanes. Default is 5. **/ UINT8 PcieRpUptp[24]; -/** Offset 0x0A24 - PCIE RP Downstream Port Transmiter Preset +/** Offset 0x0A5C - PCIE RP Downstream Port Transmiter Preset Used during Gen3 Link Equalization. Used for all lanes. Default is 7. **/ UINT8 PcieRpDptp[24]; -/** Offset 0x0A3C - PCIE RP Enable Port8xh Decode +/** Offset 0x0A74 - PCIE RP Enable Port8xh Decode This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PcieEnablePort8xhDecode; -/** Offset 0x0A3D - PCIE Port8xh Decode Port Index +/** Offset 0x0A75 - PCIE Port8xh Decode Port Index The Index of PCIe Port that is selected for Port8xh Decode (0 Based). **/ UINT8 PchPciePort8xhDecodePortIndex; -/** Offset 0x0A3E - PCH Energy Reporting +/** Offset 0x0A76 - PCH Energy Reporting Disable/Enable PCH to CPU energy report feature. $EN_DIS **/ UINT8 PchPmDisableEnergyReport; -/** Offset 0x0A3F - PCH Sata Test Mode +/** Offset 0x0A77 - PCH Sata Test Mode Allow entrance to the PCH SATA test modes. $EN_DIS **/ UINT8 SataTestMode; -/** Offset 0x0A40 - PCH USB OverCurrent mapping lock enable +/** Offset 0x0A78 - PCH USB OverCurrent mapping lock enable If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning that OC mapping data will be consumed by xHCI and OC mapping registers will be locked. $EN_DIS **/ UINT8 PchXhciOcLock; -/** Offset 0x0A41 - ReservedPchPostMemTest +/** Offset 0x0A79 - ReservedPchPostMemTest Reserved for Pch Post-Mem Test $EN_DIS **/ UINT8 ReservedPchPostMemTest[16]; -/** Offset 0x0A51 - Mctp Broadcast Cycle +/** Offset 0x0A89 - Mctp Broadcast Cycle Test, Determine if MCTP Broadcast is enabled 0: Disable; 1: Enable. $EN_DIS **/ UINT8 MctpBroadcastCycle; -/** Offset 0x0A52 +/** Offset 0x0A8A **/ - UINT8 UnusedUpdSpace28[2]; + UINT8 UnusedUpdSpace29[2]; -/** Offset 0x0A54 +/** Offset 0x0A8C **/ UINT8 ReservedFspsTestUpd[12]; } FSP_S_TEST_CONFIG; @@ -3423,15 +3489,15 @@ **/ FSP_S_CONFIG FspsConfig; -/** Offset 0x0788 +/** Offset 0x07C0 **/ FSP_S_TEST_CONFIG FspsTestConfig; -/** Offset 0x0A60 +/** Offset 0x0A98 **/ - UINT8 UnusedUpdSpace29[6]; + UINT8 UnusedUpdSpace30[6]; -/** Offset 0x0A66 +/** Offset 0x0A9E **/ UINT16 UpdTerminator; } FSPS_UPD; -- To view, visit https://review.coreboot.org/c/coreboot/+/32844 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d412424f9f5c5d2d56b789c2fef4bdb817a3019 Gerrit-Change-Number: 32844 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/arcada: Disable Heci1
by Bora Guvendik (Code Review) 12 Jun '19

12 Jun '19

Bora Guvendik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32994 Change subject: mb/google/arcada: Disable Heci1 ...................................................................... mb/google/arcada: Disable Heci1 Change-Id: I1ea5326192c95936c39612c425db0289c8c40601 Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- M src/mainboard/google/sarien/variants/sarien/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/32994/1 diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index c96423c..27b928f 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -30,6 +30,7 @@ register "PchPmSlpS4MinAssert" = "4" # 4s register "PchPmSlpSusMinAssert" = "4" # 4s register "PchPmSlpAMinAssert" = "4" # 2s + register "Heci1Disabled" = "1" register "speed_shift_enable" = "1" register "s0ix_enable" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/32994 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ea5326192c95936c39612c425db0289c8c40601 Gerrit-Change-Number: 32994 Gerrit-PatchSet: 1 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-MessageType: newchange

1 2

Change in ...coreboot[master]: mb/google/arcada: Disable Heci1
by Bora Guvendik (Code Review) 12 Jun '19

12 Jun '19

Bora Guvendik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32993 Change subject: mb/google/arcada: Disable Heci1 ...................................................................... mb/google/arcada: Disable Heci1 Change-Id: Ic886389bbeaa869ffc4dfad77382522115c4d8dc Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/32993/1 diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index d3848a2..2e050b0 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -27,6 +27,7 @@ register "PchPmSlpSusMinAssert" = "4" # 4s register "PchPmSlpAMinAssert" = "4" # 2s register "PchUnlockGpioPads" = "1" + register "Heci1Disabled" = "1" register "speed_shift_enable" = "1" register "psys_pmax" = "140" -- To view, visit https://review.coreboot.org/c/coreboot/+/32993 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic886389bbeaa869ffc4dfad77382522115c4d8dc Gerrit-Change-Number: 32993 Gerrit-PatchSet: 1 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-MessageType: newchange

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