coreboot-gerrit March 2019

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Change in ...coreboot[master]: vboot: move assert in vboot_migrate_cbmem
by Joel Kitching (Code Review) 18 Mar '19

18 Mar '19

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31923 Change subject: vboot: move assert in vboot_migrate_cbmem ...................................................................... vboot: move assert in vboot_migrate_cbmem Fix a potential null pointer dereference when calling memcpy. assert should be before the memcpy call, and not after. BUG=b:124141368, b:124192753 TEST=util/lint/checkpatch.pl -g origin/master..HEAD TEST=util/abuild/abuild -B -e -y -c 50 -p none -x TEST=make clean && make test-abuild BRANCH=none Change-Id: I5a2a99e906b9aa3bb33e1564d8d33a0aca7d06ac Signed-off-by: Joel Kitching <kitching(a)google.com> --- M src/security/vboot/common.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/31923/1 diff --git a/src/security/vboot/common.c b/src/security/vboot/common.c index 496ab78..47e1aa4 100644 --- a/src/security/vboot/common.c +++ b/src/security/vboot/common.c @@ -163,11 +163,12 @@ size_t cbmem_size = wd_preram->buffer_offset + wd_preram->buffer_size; struct vboot_working_data *wd_cbmem = cbmem_add(CBMEM_ID_VBOOT_WORKBUF, cbmem_size); + assert(wd_cbmem != NULL); + printk(BIOS_DEBUG, "VBOOT: copying vboot_working_data (%zu bytes) to CBMEM...\n", cbmem_size); memcpy(wd_cbmem, wd_preram, cbmem_size); - assert(wd_cbmem != NULL); } ROMSTAGE_CBMEM_INIT_HOOK(vboot_migrate_cbmem) #elif CONFIG(VBOOT_STARTS_IN_ROMSTAGE) -- To view, visit https://review.coreboot.org/c/coreboot/+/31923 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a2a99e906b9aa3bb33e1564d8d33a0aca7d06ac Gerrit-Change-Number: 31923 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/nsc/common/nsc.h: Drop unused includes
by HAOUAS Elyes (Code Review) 18 Mar '19

18 Mar '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31925 Change subject: src/nsc/common/nsc.h: Drop unused includes ...................................................................... src/nsc/common/nsc.h: Drop unused includes Change-Id: Id3501e65a9d0c0b5ad98679f5e78f985e87cbe55 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/superio/nsc/common/nsc.h 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/31925/1 diff --git a/src/superio/nsc/common/nsc.h b/src/superio/nsc/common/nsc.h index c2d732c..bc123d4 100644 --- a/src/superio/nsc/common/nsc.h +++ b/src/superio/nsc/common/nsc.h @@ -18,7 +18,6 @@ #ifndef SUPERIO_NSC_COMMON_PRE_RAM_H #define SUPERIO_NSC_COMMON_PRE_RAM_H -#include <device/pnp_def.h> #include <stdint.h> #include <device/pnp_type.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/31925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id3501e65a9d0c0b5ad98679f5e78f985e87cbe55 Gerrit-Change-Number: 31925 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/(ICH7): Do not try to rewrite on V1CAP register
by HAOUAS Elyes (Code Review) 18 Mar '19

18 Mar '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31004 Change subject: mb/(ICH7): Do not try to rewrite on V1CAP register ...................................................................... mb/(ICH7): Do not try to rewrite on V1CAP register V1CAP is a write-once register, and it is already programmd in intel/i945/early_init.c Change-Id: I4469cb7505d584f10c98aec579a2d78bf1950bf3 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/apple/macbook21/romstage.c M src/mainboard/getac/p470/romstage.c M src/mainboard/ibase/mb899/romstage.c M src/mainboard/intel/d945gclf/romstage.c M src/mainboard/lenovo/t60/romstage.c M src/mainboard/lenovo/x60/romstage.c M src/mainboard/lenovo/z61t/romstage.c 7 files changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/31004/1 diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c index ad184a8..4e1fd96 100644 --- a/src/mainboard/apple/macbook21/romstage.c +++ b/src/mainboard/apple/macbook21/romstage.c @@ -143,8 +143,6 @@ { /* V0CTL Virtual Channel 0 Resource Control */ RCBA32(0x0014) = 0x80000001; - /* V1CAP Virtual Channel 1 Resource Capability */ - RCBA32(0x001c) = 0x03128010; /* Device 1f interrupt pin register */ RCBA32(0x3100) = 0x00042210; diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index 471977f..6c5b441 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -146,7 +146,6 @@ { /* Set up virtual channel 0 */ //RCBA32(0x0014) = 0x80000001; - //RCBA32(0x001c) = 0x03128010; /* Device 1f interrupt pin register */ RCBA32(D31IP) = 0x00042220; diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 9eaa8de..aa8878d 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -124,7 +124,6 @@ { /* Set up virtual channel 0 */ //RCBA32(0x0014) = 0x80000001; - //RCBA32(0x001c) = 0x03128010; /* Device 1f interrupt pin register */ RCBA32(D31IP) = 0x00042210; diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index 5e3535a..35213a9 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -48,7 +48,6 @@ { /* Set up virtual channel 0 */ //RCBA32(0x0014) = 0x80000001; - //RCBA32(0x001c) = 0x03128010; /* dev irq route register */ RCBA16(D31IR) = 0x0132; diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index 3017357..f10f447 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -75,7 +75,6 @@ { /* Set up virtual channel 0 */ RCBA32(V0CTL) = 0x80000001; - RCBA32(V1CAP) = 0x03128010; /* Device 1f interrupt pin register */ RCBA32(D31IP) = 0x00001230; diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 6f66c88..1a2bc28 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -74,7 +74,6 @@ { /* Set up virtual channel 0 */ RCBA32(V0CTL) = 0x80000001; - RCBA32(V1CAP) = 0x03128010; /* Device 1f interrupt pin register */ RCBA32(D31IP) = 0x00001230; diff --git a/src/mainboard/lenovo/z61t/romstage.c b/src/mainboard/lenovo/z61t/romstage.c index 6eceaeb..5dae395 100644 --- a/src/mainboard/lenovo/z61t/romstage.c +++ b/src/mainboard/lenovo/z61t/romstage.c @@ -75,7 +75,6 @@ { /* Set up virtual channel 0 */ RCBA32(V0CTL) = 0x80000001; - RCBA32(V1CAP) = 0x03128010; /* Device 1f interrupt pin register */ RCBA32(D31IP) = 0x00001230; -- To view, visit https://review.coreboot.org/c/coreboot/+/31004 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4469cb7505d584f10c98aec579a2d78bf1950bf3 Gerrit-Change-Number: 31004 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/intel/i945: Don't try to rewrite on SLOTCAP
by HAOUAS Elyes (Code Review) 18 Mar '19

18 Mar '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31036 Change subject: nb/intel/i945: Don't try to rewrite on SLOTCAP ...................................................................... nb/intel/i945: Don't try to rewrite on SLOTCAP SLOTCAP is R/WO, it becomes RO after the first write. Change-Id: I27579bc634e357490defabb041457aaa010fb1c8 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/early_init.c 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/31036/1 diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 09a18e3..15c3a33 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -719,9 +719,6 @@ reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x328); pci_write_config32(PCI_DEV(0, 0x01, 0), 0x328, reg32); - reg8 = pci_read_config8(PCI_DEV(0, 0x01, 0), SLOTCAP); - pci_write_config8(PCI_DEV(0, 0x01, 0), SLOTCAP, reg8); - /* Additional PCIe graphics setup */ reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xf0); reg32 |= (3 << 26); -- To view, visit https://review.coreboot.org/c/coreboot/+/31036 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27579bc634e357490defabb041457aaa010fb1c8 Gerrit-Change-Number: 31036 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: ec/google/wilco: Enable software sync for VBOOT
by Duncan Laurie (Code Review) 18 Mar '19

18 Mar '19

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31920 Change subject: ec/google/wilco: Enable software sync for VBOOT ...................................................................... ec/google/wilco: Enable software sync for VBOOT Enable software sync by default if VBOOT is enabled. The slow update option is also needed, but this is moving to depthcharge so it is not defined here. Change-Id: I046661fae7315f84e96293532b4e1568558df962 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/ec/google/wilco/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/31920/1 diff --git a/src/ec/google/wilco/Kconfig b/src/ec/google/wilco/Kconfig index 4202c1d..f4a4111 100644 --- a/src/ec/google/wilco/Kconfig +++ b/src/ec/google/wilco/Kconfig @@ -3,6 +3,7 @@ default n select EC_GOOGLE_COMMON_MEC select EC_ACPI + select VBOOT_EC_SOFTWARE_SYNC if VBOOT help Google Wilco Embedded Controller interface. -- To view, visit https://review.coreboot.org/c/coreboot/+/31920 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I046661fae7315f84e96293532b4e1568558df962 Gerrit-Change-Number: 31920 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: ec/google/wilco: Fix handling of commands that do not respond
by Duncan Laurie (Code Review) 18 Mar '19

18 Mar '19

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31919 Change subject: ec/google/wilco: Fix handling of commands that do not respond ...................................................................... ec/google/wilco: Fix handling of commands that do not respond If the command does not respond the driver should not wait for it to complete before returning. Tested with SMI debug enabled to ensure that the final command does not report a failure. Change-Id: I7c1bfa19a92e8332ac1aa6ff95f94ff4cbdf789d Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/ec/google/wilco/mailbox.c 1 file changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/31919/1 diff --git a/src/ec/google/wilco/mailbox.c b/src/ec/google/wilco/mailbox.c index 1c38a5b..d47290c 100644 --- a/src/ec/google/wilco/mailbox.c +++ b/src/ec/google/wilco/mailbox.c @@ -155,12 +155,6 @@ /* Start the command */ outb(EC_MAILBOX_START_COMMAND, CONFIG_EC_BASE_HOST_COMMAND); - /* Wait for it to complete */ - if (wilco_ec_response_timed_out()) { - printk(BIOS_ERR, "%s: response timed out\n", __func__); - return -1; - } - /* Some commands will put the EC into a state where it cannot respond */ if (msg->type == WILCO_EC_MSG_NO_RESPONSE) { printk(BIOS_DEBUG, "%s: EC does not respond to this command\n", @@ -168,6 +162,12 @@ return 0; } + /* Wait for it to complete */ + if (wilco_ec_response_timed_out()) { + printk(BIOS_ERR, "%s: response timed out\n", __func__); + return -1; + } + /* Check result */ msg->result = inb(CONFIG_EC_BASE_HOST_DATA); if (msg->result != 0) { -- To view, visit https://review.coreboot.org/c/coreboot/+/31919 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c1bfa19a92e8332ac1aa6ff95f94ff4cbdf789d Gerrit-Change-Number: 31919 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/common: Update ESPI disable option
by Duncan Laurie (Code Review) 18 Mar '19

18 Mar '19

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31918 Change subject: soc/intel/common: Update ESPI disable option ...................................................................... soc/intel/common: Update ESPI disable option Update the Kconfig option for disabling ESPI SMI source to disable it entirely, not just when ACPI mode is disabled. For the situations where this is needed (just the sarien board) it is better to completely stop the EC from sending any SMI events as no actions are taken. Change-Id: Id94481bb2f0cfc948f350be45d360bfe40ddf018 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/mainboard/google/sarien/Kconfig M src/soc/intel/common/block/smm/Kconfig M src/soc/intel/common/block/smm/smihandler.c M src/soc/intel/common/block/smm/smm.c 4 files changed, 10 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/31918/1 diff --git a/src/mainboard/google/sarien/Kconfig b/src/mainboard/google/sarien/Kconfig index 8f8b37c..6164c8e 100644 --- a/src/mainboard/google/sarien/Kconfig +++ b/src/mainboard/google/sarien/Kconfig @@ -18,7 +18,7 @@ select SOC_INTEL_COMMON_ACPI_EC_PTS_WAK select SOC_INTEL_WHISKEYLAKE select SOC_INTEL_COMMON_BLOCK_HDA_VERB - select SOC_INTEL_COMMON_BLOCK_SMM_ESPI_ACPI_DIS + select SOC_INTEL_COMMON_BLOCK_SMM_ESPI_DISABLE select SPD_READ_BY_WORD select SYSTEM_TYPE_LAPTOP if BOARD_GOOGLE_SARIEN select SYSTEM_TYPE_CONVERTIBLE if BOARD_GOOGLE_ARCADA diff --git a/src/soc/intel/common/block/smm/Kconfig b/src/soc/intel/common/block/smm/Kconfig index cc6bc44..a58c631 100644 --- a/src/soc/intel/common/block/smm/Kconfig +++ b/src/soc/intel/common/block/smm/Kconfig @@ -8,13 +8,12 @@ help Intel Processor trap flag if it is supported -config SOC_INTEL_COMMON_BLOCK_SMM_ESPI_ACPI_DIS +config SOC_INTEL_COMMON_BLOCK_SMM_ESPI_DISABLE bool default n help - Disable eSPI SMI when ACPI mode is enabled. This will - prevent the embedded controller from asserting SMI when - booted into an ACPI aware OS. + Disable eSPI SMI source to prevent the embedded controller + from asserting SMI while in firmware. config SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS int diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index 16bb3a2..7aa69c5 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -361,14 +361,10 @@ break; case APM_CNT_ACPI_DISABLE: pmc_disable_pm1_control(SCI_EN); - if (CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_ESPI_ACPI_DIS)) - pmc_enable_smi(ESPI_SMI_EN); printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n"); break; case APM_CNT_ACPI_ENABLE: pmc_enable_pm1_control(SCI_EN); - if (CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_ESPI_ACPI_DIS)) - pmc_disable_smi(ESPI_SMI_EN); printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); break; case APM_CNT_GNVS_UPDATE: diff --git a/src/soc/intel/common/block/smm/smm.c b/src/soc/intel/common/block/smm/smm.c index dd8bab3..75b933e 100644 --- a/src/soc/intel/common/block/smm/smm.c +++ b/src/soc/intel/common/block/smm/smm.c @@ -41,6 +41,8 @@ void smm_southbridge_enable(uint16_t pm1_events) { + uint32_t smi_params = ENABLE_SMI_PARAMS; + printk(BIOS_DEBUG, "Enabling SMIs.\n"); /* Configure events */ pmc_enable_pm1(pm1_events); @@ -60,14 +62,16 @@ * - on APMC writes (io 0xb2) * - on writes to SLP_EN (sleep states) * - on writes to GBL_RLS (bios commands) - * - on eSPI events (does nothing on LPC systems) + * - on eSPI events, unless disabled (does nothing on LPC systems) * No SMIs: * - on microcontroller writes (io 0x62/0x66) * - on TCO events */ + if (CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_ESPI_DISABLE)) + smi_params &= ~ESPI_SMI_EN; /* Enable SMI generation: */ - pmc_enable_smi(ENABLE_SMI_PARAMS); + pmc_enable_smi(smi_params); } void smm_setup_structures(void *gnvs, void *tcg, void *smi1) @@ -94,11 +98,3 @@ *start = (void *)sa_get_tseg_base(); *size = sa_get_tseg_size(); } - -#if CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_ESPI_ACPI_DIS) -static void smm_disable_espi(void *dest) -{ - pmc_disable_smi(ESPI_SMI_EN); -} -BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, smm_disable_espi, NULL); -#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/31918 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id94481bb2f0cfc948f350be45d360bfe40ddf018 Gerrit-Change-Number: 31918 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/sarien: Enable BT Rkfill
by Lijian Zhao (Code Review) 18 Mar '19

18 Mar '19

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31765 Change subject: mb/google/sarien: Enable BT Rkfill ...................................................................... mb/google/sarien: Enable BT Rkfill Add bluetooth Rfkill function for Intel Cnvi card rtd3 support. Clear Rfkill before entering runtime D3 state, and set when exiting from D3 state. The feature for DVT1 platform only. Bug=b:123342945 TEST=Confirm bluetooth functionaility on Arcada platform before and after one s0ix cycle. Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Change-Id: Ibbe67887227af42b6c040deade7bf5da4ce3227f --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/31765/1 diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 244ba7a..1d05eaa 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -1,3 +1,4 @@ +Hchip soc/intel/cannonlake chip soc/intel/cannonlake # GPE configuration @@ -242,6 +243,7 @@ chip drivers/usb/acpi register "desc" = ""Bluetooth"" register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H15)" device usb 2.9 on end end chip drivers/usb/acpi -- To view, visit https://review.coreboot.org/c/coreboot/+/31765 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibbe67887227af42b6c040deade7bf5da4ce3227f Gerrit-Change-Number: 31765 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/mb/sifive/hifive-unleashed: initialize Gigabit Ethernet Controller
by Xiang Wang (Code Review) 18 Mar '19

18 Mar '19

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31059 Change subject: src/mb/sifive/hifive-unleashed: initialize Gigabit Ethernet Controller ...................................................................... src/mb/sifive/hifive-unleashed: initialize Gigabit Ethernet Controller Initialize the clock of Gigabit Ethernet Controller and reset the PHY. Change-Id: I172dc518c9b48c122289bba5a65beece925410d4 Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/mainboard/sifive/hifive-unleashed/romstage.c M src/soc/sifive/fu540/clock.c 2 files changed, 61 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/31059/1 diff --git a/src/mainboard/sifive/hifive-unleashed/romstage.c b/src/mainboard/sifive/hifive-unleashed/romstage.c index 17d1aef..4eb7d55 100644 --- a/src/mainboard/sifive/hifive-unleashed/romstage.c +++ b/src/mainboard/sifive/hifive-unleashed/romstage.c @@ -27,6 +27,7 @@ #include <symbols.h> #include <cbfs.h> #include <soc/otp.h> +#include <soc/addressmap.h> static void update_dtb(void) { @@ -52,6 +53,30 @@ OTHER_HLS(i)->fdt = (void *)dtb_target; } +static void nsleep(long nsec) +{ + long setp = 600; + while(*(volatile long*)&nsec > 0) + *(volatile long*)&nsec -= setp; +} + +#define GPIO_REG(n) (*(uint32_t*)(FU540_GPIO + (n))) +#define GPIO_OUTPUT_EN 0x08 +#define GPIO_OUTPUT_VAL 0x0c + +static void phy_init(void) +{ +#define PHY_NRESET 0x1000 + nsleep(2000000); + __sync_fetch_and_or(&GPIO_REG(GPIO_OUTPUT_VAL), PHY_NRESET); + __sync_fetch_and_or(&GPIO_REG(GPIO_OUTPUT_EN), PHY_NRESET); + nsleep(100); + __sync_fetch_and_and(&GPIO_REG(GPIO_OUTPUT_VAL), ~PHY_NRESET); + nsleep(100); + __sync_fetch_and_or(&GPIO_REG(GPIO_OUTPUT_VAL), PHY_NRESET); + nsleep(15000000); +} + void main(void) { console_init(); @@ -71,6 +96,7 @@ uart_init(CONFIG_UART_FOR_CONSOLE); sdram_init(); + phy_init(); cbmem_initialize_empty(); diff --git a/src/soc/sifive/fu540/clock.c b/src/soc/sifive/fu540/clock.c index 597b206..7194c3c 100644 --- a/src/soc/sifive/fu540/clock.c +++ b/src/soc/sifive/fu540/clock.c @@ -59,6 +59,8 @@ #define PRCI_DDRPLLCFG1_MASK (1u << 31) +#define PRCI_GEMGXLPPLCFG1_MASK (1u << 31) + #define PRCI_CORECLKSEL_CORECLKSEL 1 #define PRCI_DEVICESRESET_DDR_CTRL_RST_N(x) (((x) & 0x1) << 0) @@ -141,6 +143,15 @@ .fse = 1, }; +static const struct pll_settings gemgxlpll_settings = { + .divr = 0, + .divf = 59, + .divq = 5, + .range = 4, + .bypass = 0, + .fse = 1, +}; + static void init_coreclk(void) { // switch coreclk to input reference frequency before modifying PLL @@ -168,6 +179,19 @@ write32(&prci->ddrpllcfg1, cfg1); } +static void init_gemgxlclk(void) +{ + u32 cfg1 = read32(&prci->gemgxlpllcfg1); + clrbits_le32(&cfg1, PRCI_GEMGXLPPLCFG1_MASK); + write32(&prci->gemgxlpllcfg1,cfg1); + + configure_pll(&prci->gemgxlpllcfg0, &gemgxlpll_settings); + + setbits_le32(&cfg1, PRCI_GEMGXLPPLCFG1_MASK); + write32(&prci->gemgxlpllcfg1,cfg1); +} + + #define FU540_UART_DEVICES 2 #define FU540_UART_REG_DIV 0x18 #define FU540_UART_DIV_VAL 4 @@ -227,6 +251,17 @@ // device? for (int i = 0; i < 256; i++) asm volatile ("nop"); + + init_gemgxlclk(); + + write32(&prci->devicesresetreg, + PRCI_DEVICESRESET_DDR_CTRL_RST_N(1) | + PRCI_DEVICESRESET_DDR_AXI_RST_N(1) | + PRCI_DEVICESRESET_DDR_AHB_RST_N(1) | + PRCI_DEVICESRESET_DDR_PHY_RST_N(1) | + PRCI_DEVICESRESET_GEMGXL_RST_N(1)); + + asm volatile ("fence"); } #endif /* ENV_ROMSTAGE */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31059 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I172dc518c9b48c122289bba5a65beece925410d4 Gerrit-Change-Number: 31059 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mainboard/google/kahlee: Don't use AMD's secure OS
by Martin Roth (Code Review) 18 Mar '19

18 Mar '19

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31890 Change subject: mainboard/google/kahlee: Don't use AMD's secure OS ...................................................................... mainboard/google/kahlee: Don't use AMD's secure OS Disable the use of AMD's Secure OS through the Kconfig option. BUG=chromium:903833 TEST=Building aleena with the updated AMDFWTool and a 0-byte secure OS file works correctly Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: Iabb0632eef88170dde45dea2e2e15b54b3a06f7b --- M src/mainboard/google/kahlee/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/31890/1 diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig index 1c46625..fe29870 100644 --- a/src/mainboard/google/kahlee/Kconfig +++ b/src/mainboard/google/kahlee/Kconfig @@ -141,4 +141,8 @@ depends on USE_OEM_BIN default "" +# Don't use AMD's Secure OS +config USE_PSPSCUREOS + def_bool n + endif # BOARD_GOOGLE_BASEBOARD_KAHLEE -- To view, visit https://review.coreboot.org/c/coreboot/+/31890 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabb0632eef88170dde45dea2e2e15b54b3a06f7b Gerrit-Change-Number: 31890 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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