coreboot-gerrit February 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: src/drivers/intel/wifi/Kconfig: enable NO_INTEL_WIFI if !SYSTEM_TYPE_...
by mikeb mikeb (Code Review) 03 Feb '19

03 Feb '19

Hello Mike Banon, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31220 to review the following change. Change subject: src/drivers/intel/wifi/Kconfig: enable NO_INTEL_WIFI if !SYSTEM_TYPE_LAPTOP ...................................................................... src/drivers/intel/wifi/Kconfig: enable NO_INTEL_WIFI if !SYSTEM_TYPE_LAPTOP Intel PCI-e WiFi adapters are rare outside of laptops. DRIVERS_INTEL_WIFI should not be selected by default if the mainboard is not a laptop. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I93a9e8fc9ba92f755524250e6cbcf9d1ba1acbdc --- M src/drivers/intel/wifi/Kconfig 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/31220/1 diff --git a/src/drivers/intel/wifi/Kconfig b/src/drivers/intel/wifi/Kconfig index 4082d7e..8fdd0a3 100644 --- a/src/drivers/intel/wifi/Kconfig +++ b/src/drivers/intel/wifi/Kconfig @@ -8,7 +8,9 @@ # Select this for mainboard which is unlikely to have Intel PCI-e WiFi adapter. config NO_INTEL_WIFI - def_bool n + bool + default y if !SYSTEM_TYPE_LAPTOP + default n config USE_SAR bool -- To view, visit https://review.coreboot.org/c/coreboot/+/31220 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93a9e8fc9ba92f755524250e6cbcf9d1ba1acbdc Gerrit-Change-Number: 31220 Gerrit-PatchSet: 1 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/intel/g45: Use a common romstage
by Angel Pons (Code Review) 03 Feb '19

03 Feb '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31190 ) Change subject: nb/intel/g45: Use a common romstage ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/31190/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/31190/1//COMMIT_MSG@7 PS1, Line 7: g45 gm45 -- To view, visit https://review.coreboot.org/c/coreboot/+/31190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30ef7f6962aabde78b5c40e0b53bb85e01c254c1 Gerrit-Change-Number: 31190 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 03 Feb 2019 18:05:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: nb/intel/g45: Use a common romstage
by Angel Pons (Code Review) 03 Feb '19

03 Feb '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31190 ) Change subject: nb/intel/g45: Use a common romstage ...................................................................... Patch Set 1: Code-Review+1 Quick look, looks good. -- To view, visit https://review.coreboot.org/c/coreboot/+/31190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30ef7f6962aabde78b5c40e0b53bb85e01c254c1 Gerrit-Change-Number: 31190 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 03 Feb 2019 18:04:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/lenovo/r500: Add mainboard
by Angel Pons (Code Review) 03 Feb '19

03 Feb '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28644 ) Change subject: mb/lenovo/r500: Add mainboard ...................................................................... Patch Set 7: Code-Review+1 (3 comments) https://review.coreboot.org/#/c/28644/7//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/28644/7//COMMIT_MSG@17 PS7, Line 17: (Needs SeaBIOS with sercon disabled) I think this isn't needed anymore https://review.coreboot.org/#/c/28644/7//COMMIT_MSG@41 PS7, Line 41: Debian 9, Linux 4.9 Was this booted via USB? https://review.coreboot.org/#/c/28644/7/src/mainboard/lenovo/t400/Kconfig File src/mainboard/lenovo/t400/Kconfig: https://review.coreboot.org/#/c/28644/7/src/mainboard/lenovo/t400/Kconfig@13 PS7, Line 13: select BOARD_ROMSIZE_KB_8192 : select BOARD_ROMSIZE_KB_4096 if BOARD_LENOVO_R500 Doesn't this conflict? -- To view, visit https://review.coreboot.org/c/coreboot/+/28644 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e129b2e916acdf2b8534fa9d8d2cfc8f64f5815 Gerrit-Change-Number: 28644 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 03 Feb 2019 17:56:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: usbdebug: Use fixed size field
by Kyösti Mälkki (Code Review) 03 Feb '19

03 Feb '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31182 Change subject: usbdebug: Use fixed size field ...................................................................... usbdebug: Use fixed size field The structure is placed inside CBMEM, one should use types with fixed size. Change-Id: I60382664a53650b225abc1f77c87ed4e121d429e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/drivers/usb/ehci_debug.c 1 file changed, 17 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/31182/1 diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c index cf3976c..3532466 100644 --- a/src/drivers/usb/ehci_debug.c +++ b/src/drivers/usb/ehci_debug.c @@ -28,8 +28,8 @@ #include "ehci.h" struct ehci_debug_info { - void *ehci_base; - void *ehci_debug; + u64 ehci_base; + u64 ehci_debug; struct dbgp_pipe ep_pipe[DBGP_MAX_ENDPOINTS]; }; @@ -262,7 +262,9 @@ int dbgp_bulk_write_x(struct dbgp_pipe *pipe, const char *bytes, int size) { struct ehci_debug_info *dbg_info = dbgp_ehci_info(); - return dbgp_bulk_write(dbg_info->ehci_debug, pipe, bytes, size); + struct ehci_dbg_port *port; + port = (void *)(uintptr_t)dbg_info->ehci_debug; + return dbgp_bulk_write(port, pipe, bytes, size); } static int dbgp_bulk_read(struct ehci_dbg_port *ehci_debug, struct dbgp_pipe *pipe, @@ -296,7 +298,9 @@ int dbgp_bulk_read_x(struct dbgp_pipe *pipe, void *data, int size) { struct ehci_debug_info *dbg_info = dbgp_ehci_info(); - return dbgp_bulk_read(dbg_info->ehci_debug, pipe, data, size); + struct ehci_dbg_port *port; + port = (void *)(uintptr_t)dbg_info->ehci_debug; + return dbgp_bulk_read(port, pipe, data, size); } void dbgp_mdelay(int ms) @@ -446,8 +450,8 @@ /* Keep all endpoints disabled before any printk() call. */ memset(info, 0, sizeof (*info)); - info->ehci_base = (void *)ehci_bar; - info->ehci_debug = (void *)(ehci_bar + offset); + info->ehci_base = ehci_bar; + info->ehci_debug = ehci_bar + offset; info->ep_pipe[0].status |= DBGP_EP_NOT_PRESENT; dprintk(BIOS_INFO, "ehci_bar: 0x%x debug_offset 0x%x\n", ehci_bar, offset); @@ -456,7 +460,7 @@ ehci_regs = (struct ehci_regs *)(ehci_bar + HC_LENGTH(read32(&ehci_caps->hc_capbase))); - struct ehci_dbg_port *ehci_debug = info->ehci_debug; + struct ehci_dbg_port *ehci_debug = (void *)(uintptr_t)info->ehci_debug; if (CONFIG_USBDEBUG_DEFAULT_PORT > 0) ehci_debug_select_port(CONFIG_USBDEBUG_DEFAULT_PORT); @@ -581,7 +585,8 @@ dbgp_mdelay(100); - ret = dbgp_probe_gadget(info->ehci_debug, &info->ep_pipe[0]); + struct ehci_dbg_port *port = (void *)(uintptr_t)info->ehci_debug; + ret = dbgp_probe_gadget(port, &info->ep_pipe[0]); if (ret < 0) { dprintk(BIOS_INFO, "Could not probe gadget on debug port.\n"); ret = -6; @@ -653,12 +658,12 @@ void usbdebug_re_enable(unsigned ehci_base) { struct ehci_debug_info *dbg_info = dbgp_ehci_info(); - unsigned diff; + u64 diff; int i; - diff = (unsigned)dbg_info->ehci_base - ehci_base; + diff = dbg_info->ehci_base - ehci_base; dbg_info->ehci_debug -= diff; - dbg_info->ehci_base = (void *)ehci_base; + dbg_info->ehci_base = ehci_base; for (i=0; i<DBGP_MAX_ENDPOINTS; i++) if (dbg_info->ep_pipe[i].status & DBGP_EP_VALID) @@ -678,7 +683,7 @@ int usbdebug_hw_init(bool force) { struct ehci_debug_info *dbg_info = dbgp_ehci_info(); - unsigned int ehci_base, dbg_offset; + u32 ehci_base, dbg_offset; if (dbgp_enabled() && !force) return 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/31182 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60382664a53650b225abc1f77c87ed4e121d429e Gerrit-Change-Number: 31182 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/soc/intel/cannonlake: Add _DSM methods for LPIT table
by Lijian Zhao (Code Review) 02 Feb '19

02 Feb '19

Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31101 ) Change subject: src/soc/intel/cannonlake: Add _DSM methods for LPIT table ...................................................................... Patch Set 15: > Patch Set 15: > > (1 comment) I have a quick compare the dsdt.dsl generated and that's identical for patch 12 and patch 15, I may assume the didn't work will be caused by other regression on S0ix. ASL 2.0 had been introduced for several years and widely adopted in coreboot as well. -- To view, visit https://review.coreboot.org/c/coreboot/+/31101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia908969decf7cf12f505becb4f4a4a9caa7ed6db Gerrit-Change-Number: 31101 Gerrit-PatchSet: 15 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Assignee: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 02 Feb 2019 22:36:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: src/soc/intel/cannonlake: Add _DSM methods for LPIT table
by Shaunak Saha (Code Review) 02 Feb '19

02 Feb '19

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Change in ...coreboot[master]: src/soc/intel/cannonlake: Add _DSM methods for LPIT table
by Shaunak Saha (Code Review) 02 Feb '19

02 Feb '19

Shaunak Saha has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31101 ) Change subject: src/soc/intel/cannonlake: Add _DSM methods for LPIT table ...................................................................... Patch Set 15: (5 comments) > Patch Set 11: > > (4 comments) https://review.coreboot.org/#/c/31101/11//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/31101/11//COMMIT_MSG@10 PS11, Line 10: get > gets? Done https://review.coreboot.org/#/c/31101/11//COMMIT_MSG@17 PS11, Line 17: does > do Done https://review.coreboot.org/#/c/31101/11//COMMIT_MSG@17 PS11, Line 17: throws > throw Done https://review.coreboot.org/#/c/31101/5/src/soc/intel/cannonlake/acpi/lpit.… File src/soc/intel/cannonlake/acpi/lpit.asl: https://review.coreboot.org/#/c/31101/5/src/soc/intel/cannonlake/acpi/lpit.… PS5, Line 26: LEqual(Arg0, ^UUID) > Done I was testing with this new syntax but it didnt worked with this. No compilation error but seems like its not able to parse this new syntax. Need to debug if there is some version mismatch issue. https://review.coreboot.org/#/c/31101/11/src/soc/intel/cannonlake/acpi/lpit… File src/soc/intel/cannonlake/acpi/lpit.asl: https://review.coreboot.org/#/c/31101/11/src/soc/intel/cannonlake/acpi/lpit… PS11, Line 75: //device (LPID) > Space after //. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/31101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia908969decf7cf12f505becb4f4a4a9caa7ed6db Gerrit-Change-Number: 31101 Gerrit-PatchSet: 15 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Assignee: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 02 Feb 2019 18:25:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Comment-In-Reply-To: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: Fix coreboot table record alignment to 8-byte boundary
by Jonathan Neuschäfer (Code Review) 02 Feb '19

02 Feb '19

Jonathan Neuschäfer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29916 ) Change subject: Fix coreboot table record alignment to 8-byte boundary ...................................................................... Patch Set 5: https://review.coreboot.org/c/coreboot/+/18165 <--- The previous patch that changed something about the alignment in coreboot tables -- To view, visit https://review.coreboot.org/c/coreboot/+/29916 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1846be0e26ab3c81858d8cf727517e1462035e64 Gerrit-Change-Number: 29916 Gerrit-PatchSet: 5 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Shawn C <citypw(a)gmail.com> Gerrit-Reviewer: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Sat, 02 Feb 2019 17:13:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: WIP: mb/qemu-riscv: update to match current qemu version
by Philipp Hug (Code Review) 02 Feb '19

02 Feb '19

Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30554 Change subject: WIP: mb/qemu-riscv: update to match current qemu version ...................................................................... WIP: mb/qemu-riscv: update to match current qemu version Boots again to payload not found on qemu. Change-Id: Ie107eb882cbaac5a5a06c1ff990e7b9364377640 Signed-off-by: Philipp Hug <philipp(a)hug.cx> --- M src/mainboard/emulation/qemu-riscv/Kconfig M src/mainboard/emulation/qemu-riscv/Makefile.inc M src/mainboard/emulation/qemu-riscv/mainboard.c M src/mainboard/emulation/qemu-riscv/memlayout.ld D src/mainboard/emulation/qemu-riscv/mtime.c M src/mainboard/emulation/qemu-riscv/rom_media.c M src/mainboard/emulation/qemu-riscv/uart.c 7 files changed, 23 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/30554/1 diff --git a/src/mainboard/emulation/qemu-riscv/Kconfig b/src/mainboard/emulation/qemu-riscv/Kconfig index 528b21e..ecaa764 100644 --- a/src/mainboard/emulation/qemu-riscv/Kconfig +++ b/src/mainboard/emulation/qemu-riscv/Kconfig @@ -13,7 +13,8 @@ ## GNU General Public License for more details. # To execute, do: -# qemu-system-arm -M vexpress-a9 -m 1024M -nographic -kernel build/coreboot.rom +# util/riscv/make-spike-elf.sh build/coreboot.rom build/coreboot.elf +# qemu-system-riscv64 -M virt -m 1024M -nographic -kernel build/coreboot.elf if BOARD_EMULATION_QEMU_RISCV diff --git a/src/mainboard/emulation/qemu-riscv/Makefile.inc b/src/mainboard/emulation/qemu-riscv/Makefile.inc index 1d882ac..eb99544 100644 --- a/src/mainboard/emulation/qemu-riscv/Makefile.inc +++ b/src/mainboard/emulation/qemu-riscv/Makefile.inc @@ -14,7 +14,7 @@ bootblock-y += uart.c bootblock-y += rom_media.c -bootblock-y += mtime.c +bootblock-y += clint.c romstage-y += romstage.c romstage-y += uart.c @@ -22,8 +22,10 @@ ramstage-y += uart.c ramstage-y += rom_media.c -ramstage-y += mtime.c +ramstage-y += clint.c bootblock-y += memlayout.ld romstage-y += memlayout.ld ramstage-y += memlayout.ld + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include diff --git a/src/mainboard/emulation/qemu-riscv/mainboard.c b/src/mainboard/emulation/qemu-riscv/mainboard.c index 7061bcf..4b428aa 100644 --- a/src/mainboard/emulation/qemu-riscv/mainboard.c +++ b/src/mainboard/emulation/qemu-riscv/mainboard.c @@ -16,6 +16,7 @@ #include <console/console.h> #include <device/device.h> #include <cbmem.h> +#include <symbols.h> static void mainboard_enable(struct device *dev) { @@ -24,7 +25,7 @@ die("No dev0; die\n"); } - ram_resource(dev, 0, 2048, 32768); + ram_resource(dev, 0, (uintptr_t)_dram / KiB, CONFIG_DRAM_SIZE_MB * KiB); cbmem_recovery(0); } diff --git a/src/mainboard/emulation/qemu-riscv/memlayout.ld b/src/mainboard/emulation/qemu-riscv/memlayout.ld index 615d1f2..032fbdd 100644 --- a/src/mainboard/emulation/qemu-riscv/memlayout.ld +++ b/src/mainboard/emulation/qemu-riscv/memlayout.ld @@ -14,15 +14,16 @@ */ #include <memlayout.h> - #include <arch/header.ld> +#define START 0x80000000 + SECTIONS { - DRAM_START(0x0) - BOOTBLOCK(0x0, 64K) - ROMSTAGE(0x20000, 128K) - STACK(0x40000, 0x3ff00) - PRERAM_CBMEM_CONSOLE(0x80000, 8K) - RAMSTAGE(0x100000, 16M) + DRAM_START(START) + BOOTBLOCK(START, 64K) + STACK(START + 4M, 4K) + ROMSTAGE(START + 4M + 64K, 128K) + PRERAM_CBMEM_CONSOLE(START + 4M + 192K, 8K) + RAMSTAGE(START + 4M + 200K, 16M) } diff --git a/src/mainboard/emulation/qemu-riscv/mtime.c b/src/mainboard/emulation/qemu-riscv/mtime.c deleted file mode 100644 index f8c2717..0000000 --- a/src/mainboard/emulation/qemu-riscv/mtime.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 HardenedLinux - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <mcall.h> - -/* FIXME: This is an empty implementation, please improve */ -/* This function is used to initialize HLS()->time/HLS()->timecmp */ -void mtime_init(void) -{ -} diff --git a/src/mainboard/emulation/qemu-riscv/rom_media.c b/src/mainboard/emulation/qemu-riscv/rom_media.c index c171307..bac1984 100644 --- a/src/mainboard/emulation/qemu-riscv/rom_media.c +++ b/src/mainboard/emulation/qemu-riscv/rom_media.c @@ -14,11 +14,12 @@ * GNU General Public License for more details. */ #include <boot_device.h> +#include <symbols.h> -/* This assumes that the CBFS resides at 0x0, which is true for the default - * configuration. */ +/* This assumes that the CBFS resides at start of dram, which is true for the + * default configuration. */ static const struct mem_region_device boot_dev = - MEM_REGION_DEV_RO_INIT(NULL, CONFIG_ROM_SIZE); + MEM_REGION_DEV_RO_INIT(_dram, CONFIG_ROM_SIZE); const struct region_device *boot_device_ro(void) { diff --git a/src/mainboard/emulation/qemu-riscv/uart.c b/src/mainboard/emulation/qemu-riscv/uart.c index 730ef3e..084362a 100644 --- a/src/mainboard/emulation/qemu-riscv/uart.c +++ b/src/mainboard/emulation/qemu-riscv/uart.c @@ -17,8 +17,9 @@ #include <console/uart.h> #include <arch/io.h> #include <boot/coreboot_tables.h> +#include <mainboard/addressmap.h> -static uint8_t *buf = (void *)0x3f8; +static uint8_t *buf = (void *)QEMU_VIRT_UART0; uintptr_t uart_platform_base(int idx) { return (uintptr_t) buf; @@ -47,7 +48,7 @@ { struct lb_serial serial; serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; - serial.baseaddr = 0x3f8; + serial.baseaddr = QEMU_VIRT_UART0; serial.baud = 115200; serial.regwidth = 1; lb_add_serial(&serial, data); -- To view, visit https://review.coreboot.org/c/coreboot/+/30554 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie107eb882cbaac5a5a06c1ff990e7b9364377640 Gerrit-Change-Number: 30554 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-MessageType: newchange

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2019

2018

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2013

coreboot-gerrit February 2019