Hello Werner Zeh, Aaron Durbin, Julius Werner, Patrick Rudolph, Paul Menzel, David Hendricks, build bot (Jenkins), Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/29563
to look at the new patch set (#28).
Change subject: security/tpm: Fix TCPA log feature
......................................................................
security/tpm: Fix TCPA log feature
Until now the TCPA log wasn't working correctly.
* Refactor TCPA log code.
* Add TCPA log dump fucntion.
* Make TCPA log available in bootblock.
* Fix TCPA log formatting.
* Add x86 and Cavium memory for early log.
Change-Id: Ic93133531b84318f48940d34bded48cbae739c44
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>
---
M src/arch/x86/car.ld
M src/commonlib/include/commonlib/tcpa_log_serialized.h
M src/include/memlayout.h
M src/security/tpm/tspi.h
M src/security/tpm/tspi/log.c
M src/security/tpm/tspi/tspi.c
M src/security/vboot/Kconfig
M src/security/vboot/symbols.h
M src/security/vboot/vboot_crtm.c
M src/soc/cavium/cn81xx/include/soc/memlayout.ld
M src/soc/imgtec/pistachio/include/soc/memlayout.ld
M src/soc/mediatek/mt8173/include/soc/memlayout.ld
M src/soc/mediatek/mt8183/include/soc/memlayout.ld
M src/soc/nvidia/tegra124/include/soc/memlayout.ld
M src/soc/nvidia/tegra210/include/soc/memlayout.ld
M src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld
M src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
M src/soc/qualcomm/sdm845/include/soc/memlayout.ld
M src/soc/rockchip/rk3288/include/soc/memlayout.ld
M src/soc/rockchip/rk3399/include/soc/memlayout.ld
M src/soc/samsung/exynos5250/include/soc/memlayout.ld
M util/cbmem/cbmem.c
22 files changed, 171 insertions(+), 64 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/29563/28
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Gerrit-Change-Number: 29563
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29563 )
Change subject: security/tpm: Fix TCPA log feature
......................................................................
Patch Set 27:
(2 comments)
https://review.coreboot.org/#/c/29563/27/src/include/memlayout.h
File src/include/memlayout.h:
https://review.coreboot.org/#/c/29563/27/src/include/memlayout.h@167
PS27, Line 167: #define VBOOT2_TPM_LOG(addr, size) \
Macros with multiple statements should be enclosed in a do - while loop
https://review.coreboot.org/#/c/29563/27/src/include/memlayout.h@167
PS27, Line 167: #define VBOOT2_TPM_LOG(addr, size) \
macros should not use a trailing semicolon
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Gerrit-Change-Number: 29563
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Gerrit-Comment-Date: Fri, 01 Feb 2019 12:51:21 +0000
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Gerrit-MessageType: comment
Hello Werner Zeh, Aaron Durbin, Julius Werner, Patrick Rudolph, Paul Menzel, David Hendricks, build bot (Jenkins), Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/29563
to look at the new patch set (#27).
Change subject: security/tpm: Fix TCPA log feature
......................................................................
security/tpm: Fix TCPA log feature
Until now the TCPA log wasn't working correctly.
* Refactor TCPA log code.
* Add TCPA log dump fucntion.
* Make TCPA log available in bootblock.
* Fix TCPA log formatting.
* Add x86 and Cavium memory for early log.
Change-Id: Ic93133531b84318f48940d34bded48cbae739c44
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>
---
M src/arch/x86/car.ld
M src/commonlib/include/commonlib/tcpa_log_serialized.h
M src/include/memlayout.h
M src/security/tpm/tspi.h
M src/security/tpm/tspi/log.c
M src/security/tpm/tspi/tspi.c
M src/security/vboot/Kconfig
M src/security/vboot/symbols.h
M src/security/vboot/vboot_crtm.c
M src/soc/cavium/cn81xx/include/soc/memlayout.ld
M src/soc/imgtec/pistachio/include/soc/memlayout.ld
M src/soc/mediatek/mt8173/include/soc/memlayout.ld
M src/soc/mediatek/mt8183/include/soc/memlayout.ld
M src/soc/nvidia/tegra124/include/soc/memlayout.ld
M src/soc/nvidia/tegra210/include/soc/memlayout.ld
M src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld
M src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
M src/soc/qualcomm/sdm845/include/soc/memlayout.ld
M src/soc/rockchip/rk3288/include/soc/memlayout.ld
M src/soc/rockchip/rk3399/include/soc/memlayout.ld
M src/soc/samsung/exynos5250/include/soc/memlayout.ld
M util/cbmem/cbmem.c
22 files changed, 169 insertions(+), 62 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/29563/27
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Gerrit-MessageType: newpatchset
Hello Alexander Couzens, Patrick Rudolph, Angel Pons, Paul Menzel, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/28644
to look at the new patch set (#7).
Change subject: mb/lenovo/r500: Add mainboard
......................................................................
mb/lenovo/r500: Add mainboard
Tested:
- Ethernet NIC
- Wifi RFKill
- USB
- LVDS, VGA with libgfxinit
- Booting with dock attached (COM1)
- Keyboard, trackpoint
- SeaBIOS 1.10.3
- S3 resume (Needs SeaBIOS with sercon disabled)
- Tested in descriptor mode, with vendor FD and ME
Untested:
- SATA (likely works)
- Trackpad (my cable is broken, likely works)
- Displayport (likely works)
- Descriptorless mode
- DVD drive
- Extra battery
Does not work:
- Dock hotplug
- Quad core CPU (hangs during AP init, probably needs hardware mod)
- Models with a sole ATI GPU (needs probing of PEG in romstage)
- Hotplugging the expresscard slot (works with 'echo 1 | sudo tee
/sys/bus/pci/rescan')
TODO:
- proper dock support
- documentation
note: This board was hard to flash, I had to desolder the flash.
TESTED: on a R500 with an Intel iGPU, SeaBIOS 1.10.3, Debian 9, Linux 4.9
Change-Id: I9e129b2e916acdf2b8534fa9d8d2cfc8f64f5815
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/mainboard/lenovo/t400/Kconfig
M src/mainboard/lenovo/t400/Kconfig.name
M src/mainboard/lenovo/t400/Makefile.inc
M src/mainboard/lenovo/t400/devicetree.cb
M src/mainboard/lenovo/t400/dsdt.asl
A src/mainboard/lenovo/t400/variants/r500/Makefile.inc
A src/mainboard/lenovo/t400/variants/r500/data.vbt
A src/mainboard/lenovo/t400/variants/r500/gpio.c
A src/mainboard/lenovo/t400/variants/r500/overridetree.cb
A src/mainboard/lenovo/t400/variants/t400/Makefile.inc
R src/mainboard/lenovo/t400/variants/t400/gpio.c
A src/mainboard/lenovo/t400/variants/t400/overridetree.cb
12 files changed, 246 insertions(+), 38 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/28644/7
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Gerrit-Change-Number: 28644
Gerrit-PatchSet: 7
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu>
Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
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HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25431 )
Change subject: soc/intel/denverton_ns: Enable Fast Strings
......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/#/c/25431/7/src/soc/intel/denverton_ns/include/…
File src/soc/intel/denverton_ns/include/soc/msr.h:
https://review.coreboot.org/#/c/25431/7/src/soc/intel/denverton_ns/include/…
PS7, Line 95: #define FAST_STRINGS_ENABLE_BIT (1 << 0)
: #define SPEED_STEP_ENABLE_BIT (1 << 16)
> I think that's a good idea
I thought that fast string is enabled by default.
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David Guckian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25431 )
Change subject: soc/intel/denverton_ns: Enable Fast Strings
......................................................................
Patch Set 8:
(1 comment)
> Patch Set 7:
>
> (1 comment)
I agree
https://review.coreboot.org/#/c/25431/7/src/soc/intel/denverton_ns/include/…
File src/soc/intel/denverton_ns/include/soc/msr.h:
https://review.coreboot.org/#/c/25431/7/src/soc/intel/denverton_ns/include/…
PS7, Line 95: #define FAST_STRINGS_ENABLE_BIT (1 << 0)
: #define SPEED_STEP_ENABLE_BIT (1 << 16)
> Can we move this to include/cpu/x86/msr. […]
I think that's a good idea
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Gerrit-Comment-Date: Fri, 01 Feb 2019 10:16:33 +0000
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Chandana Kishori Chiluveru has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25213 )
Change subject: sdm845: Add USB support on cheza platform
......................................................................
Patch Set 65:
(2 comments)
https://review.coreboot.org/#/c/25213/64/src/soc/qualcomm/sdm845/usb.c
File src/soc/qualcomm/sdm845/usb.c:
https://review.coreboot.org/#/c/25213/64/src/soc/qualcomm/sdm845/usb.c@585
PS64, Line 585: int serdes_tbl_num;
> Hmmm... okay, crap, I didn't see all those other differences. […]
sounds good, I will separate out the usb_dwc3_cfg data for usb ports.
I will push the changes in next patch
https://review.coreboot.org/#/c/25213/64/src/soc/qualcomm/sdm845/usb.c@824
PS64, Line 824: USB3_PCS_PHYSTATUS));
> Okay, thanks, just wanted to double-check. […]
we already shared the HPG documents to google.
I will check more info from shon on this and update you over partner account
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Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31189 )
Change subject: mb/lenovo/{x200,t400}: Set SMBUS mux using common SB functions
......................................................................
Patch Set 1: Code-Review+2
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