coreboot-gerrit February 2019

coreboot-gerrit@coreboot.org

1 participants
1249 discussions

Change in ...coreboot[master]: soc/intel/icelake: Don't use CAR_GLOBAL
by Kyösti Mälkki (Code Review) 02 Feb '19

02 Feb '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30515 ) Change subject: soc/intel/icelake: Don't use CAR_GLOBAL ...................................................................... Patch Set 2: Arthur, can you send RFC on the mailing list about this. I would not mind starting to remove CAR_GLOBAL and all car_get/set_var() stuff, from the platform codes, starting with the latest Intel one so that these are no longer copied around further. -- To view, visit https://review.coreboot.org/c/coreboot/+/30515 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia210af6ef1a97da67d00036070faa1ceb3ce250b Gerrit-Change-Number: 30515 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Sat, 02 Feb 2019 00:07:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: vendorcode/google/chromeos: Add option for using ACPI GPIO pin
by Duncan Laurie (Code Review) 01 Feb '19

01 Feb '19

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31080 Change subject: vendorcode/google/chromeos: Add option for using ACPI GPIO pin ...................................................................... vendorcode/google/chromeos: Add option for using ACPI GPIO pin This new option will have the generated Chrome OS ACPI GPIO table provide the ACPI GPIO pin number instead of the raw GPIO number. This is necessary if the OS uses a different numbering for GPIOs that are reported in ACPI than the actual underlying GPIO number. For example, if the SOC OS driver declares more pins in an ACPI GPIO bank than there are actual pins in the hardware it will have gaps in the number space. This is a reworked version of 6217e9beff16d805ca833e79a2931bcdb3d02a44 which uses a new option instead of just relying on GENERIC_GPIO_LIB. BUG=b:120686247 TEST=pass firmware_WriteProtect test on Sarien Change-Id: I3ad5099b7f2f871c7e516988f60a54eb2a75bef7 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/vendorcode/google/chromeos/Kconfig M src/vendorcode/google/chromeos/acpi.c 2 files changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/31080/1 diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index 26ee31e..2edb46f 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -89,5 +89,17 @@ on normal boot as well as resume and coreboot is only involved in the resume piece w.r.t. the platform hierarchy. +config CHROMEOS_ACPI_GPIO_GENERATE_PIN + bool + default n + depends on HAVE_ACPI_TABLES && GENERIC_GPIO_LIB + help + This option will have the generated Chrome OS ACPI GPIO table + provide the ACPI GPIO pin number instead of the raw GPIO number. + This is necessary if the OS uses a different numbering for GPIOs + that are reported in ACPI. For example, if the SOC declares more + pins in an ACPI GPIO bank than there are actual pins in the hardware + it will have gaps in the number space. + endif # CHROMEOS endmenu diff --git a/src/vendorcode/google/chromeos/acpi.c b/src/vendorcode/google/chromeos/acpi.c index 6605809..849f4c3 100644 --- a/src/vendorcode/google/chromeos/acpi.c +++ b/src/vendorcode/google/chromeos/acpi.c @@ -15,6 +15,9 @@ #include <arch/acpigen.h> #include "chromeos.h" +#if IS_ENABLED(CONFIG_CHROMEOS_ACPI_GPIO_GENERATE_PIN) +#include <gpio.h> +#endif void chromeos_acpi_gpio_generate(const struct cros_gpio *gpios, size_t num) { @@ -28,7 +31,11 @@ acpigen_write_package(4); acpigen_write_integer(gpios[i].type); acpigen_write_integer(gpios[i].polarity); +#if IS_ENABLED(CONFIG_CHROMEOS_ACPI_GPIO_GENERATE_PIN) + acpigen_write_integer(gpio_acpi_pin(gpios[i].gpio_num)); +#else acpigen_write_integer(gpios[i].gpio_num); +#endif acpigen_write_string(gpios[i].device); acpigen_pop_len(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/31080 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ad5099b7f2f871c7e516988f60a54eb2a75bef7 Gerrit-Change-Number: 31080 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

3 9

Change in ...coreboot[master]: sb/intel/common: Rename i2c_block_read() to i2c_eeprom_read()
by Kyösti Mälkki (Code Review) 01 Feb '19

01 Feb '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31151 Change subject: sb/intel/common: Rename i2c_block_read() to i2c_eeprom_read() ...................................................................... sb/intel/common: Rename i2c_block_read() to i2c_eeprom_read() Datasheets describe the used command as 'I2C Read' but adding the word 'eeprom' in between should avoid further confusion with other block commands. Followups will add a symmetrical pair of commands i2c_block_read() and i2c_block_write() that operate via I2C_EN bit and have a 32 byte size restriction on block transfers. For some hardware revision these block commands are available, while 'I2C Read' was not. Change-Id: I4494ab2985afc7f737ddacc8d706a5d5395e35cf Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/northbridge/intel/i945/raminit.c M src/northbridge/intel/pineview/raminit.c M src/northbridge/intel/x4x/raminit.c M src/southbridge/intel/common/smbus.c M src/southbridge/intel/common/smbus.h M src/southbridge/intel/i82801gx/early_smbus.c M src/southbridge/intel/i82801gx/i82801gx.h M src/southbridge/intel/i82801jx/early_smbus.c M src/southbridge/intel/i82801jx/i82801jx.h 9 files changed, 25 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/31151/1 diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index f3c3df6..dece9bf 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -381,7 +381,7 @@ * only the first 64 bytes contain data needed for raminit. */ - bytes_read = i2c_block_read(device, 0, 64, raw_spd); + bytes_read = i2c_eeprom_read(device, 0, 64, raw_spd); printk(BIOS_DEBUG, "Reading SPD using i2c block operation.\n"); if (IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) && bytes_read > 0) hexdump(raw_spd, bytes_read); diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index ee19b61..ed633fd 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -273,7 +273,7 @@ u8 i, chan; s->dt0mode = 0; FOR_EACH_DIMM(i) { - if (i2c_block_read(s->spd_map[i], 0, 64, s->dimms[i].spd_data) != 64) + if (i2c_eeprom_read(s->spd_map[i], 0, 64, s->dimms[i].spd_data) != 64) s->dimms[i].card_type = 0; s->dimms[i].card_type = s->dimms[i].spd_data[62] & 0x1f; diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index d9fa49d..1fd6004 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -47,15 +47,15 @@ static u16 ddr2_get_crc(u8 device, u8 len) { u8 raw_spd[128] = {}; - i2c_block_read(device, 64, 9, &raw_spd[64]); - i2c_block_read(device, 93, 6, &raw_spd[93]); + i2c_eeprom_read(device, 64, 9, &raw_spd[64]); + i2c_eeprom_read(device, 93, 6, &raw_spd[93]); return spd_ddr2_calc_unique_crc(raw_spd, len); } static u16 ddr3_get_crc(u8 device, u8 len) { u8 raw_spd[256] = {}; - i2c_block_read(device, 117, 11, &raw_spd[117]); + i2c_eeprom_read(device, 117, 11, &raw_spd[117]); return spd_ddr3_calc_unique_crc(raw_spd, len); } @@ -531,7 +531,7 @@ die("Mixing up dimm types is not supported!\n"); printk(BIOS_DEBUG, "Decoding dimm %d\n", i); - if (i2c_block_read(device, 0, 128, raw_spd) != 128) { + if (i2c_eeprom_read(device, 0, 128, raw_spd) != 128) { printk(BIOS_DEBUG, "i2c block operation failed," " trying smbus byte operation.\n"); for (j = 0; j < 128; j++) diff --git a/src/southbridge/intel/common/smbus.c b/src/southbridge/intel/common/smbus.c index fd8b6aa..a842a61 100644 --- a/src/southbridge/intel/common/smbus.c +++ b/src/southbridge/intel/common/smbus.c @@ -363,11 +363,22 @@ } /* Only since ICH5 */ -int do_i2c_block_read(unsigned int smbus_base, u8 device, +static int has_i2c_read_command(void) +{ + if (IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82371EB) || + IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801DX)) + return 0; + return 1; +} + +int do_i2c_eeprom_read(unsigned int smbus_base, u8 device, unsigned int offset, const unsigned int bytes, u8 *buf) { int ret; + if (!has_i2c_read_command()) + return SMBUS_ERROR; + /* Set up for a i2c block data read. * * FIXME: Address parameter changes to XMIT_READ(device) with diff --git a/src/southbridge/intel/common/smbus.h b/src/southbridge/intel/common/smbus.h index be1aa76..ded31d0 100644 --- a/src/southbridge/intel/common/smbus.h +++ b/src/southbridge/intel/common/smbus.h @@ -41,6 +41,6 @@ int do_smbus_block_write(unsigned int smbus_base, u8 device, u8 cmd, unsigned int bytes, const u8 *buf); /* Only since ICH5 */ -int do_i2c_block_read(unsigned int smbus_base, u8 device, +int do_i2c_eeprom_read(unsigned int smbus_base, u8 device, unsigned int offset, unsigned int bytes, u8 *buf); #endif diff --git a/src/southbridge/intel/i82801gx/early_smbus.c b/src/southbridge/intel/i82801gx/early_smbus.c index 698458b..9dddcec 100644 --- a/src/southbridge/intel/i82801gx/early_smbus.c +++ b/src/southbridge/intel/i82801gx/early_smbus.c @@ -54,9 +54,9 @@ return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -int i2c_block_read(unsigned int device, unsigned int offset, u32 bytes, u8 *buf) +int i2c_eeprom_read(unsigned int device, unsigned int offset, u32 bytes, u8 *buf) { - return do_i2c_block_read(SMBUS_IO_BASE, device, offset, bytes, buf); + return do_i2c_eeprom_read(SMBUS_IO_BASE, device, offset, bytes, buf); } int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf) diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 66d47ae..12935c2 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -45,7 +45,7 @@ #else void enable_smbus(void); int smbus_read_byte(unsigned int device, unsigned int address); -int i2c_block_read(unsigned int device, unsigned int cmd, unsigned int bytes, +int i2c_eeprom_read(unsigned int device, unsigned int cmd, unsigned int bytes, u8 *buf); int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf); int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, diff --git a/src/southbridge/intel/i82801jx/early_smbus.c b/src/southbridge/intel/i82801jx/early_smbus.c index bd68955..8c87045 100644 --- a/src/southbridge/intel/i82801jx/early_smbus.c +++ b/src/southbridge/intel/i82801jx/early_smbus.c @@ -51,9 +51,9 @@ return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -int i2c_block_read(unsigned int device, unsigned int offset, u32 bytes, u8 *buf) +int i2c_eeprom_read(unsigned int device, unsigned int offset, u32 bytes, u8 *buf) { - return do_i2c_block_read(SMBUS_IO_BASE, device, offset, bytes, buf); + return do_i2c_eeprom_read(SMBUS_IO_BASE, device, offset, bytes, buf); } int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf) diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h index ad3b381..0014848 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.h +++ b/src/southbridge/intel/i82801jx/i82801jx.h @@ -233,7 +233,7 @@ #if defined(__PRE_RAM__) void enable_smbus(void); int smbus_read_byte(unsigned device, unsigned address); -int i2c_block_read(unsigned int device, unsigned int cmd, unsigned int bytes, +int i2c_eeprom_read(unsigned int device, unsigned int cmd, unsigned int bytes, u8 *buf); int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf); int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, -- To view, visit https://review.coreboot.org/c/coreboot/+/31151 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4494ab2985afc7f737ddacc8d706a5d5395e35cf Gerrit-Change-Number: 31151 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

5 5

Change in ...coreboot[master]: arch/x86: Remove weak tsc_freq_mhz() implementation
by Kyösti Mälkki (Code Review) 01 Feb '19

01 Feb '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30762 Change subject: arch/x86: Remove weak tsc_freq_mhz() implementation ...................................................................... arch/x86: Remove weak tsc_freq_mhz() implementation Build with TSC_CONSTANT_RATE must fail when this function is not implemented for the platform. Weak implementation causes division by zero in timer_monotonic_get() and turns udelay() into no delay. Change-Id: Id3b105ea3aac37cd0cba18ce2fb06d87a055486f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/timestamp.c 1 file changed, 3 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/30762/1 diff --git a/src/arch/x86/timestamp.c b/src/arch/x86/timestamp.c index 928d7d7..cbc7bac 100644 --- a/src/arch/x86/timestamp.c +++ b/src/arch/x86/timestamp.c @@ -21,15 +21,10 @@ return rdtscll(); } -unsigned long __weak tsc_freq_mhz(void) -{ - /* Default to not knowing TSC frequency. cbmem will have to fallback - * on trying to determine it in userspace. */ - return 0; -} - int timestamp_tick_freq_mhz(void) { /* Chipsets that have a constant TSC provide this value correctly. */ - return tsc_freq_mhz(); + if (IS_ENABLED(CONFIG_TSC_CONSTANT_RATE)) + return tsc_freq_mhz(); + return 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/30762 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id3b105ea3aac37cd0cba18ce2fb06d87a055486f Gerrit-Change-Number: 30762 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 3

Change in ...coreboot[master]: hatch: Enable S0ix
by Shelley Chen (Code Review) 01 Feb '19

01 Feb '19

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31157 Change subject: hatch: Enable S0ix ...................................................................... hatch: Enable S0ix BUG=b:123540469 BRANCH=None TEST=None Change-Id: I713e6ad70efdd152895afa45aee44a5b53a8136b Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/31157/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index cea64e4..2bc4f78 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -55,6 +55,8 @@ register "HeciEnabled" = "1" # Enable Speed Shift Technology support register "speed_shift_enable" = "1" + # Enable S0ix + register "s0ix_enable" = "1" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 0 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/31157 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I713e6ad70efdd152895afa45aee44a5b53a8136b Gerrit-Change-Number: 31157 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newchange

6 7

Change in ...coreboot[master]: soc/intel/cannonlake: Add SOC_INTEL_WHISKEYLAKE kconfig
by Subrata Banik (Code Review) 01 Feb '19

01 Feb '19

Hello Patrick Rudolph, PraveenX Hodagatta Pranesh, Angel Pons, Aamir Bohra, Duncan Laurie, Rizwan Qureshi, build bot (Jenkins), Lijian Zhao, Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/31133 to look at the new patch set (#6). Change subject: soc/intel/cannonlake: Add SOC_INTEL_WHISKEYLAKE kconfig ...................................................................... soc/intel/cannonlake: Add SOC_INTEL_WHISKEYLAKE kconfig This patch selects correct SoC support for hatch, sarien, cflrvps and whlrvp. * Hatch is WHL SoC based board * Sarien is WHL SoC based board * CFLRVP U/8/11 are CFL SoC based board * WHLRVP is based on WHL SoC Also add correct FSP blobs path for WHL SoC based designs. Change-Id: I66b63361841f5a16615ddce4225c4f6182eabdb3 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/drivers/intel/fsp2_0/Kconfig M src/mainboard/google/hatch/Kconfig M src/mainboard/google/sarien/Kconfig M src/mainboard/intel/coffeelake_rvp/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/romstage/fsp_params.c 7 files changed, 20 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/31133/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/31133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66b63361841f5a16615ddce4225c4f6182eabdb3 Gerrit-Change-Number: 31133 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: soc/amd/stoneyridge: Add generic PM1 register clear function
by Marshall Dawson (Code Review) 01 Feb '19

01 Feb '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31159 Change subject: soc/amd/stoneyridge: Add generic PM1 register clear function ...................................................................... soc/amd/stoneyridge: Add generic PM1 register clear function Convert vboot_platform_prepare_reboot() to call a function in soc//stoneyridge. A subsequent patch will add another call to the new function, and this change removes any inference of a dependency on vboot. BUG=b:122725586 Change-Id: I634fcd030e206c790bda697a3dbef4e8cc21b3a8 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/pmutil.c 2 files changed, 14 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/31159/1 diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 1652bbc..3ae6b4a 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -604,4 +604,10 @@ /* Initialize all the i2c buses that are not marked with early init. */ void i2c_soc_init(void); +/* + * If a system reset is about to be requested, modify the PM1 register so it + * will never be misinterpreted as an S3 resume. + */ +void set_pm1cnt_s5(void); + #endif /* __STONEYRIDGE_H__ */ diff --git a/src/soc/amd/stoneyridge/pmutil.c b/src/soc/amd/stoneyridge/pmutil.c index d2b3ac7..bfb5f42 100644 --- a/src/soc/amd/stoneyridge/pmutil.c +++ b/src/soc/amd/stoneyridge/pmutil.c @@ -34,9 +34,9 @@ return acpi_sleep_from_pm1(pm_cnt) == ACPI_S3; } -/* If vboot requests a system reset, modify the PM1 register so it will never be - * misinterpreted as an S3 resume. */ -void vboot_platform_prepare_reboot(void) +/* If a system reset is about to be requested, modify the PM1 register so it + * will never be misinterpreted as an S3 resume. */ +void set_pm1cnt_s5(void) { uint16_t pm1; @@ -45,3 +45,8 @@ pm1 |= SLP_TYP_S5 << SLP_TYP_SHIFT; acpi_write16(MMIO_ACPI_PM1_CNT_BLK, pm1); } + +void vboot_platform_prepare_reboot(void) +{ + set_pm1cnt_s5(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/31159 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I634fcd030e206c790bda697a3dbef4e8cc21b3a8 Gerrit-Change-Number: 31159 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

3 3

Change in ...coreboot[master]: cbmem: use aligned_memcpy for reading cbmem address information
by Aaron Durbin (Code Review) 01 Feb '19

01 Feb '19

Aaron Durbin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31181 Change subject: cbmem: use aligned_memcpy for reading cbmem address information ...................................................................... cbmem: use aligned_memcpy for reading cbmem address information The coreboot table entry containing the memory entries can have fields unnaturally aligned in memory. Therefore one needs to perform an aligned_memcpy() so that it doesn't cause faults on certain architectures that assume naturally aligned accesses. chromium:925961 Change-Id: I28365b204962ac89d65d046076d862b6f9374c06 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- M util/cbmem/cbmem.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/31181/1 diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index 8e73d9c..fc2dcdc 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -302,7 +302,7 @@ continue; debug(" LB_MEM_TABLE found.\n"); /* The last one found is CBMEM */ - cbmem = mem->map[i]; + aligned_memcpy(&cbmem, &mem->map[i], sizeof(cbmem)); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/31181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28365b204962ac89d65d046076d862b6f9374c06 Gerrit-Change-Number: 31181 Gerrit-PatchSet: 1 Gerrit-Owner: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

4 5

Change in ...coreboot[master]: security/tpm: Fix TCPA log feature
by build bot (Jenkins) (Code Review) 01 Feb '19

01 Feb '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29563 ) Change subject: security/tpm: Fix TCPA log feature ...................................................................... Patch Set 28: (2 comments) https://review.coreboot.org/#/c/29563/28/src/include/memlayout.h File src/include/memlayout.h: https://review.coreboot.org/#/c/29563/28/src/include/memlayout.h@167 PS28, Line 167: #define VBOOT2_TPM_LOG(addr, size) \ Macros with multiple statements should be enclosed in a do - while loop https://review.coreboot.org/#/c/29563/28/src/include/memlayout.h@167 PS28, Line 167: #define VBOOT2_TPM_LOG(addr, size) \ macros should not use a trailing semicolon -- To view, visit https://review.coreboot.org/c/coreboot/+/29563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic93133531b84318f48940d34bded48cbae739c44 Gerrit-Change-Number: 29563 Gerrit-PatchSet: 28 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 01 Feb 2019 12:54:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: security/tpm: Fix TCPA log feature
by Philipp Deppenwiese (Code Review) 01 Feb '19

01 Feb '19

Hello Werner Zeh, Aaron Durbin, Julius Werner, Patrick Rudolph, Paul Menzel, David Hendricks, build bot (Jenkins), Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29563 to look at the new patch set (#28). Change subject: security/tpm: Fix TCPA log feature ...................................................................... security/tpm: Fix TCPA log feature Until now the TCPA log wasn't working correctly. * Refactor TCPA log code. * Add TCPA log dump fucntion. * Make TCPA log available in bootblock. * Fix TCPA log formatting. * Add x86 and Cavium memory for early log. Change-Id: Ic93133531b84318f48940d34bded48cbae739c44 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M src/arch/x86/car.ld M src/commonlib/include/commonlib/tcpa_log_serialized.h M src/include/memlayout.h M src/security/tpm/tspi.h M src/security/tpm/tspi/log.c M src/security/tpm/tspi/tspi.c M src/security/vboot/Kconfig M src/security/vboot/symbols.h M src/security/vboot/vboot_crtm.c M src/soc/cavium/cn81xx/include/soc/memlayout.ld M src/soc/imgtec/pistachio/include/soc/memlayout.ld M src/soc/mediatek/mt8173/include/soc/memlayout.ld M src/soc/mediatek/mt8183/include/soc/memlayout.ld M src/soc/nvidia/tegra124/include/soc/memlayout.ld M src/soc/nvidia/tegra210/include/soc/memlayout.ld M src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld M src/soc/qualcomm/ipq806x/include/soc/memlayout.ld M src/soc/qualcomm/sdm845/include/soc/memlayout.ld M src/soc/rockchip/rk3288/include/soc/memlayout.ld M src/soc/rockchip/rk3399/include/soc/memlayout.ld M src/soc/samsung/exynos5250/include/soc/memlayout.ld M util/cbmem/cbmem.c 22 files changed, 171 insertions(+), 64 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/29563/28 -- To view, visit https://review.coreboot.org/c/coreboot/+/29563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic93133531b84318f48940d34bded48cbae739c44 Gerrit-Change-Number: 29563 Gerrit-PatchSet: 28 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2019