
Change in ...coreboot[master]: mb/siemens/mc_apl1: Enable VTD for mc_apl2 and mc_apl5
by Werner Zeh (Code Review) Feb. 5, 2019
by Werner Zeh (Code Review) Feb. 5, 2019
Feb. 5, 2019
2
3

Change in ...coreboot[master]: intel/apollolake: Add parameter to enable VTD in devicetree
by Werner Zeh (Code Review) Feb. 5, 2019
by Werner Zeh (Code Review) Feb. 5, 2019
Feb. 5, 2019
5
10

Change in ...coreboot[master]: mb/google/octopus: Add USB ACPI configuration for CNVi BT module
by Karthik Ramasubramanian (Code Review) Feb. 5, 2019
by Karthik Ramasubramanian (Code Review) Feb. 5, 2019
Feb. 5, 2019
2
2

Change in ...coreboot[master]: soc/intel/apollolake: Update XHCI ports for GLK in ACPI tables
by Furquan Shaikh (Code Review) Feb. 5, 2019
by Furquan Shaikh (Code Review) Feb. 5, 2019
Feb. 5, 2019
4
7

Change in ...coreboot[master]: mb/google/hatch: Add USB port capabality ACPI support for USB2 port10
by Aamir Bohra (Code Review) Feb. 5, 2019
by Aamir Bohra (Code Review) Feb. 5, 2019
Feb. 5, 2019
4
5

Change in ...coreboot[master]: Fix coreboot table record alignment to 8-byte boundary
by Xiang Wang (Code Review) Feb. 5, 2019
by Xiang Wang (Code Review) Feb. 5, 2019
Feb. 5, 2019
1
0

Change in ...coreboot[master]: Fix coreboot table record alignment to 8-byte boundary
by Xiang Wang (Code Review) Feb. 5, 2019
by Xiang Wang (Code Review) Feb. 5, 2019
Feb. 5, 2019
1
0

Change in ...coreboot[master]: mb/google/kahlee/variants/liara: Update eDP power off timing sequence
by Martin Roth (Code Review) Feb. 4, 2019
by Martin Roth (Code Review) Feb. 4, 2019
Feb. 4, 2019
1
0

Change in ...coreboot[master]: soc/amd/stoneyridge: Reboot if missing MRC cache info
by Marshall Dawson (Code Review) Feb. 4, 2019
by Marshall Dawson (Code Review) Feb. 4, 2019
Feb. 4, 2019
3
13

Change in ...coreboot[master]: Fix coreboot table record alignment to 8-byte boundary
by Julius Werner (Code Review) Feb. 4, 2019
by Julius Werner (Code Review) Feb. 4, 2019
Feb. 4, 2019
1
0