Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31194
Change subject: intel/apollolake: Add parameter to enable VTD in devicetree
......................................................................
intel/apollolake: Add parameter to enable VTD in devicetree
The FSP has a parameter to enable or disable the VTD feature. VTD is
disabled per default. Add a chip parameter so that VTD can be enabled on
mainboard level in devicetree.
Change-Id: Ic0bfcf1719e1ccc678a932bf3d38c6dbce3556bc
Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com>
---
M src/soc/intel/apollolake/chip.c
M src/soc/intel/apollolake/chip.h
2 files changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/31194/1
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index cddfe44..735fed0 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -751,6 +751,9 @@
if (!xdci_can_enable())
dev->enabled = 0;
silconfig->UsbOtg = dev->enabled;
+
+ /* Set VTD feature according to devicetree */
+ silconfig->VtdEnable = cfg->enable_vtd;
}
struct chip_operations soc_intel_apollolake_ops = {
diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h
index 6c2404a..b9e368c 100644
--- a/src/soc/intel/apollolake/chip.h
+++ b/src/soc/intel/apollolake/chip.h
@@ -188,6 +188,12 @@
* 00=1.10v, 01=1.15v, 10=1.24v, 11=1.20v (default).
*/
uint32_t PmicVdd2Voltage;
+
+ /* Option to enable VTD feature. Default is 0 which disables VTD
+ * capability in FSP. Setting this option to 1 in devicetree will enable
+ * the Upd parameter VtdEnable.
+ */
+ uint8_t enable_vtd;
};
typedef struct soc_intel_apollolake_config config_t;
--
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Gerrit-Change-Id: Ic0bfcf1719e1ccc678a932bf3d38c6dbce3556bc
Gerrit-Change-Number: 31194
Gerrit-PatchSet: 1
Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com>
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Hello Karthikeyan Ramasubramanian,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/31183
to review the following change.
Change subject: mb/google/octopus: Add USB ACPI configuration for CNVi BT module
......................................................................
mb/google/octopus: Add USB ACPI configuration for CNVi BT module
This change enables exporting the reset GPIO for CNVi Bluetooth module to
the kernel for use in an rf-kill operation.
BUG=b:123296264
BRANCH=octopus
TEST=Boots to ChromeOS. Checked the SSDT table to ensure that the reset
gpio is exported under the device \_SB_.PCI0.XHCI.RHUB.HS09. Ensured
that the kernel btusb driver is able to find the exported GPIO in the
devices with CNVi BT module.
Change-Id: I10f28bfe705da5104d709ae2ed91a8ae003fa639
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
---
M src/mainboard/google/octopus/variants/baseboard/devicetree.cb
1 file changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/31183/1
diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb
index bbaa312..1d36b53 100644
--- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb
@@ -154,6 +154,12 @@
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_109)"
device usb 2.2 on end
end
+ chip drivers/usb/acpi
+ register "desc" = ""Bluetooth""
+ register "type" = "UPC_TYPE_INTERNAL"
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_109)"
+ device usb 2.9 on end
+ end
end
end
end # - XHCI
--
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Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com>
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Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31172
Change subject: soc/intel/apollolake: Update XHCI ports for GLK in ACPI tables
......................................................................
soc/intel/apollolake: Update XHCI ports for GLK in ACPI tables
GLK has a dedicated USB2 port that is used specifically for CNVi
BT. This requires that the ACPI tables define an additional USB 2 port
which results in _ADR for USB 3 ports being different for GLK than
APL.
This change splits the ports in xhci.asl into APL and GLK specific
ports.asl and selects the appropriate file based on
CONFIG_SOC_INTEL_GLK. It also adds support for returning HS09 for GLK
if ACPI name is requested for that port.
BUG=b:123670712
BRANCH=octopus
TEST=Verified that generated DSDT for octopus(GLK) includes HS09 and
for reef(APL) does not include HS09 definition.
Change-Id: I2d3d3690ec9ea1f6e35c38c3b3cbb82e961b7950
Signed-off-by: Furquan Shaikh <furquan(a)google.com>
---
M src/soc/intel/apollolake/acpi/xhci.asl
A src/soc/intel/apollolake/acpi/xhci_apl_ports.asl
A src/soc/intel/apollolake/acpi/xhci_glk_ports.asl
M src/soc/intel/apollolake/chip.c
4 files changed, 77 insertions(+), 17 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/31172/1
diff --git a/src/soc/intel/apollolake/acpi/xhci.asl b/src/soc/intel/apollolake/acpi/xhci.asl
index 8222cb5..7632af6 100644
--- a/src/soc/intel/apollolake/acpi/xhci.asl
+++ b/src/soc/intel/apollolake/acpi/xhci.asl
@@ -34,22 +34,10 @@
/* Root Hub */
Name (_ADR, Zero)
- /* USB2 */
- Device (HS01) { Name (_ADR, 1) }
- Device (HS02) { Name (_ADR, 2) }
- Device (HS03) { Name (_ADR, 3) }
- Device (HS04) { Name (_ADR, 4) }
- Device (HS05) { Name (_ADR, 5) }
- Device (HS06) { Name (_ADR, 6) }
- Device (HS07) { Name (_ADR, 7) }
- Device (HS08) { Name (_ADR, 8) }
-
- /* USB3 */
- Device (SS01) { Name (_ADR, 9) }
- Device (SS02) { Name (_ADR, 10) }
- Device (SS03) { Name (_ADR, 11) }
- Device (SS04) { Name (_ADR, 12) }
- Device (SS05) { Name (_ADR, 13) }
- Device (SS06) { Name (_ADR, 14) }
+#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
+#include "xhci_glk_ports.asl"
+#else
+#include "xhci_apl_ports.asl"
+#endif
}
}
diff --git a/src/soc/intel/apollolake/acpi/xhci_apl_ports.asl b/src/soc/intel/apollolake/acpi/xhci_apl_ports.asl
new file mode 100644
index 0000000..ebb3e8c
--- /dev/null
+++ b/src/soc/intel/apollolake/acpi/xhci_apl_ports.asl
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Google LLC.
+ * Copyright 2019 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* USB2 */
+Device (HS01) { Name (_ADR, 1) }
+Device (HS02) { Name (_ADR, 2) }
+Device (HS03) { Name (_ADR, 3) }
+Device (HS04) { Name (_ADR, 4) }
+Device (HS05) { Name (_ADR, 5) }
+Device (HS06) { Name (_ADR, 6) }
+Device (HS07) { Name (_ADR, 7) }
+Device (HS08) { Name (_ADR, 8) }
+
+/* USB3 */
+Device (SS01) { Name (_ADR, 9) }
+Device (SS02) { Name (_ADR, 10) }
+Device (SS03) { Name (_ADR, 11) }
+Device (SS04) { Name (_ADR, 12) }
+Device (SS05) { Name (_ADR, 13) }
+Device (SS06) { Name (_ADR, 14) }
diff --git a/src/soc/intel/apollolake/acpi/xhci_glk_ports.asl b/src/soc/intel/apollolake/acpi/xhci_glk_ports.asl
new file mode 100644
index 0000000..e3b045c
--- /dev/null
+++ b/src/soc/intel/apollolake/acpi/xhci_glk_ports.asl
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Google LLC.
+ * Copyright 2019 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* USB2 */
+Device (HS01) { Name (_ADR, 1) }
+Device (HS02) { Name (_ADR, 2) }
+Device (HS03) { Name (_ADR, 3) }
+Device (HS04) { Name (_ADR, 4) }
+Device (HS05) { Name (_ADR, 5) }
+Device (HS06) { Name (_ADR, 6) }
+Device (HS07) { Name (_ADR, 7) }
+Device (HS08) { Name (_ADR, 8) }
+Device (HS09) { Name (_ADR, 9) }
+
+/* USB3 */
+Device (SS01) { Name (_ADR, 10) }
+Device (SS02) { Name (_ADR, 11) }
+Device (SS03) { Name (_ADR, 12) }
+Device (SS04) { Name (_ADR, 13) }
+Device (SS05) { Name (_ADR, 14) }
+Device (SS06) { Name (_ADR, 15) }
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index cddfe44..de33e82 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -121,6 +121,9 @@
case 5: return "HS06";
case 6: return "HS07";
case 7: return "HS08";
+ case 8:
+ if (IS_ENABLED(CONFIG_SOC_INTEL_GLK))
+ return "HS09";
}
break;
case 3:
--
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Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31197
Change subject: mb/google/hatch: Add USB port capabality ACPI support for USB2 port10
......................................................................
mb/google/hatch: Add USB port capabality ACPI support for USB2 port10
This implementation adds support to create ACPI package for USB port
capablity(_UPC) and physical location of device(_PLD) for USB2 port 10.
BUG:b:123375275
TEST:Verify _UPC and _PLD ACPI packages gets published for USB2 Port 10
in SSDT and BT is functional in discrete and integrated mode.
Change-Id: Ifeab24505a700e8e4677be20074c7d0400769cec
Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com>
---
M src/mainboard/google/hatch/Kconfig
M src/mainboard/google/hatch/variants/baseboard/devicetree.cb
2 files changed, 7 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/31197/1
diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig
index d3ad1a0..9953648 100644
--- a/src/mainboard/google/hatch/Kconfig
+++ b/src/mainboard/google/hatch/Kconfig
@@ -5,6 +5,7 @@
select DRIVERS_I2C_GENERIC
select DRIVERS_I2C_HID
select DRIVERS_SPI_ACPI
+ select DRIVERS_USB_ACPI
select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_LPC
select HAVE_ACPI_RESUME
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
index cea64e4..2520d29 100644
--- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
@@ -132,7 +132,7 @@
device usb 2.3 on end
end
chip drivers/usb/acpi
- register "desc" = ""Bluetooth""
+ register "desc" = ""Discrete bluetooth""
register "type" = "UPC_TYPE_INTERNAL"
device usb 2.4 on end
end
@@ -147,6 +147,11 @@
device usb 2.6 on end
end
chip drivers/usb/acpi
+ register "desc" = ""Integrated CnVi bluetooth""
+ register "type" = "UPC_TYPE_INTERNAL"
+ device usb 2.9 on end
+ end
+ chip drivers/usb/acpi
register "desc" = ""Left Type-C Port""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "group" = "ACPI_PLD_GROUP(1, 1)"
--
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Xiang Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29916 )
Change subject: Fix coreboot table record alignment to 8-byte boundary
......................................................................
Patch Set 5:
> Why are we doing this? The coreboot table has always had unaligned
> records. It's the responsibility of the caller to deal with that.
Yes, the coreboot table can be unaligned records. But this will cause a lot of misaligned memory access exceptions, such as adding some padding will not affect the program to run
--
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Xiang Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29916 )
Change subject: Fix coreboot table record alignment to 8-byte boundary
......................................................................
Patch Set 5:
> https://review.coreboot.org/c/coreboot/+/18165 <--- The previous
> patch that changed something about the alignment in coreboot tables
Yes, this patch can solve the problem under the RISC-V platform, but if you add a 128-bit new platform, you need to modify a lot of code.
--
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Martin Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/30042 )
Change subject: mb/google/kahlee/variants/liara: Update eDP power off timing sequence
......................................................................
Abandoned
No longer needed.
--
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Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31160
Change subject: soc/amd/stoneyridge: Reboot if missing MRC cache info
......................................................................
soc/amd/stoneyridge: Reboot if missing MRC cache info
AGESA doesn't detect invalid NV data during AmdInitResume(). In
cases where the data has been erased, or cannot be found, reboot
the system. Otherwise the user will experience a hang when cbmem
isn't recovered and the postcar frame cannot be initialized.
BUG=b:122725586
TEST=Write S3 NV save data with 0xff and force reboot
Change-Id: Ib3cf2515f300decd3de198f7741660d95ee4c744
Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com>
---
M src/soc/amd/common/block/s3/s3_resume.c
1 file changed, 21 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/31160/1
diff --git a/src/soc/amd/common/block/s3/s3_resume.c b/src/soc/amd/common/block/s3/s3_resume.c
index 04414e8..adbda64 100644
--- a/src/soc/amd/common/block/s3/s3_resume.c
+++ b/src/soc/amd/common/block/s3/s3_resume.c
@@ -16,7 +16,9 @@
#include <stage_cache.h>
#include <mrc_cache.h>
+#include <reset.h>
#include <console/console.h>
+#include <soc/southbridge.h>
#include <amdblocks/s3_resume.h>
/* Training data versioning is not supported or tracked. */
@@ -33,11 +35,25 @@
}
*base = rdev_mmap_full(&rdev);
*size = region_device_sz(&rdev);
- if (!*base || !*size)
- printk(BIOS_ERR, "Error: S3 NV data not found\n");
- else
- printk(BIOS_SPEW, "S3 NV data @0x%p 0x%0zx total bytes\n",
- *base, *size);
+ if (!*base || !*size) {
+ printk(BIOS_ERR, "Error: S3 NV data not found, rebooting...\n");
+ set_pm1cnt_s5();
+ board_reset();
+ }
+
+ int i;
+ uint8_t erased = 0xff;
+ uint8_t *s3nv = *base;
+ for (i = 0 ; i < *size ; i++)
+ erased &= *(s3nv + i);
+
+ if (erased == 0xff) {
+ printk(BIOS_ERR, "Error: S3 NV data invalid, rebooting...\n");
+ set_pm1cnt_s5();
+ board_reset();
+ }
+
+ printk(BIOS_SPEW, "S3 NV data @0x%p, 0x%0zx bytes\n", *base, *size);
}
void get_s3vol_info(void **base, size_t *size)
--
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Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29916 )
Change subject: Fix coreboot table record alignment to 8-byte boundary
......................................................................
Patch Set 5:
Why are we doing this? The coreboot table has always had unaligned records. It's the responsibility of the caller to deal with that.
--
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