Keith Short has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31209
Change subject: src/soc/intel/common: Clear GPIO driver ownership when not requested
......................................................................
src/soc/intel/common: Clear GPIO driver ownership when not requested
The default state of the HOSTSW_OWN register in the PCH is zero, which
configures GPIO pins for ACPI ownership. The board variabt GPIO tables
can request specific pins to be configured for GPIO driver ownership.
This change sets the HOSTSW_OWN ownership bit when requested and
explicitly clears the ownership bit if not requested.
BUG=b:120884290
BRANCH=none
TEST=Build coreboot on sarien. Verified UEFI to coreboot transition
boots successfully.
Change-Id: Ia82539dbbbc7cf5dfb9223902d563cafec1a73e5
Signed-off-by: Keith Short <keithshort(a)chromium.org>
---
M src/soc/intel/common/block/gpio/gpio.c
1 file changed, 17 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/31209/1
diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c
index 294218c..51e7b47 100644
--- a/src/soc/intel/common/block/gpio/gpio.c
+++ b/src/soc/intel/common/block/gpio/gpio.c
@@ -131,23 +131,30 @@
static void gpio_configure_owner(const struct pad_config *cfg,
const struct pad_community *comm)
{
- uint16_t hostsw_reg;
+ uint32_t hostsw_own;
+ uint16_t hostsw_own_offset;
int pin;
pin = relative_pad_in_comm(comm, cfg->pad);
- /* The 4th bit in pad_config 1 (RO) is used to indicate if the pad
- * needs GPIO driver ownership.
- */
- if (!(cfg->pad_config[1] & PAD_CFG1_GPIO_DRIVER))
- return;
-
/* Based on the gpio pin number configure the corresponding bit in
* HOSTSW_OWN register. Value of 0x1 indicates GPIO Driver onwership.
*/
- hostsw_reg = comm->host_own_reg_0;
- hostsw_reg += gpio_group_index_scaled(comm, pin, sizeof(uint32_t));
- pcr_or32(comm->port, hostsw_reg, gpio_bitmask_within_group(comm, pin));
+ hostsw_own_offset = comm->host_own_reg_0;
+ hostsw_own_offset += gpio_group_index_scaled(comm, pin, sizeof(uint32_t));
+
+ hostsw_own = pcr_read32(comm->port, hostsw_own_offset);
+
+ /* The 4th bit in pad_config 1 (RO) is used to indicate if the pad
+ * needs GPIO driver ownership. Set the bit if GPIO driver ownership
+ * requested, otherwise clear the bit.
+ */
+ if (cfg->pad_config[1] & PAD_CFG1_GPIO_DRIVER)
+ hostsw_own |= gpio_bitmask_within_group(comm, pin);
+ else
+ hostsw_own &= ~gpio_bitmask_within_group(comm, pin);
+
+ pcr_write32(comm->port, hostsw_own_offset, hostsw_own);
}
static void gpi_enable_smi(const struct pad_config *cfg,
--
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Gerrit-Change-Id: Ia82539dbbbc7cf5dfb9223902d563cafec1a73e5
Gerrit-Change-Number: 31209
Gerrit-PatchSet: 1
Gerrit-Owner: Keith Short <keithshort(a)chromium.org>
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Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31200
Change subject: soc/intel/apl: Call mca_configure() on cold boots only
......................................................................
soc/intel/apl: Call mca_configure() on cold boots only
By BIOS Spec we must not do this on warm boots. It also addresses half
of the TODO comment.
TEST=Confirmed that warm boots on Kontron/mAL10 don't hang any more.
Change-Id: I09b4a2fe22267d7318951aac20a3ea566403492e
Signed-off-by: Nico Huber <nico.huber(a)secunet.com>
---
M src/soc/intel/apollolake/cpu.c
1 file changed, 5 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/31200/1
diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c
index bcec28e..c3b689a 100644
--- a/src/soc/intel/apollolake/cpu.c
+++ b/src/soc/intel/apollolake/cpu.c
@@ -17,6 +17,7 @@
* GNU General Public License for more details.
*/
+#include <arch/acpi.h>
#include <assert.h>
#include <console/console.h>
#include "chip.h"
@@ -70,10 +71,10 @@
void soc_core_init(struct device *cpu)
{
/* Clear out pending MCEs */
- /* TODO(adurbin): This should only be done on a cold boot. Also, some
- * of these banks are core vs package scope. For now every CPU clears
- * every bank. */
- mca_configure(NULL);
+ /* TODO(adurbin): Some of these banks are core vs package
+ scope. For now every CPU clears every bank. */
+ if (acpi_get_sleep_type() != ACPI_S0)
+ mca_configure(NULL);
/* Set core MSRs */
reg_script_run(core_msr_script);
--
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Gerrit-Change-Id: I09b4a2fe22267d7318951aac20a3ea566403492e
Gerrit-Change-Number: 31200
Gerrit-PatchSet: 1
Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>
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Hung-Te Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31088
Change subject: mb/google/kukui: Add default HWID for Chrome OS
......................................................................
mb/google/kukui: Add default HWID for Chrome OS
The default value for Chrome OS HWID should be different.
Calculated as HWID v1.
BUG=None
BRANCH=kukui
TEST=build and boots properly.
Change-Id: I39c640562c1c3b117292b8abacd36a4a9c2fa6c6
Signed-off-by: Hung-Te Lin <hungte(a)chromium.org>
---
M src/mainboard/google/kukui/Kconfig
1 file changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/31088/1
diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig
index 7635e5f..1a594a3 100644
--- a/src/mainboard/google/kukui/Kconfig
+++ b/src/mainboard/google/kukui/Kconfig
@@ -59,4 +59,9 @@
hex
default 0x2
+config GBB_HWID
+ string
+ depends on CHROMEOS
+ default "KUKUI TEST 9847"
+
endif
--
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Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30502 )
Change subject: cpu/x86/mtrr: Fix sign overflow
......................................................................
cpu/x86/mtrr: Fix sign overflow
Use unsigned long to prevent sign overflow.
Fixes wrong MTRRs settings on x86_64 romstage.
Signed-off-by: Patrick Rudolph <siro(a)das-labor.org>
Change-Id: I71b61a45becc17bf60a619e4131864c82a16b0d1
Reviewed-on: https://review.coreboot.org/c/30502
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Angel Pons <th3fanbus(a)gmail.com>
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
---
M src/include/cpu/x86/mtrr.h
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Paul Menzel: Looks good to me, but someone else must approve
Angel Pons: Looks good to me, approved
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h
index eb7d78d..0398a2e 100644
--- a/src/include/cpu/x86/mtrr.h
+++ b/src/include/cpu/x86/mtrr.h
@@ -150,7 +150,7 @@
#define _ALIGN_DOWN_POW2(x) ((x) & ~_POW2_MASK(x))
/* Calculate `4GiB - x` (e.g. absolute address for offset from 4GiB) */
-#define _FROM_4G_TOP(x) (((1 << 20) - ((x) >> 12)) << 12)
+#define _FROM_4G_TOP(x) (((1UL << 20) - ((x) >> 12)) << 12)
/* At the end of romstage, low RAM 0..CACHE_TM_RAMTOP may be set
* as write-back cacheable to speed up ramstage decompression.
--
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Gerrit-Change-Number: 30502
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31190 )
Change subject: nb/intel/gm45: Use a common romstage
......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/#/c/31190/4/src/northbridge/intel/gm45/gm45.h
File src/northbridge/intel/gm45/gm45.h:
https://review.coreboot.org/#/c/31190/4/src/northbridge/intel/gm45/gm45.h@4…
PS4, Line 443: void mb_pre_raminit_setup(sysinfo_t *); /* optional */
function definition argument 'sysinfo_t *' should also have an identifier name
--
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