February 2019 - coreboot-gerrit

Change in ...coreboot[master]: mb/google/hatch: Add keyboard backlight support
by Ivy Jian (Code Review) Feb. 5, 2019

Feb. 5, 2019

Ivy Jian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31175 Change subject: mb/google/hatch: Add keyboard backlight support ...................................................................... mb/google/hatch: Add keyboard backlight support This change adds keyboard backlight feature for Hatch platform BUG=b:122799544 BRANCH=none TEST=keyboard backlight works when EC reports correct info. Change-Id: I29273122f061e0e442f6629351ef3670535c0507 Signed-off-by: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> --- M src/mainboard/google/hatch/variants/baseboard/include/baseboard/ec.h 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/31175/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/ec.h index f9cebd7..75d583e 100644 --- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/ec.h @@ -78,4 +78,7 @@ #define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ #define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ +/* Enable EC backed Keyboard Backlight in ACPI */ +#define EC_ENABLE_KEYBOARD_BACKLIGHT + #endif /* __BASEBOARD_EC_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31175 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29273122f061e0e442f6629351ef3670535c0507 Gerrit-Change-Number: 31175 Gerrit-PatchSet: 1 Gerrit-Owner: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: intel/quark: Fix COMMONLIB_STORAGE in CAR
by Kyösti Mälkki (Code Review) Feb. 5, 2019

Feb. 5, 2019

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31191 Change subject: intel/quark: Fix COMMONLIB_STORAGE in CAR ...................................................................... intel/quark: Fix COMMONLIB_STORAGE in CAR The allocation is not required before romstage, so it can be just another CAR_GLOBAL instead of polluting the linker script. Change-Id: I0738a655f6cc924fbed92ea630f85406e3f58c0b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/car.ld M src/soc/intel/quark/storage_test.c 2 files changed, 7 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/31191/1 diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 44b394e..58961ac 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -61,11 +61,6 @@ * to reside in the migrated area (between _car_relocatable_data_start * and _car_relocatable_data_end). */ TIMESTAMP(., 0x200) -#if IS_ENABLED(CONFIG_COMMONLIB_STORAGE) - _car_drivers_storage_start = .; - . += 256; - _car_drivers_storage_end = .; -#endif _car_ehci_dbg_info_start = .; /* Reserve sizeof(struct ehci_dbg_info). */ . += 0x60; diff --git a/src/soc/intel/quark/storage_test.c b/src/soc/intel/quark/storage_test.c index 0a5e22d..d3cd1d3 100644 --- a/src/soc/intel/quark/storage_test.c +++ b/src/soc/intel/quark/storage_test.c @@ -33,8 +33,8 @@ int log_full CAR_GLOBAL; long log_start_time CAR_GLOBAL; #endif -extern uint8_t _car_drivers_storage_start; -extern uint8_t _car_drivers_storage_end; + +static uint8_t drivers_storage[256] CAR_GLOBAL; #define STORAGE_DEBUG BIOS_DEBUG #define LOG_DEBUG (IS_ENABLED(CONFIG_STORAGE_LOG) ? STORAGE_DEBUG : BIOS_NEVER) @@ -169,16 +169,15 @@ unsigned int previous_partition; struct sdhci_ctrlr *sdhci_ctrlr; + ASSERT(sizeof(struct sdhci_ctrlr) <= sizeof(drivers_storage)); + /* Get the structure addresses */ media = NULL; if (ENV_ROMSTAGE) - media = car_get_var_ptr(&_car_drivers_storage_start); + media = car_get_var_ptr(drivers_storage); else media = cbmem_find(CBMEM_ID_STORAGE_DATA); sdhci_ctrlr = (void *)(((uintptr_t)(media + 1) + 0x7) & ~7); - if (ENV_ROMSTAGE) - ASSERT((struct sdhci_ctrlr *)&_car_drivers_storage_end - >= (sdhci_ctrlr + 1)); media->ctrlr = (struct sd_mmc_ctrlr *)sdhci_ctrlr; sdhci_ctrlr->ioaddr = (void *)bar; @@ -247,19 +246,15 @@ { struct storage_media *media; struct sdhci_ctrlr *sdhci_ctrlr; - size_t size; + size_t size = sizeof(drivers_storage); /* Locate the data structures in CBMEM */ - size = &_car_drivers_storage_end - &_car_drivers_storage_start; - ASSERT(size == 256); media = cbmem_add(CBMEM_ID_STORAGE_DATA, size); ASSERT(media != NULL); sdhci_ctrlr = (void *)(((uintptr_t)(media + 1) + 0x7) & ~7); - ASSERT((sdhci_ctrlr + 1) - <= (struct sdhci_ctrlr *)&_car_drivers_storage_end); /* Migrate the data into CBMEM */ - memcpy(media, &_car_drivers_storage_start, size); + memcpy(media, car_get_var_ptr(drivers_storage), size); media->ctrlr = &sdhci_ctrlr->sd_mmc_ctrlr; } -- To view, visit https://review.coreboot.org/c/coreboot/+/31191 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0738a655f6cc924fbed92ea630f85406e3f58c0b Gerrit-Change-Number: 31191 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/soc/intel/common: Clear GPIO driver ownership when not requested
by Keith Short (Code Review) Feb. 5, 2019

Feb. 5, 2019

Keith Short has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31209 Change subject: src/soc/intel/common: Clear GPIO driver ownership when not requested ...................................................................... src/soc/intel/common: Clear GPIO driver ownership when not requested The default state of the HOSTSW_OWN register in the PCH is zero, which configures GPIO pins for ACPI ownership. The board variabt GPIO tables can request specific pins to be configured for GPIO driver ownership. This change sets the HOSTSW_OWN ownership bit when requested and explicitly clears the ownership bit if not requested. BUG=b:120884290 BRANCH=none TEST=Build coreboot on sarien. Verified UEFI to coreboot transition boots successfully. Change-Id: Ia82539dbbbc7cf5dfb9223902d563cafec1a73e5 Signed-off-by: Keith Short <keithshort(a)chromium.org> --- M src/soc/intel/common/block/gpio/gpio.c 1 file changed, 17 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/31209/1 diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c index 294218c..51e7b47 100644 --- a/src/soc/intel/common/block/gpio/gpio.c +++ b/src/soc/intel/common/block/gpio/gpio.c @@ -131,23 +131,30 @@ static void gpio_configure_owner(const struct pad_config *cfg, const struct pad_community *comm) { - uint16_t hostsw_reg; + uint32_t hostsw_own; + uint16_t hostsw_own_offset; int pin; pin = relative_pad_in_comm(comm, cfg->pad); - /* The 4th bit in pad_config 1 (RO) is used to indicate if the pad - * needs GPIO driver ownership. - */ - if (!(cfg->pad_config[1] & PAD_CFG1_GPIO_DRIVER)) - return; - /* Based on the gpio pin number configure the corresponding bit in * HOSTSW_OWN register. Value of 0x1 indicates GPIO Driver onwership. */ - hostsw_reg = comm->host_own_reg_0; - hostsw_reg += gpio_group_index_scaled(comm, pin, sizeof(uint32_t)); - pcr_or32(comm->port, hostsw_reg, gpio_bitmask_within_group(comm, pin)); + hostsw_own_offset = comm->host_own_reg_0; + hostsw_own_offset += gpio_group_index_scaled(comm, pin, sizeof(uint32_t)); + + hostsw_own = pcr_read32(comm->port, hostsw_own_offset); + + /* The 4th bit in pad_config 1 (RO) is used to indicate if the pad + * needs GPIO driver ownership. Set the bit if GPIO driver ownership + * requested, otherwise clear the bit. + */ + if (cfg->pad_config[1] & PAD_CFG1_GPIO_DRIVER) + hostsw_own |= gpio_bitmask_within_group(comm, pin); + else + hostsw_own &= ~gpio_bitmask_within_group(comm, pin); + + pcr_write32(comm->port, hostsw_own_offset, hostsw_own); } static void gpi_enable_smi(const struct pad_config *cfg, -- To view, visit https://review.coreboot.org/c/coreboot/+/31209 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia82539dbbbc7cf5dfb9223902d563cafec1a73e5 Gerrit-Change-Number: 31209 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Short <keithshort(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/apl: Call mca_configure() on cold boots only
by Nico Huber (Code Review) Feb. 5, 2019

Feb. 5, 2019

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31200 Change subject: soc/intel/apl: Call mca_configure() on cold boots only ...................................................................... soc/intel/apl: Call mca_configure() on cold boots only By BIOS Spec we must not do this on warm boots. It also addresses half of the TODO comment. TEST=Confirmed that warm boots on Kontron/mAL10 don't hang any more. Change-Id: I09b4a2fe22267d7318951aac20a3ea566403492e Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/soc/intel/apollolake/cpu.c 1 file changed, 5 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/31200/1 diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index bcec28e..c3b689a 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -17,6 +17,7 @@ * GNU General Public License for more details. */ +#include <arch/acpi.h> #include <assert.h> #include <console/console.h> #include "chip.h" @@ -70,10 +71,10 @@ void soc_core_init(struct device *cpu) { /* Clear out pending MCEs */ - /* TODO(adurbin): This should only be done on a cold boot. Also, some - * of these banks are core vs package scope. For now every CPU clears - * every bank. */ - mca_configure(NULL); + /* TODO(adurbin): Some of these banks are core vs package + scope. For now every CPU clears every bank. */ + if (acpi_get_sleep_type() != ACPI_S0) + mca_configure(NULL); /* Set core MSRs */ reg_script_run(core_msr_script); -- To view, visit https://review.coreboot.org/c/coreboot/+/31200 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I09b4a2fe22267d7318951aac20a3ea566403492e Gerrit-Change-Number: 31200 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/cpulib: Add debug message to mca_configure()
by Nico Huber (Code Review) Feb. 5, 2019

Feb. 5, 2019

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31199 Change subject: soc/intel/cpulib: Add debug message to mca_configure() ...................................................................... soc/intel/cpulib: Add debug message to mca_configure() Change-Id: Idfe93e454cc0ce0d8e06e23beaddee2f11f5eedd Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/soc/intel/common/block/cpu/cpulib.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/31199/1 diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index d18b50c..ece79d6 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -323,6 +323,8 @@ int i; int num_banks; + printk(BIOS_DEBUG, "Clearing out pending MCEs\n"); + msr = rdmsr(IA32_MCG_CAP); num_banks = msr.lo & 0xff; msr.lo = msr.hi = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/31199 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idfe93e454cc0ce0d8e06e23beaddee2f11f5eedd Gerrit-Change-Number: 31199 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/poppy/variants/atlas: config GPP_D1 as no-connect
by Patrick Georgi (Code Review) Feb. 5, 2019

Feb. 5, 2019

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31210 ) Change subject: mb/google/poppy/variants/atlas: config GPP_D1 as no-connect ...................................................................... mb/google/poppy/variants/atlas: config GPP_D1 as no-connect This reconfigures the GPP_D1 GPIO pin as a no-connect. It really doesn't go anywhere today or on previous revs of the board. BUG=b:110614620 BRANCH=none TEST=atlas still boots Change-Id: Iea53cf909f8f060c4e0f14e8b4ad579b838b7caa Signed-off-by: Caveh Jalali <caveh(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/31210 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/poppy/variants/atlas/gpio.c 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/mainboard/google/poppy/variants/atlas/gpio.c b/src/mainboard/google/poppy/variants/atlas/gpio.c index 5a76d83..372c66a 100644 --- a/src/mainboard/google/poppy/variants/atlas/gpio.c +++ b/src/mainboard/google/poppy/variants/atlas/gpio.c @@ -160,8 +160,8 @@ /* D0 : SPI1_CS# ==> NC */ PAD_CFG_NC(GPP_D0), - /* D1 : SPI1_CLK ==> TRACKPAD_RESET_1V8_ODL */ - PAD_CFG_GPO(GPP_D1, 0, DEEP), + /* D1 : SPI1_CLK ==> NC */ + PAD_CFG_NC(GPP_D1), /* D2 : SPI1_MISO ==> NC */ PAD_CFG_NC(GPP_D2), /* D3 : SPI1_MOSI ==> NC */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31210 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea53cf909f8f060c4e0f14e8b4ad579b838b7caa Gerrit-Change-Number: 31210 Gerrit-PatchSet: 2 Gerrit-Owner: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: Revert "mb/google/poppy/variant/atlas: I2C: run trackpad at 1MHz"
by Patrick Georgi (Code Review) Feb. 5, 2019

Feb. 5, 2019

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31212 ) Change subject: Revert "mb/google/poppy/variant/atlas: I2C: run trackpad at 1MHz" ...................................................................... Revert "mb/google/poppy/variant/atlas: I2C: run trackpad at 1MHz" This reverts commit 7696290004b6490c7ef8027d7ddf67b163e7dad8. We're seeing trackpad problems on some units with the I2C bus running at 1MHz but not at 400KHz. So, revert back to 400KHz until we understand how to make 1MHz operation more robust. BUG=b:123650686 Change-Id: Ifb06afece9eee0c153240d35e6c3001f5b74f310 Signed-off-by: Caveh Jalali <caveh(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/31212 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/poppy/variants/atlas/devicetree.cb 1 file changed, 6 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index f8a6e6d..275b27d 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -207,15 +207,14 @@ .fall_time_ns = 38, }, .i2c[2] = { - .speed = I2C_SPEED_FAST_PLUS, + .speed = I2C_SPEED_FAST, .speed_config[0] = { - .speed = I2C_SPEED_FAST_PLUS, - .scl_lcnt = 69, - .scl_hcnt = 33, - .sda_hold = 20, - } + .speed = I2C_SPEED_FAST, + .scl_lcnt = 186, + .scl_hcnt = 93, + .sda_hold = 36, + }, }, - .i2c[3] = { .speed = I2C_SPEED_FAST, .rise_time_ns = 98, @@ -296,7 +295,6 @@ register "generic.hid" = ""ACPI0C50"" register "generic.desc" = ""ELAN Touchpad"" register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_A19_IRQ)" - register "generic.speed" = "I2C_SPEED_FAST_PLUS" register "generic.wake" = "GPE0_DW0_23" # GPP_A23 register "hid_desc_reg_offset" = "0x01" device i2c 0x15 on end -- To view, visit https://review.coreboot.org/c/coreboot/+/31212 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb06afece9eee0c153240d35e6c3001f5b74f310 Gerrit-Change-Number: 31212 Gerrit-PatchSet: 3 Gerrit-Owner: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: mb/google/kukui: Add default HWID for Chrome OS
by Hung-Te Lin (Code Review) Feb. 5, 2019

Feb. 5, 2019

Hung-Te Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31088 Change subject: mb/google/kukui: Add default HWID for Chrome OS ...................................................................... mb/google/kukui: Add default HWID for Chrome OS The default value for Chrome OS HWID should be different. Calculated as HWID v1. BUG=None BRANCH=kukui TEST=build and boots properly. Change-Id: I39c640562c1c3b117292b8abacd36a4a9c2fa6c6 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- M src/mainboard/google/kukui/Kconfig 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/31088/1 diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig index 7635e5f..1a594a3 100644 --- a/src/mainboard/google/kukui/Kconfig +++ b/src/mainboard/google/kukui/Kconfig @@ -59,4 +59,9 @@ hex default 0x2 +config GBB_HWID + string + depends on CHROMEOS + default "KUKUI TEST 9847" + endif -- To view, visit https://review.coreboot.org/c/coreboot/+/31088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I39c640562c1c3b117292b8abacd36a4a9c2fa6c6 Gerrit-Change-Number: 31088 Gerrit-PatchSet: 1 Gerrit-Owner: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: cpu/x86/mtrr: Fix sign overflow
by Patrick Georgi (Code Review) Feb. 5, 2019

Feb. 5, 2019

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30502 ) Change subject: cpu/x86/mtrr: Fix sign overflow ...................................................................... cpu/x86/mtrr: Fix sign overflow Use unsigned long to prevent sign overflow. Fixes wrong MTRRs settings on x86_64 romstage. Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Change-Id: I71b61a45becc17bf60a619e4131864c82a16b0d1 Reviewed-on: https://review.coreboot.org/c/30502 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- M src/include/cpu/x86/mtrr.h 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index eb7d78d..0398a2e 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -150,7 +150,7 @@ #define _ALIGN_DOWN_POW2(x) ((x) & ~_POW2_MASK(x)) /* Calculate `4GiB - x` (e.g. absolute address for offset from 4GiB) */ -#define _FROM_4G_TOP(x) (((1 << 20) - ((x) >> 12)) << 12) +#define _FROM_4G_TOP(x) (((1UL << 20) - ((x) >> 12)) << 12) /* At the end of romstage, low RAM 0..CACHE_TM_RAMTOP may be set * as write-back cacheable to speed up ramstage decompression. -- To view, visit https://review.coreboot.org/c/coreboot/+/30502 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71b61a45becc17bf60a619e4131864c82a16b0d1 Gerrit-Change-Number: 30502 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: nb/intel/gm45: Use a common romstage
by build bot (Jenkins) (Code Review) Feb. 5, 2019

Feb. 5, 2019

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31190 ) Change subject: nb/intel/gm45: Use a common romstage ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/#/c/31190/4/src/northbridge/intel/gm45/gm45.h File src/northbridge/intel/gm45/gm45.h: https://review.coreboot.org/#/c/31190/4/src/northbridge/intel/gm45/gm45.h@4… PS4, Line 443: void mb_pre_raminit_setup(sysinfo_t *); /* optional */ function definition argument 'sysinfo_t *' should also have an identifier name -- To view, visit https://review.coreboot.org/c/coreboot/+/31190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30ef7f6962aabde78b5c40e0b53bb85e01c254c1 Gerrit-Change-Number: 31190 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 05 Feb 2019 12:34:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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