February 2019 - coreboot-gerrit

Change in ...coreboot[master]: src/soc/intel/cannonlake: Add _DSM methods for LPIT table

by Shaunak Saha (Code Review)

Shaunak Saha has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31101 ) Change subject: src/soc/intel/cannonlake: Add _DSM methods for LPIT table ...................................................................... Patch Set 15: (5 comments) > Patch Set 11: > > (4 comments) https://review.coreboot.org/#/c/31101/11//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/31101/11//COMMIT_MSG@10 PS11, Line 10: get > gets? Done https://review.coreboot.org/#/c/31101/11//COMMIT_MSG@17 PS11, Line 17: does > do Done https://review.coreboot.org/#/c/31101/11//COMMIT_MSG@17 PS11, Line 17: throws > throw Done https://review.coreboot.org/#/c/31101/5/src/soc/intel/cannonlake/acpi/lpit.… File src/soc/intel/cannonlake/acpi/lpit.asl: https://review.coreboot.org/#/c/31101/5/src/soc/intel/cannonlake/acpi/lpit.… PS5, Line 26: LEqual(Arg0, ^UUID) > Done I was testing with this new syntax but it didnt worked with this. No compilation error but seems like its not able to parse this new syntax. Need to debug if there is some version mismatch issue. https://review.coreboot.org/#/c/31101/11/src/soc/intel/cannonlake/acpi/lpit… File src/soc/intel/cannonlake/acpi/lpit.asl: https://review.coreboot.org/#/c/31101/11/src/soc/intel/cannonlake/acpi/lpit… PS11, Line 75: //device (LPID) > Space after //. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/31101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia908969decf7cf12f505becb4f4a4a9caa7ed6db Gerrit-Change-Number: 31101 Gerrit-PatchSet: 15 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Assignee: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 02 Feb 2019 18:25:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Comment-In-Reply-To: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: comment

2 years, 4 months

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Change in ...coreboot[master]: Fix coreboot table record alignment to 8-byte boundary

by Jonathan Neuschäfer (Code Review)

Jonathan Neuschäfer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29916 ) Change subject: Fix coreboot table record alignment to 8-byte boundary ...................................................................... Patch Set 5: https://review.coreboot.org/c/coreboot/+/18165 <--- The previous patch that changed something about the alignment in coreboot tables -- To view, visit https://review.coreboot.org/c/coreboot/+/29916 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1846be0e26ab3c81858d8cf727517e1462035e64 Gerrit-Change-Number: 29916 Gerrit-PatchSet: 5 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Shawn C <citypw(a)gmail.com> Gerrit-Reviewer: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Sat, 02 Feb 2019 17:13:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

2 years, 4 months

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Change in ...coreboot[master]: WIP: mb/qemu-riscv: update to match current qemu version

by Philipp Hug (Code Review)

Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30554 Change subject: WIP: mb/qemu-riscv: update to match current qemu version ...................................................................... WIP: mb/qemu-riscv: update to match current qemu version Boots again to payload not found on qemu. Change-Id: Ie107eb882cbaac5a5a06c1ff990e7b9364377640 Signed-off-by: Philipp Hug <philipp(a)hug.cx> --- M src/mainboard/emulation/qemu-riscv/Kconfig M src/mainboard/emulation/qemu-riscv/Makefile.inc M src/mainboard/emulation/qemu-riscv/mainboard.c M src/mainboard/emulation/qemu-riscv/memlayout.ld D src/mainboard/emulation/qemu-riscv/mtime.c M src/mainboard/emulation/qemu-riscv/rom_media.c M src/mainboard/emulation/qemu-riscv/uart.c 7 files changed, 23 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/30554/1 diff --git a/src/mainboard/emulation/qemu-riscv/Kconfig b/src/mainboard/emulation/qemu-riscv/Kconfig index 528b21e..ecaa764 100644 --- a/src/mainboard/emulation/qemu-riscv/Kconfig +++ b/src/mainboard/emulation/qemu-riscv/Kconfig @@ -13,7 +13,8 @@ ## GNU General Public License for more details. # To execute, do: -# qemu-system-arm -M vexpress-a9 -m 1024M -nographic -kernel build/coreboot.rom +# util/riscv/make-spike-elf.sh build/coreboot.rom build/coreboot.elf +# qemu-system-riscv64 -M virt -m 1024M -nographic -kernel build/coreboot.elf if BOARD_EMULATION_QEMU_RISCV diff --git a/src/mainboard/emulation/qemu-riscv/Makefile.inc b/src/mainboard/emulation/qemu-riscv/Makefile.inc index 1d882ac..eb99544 100644 --- a/src/mainboard/emulation/qemu-riscv/Makefile.inc +++ b/src/mainboard/emulation/qemu-riscv/Makefile.inc @@ -14,7 +14,7 @@ bootblock-y += uart.c bootblock-y += rom_media.c -bootblock-y += mtime.c +bootblock-y += clint.c romstage-y += romstage.c romstage-y += uart.c @@ -22,8 +22,10 @@ ramstage-y += uart.c ramstage-y += rom_media.c -ramstage-y += mtime.c +ramstage-y += clint.c bootblock-y += memlayout.ld romstage-y += memlayout.ld ramstage-y += memlayout.ld + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include diff --git a/src/mainboard/emulation/qemu-riscv/mainboard.c b/src/mainboard/emulation/qemu-riscv/mainboard.c index 7061bcf..4b428aa 100644 --- a/src/mainboard/emulation/qemu-riscv/mainboard.c +++ b/src/mainboard/emulation/qemu-riscv/mainboard.c @@ -16,6 +16,7 @@ #include <console/console.h> #include <device/device.h> #include <cbmem.h> +#include <symbols.h> static void mainboard_enable(struct device *dev) { @@ -24,7 +25,7 @@ die("No dev0; die\n"); } - ram_resource(dev, 0, 2048, 32768); + ram_resource(dev, 0, (uintptr_t)_dram / KiB, CONFIG_DRAM_SIZE_MB * KiB); cbmem_recovery(0); } diff --git a/src/mainboard/emulation/qemu-riscv/memlayout.ld b/src/mainboard/emulation/qemu-riscv/memlayout.ld index 615d1f2..032fbdd 100644 --- a/src/mainboard/emulation/qemu-riscv/memlayout.ld +++ b/src/mainboard/emulation/qemu-riscv/memlayout.ld @@ -14,15 +14,16 @@ */ #include <memlayout.h> - #include <arch/header.ld> +#define START 0x80000000 + SECTIONS { - DRAM_START(0x0) - BOOTBLOCK(0x0, 64K) - ROMSTAGE(0x20000, 128K) - STACK(0x40000, 0x3ff00) - PRERAM_CBMEM_CONSOLE(0x80000, 8K) - RAMSTAGE(0x100000, 16M) + DRAM_START(START) + BOOTBLOCK(START, 64K) + STACK(START + 4M, 4K) + ROMSTAGE(START + 4M + 64K, 128K) + PRERAM_CBMEM_CONSOLE(START + 4M + 192K, 8K) + RAMSTAGE(START + 4M + 200K, 16M) } diff --git a/src/mainboard/emulation/qemu-riscv/mtime.c b/src/mainboard/emulation/qemu-riscv/mtime.c deleted file mode 100644 index f8c2717..0000000 --- a/src/mainboard/emulation/qemu-riscv/mtime.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 HardenedLinux - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <mcall.h> - -/* FIXME: This is an empty implementation, please improve */ -/* This function is used to initialize HLS()->time/HLS()->timecmp */ -void mtime_init(void) -{ -} diff --git a/src/mainboard/emulation/qemu-riscv/rom_media.c b/src/mainboard/emulation/qemu-riscv/rom_media.c index c171307..bac1984 100644 --- a/src/mainboard/emulation/qemu-riscv/rom_media.c +++ b/src/mainboard/emulation/qemu-riscv/rom_media.c @@ -14,11 +14,12 @@ * GNU General Public License for more details. */ #include <boot_device.h> +#include <symbols.h> -/* This assumes that the CBFS resides at 0x0, which is true for the default - * configuration. */ +/* This assumes that the CBFS resides at start of dram, which is true for the + * default configuration. */ static const struct mem_region_device boot_dev = - MEM_REGION_DEV_RO_INIT(NULL, CONFIG_ROM_SIZE); + MEM_REGION_DEV_RO_INIT(_dram, CONFIG_ROM_SIZE); const struct region_device *boot_device_ro(void) { diff --git a/src/mainboard/emulation/qemu-riscv/uart.c b/src/mainboard/emulation/qemu-riscv/uart.c index 730ef3e..084362a 100644 --- a/src/mainboard/emulation/qemu-riscv/uart.c +++ b/src/mainboard/emulation/qemu-riscv/uart.c @@ -17,8 +17,9 @@ #include <console/uart.h> #include <arch/io.h> #include <boot/coreboot_tables.h> +#include <mainboard/addressmap.h> -static uint8_t *buf = (void *)0x3f8; +static uint8_t *buf = (void *)QEMU_VIRT_UART0; uintptr_t uart_platform_base(int idx) { return (uintptr_t) buf; @@ -47,7 +48,7 @@ { struct lb_serial serial; serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; - serial.baseaddr = 0x3f8; + serial.baseaddr = QEMU_VIRT_UART0; serial.baud = 115200; serial.regwidth = 1; lb_add_serial(&serial, data); -- To view, visit https://review.coreboot.org/c/coreboot/+/30554 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie107eb882cbaac5a5a06c1ff990e7b9364377640 Gerrit-Change-Number: 30554 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-MessageType: newchange

2 years, 4 months

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Change in ...coreboot[master]: riscv: Show hart id in trap handler

by Philipp Hug (Code Review)

Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31201 Change subject: riscv: Show hart id in trap handler ...................................................................... riscv: Show hart id in trap handler Also show hart id in trap information for easier debugging. Change-Id: I20acf86e1af111600c158295ae03b2167838d127 Signed-off-by: Philipp Hug <philipp(a)hug.cx> --- M src/arch/riscv/trap_handler.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/31201/1 diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c index e072bf7..6ec8e19 100644 --- a/src/arch/riscv/trap_handler.c +++ b/src/arch/riscv/trap_handler.c @@ -57,6 +57,7 @@ { const char *previous_mode; bool mprv = !!(tf->status & MSTATUS_MPRV); + int hart_id = read_csr(mhartid); /* Leave some space around the trap message */ printk(BIOS_DEBUG, "\n"); @@ -69,6 +70,7 @@ (void *)tf->cause); previous_mode = mstatus_to_previous_mode(read_csr(mstatus)); + printk(BIOS_DEBUG, "Hart ID: %d\n", hart_id); printk(BIOS_DEBUG, "Previous mode: %s%s\n", previous_mode, mprv? " (MPRV)":""); printk(BIOS_DEBUG, "Bad instruction pc: %p\n", (void *)tf->epc); -- To view, visit https://review.coreboot.org/c/coreboot/+/31201 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20acf86e1af111600c158295ae03b2167838d127 Gerrit-Change-Number: 31201 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-MessageType: newchange

2 years, 4 months

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Change in ...coreboot[master]: riscv: Simplify payload handling

by Philipp Hug (Code Review)

Hello Xiang Wang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31179 to review the following change. Change subject: riscv: Simplify payload handling ...................................................................... riscv: Simplify payload handling 1. Simplify payload code and convert it to C 2. Save the FDT pointer to HLS (hart-local storage). 3. Don't use mscratch to pass FDT pointer as it is used for exception handling. Change-Id: I32bf2a99e07a65358a7f19b899259f0816eb45e8 Signed-off-by: Xiang Wang <wxjstz(a)126.com> Signed-off-by: Philipp Hug <philipp(a)hug.cx> --- M src/arch/riscv/Makefile.inc M src/arch/riscv/boot.c M src/arch/riscv/bootblock.S M src/arch/riscv/include/arch/boot.h M src/arch/riscv/include/arch/stages.h M src/arch/riscv/include/mcall.h M src/arch/riscv/mcall.c D src/arch/riscv/payload.S A src/arch/riscv/payload.c M src/arch/riscv/stages.c 10 files changed, 87 insertions(+), 57 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/31179/1 diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index e4c8468..9d91f0c 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -137,7 +137,7 @@ ramstage-y += smp.c ramstage-y += boot.c ramstage-y += tables.c -ramstage-y += payload.S +ramstage-y += payload.c ramstage-$(ARCH_RISCV_PMP) += pmp.c ramstage-y += \ $(top)/src/lib/memchr.c \ diff --git a/src/arch/riscv/boot.c b/src/arch/riscv/boot.c index 3d8d5d6..dab4e09 100644 --- a/src/arch/riscv/boot.c +++ b/src/arch/riscv/boot.c @@ -19,6 +19,7 @@ #include <arch/encoding.h> #include <console/console.h> #include <arch/smp/smp.h> +#include <mcall.h> /* * A pointer to the Flattened Device Tree passed to coreboot by the boot ROM. @@ -26,27 +27,27 @@ * * This pointer is only used in ramstage! */ -const void *rom_fdt; static void do_arch_prog_run(struct prog *prog) { - void (*doit)(void *) = prog_entry(prog); - void riscvpayload(const void *fdt, void *payload); + void (*doit)(int hart_id, void *fdt); + int hart_id; + void *fdt = prog_entry_arg(prog); if (ENV_RAMSTAGE && prog_type(prog) == PROG_PAYLOAD) { /* - * FIXME: This is wrong and will crash. Linux can't (in early - * boot) access memory that's before its own loading address. - * We need to copy the FDT to a place where Linux can access it. + * If prog_entry_arg is not set (e.g. by fit_payload), use fdt from HLS instead. */ - const void *fdt = rom_fdt; - - printk(BIOS_SPEW, "FDT is at %p\n", fdt); - printk(BIOS_SPEW, "OK, let's go\n"); - riscvpayload(fdt, doit); + if (fdt == NULL) + fdt = HLS()->fdt; + run_payload(prog, fdt, RISCV_PAYLOAD_MODE_S); + return; } - doit(prog_entry_arg(prog)); + doit = prog_entry(prog); + hart_id = HLS()->hart_id; + + doit(hart_id, fdt); } void arch_prog_run(struct prog *prog) diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S index 7f84215..d4b8be7 100644 --- a/src/arch/riscv/bootblock.S +++ b/src/arch/riscv/bootblock.S @@ -50,6 +50,7 @@ # initialize hart-local storage csrr a0, mhartid + csrrw a1, mscratch, zero call hls_init li a0, CONFIG_RISCV_WORKING_HARTID diff --git a/src/arch/riscv/include/arch/boot.h b/src/arch/riscv/include/arch/boot.h index 24c1bed..34a507e 100644 --- a/src/arch/riscv/include/arch/boot.h +++ b/src/arch/riscv/include/arch/boot.h @@ -16,6 +16,12 @@ #ifndef ARCH_RISCV_INCLUDE_ARCH_BOOT_H #define ARCH_RISCV_INCLUDE_ARCH_BOOT_H -extern const void *rom_fdt; +#include <program_loading.h> + +#define RISCV_PAYLOAD_MODE_U 0 +#define RISCV_PAYLOAD_MODE_S 1 +#define RISCV_PAYLOAD_MODE_M 3 + +void run_payload(struct prog *prog, void *fdt, int payload_mode); #endif diff --git a/src/arch/riscv/include/arch/stages.h b/src/arch/riscv/include/arch/stages.h index 90bd60b..138298f 100644 --- a/src/arch/riscv/include/arch/stages.h +++ b/src/arch/riscv/include/arch/stages.h @@ -18,6 +18,7 @@ #include <main_decl.h> -void stage_entry(void) __attribute__((section(".text.stage_entry"))); +void stage_entry(int hart_id, void *fdt) + __attribute__((section(".text.stage_entry"))); #endif diff --git a/src/arch/riscv/include/mcall.h b/src/arch/riscv/include/mcall.h index 29df736..cd1ed6d 100644 --- a/src/arch/riscv/include/mcall.h +++ b/src/arch/riscv/include/mcall.h @@ -52,9 +52,14 @@ int ipi_pending; uint64_t *timecmp; uint64_t *time; + void *fdt; struct blocker entry; } hls_t; +_Static_assert( + sizeof(hls_t) == HLS_SIZE, + "HLS_SIZE must equal to sizeof(hls_t)"); + #define MACHINE_STACK_TOP() ({ \ /* coverity[uninit_use] : FALSE */ \ register uintptr_t sp asm ("sp"); \ @@ -66,7 +71,8 @@ #define MACHINE_STACK_SIZE RISCV_PGSIZE -void hls_init(uint32_t hart_id); // need to call this before launching linux +// need to call this before launching linux +void hls_init(uint32_t hart_id, void *fdt); /* This function is used to initialize HLS()->time/HLS()->timecmp */ void mtime_init(void); diff --git a/src/arch/riscv/mcall.c b/src/arch/riscv/mcall.c index 47cdd88..eaef644 100644 --- a/src/arch/riscv/mcall.c +++ b/src/arch/riscv/mcall.c @@ -34,10 +34,11 @@ int mcalldebug; // set this interactively for copious debug. -void hls_init(uint32_t hart_id) +void hls_init(uint32_t hart_id, void *fdt) { printk(BIOS_SPEW, "hart %d: HLS is %p\n", hart_id, HLS()); memset(HLS(), 0, sizeof(*HLS())); + HLS()->fdt = fdt; HLS()->hart_id = hart_id; mtime_init(); diff --git a/src/arch/riscv/payload.S b/src/arch/riscv/payload.S deleted file mode 100644 index 1b8cb96..0000000 --- a/src/arch/riscv/payload.S +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Google Inc - * Copyright (C) 2018 Jonathan Neuschäfer - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -// "return" to a payload. a0: FDT, a1: entry point - .global riscvpayload -riscvpayload: - /* Load the entry point */ - mv t0, a1 - csrw mepc, t0 - csrr t0, mstatus - - /* Set mstatus.MPP (the previous privilege mode) to supervisor mode */ - li t1, ~(3<<11) - and t0, t0, t1 - li t2, (1<<11) - or t0, t0, t2 - csrw mstatus, t0 - - /* Pass the right arguments and jump! */ - mv a1, a0 - csrr a0, mhartid - mret diff --git a/src/arch/riscv/payload.c b/src/arch/riscv/payload.c new file mode 100644 index 0000000..af2542f --- /dev/null +++ b/src/arch/riscv/payload.c @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc + * Copyright (C) 2018 HardenedLinux + * Copyright (C) 2018 Jonathan Neuschäfer + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <arch/boot.h> +#include <arch/encoding.h> +#include <console/console.h> + +void run_payload(struct prog *prog, void *fdt, int payload_mode) +{ + void (*doit)(int hart_id, void *fdt) = prog_entry(prog); + int hart_id = read_csr(mhartid); + uintptr_t status = read_csr(mstatus); + status &= ~MSTATUS_MPIE; + status &= ~MSTATUS_MPP; + switch (payload_mode) { + case RISCV_PAYLOAD_MODE_U: + break; + case RISCV_PAYLOAD_MODE_S: + status |= MSTATUS_SPP; + break; + case RISCV_PAYLOAD_MODE_M: + doit(hart_id, fdt); + return; + default: + die("wrong privilege level for payload"); + break; + } + write_csr(mstatus, status); + write_csr(mepc, doit); + asm volatile("mv a0, %0"::"r"(hart_id):"a0"); + asm volatile("mv a1, %0"::"r"(fdt):"a1"); + asm volatile("mret"); +} diff --git a/src/arch/riscv/stages.c b/src/arch/riscv/stages.c index 5e7fa4f..07b898f 100644 --- a/src/arch/riscv/stages.c +++ b/src/arch/riscv/stages.c @@ -28,18 +28,19 @@ #include <arch/encoding.h> #include <arch/stages.h> #include <arch/smp/smp.h> +#include <rules.h> +#include <mcall.h> -void stage_entry(void) +void stage_entry(int hart_id, void *fdt) { - smp_pause(CONFIG_RISCV_WORKING_HARTID); - /* * Save the FDT pointer before entering ramstage, because mscratch * might be overwritten in the trap handler, and there is code in * ramstage that generates misaligned access faults. */ - if (ENV_RAMSTAGE) - rom_fdt = (const void *)read_csr(mscratch); + HLS()->hart_id = hart_id; + HLS()->fdt = fdt; + smp_pause(CONFIG_RISCV_WORKING_HARTID); main(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/31179 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32bf2a99e07a65358a7f19b899259f0816eb45e8 Gerrit-Change-Number: 31179 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Xiang Wang <wxjstz(a)126.com> Gerrit-MessageType: newchange

2 years, 4 months

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Change in ...coreboot[master]: riscv: save FDT pointer from mscratch to HLS

by Philipp Hug (Code Review)

Philipp Hug has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27545 ) Change subject: riscv: save FDT pointer from mscratch to HLS ...................................................................... Patch Set 29: Code-Review-1 Superseeded by 31179 -- To view, visit https://review.coreboot.org/c/coreboot/+/27545 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24554528969e36c9e98c0ebd733e002e215a52e5 Gerrit-Change-Number: 27545 Gerrit-PatchSet: 29 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Shawn C <citypw(a)gmail.com> Gerrit-Reviewer: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Sat, 02 Feb 2019 16:39:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: riscv: add support to select the privilege level of the payload running

by Philipp Hug (Code Review)

Philipp Hug has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29494 ) Change subject: riscv: add support to select the privilege level of the payload running ...................................................................... Patch Set 30: Code-Review-1 Superseeded by 31179 -- To view, visit https://review.coreboot.org/c/coreboot/+/29494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96961246cd257b63cf167238aa0cf6e65272b951 Gerrit-Change-Number: 29494 Gerrit-PatchSet: 30 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Shawn C <citypw(a)gmail.com> Gerrit-Reviewer: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Sat, 02 Feb 2019 16:38:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/clevo/n130wu: Add mainboard

by build bot (Jenkins) (Code Review)

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28640 ) Change subject: mb/clevo/n130wu: Add mainboard ...................................................................... Patch Set 80: (2 comments) https://review.coreboot.org/#/c/28640/80/src/mainboard/clevo/n130wu/gpio.h File src/mainboard/clevo/n130wu/gpio.h: https://review.coreboot.org/#/c/28640/80/src/mainboard/clevo/n130wu/gpio.h@… PS80, Line 168: /* I2C5_SDA/ISH_I2C2_SDA */ _PAD_CFG_STRUCT(GPP_F10, 0x44000b02, 0x2000000), line over 80 characters https://review.coreboot.org/#/c/28640/80/src/mainboard/clevo/n130wu/gpio.h@… PS80, Line 169: /* I2C5_SCL/ISH_I2C2_SCL */ _PAD_CFG_STRUCT(GPP_F11, 0x44000b02, 0x2000000), line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/28640 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I364f5849ef88f43b85efbd7a635a27e54d08c513 Gerrit-Change-Number: 28640 Gerrit-PatchSet: 80 Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-Reviewer: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Shaleen jain <shaleen(a)jain.sh> Gerrit-Comment-Date: Sat, 02 Feb 2019 16:38:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/clevo/n130wu: Add mainboard

by Felix Singer (Code Review)

Hello Paul Menzel, Stefan Reinauer, Philipp Deppenwiese, build bot (Jenkins), Martin Roth, Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/28640 to look at the new patch set (#80). Change subject: mb/clevo/n130wu: Add mainboard ...................................................................... mb/clevo/n130wu: Add mainboard Devices: - N130WU / N131WU Working: - Compiling - Seabios, iPXE - NVMe, SATA3, booting from SSD into Arch Linux - USB2, USB3 - Graphics, mDP, HDMI - Sound - Webcam - WLAN, LAN, Bluetooth, LTE - Keyboard, touchpad - TPM - flashrom support; reading / flashing from Linux Works, but needs testing: - Thunderbolt WIP: - Documentation Not working: - EC ACPI Untested: - Virtualization Change-Id: I364f5849ef88f43b85efbd7a635a27e54d08c513 Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de> --- A Documentation/mainboard/clevo/index.md A Documentation/mainboard/clevo/n130wu/index.md A Documentation/mainboard/clevo/n130wu/n130wu_overview.jpg M Documentation/mainboard/index.md A src/mainboard/clevo/Kconfig A src/mainboard/clevo/Kconfig.name A src/mainboard/clevo/n130wu/Kconfig A src/mainboard/clevo/n130wu/Kconfig.name A src/mainboard/clevo/n130wu/Makefile.inc A src/mainboard/clevo/n130wu/acpi/ec.asl A src/mainboard/clevo/n130wu/acpi/superio.asl A src/mainboard/clevo/n130wu/acpi_tables.c A src/mainboard/clevo/n130wu/board_info.txt A src/mainboard/clevo/n130wu/devicetree.cb A src/mainboard/clevo/n130wu/dsdt.asl A src/mainboard/clevo/n130wu/gpio.h A src/mainboard/clevo/n130wu/hda_verb.c A src/mainboard/clevo/n130wu/pei_data.c A src/mainboard/clevo/n130wu/pei_data.h A src/mainboard/clevo/n130wu/ramstage.c A src/mainboard/clevo/n130wu/romstage.c A src/mainboard/clevo/n130wu/variants/n13xwu/data.vbt A src/mainboard/clevo/n130wu/variants/n13xwu/overridetree.cb 23 files changed, 933 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/28640/80 -- To view, visit https://review.coreboot.org/c/coreboot/+/28640 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I364f5849ef88f43b85efbd7a635a27e54d08c513 Gerrit-Change-Number: 28640 Gerrit-PatchSet: 80 Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-Reviewer: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Shaleen jain <shaleen(a)jain.sh> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: mb/ocp/wedge100s: Remove MAINBOARD_USES_IFD_GBE_REGION

by Patrick Rudolph (Code Review)

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31198 Change subject: mb/ocp/wedge100s: Remove MAINBOARD_USES_IFD_GBE_REGION ...................................................................... mb/ocp/wedge100s: Remove MAINBOARD_USES_IFD_GBE_REGION It has 2x 10GbE XGMII and 1x i210IT on PCIe, but no GBE. Change-Id: I641c336350a0b05f3db7603cc7f6281ff3b0c388 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/ocp/wedge100s/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/31198/1 diff --git a/src/mainboard/ocp/wedge100s/Kconfig b/src/mainboard/ocp/wedge100s/Kconfig index 846d979..bd5e665 100644 --- a/src/mainboard/ocp/wedge100s/Kconfig +++ b/src/mainboard/ocp/wedge100s/Kconfig @@ -16,7 +16,6 @@ select MAINBOARD_HAS_TPM1 select DRIVERS_UART_8250IO select SUPERIO_ITE_IT8528E - select MAINBOARD_USES_IFD_GBE_REGION config VBOOT select VBOOT_VBNV_CMOS -- To view, visit https://review.coreboot.org/c/coreboot/+/31198 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I641c336350a0b05f3db7603cc7f6281ff3b0c388 Gerrit-Change-Number: 31198 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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