February 2019 - coreboot-gerrit

Change in ...coreboot[master]: sb/amd/agesa/hudson/Kconfig: Disable xHCI by default if no USE_BLOBS
by mikeb mikeb (Code Review) Feb. 4, 2019

Feb. 4, 2019

Hello Mike Banon, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31216 to review the following change. Change subject: sb/amd/agesa/hudson/Kconfig: Disable xHCI by default if no USE_BLOBS ...................................................................... sb/amd/agesa/hudson/Kconfig: Disable xHCI by default if no USE_BLOBS Disable xHCI by default if USE_BLOBS option has not been selected. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I1c3f0ff49fbe3db3ef095d99055f75d65cd6f661 --- M src/southbridge/amd/agesa/hudson/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/31216/1 diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index 3bb9385..8b6a60e 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -38,7 +38,7 @@ config HUDSON_XHCI_ENABLE bool "Enable Hudson XHCI Controller" - default y + default y if USE_BLOBS help The XHCI controller must be enabled and the XHCI firmware must be added in order to have USB 3.0 support configured -- To view, visit https://review.coreboot.org/c/coreboot/+/31216 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1c3f0ff49fbe3db3ef095d99055f75d65cd6f661 Gerrit-Change-Number: 31216 Gerrit-PatchSet: 1 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: superio/winbond/w83627ehg: Correct CR 0x2a comment
by HAOUAS Elyes (Code Review) Feb. 4, 2019

Feb. 4, 2019

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31185 Change subject: superio/winbond/w83627ehg: Correct CR 0x2a comment ...................................................................... superio/winbond/w83627ehg: Correct CR 0x2a comment Register 0x2a [Bit 1] is a PIN89, PIN90 function select for i2c Change-Id: I9231a68ec7e9a3130a6b6975544bf89ab09cb3e6 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/superio/winbond/w83627ehg/superio.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/31185/1 diff --git a/src/superio/winbond/w83627ehg/superio.c b/src/superio/winbond/w83627ehg/superio.c index 04dda6e..736d660 100644 --- a/src/superio/winbond/w83627ehg/superio.c +++ b/src/superio/winbond/w83627ehg/superio.c @@ -32,7 +32,7 @@ { u8 reg8; - /* Configure pins 91/92 as SDA/SCL (I2C bus). */ + /* Configure pins 89/90 as SDA/SCL (I2C bus). */ reg8 = pnp_read_config(dev, 0x2a); reg8 |= (1 << 1); pnp_write_config(dev, 0x2a, reg8); -- To view, visit https://review.coreboot.org/c/coreboot/+/31185 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9231a68ec7e9a3130a6b6975544bf89ab09cb3e6 Gerrit-Change-Number: 31185 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/lenovo/{x200,t400}: Set SMBUS mux using common SB functions
by Arthur Heymans (Code Review) Feb. 4, 2019

Feb. 4, 2019

Hello Alexander Couzens, Patrick Rudolph, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/31189 to look at the new patch set (#2). Change subject: mb/lenovo/{x200,t400}: Set SMBUS mux using common SB functions ...................................................................... mb/lenovo/{x200,t400}: Set SMBUS mux using common SB functions Change-Id: I1e9a165b722006557557058a14e9f5dac78d4538 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/t400/romstage.c M src/mainboard/lenovo/x200/romstage.c 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/31189/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/31189 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e9a165b722006557557058a14e9f5dac78d4538 Gerrit-Change-Number: 31189 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: nb/intel/gm45: Use a common romstage
by Arthur Heymans (Code Review) Feb. 4, 2019

Feb. 4, 2019

Hello Alexander Couzens, Patrick Rudolph, Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/31190 to look at the new patch set (#2). Change subject: nb/intel/gm45: Use a common romstage ...................................................................... nb/intel/gm45: Use a common romstage This moves a lot of the common romstage boilerplate code to a common location, while adding a few mainboard specific hooks. Another difference is that the settings for enable_igd and enable_peg are now based on the static devicetree settings. Change-Id: I30ef7f6962aabde78b5c40e0b53bb85e01c254c1 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/t400/romstage.c M src/mainboard/lenovo/x200/romstage.c M src/mainboard/roda/rk9/romstage.c M src/northbridge/intel/gm45/Makefile.inc M src/northbridge/intel/gm45/gm45.h A src/northbridge/intel/gm45/romstage.c 6 files changed, 179 insertions(+), 267 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/31190/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/31190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30ef7f6962aabde78b5c40e0b53bb85e01c254c1 Gerrit-Change-Number: 31190 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: soc/intel/cannonlake: Add max uart config
by Subrata Banik (Code Review) Feb. 4, 2019

Feb. 4, 2019

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31213 Change subject: soc/intel/cannonlake: Add max uart config ...................................................................... soc/intel/cannonlake: Add max uart config This patch adds SOC_INTEL_UART_DEV_MAX for cannonlake soc. Change-Id: I7a04558869f966288fae00c8a0a75433b36c9735 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/cannonlake/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/31213/1 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 0a1cff0..3e8ace3 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -187,6 +187,10 @@ default 4 if SOC_INTEL_CANNONLAKE_PCH_H default 6 +config SOC_INTEL_UART_DEV_MAX + int + default 3 + # Clock divider parameters for 115200 baud rate config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL hex -- To view, visit https://review.coreboot.org/c/coreboot/+/31213 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a04558869f966288fae00c8a0a75433b36c9735 Gerrit-Change-Number: 31213 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/cannonlake: Remove SOC_INTEL_CANNONLAKE_MEMCFG_INIT Kconfig
by Subrata Banik (Code Review) Feb. 4, 2019

Feb. 4, 2019

Subrata Banik has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31134 ) Change subject: soc/intel/cannonlake: Remove SOC_INTEL_CANNONLAKE_MEMCFG_INIT Kconfig ...................................................................... soc/intel/cannonlake: Remove SOC_INTEL_CANNONLAKE_MEMCFG_INIT Kconfig This patch removes duplicate selects of same SOC_INTEL_CANNONLAKE_MEMCFG_INIT from various CFL/WHL SoC based boards to include cnl_memcfg_init.c file and include the cnl_memcfg_init.c file by default in CNL SoC Makefile.inc. Change-Id: Ib21ea305871dc859e7db0720c18a9479100346c3 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-on: https://review.coreboot.org/c/31134 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/sarien/Kconfig M src/mainboard/intel/coffeelake_rvp/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/Makefile.inc 5 files changed, 1 insertion(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index d3ad1a0..6a37325 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -13,7 +13,6 @@ select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_SPI_TPM_CR50 select MAINBOARD_HAS_TPM2 - select SOC_INTEL_CANNONLAKE_MEMCFG_INIT select SOC_INTEL_COFFEELAKE select SYSTEM_TYPE_LAPTOP diff --git a/src/mainboard/google/sarien/Kconfig b/src/mainboard/google/sarien/Kconfig index 67f879f..c6a9988 100644 --- a/src/mainboard/google/sarien/Kconfig +++ b/src/mainboard/google/sarien/Kconfig @@ -15,7 +15,6 @@ select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_I2C_TPM_CR50 select MAINBOARD_HAS_TPM2 - select SOC_INTEL_CANNONLAKE_MEMCFG_INIT select SOC_INTEL_COMMON_ACPI_EC_PTS_WAK select SOC_INTEL_COFFEELAKE select SOC_INTEL_COMMON_BLOCK_HDA_VERB diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig b/src/mainboard/intel/coffeelake_rvp/Kconfig index b208e9b..1019805 100644 --- a/src/mainboard/intel/coffeelake_rvp/Kconfig +++ b/src/mainboard/intel/coffeelake_rvp/Kconfig @@ -13,7 +13,6 @@ select DRIVERS_I2C_HID select DRIVERS_I2C_GENERIC select SOC_INTEL_COFFEELAKE - select SOC_INTEL_CANNONLAKE_MEMCFG_INIT select SOC_INTEL_CANNONLAKE_PCH_H if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVP8 select SOC_INTEL_COMMON_BLOCK_HDA_VERB if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVP8 || BOARD_INTEL_WHISKEYLAKE_RVP select SOC_INTEL_COMMON_BLOCK_HDA if BOARD_INTEL_WHISKEYLAKE_RVP diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index f8193cd..0a1cff0 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -170,10 +170,6 @@ int default 100 -config SOC_INTEL_CANNONLAKE_MEMCFG_INIT - bool - default n - config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ int default 120 diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index b2ba0fd..d1fc141 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -21,7 +21,7 @@ bootblock-y += p2sb.c bootblock-y += uart.c -romstage-$(CONFIG_SOC_INTEL_CANNONLAKE_MEMCFG_INIT) += cnl_memcfg_init.c +romstage-y += cnl_memcfg_init.c romstage-y += gspi.c romstage-y += i2c.c romstage-y += lpc.c -- To view, visit https://review.coreboot.org/c/coreboot/+/31134 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib21ea305871dc859e7db0720c18a9479100346c3 Gerrit-Change-Number: 31134 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in ...coreboot[master]: arcada: disable TP for test
by Li1 Feng (Code Review) Feb. 4, 2019

Feb. 4, 2019

Li1 Feng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31184 Change subject: arcada: disable TP for test ...................................................................... arcada: disable TP for test WIP Change-Id: Ie024ba44047f3bb3714c1c5fc1e87f111c209d40 Signed-off-by: li feng <li1.feng(a)intel.com> --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/31184/1 diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index a47a53d..229e9e6 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -214,7 +214,7 @@ device i2c 0A on end end end # I2C #0 - device pci 15.1 on + device pci 15.1 off chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" -- To view, visit https://review.coreboot.org/c/coreboot/+/31184 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie024ba44047f3bb3714c1c5fc1e87f111c209d40 Gerrit-Change-Number: 31184 Gerrit-PatchSet: 1 Gerrit-Owner: Li1 Feng <li1.feng(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: WIP ish: enable integrated sensor hub for Sarien
by Li1 Feng (Code Review) Feb. 4, 2019

Feb. 4, 2019

Li1 Feng has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/29493 ) Change subject: WIP ish: enable integrated sensor hub for Sarien ...................................................................... Abandoned No ISH on Sarien, it's enabled on Arcada. -- To view, visit https://review.coreboot.org/c/coreboot/+/29493 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdb9eae3bb5e8beef3b6727ef8aae88d16893666 Gerrit-Change-Number: 29493 Gerrit-PatchSet: 2 Gerrit-Owner: Li1 Feng <li1.feng(a)intel.com> Gerrit-Reviewer: Li1 Feng <li1.feng(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shine Liu <shine.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-CC: Shine Liu <shine.liu(a)intel.com> Gerrit-MessageType: abandon

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Change in ...coreboot[master]: src/mainboard/lenovo/g505s/Kconfig: select NO_INTEL_WIFI option
by mikeb mikeb (Code Review) Feb. 3, 2019

Feb. 3, 2019

Hello Mike Banon, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31221 to review the following change. Change subject: src/mainboard/lenovo/g505s/Kconfig: select NO_INTEL_WIFI option ...................................................................... src/mainboard/lenovo/g505s/Kconfig: select NO_INTEL_WIFI option There were no G505S shipped with pre-installed Intel PCI-e WiFi adapters, almost all such adapters (except Intel 135) could not be installed under proprietary UEFI because of a whitelist, and I am not aware of anyone who installed them after upgrading to coreboot - maybe because Atheros ath9k have a much better software freedom status and are the preferred choice. Select NO_INTEL_WIFI option to disable DRIVERS_INTEL_WIFI by default. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I2e32436a88777fa58661611cb9dbca7f56a65b6e --- M src/mainboard/lenovo/g505s/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/31221/1 diff --git a/src/mainboard/lenovo/g505s/Kconfig b/src/mainboard/lenovo/g505s/Kconfig index 883ef27..53858ca 100644 --- a/src/mainboard/lenovo/g505s/Kconfig +++ b/src/mainboard/lenovo/g505s/Kconfig @@ -30,6 +30,7 @@ select BOARD_ROMSIZE_KB_4096 select GFXUMA select NO_UART_ON_SUPERIO + select NO_INTEL_WIFI config MAINBOARD_DIR string -- To view, visit https://review.coreboot.org/c/coreboot/+/31221 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e32436a88777fa58661611cb9dbca7f56a65b6e Gerrit-Change-Number: 31221 Gerrit-PatchSet: 1 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/drivers/intel/wifi/Kconfig: add NO_INTEL_WIFI option
by mikeb mikeb (Code Review) Feb. 3, 2019

Feb. 3, 2019

Hello Mike Banon, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31219 to review the following change. Change subject: src/drivers/intel/wifi/Kconfig: add NO_INTEL_WIFI option ...................................................................... src/drivers/intel/wifi/Kconfig: add NO_INTEL_WIFI option This NO_INTEL_WIFI option will help to disable DRIVERS_INTEL_WIFI by default for the boards which are unlikely to have Intel PCI-e WiFi adapters. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: Ia21a141e25e58f6126a6d48d83cdfb4f746f3320 --- M src/drivers/intel/wifi/Kconfig 1 file changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/31219/1 diff --git a/src/drivers/intel/wifi/Kconfig b/src/drivers/intel/wifi/Kconfig index 4dc4d7f..4082d7e 100644 --- a/src/drivers/intel/wifi/Kconfig +++ b/src/drivers/intel/wifi/Kconfig @@ -1,11 +1,15 @@ config DRIVERS_INTEL_WIFI bool "Support Intel PCI-e WiFi adapters" depends on ARCH_X86 - default y if PCIEXP_PLUGIN_SUPPORT + default y if PCIEXP_PLUGIN_SUPPORT && !NO_INTEL_WIFI help When enabled, add identifiers in ACPI and SMBIOS tables to make OS drivers work with certain Intel PCI-e WiFi chipsets. +# Select this for mainboard which is unlikely to have Intel PCI-e WiFi adapter. +config NO_INTEL_WIFI + def_bool n + config USE_SAR bool default n -- To view, visit https://review.coreboot.org/c/coreboot/+/31219 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia21a141e25e58f6126a6d48d83cdfb4f746f3320 Gerrit-Change-Number: 31219 Gerrit-PatchSet: 1 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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