February 2019 - coreboot-gerrit

Change in ...coreboot[master]: WIP ish: enable integrated sensor hub for Sarien

by Li1 Feng (Code Review)

Li1 Feng has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/29493 ) Change subject: WIP ish: enable integrated sensor hub for Sarien ...................................................................... Abandoned No ISH on Sarien, it's enabled on Arcada. -- To view, visit https://review.coreboot.org/c/coreboot/+/29493 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdb9eae3bb5e8beef3b6727ef8aae88d16893666 Gerrit-Change-Number: 29493 Gerrit-PatchSet: 2 Gerrit-Owner: Li1 Feng <li1.feng(a)intel.com> Gerrit-Reviewer: Li1 Feng <li1.feng(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shine Liu <shine.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-CC: Shine Liu <shine.liu(a)intel.com> Gerrit-MessageType: abandon

2 years, 4 months

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Change in ...coreboot[master]: src/mainboard/lenovo/g505s/Kconfig: select NO_INTEL_WIFI option

by mikeb mikeb (Code Review)

Hello Mike Banon, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31221 to review the following change. Change subject: src/mainboard/lenovo/g505s/Kconfig: select NO_INTEL_WIFI option ...................................................................... src/mainboard/lenovo/g505s/Kconfig: select NO_INTEL_WIFI option There were no G505S shipped with pre-installed Intel PCI-e WiFi adapters, almost all such adapters (except Intel 135) could not be installed under proprietary UEFI because of a whitelist, and I am not aware of anyone who installed them after upgrading to coreboot - maybe because Atheros ath9k have a much better software freedom status and are the preferred choice. Select NO_INTEL_WIFI option to disable DRIVERS_INTEL_WIFI by default. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I2e32436a88777fa58661611cb9dbca7f56a65b6e --- M src/mainboard/lenovo/g505s/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/31221/1 diff --git a/src/mainboard/lenovo/g505s/Kconfig b/src/mainboard/lenovo/g505s/Kconfig index 883ef27..53858ca 100644 --- a/src/mainboard/lenovo/g505s/Kconfig +++ b/src/mainboard/lenovo/g505s/Kconfig @@ -30,6 +30,7 @@ select BOARD_ROMSIZE_KB_4096 select GFXUMA select NO_UART_ON_SUPERIO + select NO_INTEL_WIFI config MAINBOARD_DIR string -- To view, visit https://review.coreboot.org/c/coreboot/+/31221 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e32436a88777fa58661611cb9dbca7f56a65b6e Gerrit-Change-Number: 31221 Gerrit-PatchSet: 1 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

2 years, 4 months

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Change in ...coreboot[master]: src/drivers/intel/wifi/Kconfig: add NO_INTEL_WIFI option

by mikeb mikeb (Code Review)

Hello Mike Banon, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31219 to review the following change. Change subject: src/drivers/intel/wifi/Kconfig: add NO_INTEL_WIFI option ...................................................................... src/drivers/intel/wifi/Kconfig: add NO_INTEL_WIFI option This NO_INTEL_WIFI option will help to disable DRIVERS_INTEL_WIFI by default for the boards which are unlikely to have Intel PCI-e WiFi adapters. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: Ia21a141e25e58f6126a6d48d83cdfb4f746f3320 --- M src/drivers/intel/wifi/Kconfig 1 file changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/31219/1 diff --git a/src/drivers/intel/wifi/Kconfig b/src/drivers/intel/wifi/Kconfig index 4dc4d7f..4082d7e 100644 --- a/src/drivers/intel/wifi/Kconfig +++ b/src/drivers/intel/wifi/Kconfig @@ -1,11 +1,15 @@ config DRIVERS_INTEL_WIFI bool "Support Intel PCI-e WiFi adapters" depends on ARCH_X86 - default y if PCIEXP_PLUGIN_SUPPORT + default y if PCIEXP_PLUGIN_SUPPORT && !NO_INTEL_WIFI help When enabled, add identifiers in ACPI and SMBIOS tables to make OS drivers work with certain Intel PCI-e WiFi chipsets. +# Select this for mainboard which is unlikely to have Intel PCI-e WiFi adapter. +config NO_INTEL_WIFI + def_bool n + config USE_SAR bool default n -- To view, visit https://review.coreboot.org/c/coreboot/+/31219 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia21a141e25e58f6126a6d48d83cdfb4f746f3320 Gerrit-Change-Number: 31219 Gerrit-PatchSet: 1 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

2 years, 4 months

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Change in ...coreboot[master]: src/drivers/intel/wifi/Kconfig: enable NO_INTEL_WIFI if !SYSTEM_TYPE_...

by mikeb mikeb (Code Review)

Hello Mike Banon, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31220 to review the following change. Change subject: src/drivers/intel/wifi/Kconfig: enable NO_INTEL_WIFI if !SYSTEM_TYPE_LAPTOP ...................................................................... src/drivers/intel/wifi/Kconfig: enable NO_INTEL_WIFI if !SYSTEM_TYPE_LAPTOP Intel PCI-e WiFi adapters are rare outside of laptops. DRIVERS_INTEL_WIFI should not be selected by default if the mainboard is not a laptop. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I93a9e8fc9ba92f755524250e6cbcf9d1ba1acbdc --- M src/drivers/intel/wifi/Kconfig 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/31220/1 diff --git a/src/drivers/intel/wifi/Kconfig b/src/drivers/intel/wifi/Kconfig index 4082d7e..8fdd0a3 100644 --- a/src/drivers/intel/wifi/Kconfig +++ b/src/drivers/intel/wifi/Kconfig @@ -8,7 +8,9 @@ # Select this for mainboard which is unlikely to have Intel PCI-e WiFi adapter. config NO_INTEL_WIFI - def_bool n + bool + default y if !SYSTEM_TYPE_LAPTOP + default n config USE_SAR bool -- To view, visit https://review.coreboot.org/c/coreboot/+/31220 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93a9e8fc9ba92f755524250e6cbcf9d1ba1acbdc Gerrit-Change-Number: 31220 Gerrit-PatchSet: 1 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

2 years, 4 months

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Change in ...coreboot[master]: nb/intel/g45: Use a common romstage

by Angel Pons (Code Review)

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31190 ) Change subject: nb/intel/g45: Use a common romstage ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/31190/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/31190/1//COMMIT_MSG@7 PS1, Line 7: g45 gm45 -- To view, visit https://review.coreboot.org/c/coreboot/+/31190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30ef7f6962aabde78b5c40e0b53bb85e01c254c1 Gerrit-Change-Number: 31190 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 03 Feb 2019 18:05:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

2 years, 4 months

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Change in ...coreboot[master]: nb/intel/g45: Use a common romstage

by Angel Pons (Code Review)

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31190 ) Change subject: nb/intel/g45: Use a common romstage ...................................................................... Patch Set 1: Code-Review+1 Quick look, looks good. -- To view, visit https://review.coreboot.org/c/coreboot/+/31190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30ef7f6962aabde78b5c40e0b53bb85e01c254c1 Gerrit-Change-Number: 31190 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 03 Feb 2019 18:04:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

2 years, 4 months

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Change in ...coreboot[master]: mb/lenovo/r500: Add mainboard

by Angel Pons (Code Review)

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28644 ) Change subject: mb/lenovo/r500: Add mainboard ...................................................................... Patch Set 7: Code-Review+1 (3 comments) https://review.coreboot.org/#/c/28644/7//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/28644/7//COMMIT_MSG@17 PS7, Line 17: (Needs SeaBIOS with sercon disabled) I think this isn't needed anymore https://review.coreboot.org/#/c/28644/7//COMMIT_MSG@41 PS7, Line 41: Debian 9, Linux 4.9 Was this booted via USB? https://review.coreboot.org/#/c/28644/7/src/mainboard/lenovo/t400/Kconfig File src/mainboard/lenovo/t400/Kconfig: https://review.coreboot.org/#/c/28644/7/src/mainboard/lenovo/t400/Kconfig@13 PS7, Line 13: select BOARD_ROMSIZE_KB_8192 : select BOARD_ROMSIZE_KB_4096 if BOARD_LENOVO_R500 Doesn't this conflict? -- To view, visit https://review.coreboot.org/c/coreboot/+/28644 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e129b2e916acdf2b8534fa9d8d2cfc8f64f5815 Gerrit-Change-Number: 28644 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 03 Feb 2019 17:56:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

2 years, 4 months

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Change in ...coreboot[master]: usbdebug: Use fixed size field

by Kyösti Mälkki (Code Review)

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31182 Change subject: usbdebug: Use fixed size field ...................................................................... usbdebug: Use fixed size field The structure is placed inside CBMEM, one should use types with fixed size. Change-Id: I60382664a53650b225abc1f77c87ed4e121d429e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/drivers/usb/ehci_debug.c 1 file changed, 17 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/31182/1 diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c index cf3976c..3532466 100644 --- a/src/drivers/usb/ehci_debug.c +++ b/src/drivers/usb/ehci_debug.c @@ -28,8 +28,8 @@ #include "ehci.h" struct ehci_debug_info { - void *ehci_base; - void *ehci_debug; + u64 ehci_base; + u64 ehci_debug; struct dbgp_pipe ep_pipe[DBGP_MAX_ENDPOINTS]; }; @@ -262,7 +262,9 @@ int dbgp_bulk_write_x(struct dbgp_pipe *pipe, const char *bytes, int size) { struct ehci_debug_info *dbg_info = dbgp_ehci_info(); - return dbgp_bulk_write(dbg_info->ehci_debug, pipe, bytes, size); + struct ehci_dbg_port *port; + port = (void *)(uintptr_t)dbg_info->ehci_debug; + return dbgp_bulk_write(port, pipe, bytes, size); } static int dbgp_bulk_read(struct ehci_dbg_port *ehci_debug, struct dbgp_pipe *pipe, @@ -296,7 +298,9 @@ int dbgp_bulk_read_x(struct dbgp_pipe *pipe, void *data, int size) { struct ehci_debug_info *dbg_info = dbgp_ehci_info(); - return dbgp_bulk_read(dbg_info->ehci_debug, pipe, data, size); + struct ehci_dbg_port *port; + port = (void *)(uintptr_t)dbg_info->ehci_debug; + return dbgp_bulk_read(port, pipe, data, size); } void dbgp_mdelay(int ms) @@ -446,8 +450,8 @@ /* Keep all endpoints disabled before any printk() call. */ memset(info, 0, sizeof (*info)); - info->ehci_base = (void *)ehci_bar; - info->ehci_debug = (void *)(ehci_bar + offset); + info->ehci_base = ehci_bar; + info->ehci_debug = ehci_bar + offset; info->ep_pipe[0].status |= DBGP_EP_NOT_PRESENT; dprintk(BIOS_INFO, "ehci_bar: 0x%x debug_offset 0x%x\n", ehci_bar, offset); @@ -456,7 +460,7 @@ ehci_regs = (struct ehci_regs *)(ehci_bar + HC_LENGTH(read32(&ehci_caps->hc_capbase))); - struct ehci_dbg_port *ehci_debug = info->ehci_debug; + struct ehci_dbg_port *ehci_debug = (void *)(uintptr_t)info->ehci_debug; if (CONFIG_USBDEBUG_DEFAULT_PORT > 0) ehci_debug_select_port(CONFIG_USBDEBUG_DEFAULT_PORT); @@ -581,7 +585,8 @@ dbgp_mdelay(100); - ret = dbgp_probe_gadget(info->ehci_debug, &info->ep_pipe[0]); + struct ehci_dbg_port *port = (void *)(uintptr_t)info->ehci_debug; + ret = dbgp_probe_gadget(port, &info->ep_pipe[0]); if (ret < 0) { dprintk(BIOS_INFO, "Could not probe gadget on debug port.\n"); ret = -6; @@ -653,12 +658,12 @@ void usbdebug_re_enable(unsigned ehci_base) { struct ehci_debug_info *dbg_info = dbgp_ehci_info(); - unsigned diff; + u64 diff; int i; - diff = (unsigned)dbg_info->ehci_base - ehci_base; + diff = dbg_info->ehci_base - ehci_base; dbg_info->ehci_debug -= diff; - dbg_info->ehci_base = (void *)ehci_base; + dbg_info->ehci_base = ehci_base; for (i=0; i<DBGP_MAX_ENDPOINTS; i++) if (dbg_info->ep_pipe[i].status & DBGP_EP_VALID) @@ -678,7 +683,7 @@ int usbdebug_hw_init(bool force) { struct ehci_debug_info *dbg_info = dbgp_ehci_info(); - unsigned int ehci_base, dbg_offset; + u32 ehci_base, dbg_offset; if (dbgp_enabled() && !force) return 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/31182 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60382664a53650b225abc1f77c87ed4e121d429e Gerrit-Change-Number: 31182 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

2 years, 4 months

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Change in ...coreboot[master]: src/soc/intel/cannonlake: Add _DSM methods for LPIT table

by Lijian Zhao (Code Review)

Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31101 ) Change subject: src/soc/intel/cannonlake: Add _DSM methods for LPIT table ...................................................................... Patch Set 15: > Patch Set 15: > > (1 comment) I have a quick compare the dsdt.dsl generated and that's identical for patch 12 and patch 15, I may assume the didn't work will be caused by other regression on S0ix. ASL 2.0 had been introduced for several years and widely adopted in coreboot as well. -- To view, visit https://review.coreboot.org/c/coreboot/+/31101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia908969decf7cf12f505becb4f4a4a9caa7ed6db Gerrit-Change-Number: 31101 Gerrit-PatchSet: 15 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Assignee: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 02 Feb 2019 22:36:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

2 years, 4 months

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Change in ...coreboot[master]: src/soc/intel/cannonlake: Add _DSM methods for LPIT table

by Shaunak Saha (Code Review)

Shaunak Saha has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31101 ) Change subject: src/soc/intel/cannonlake: Add _DSM methods for LPIT table ...................................................................... Patch Set 15: (1 comment) https://review.coreboot.org/#/c/31101/15/src/soc/intel/cannonlake/acpi/lpit… File src/soc/intel/cannonlake/acpi/lpit.asl: https://review.coreboot.org/#/c/31101/15/src/soc/intel/cannonlake/acpi/lpit… PS15, Line 25: If(Arg0 == ^UUID) { This week i was testing with this new syntax but it didn't worked. No compilation error but seems like its not able to parse this new syntax. Need to debug if there is some version mismatch issue. -- To view, visit https://review.coreboot.org/c/coreboot/+/31101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia908969decf7cf12f505becb4f4a4a9caa7ed6db Gerrit-Change-Number: 31101 Gerrit-PatchSet: 15 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Assignee: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 02 Feb 2019 18:26:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

2 years, 4 months

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coreboot-gerrit February 2019