coreboot-gerrit February 2019

coreboot-gerrit@coreboot.org

1 participants
1249 discussions

Change in ...coreboot[master]: nb/intel/gm45: Use a common romstage
by Arthur Heymans (Code Review) 04 Feb '19

04 Feb '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31190 ) Change subject: nb/intel/gm45: Use a common romstage ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/31190/2/src/mainboard/lenovo/t400/romstage.c File src/mainboard/lenovo/t400/romstage.c: https://review.coreboot.org/#/c/31190/2/src/mainboard/lenovo/t400/romstage.… PS2, Line 71: if (dock_err) > that should be in mb_setup_superio, please add a comment and explain why it should stay here Console is not yet initialised in mb_setup_superio. -- To view, visit https://review.coreboot.org/c/coreboot/+/31190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30ef7f6962aabde78b5c40e0b53bb85e01c254c1 Gerrit-Change-Number: 31190 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 04 Feb 2019 20:06:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: comment

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Change in ...coreboot[master]: src/soc/intel/cannonlake: Add _DSM methods for LPIT table
by Shaunak Saha (Code Review) 04 Feb '19

04 Feb '19

Shaunak Saha has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31101 ) Change subject: src/soc/intel/cannonlake: Add _DSM methods for LPIT table ...................................................................... Patch Set 15: (1 comment) https://review.coreboot.org/#/c/31101/5/src/soc/intel/cannonlake/acpi/lpit.… File src/soc/intel/cannonlake/acpi/lpit.asl: https://review.coreboot.org/#/c/31101/5/src/soc/intel/cannonlake/acpi/lpit.… PS5, Line 26: LEqual(Arg0, ^UUID) > I was testing with this new syntax but it didnt worked with this. […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/31101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia908969decf7cf12f505becb4f4a4a9caa7ed6db Gerrit-Change-Number: 31101 Gerrit-PatchSet: 15 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Assignee: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 04 Feb 2019 20:01:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Shaunak Saha <shaunak.saha(a)intel.com> Comment-In-Reply-To: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: usbdebug: Fix reserve in CAR
by Kyösti Mälkki (Code Review) 04 Feb '19

04 Feb '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31174 Change subject: usbdebug: Fix reserve in CAR ...................................................................... usbdebug: Fix reserve in CAR We need sizeof(struct ehci_dbg_info) of 88 but only reserved 64 bytes. If usbdebug_hw_init() was called late in romstage, for some builds it would corrupt CAR_GLOBALs like console_inited variable and stop logging anything. Also change pointer initialisation such that glob_dbg_info will hit garbage collection for PRE_RAM stages. Change-Id: Ib49fca781e55619179aa8888e2d859560e050876 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/car.ld M src/drivers/usb/ehci_debug.c 2 files changed, 9 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/31174/1 diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 7b10f43..3f33702 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -67,7 +67,7 @@ _car_drivers_storage_end = .; #endif _car_ehci_dbg_info_start = .; - . += 64; + . += 0x60; _car_ehci_dbg_info_end = .; /* _car_global_start and _car_global_end provide symbols to per-stage * variables that are not shared like the timestamp and the pre-ram diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c index 18d0491..04272e6 100644 --- a/src/drivers/usb/ehci_debug.c +++ b/src/drivers/usb/ehci_debug.c @@ -66,13 +66,14 @@ static inline struct ehci_debug_info *dbgp_ehci_info(void) { - if (IS_ENABLED(CONFIG_USBDEBUG_IN_PRE_RAM) - && (ENV_ROMSTAGE || ENV_BOOTBLOCK || ENV_VERSTAGE)) - glob_dbg_info_p = - (struct ehci_debug_info *)_car_ehci_dbg_info_start; - if (car_get_var(glob_dbg_info_p) == NULL) - car_set_var(glob_dbg_info_p, &glob_dbg_info); - + if (car_get_var(glob_dbg_info_p) == NULL) { + struct ehci_debug_info *info; + if (ENV_BOOTBLOCK || ENV_VERSTAGE || ENV_ROMSTAGE) + info = (void *)_car_ehci_dbg_info_start; + else + info = &glob_dbg_info; + car_set_var(glob_dbg_info_p, info); + } return car_get_var(glob_dbg_info_p); } -- To view, visit https://review.coreboot.org/c/coreboot/+/31174 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib49fca781e55619179aa8888e2d859560e050876 Gerrit-Change-Number: 31174 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/soc/intel/cannonlake: Add _DSM methods for LPIT table
by Shaunak Saha (Code Review) 04 Feb '19

04 Feb '19

Shaunak Saha has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31101 ) Change subject: src/soc/intel/cannonlake: Add _DSM methods for LPIT table ...................................................................... Patch Set 15: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/31101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia908969decf7cf12f505becb4f4a4a9caa7ed6db Gerrit-Change-Number: 31101 Gerrit-PatchSet: 15 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Assignee: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 04 Feb 2019 19:37:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: ec/google/wilco: Add ACPI device for event interface
by Duncan Laurie (Code Review) 04 Feb '19

04 Feb '19

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31204 Change subject: ec/google/wilco: Add ACPI device for event interface ...................................................................... ec/google/wilco: Add ACPI device for event interface Add a separate ACPI device for the Wilco EC event interface so that the OS drivers can bind to it separately. Since the event handling is all done with ACPI and not mailbox calls this will be implemented as a standard acpi_driver in the kernel. BUG=b:119046283 TEST=veriy device exists in DSDT Change-Id: I5259a926fb6d5faea835bcdefa12f0184c5adf4a Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/ec/google/wilco/acpi/ec_dev.asl M src/ec/google/wilco/acpi/event.asl 2 files changed, 28 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/31204/1 diff --git a/src/ec/google/wilco/acpi/ec_dev.asl b/src/ec/google/wilco/acpi/ec_dev.asl index a3e8c48..fb43747 100644 --- a/src/ec/google/wilco/acpi/ec_dev.asl +++ b/src/ec/google/wilco/acpi/ec_dev.asl @@ -62,3 +62,31 @@ EndDependentFn () }) } + +Device (WEVT) +{ + Name (_HID, "GOOG000D") + Name (_UID, 1) + Name (_DDN, "Wilco EC Event Interface") + + Method (_STA) + { + Return (0xB) + } + + /* Get Event Buffer */ + Method (QSET, 0, Serialized) + { + /* Get count of event bytes */ + Local0 = R (QSEC) + Name (QBUF, Buffer (Local0) {}) + + /* Fill QS event buffer with Local0 bytes */ + For (Local1 = 0, Local1 < Local0, Local1++) { + QBUF[Local1] = R (QSEB) + } + + Printf ("QS = %o", QBUF) + Return (QBUF) + } +} diff --git a/src/ec/google/wilco/acpi/event.asl b/src/ec/google/wilco/acpi/event.asl index 4a3394f..754ed26 100644 --- a/src/ec/google/wilco/acpi/event.asl +++ b/src/ec/google/wilco/acpi/event.asl @@ -125,19 +125,3 @@ ECQ4 (Local0) } } - -/* Get Event Buffer */ -Method (QSET, 0, Serialized) -{ - /* Get count of event bytes */ - Local0 = R (QSEC) - Name (QBUF, Buffer (Local0) {}) - - /* Fill QS event buffer with Local0 bytes */ - For (Local1 = 0, Local1 < Local0, Local1++) { - QBUF[Local1] = R (QSEB) - } - - Printf ("QS = %o", QBUF) - Return (QBUF) -} -- To view, visit https://review.coreboot.org/c/coreboot/+/31204 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5259a926fb6d5faea835bcdefa12f0184c5adf4a Gerrit-Change-Number: 31204 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: ec/google/wilco: Add S0ix support handlers
by Duncan Laurie (Code Review) 04 Feb '19

04 Feb '19

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31094 Change subject: ec/google/wilco: Add S0ix support handlers ...................................................................... ec/google/wilco: Add S0ix support handlers 1) In the EC _REG method set the flag indicating S0ix support in the OS. 2) Add a function that can be called by the LPI _DSM method to indicate to the EC that the OS is entering or exiting S0ix. BUG=b:73137291 Change-Id: Iddc33a08542a6657694c47a9fda1b02dd39d89f7 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/ec/google/wilco/acpi/ec.asl M src/ec/google/wilco/acpi/ec_ram.asl 2 files changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/31094/1 diff --git a/src/ec/google/wilco/acpi/ec.asl b/src/ec/google/wilco/acpi/ec.asl index f9b16b5..db4acd4 100644 --- a/src/ec/google/wilco/acpi/ec.asl +++ b/src/ec/google/wilco/acpi/ec.asl @@ -47,6 +47,9 @@ /* Indicate to EC that OS is ready for queries */ W (ERDY, Arg1) + /* Indicate that the OS supports S0ix */ + W (CSOS, One) + /* Tell EC to stop emulating PS/2 mouse */ W (PS2M, Zero) @@ -140,6 +143,17 @@ Return (ECRW (Arg0, Arg1)) } + /* + * Tell EC that the OS is entering or exiting S0ix + Method (S0IX, 1, Serialized) + { + If (Arg0) { + W (CSEX, One) + } Else { + W (CSEX, Zero) + } + } + #include "ec_dev.asl" #include "ec_ram.asl" #include "ac.asl" diff --git a/src/ec/google/wilco/acpi/ec_ram.asl b/src/ec/google/wilco/acpi/ec_ram.asl index 1563a3c..1e5d7cb 100644 --- a/src/ec/google/wilco/acpi/ec_ram.asl +++ b/src/ec/google/wilco/acpi/ec_ram.asl @@ -142,3 +142,5 @@ Name (DWTH, Package () { 0x36, 0xff, WR }) /* DPTF: Write Trip High */ Name (DWHY, Package () { 0x37, 0xff, WR }) /* DPTF: Write Hysteresis */ Name (DWTQ, Package () { 0x38, 0xff, WR }) /* DPTF: Write Trip Query */ +Name (CSOS, Package () { 0xb8, 0xff, WR }) /* OS support for S0ix */ +Name (CSEX, Package () { 0xb9, 0xff, WR }) /* OS enter(1)/exit(0) S0ix */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31094 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iddc33a08542a6657694c47a9fda1b02dd39d89f7 Gerrit-Change-Number: 31094 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sb/intel/common: SMBus complete_command()
by Kyösti Mälkki (Code Review) 04 Feb '19

04 Feb '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/21120 ) Change subject: sb/intel/common: SMBus complete_command() ...................................................................... Patch Set 11: (1 comment) https://review.coreboot.org/#/c/21120/11/src/southbridge/intel/common/smbus… File src/southbridge/intel/common/smbus.c: https://review.coreboot.org/#/c/21120/11/src/southbridge/intel/common/smbus… PS11, Line 85: static int cb_err_from_stat(u8 status) : { : /* Ignore the "In Use" status... */ : status &= ~(SMBHSTSTS_SMBALERT_STS | SMBHSTSTS_INUSE_STS); : : if (status == SMBHSTSTS_INTR) : return 0; : : return SMBUS_ERROR; : } > this seems to have false positives on at least ich10 with i2c_block_read. Please elaborate. Like set DEBUG_SMBUS=y. -- To view, visit https://review.coreboot.org/c/coreboot/+/21120 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idea15e03edde7aeedf198c1529f09c24a5bc0b06 Gerrit-Change-Number: 21120 Gerrit-PatchSet: 11 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 04 Feb 2019 18:49:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in ...coreboot[master]: nb/intel/gm45: Use a common romstage
by Patrick Rudolph (Code Review) 04 Feb '19

04 Feb '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31190 ) Change subject: nb/intel/gm45: Use a common romstage ...................................................................... Patch Set 2: Code-Review+1 (2 comments) https://review.coreboot.org/#/c/31190/2/src/mainboard/lenovo/t400/romstage.c File src/mainboard/lenovo/t400/romstage.c: https://review.coreboot.org/#/c/31190/2/src/mainboard/lenovo/t400/romstage.… PS2, Line 71: if (dock_err) that should be in mb_setup_superio, please add a comment and explain why it should stay here https://review.coreboot.org/#/c/31190/2/src/northbridge/intel/gm45/gm45.h File src/northbridge/intel/gm45/gm45.h: https://review.coreboot.org/#/c/31190/2/src/northbridge/intel/gm45/gm45.h@4… PS2, Line 442: void get_mb_spd_addrmap(u8 *spd_addrmap); spd_addrmap[4] -- To view, visit https://review.coreboot.org/c/coreboot/+/31190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30ef7f6962aabde78b5c40e0b53bb85e01c254c1 Gerrit-Change-Number: 31190 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 04 Feb 2019 18:36:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/amd: Add Merlin Falcon soc code
by Richard Spiegel (Code Review) 04 Feb '19

04 Feb '19

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31233 Change subject: soc/amd: Add Merlin Falcon soc code ...................................................................... soc/amd: Add Merlin Falcon soc code In preparation to add padmelon to coreboot, add the the code for the soc Merlin Falcon used by padmelon. BUG=b:none. TEST=Tested later with pasmelon board. Change-Id: Ie764f1a628067c168e5d802006d4113aa95fdf3f Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/Kconfig A src/soc/amd/merlinfalcon/BiosCallOuts.c A src/soc/amd/merlinfalcon/Kconfig A src/soc/amd/merlinfalcon/Makefile.inc A src/soc/amd/merlinfalcon/acpi.c A src/soc/amd/merlinfalcon/acpi/AmdImc.asl A src/soc/amd/merlinfalcon/acpi/acpi_wake_source.asl A src/soc/amd/merlinfalcon/acpi/cpu.asl A src/soc/amd/merlinfalcon/acpi/globalnvs.asl A src/soc/amd/merlinfalcon/acpi/gpio_lib.asl A src/soc/amd/merlinfalcon/acpi/lpc.asl A src/soc/amd/merlinfalcon/acpi/northbridge.asl A src/soc/amd/merlinfalcon/acpi/pci_int.asl A src/soc/amd/merlinfalcon/acpi/pcie.asl A src/soc/amd/merlinfalcon/acpi/sb_fch.asl A src/soc/amd/merlinfalcon/acpi/sb_pci0_fch.asl A src/soc/amd/merlinfalcon/acpi/sleepstates.asl A src/soc/amd/merlinfalcon/acpi/soc.asl A src/soc/amd/merlinfalcon/acpi/usb.asl A src/soc/amd/merlinfalcon/bootblock/bootblock.c A src/soc/amd/merlinfalcon/chip.c A src/soc/amd/merlinfalcon/chip.h A src/soc/amd/merlinfalcon/cpu.c A src/soc/amd/merlinfalcon/enable_usbdebug.c A src/soc/amd/merlinfalcon/finalize.c A src/soc/amd/merlinfalcon/gpio.c A src/soc/amd/merlinfalcon/hda.c A src/soc/amd/merlinfalcon/i2c.c A src/soc/amd/merlinfalcon/imc.c A src/soc/amd/merlinfalcon/include/soc/acpi.h A src/soc/amd/merlinfalcon/include/soc/amd_pci_int_defs.h A src/soc/amd/merlinfalcon/include/soc/cpu.h A src/soc/amd/merlinfalcon/include/soc/fchec.h A src/soc/amd/merlinfalcon/include/soc/gpio.h A src/soc/amd/merlinfalcon/include/soc/imc.h A src/soc/amd/merlinfalcon/include/soc/iomap.h A src/soc/amd/merlinfalcon/include/soc/northbridge.h A src/soc/amd/merlinfalcon/include/soc/nvs.h A src/soc/amd/merlinfalcon/include/soc/pci_devs.h A src/soc/amd/merlinfalcon/include/soc/romstage.h A src/soc/amd/merlinfalcon/include/soc/smbus.h A src/soc/amd/merlinfalcon/include/soc/smi.h A src/soc/amd/merlinfalcon/include/soc/southbridge.h A src/soc/amd/merlinfalcon/iommu.c A src/soc/amd/merlinfalcon/lpc.c A src/soc/amd/merlinfalcon/mca.c A src/soc/amd/merlinfalcon/monotonic_timer.c A src/soc/amd/merlinfalcon/nb_util.c A src/soc/amd/merlinfalcon/northbridge.c A src/soc/amd/merlinfalcon/pmutil.c A src/soc/amd/merlinfalcon/ramtop.c A src/soc/amd/merlinfalcon/reset.c A src/soc/amd/merlinfalcon/romstage.c A src/soc/amd/merlinfalcon/sata.c A src/soc/amd/merlinfalcon/sb_util.c A src/soc/amd/merlinfalcon/sm.c A src/soc/amd/merlinfalcon/smbus.c A src/soc/amd/merlinfalcon/smbus_spd.c A src/soc/amd/merlinfalcon/smi.c A src/soc/amd/merlinfalcon/smi_util.c A src/soc/amd/merlinfalcon/smihandler.c A src/soc/amd/merlinfalcon/southbridge.c A src/soc/amd/merlinfalcon/spi.c A src/soc/amd/merlinfalcon/tsc_freq.c A src/soc/amd/merlinfalcon/uart.c A src/soc/amd/merlinfalcon/usb.c 66 files changed, 11,683 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/31233/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/31233 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie764f1a628067c168e5d802006d4113aa95fdf3f Gerrit-Change-Number: 31233 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sb/intel/common: SMBus complete_command()
by Arthur Heymans (Code Review) 04 Feb '19

04 Feb '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/21120 ) Change subject: sb/intel/common: SMBus complete_command() ...................................................................... Patch Set 11: (1 comment) https://review.coreboot.org/#/c/21120/11/src/southbridge/intel/common/smbus… File src/southbridge/intel/common/smbus.c: https://review.coreboot.org/#/c/21120/11/src/southbridge/intel/common/smbus… PS11, Line 85: static int cb_err_from_stat(u8 status) : { : /* Ignore the "In Use" status... */ : status &= ~(SMBHSTSTS_SMBALERT_STS | SMBHSTSTS_INUSE_STS); : : if (status == SMBHSTSTS_INTR) : return 0; : : return SMBUS_ERROR; : } this seems to have false positives on at least ich10 with i2c_block_read. -- To view, visit https://review.coreboot.org/c/coreboot/+/21120 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idea15e03edde7aeedf198c1529f09c24a5bc0b06 Gerrit-Change-Number: 21120 Gerrit-PatchSet: 11 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 04 Feb 2019 15:36:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit February 2019