Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31233
Change subject: soc/amd: Add Merlin Falcon soc code ......................................................................
soc/amd: Add Merlin Falcon soc code
In preparation to add padmelon to coreboot, add the the code for the soc Merlin Falcon used by padmelon.
BUG=b:none. TEST=Tested later with pasmelon board.
Change-Id: Ie764f1a628067c168e5d802006d4113aa95fdf3f Signed-off-by: Richard Spiegel richard.spiegel@silverbackltd.com --- M src/soc/amd/Kconfig A src/soc/amd/merlinfalcon/BiosCallOuts.c A src/soc/amd/merlinfalcon/Kconfig A src/soc/amd/merlinfalcon/Makefile.inc A src/soc/amd/merlinfalcon/acpi.c A src/soc/amd/merlinfalcon/acpi/AmdImc.asl A src/soc/amd/merlinfalcon/acpi/acpi_wake_source.asl A src/soc/amd/merlinfalcon/acpi/cpu.asl A src/soc/amd/merlinfalcon/acpi/globalnvs.asl A src/soc/amd/merlinfalcon/acpi/gpio_lib.asl A src/soc/amd/merlinfalcon/acpi/lpc.asl A src/soc/amd/merlinfalcon/acpi/northbridge.asl A src/soc/amd/merlinfalcon/acpi/pci_int.asl A src/soc/amd/merlinfalcon/acpi/pcie.asl A src/soc/amd/merlinfalcon/acpi/sb_fch.asl A src/soc/amd/merlinfalcon/acpi/sb_pci0_fch.asl A src/soc/amd/merlinfalcon/acpi/sleepstates.asl A src/soc/amd/merlinfalcon/acpi/soc.asl A src/soc/amd/merlinfalcon/acpi/usb.asl A src/soc/amd/merlinfalcon/bootblock/bootblock.c A src/soc/amd/merlinfalcon/chip.c A src/soc/amd/merlinfalcon/chip.h A src/soc/amd/merlinfalcon/cpu.c A src/soc/amd/merlinfalcon/enable_usbdebug.c A src/soc/amd/merlinfalcon/finalize.c A src/soc/amd/merlinfalcon/gpio.c A src/soc/amd/merlinfalcon/hda.c A src/soc/amd/merlinfalcon/i2c.c A src/soc/amd/merlinfalcon/imc.c A src/soc/amd/merlinfalcon/include/soc/acpi.h A src/soc/amd/merlinfalcon/include/soc/amd_pci_int_defs.h A src/soc/amd/merlinfalcon/include/soc/cpu.h A src/soc/amd/merlinfalcon/include/soc/fchec.h A src/soc/amd/merlinfalcon/include/soc/gpio.h A src/soc/amd/merlinfalcon/include/soc/imc.h A src/soc/amd/merlinfalcon/include/soc/iomap.h A src/soc/amd/merlinfalcon/include/soc/northbridge.h A src/soc/amd/merlinfalcon/include/soc/nvs.h A src/soc/amd/merlinfalcon/include/soc/pci_devs.h A src/soc/amd/merlinfalcon/include/soc/romstage.h A src/soc/amd/merlinfalcon/include/soc/smbus.h A src/soc/amd/merlinfalcon/include/soc/smi.h A src/soc/amd/merlinfalcon/include/soc/southbridge.h A src/soc/amd/merlinfalcon/iommu.c A src/soc/amd/merlinfalcon/lpc.c A src/soc/amd/merlinfalcon/mca.c A src/soc/amd/merlinfalcon/monotonic_timer.c A src/soc/amd/merlinfalcon/nb_util.c A src/soc/amd/merlinfalcon/northbridge.c A src/soc/amd/merlinfalcon/pmutil.c A src/soc/amd/merlinfalcon/ramtop.c A src/soc/amd/merlinfalcon/reset.c A src/soc/amd/merlinfalcon/romstage.c A src/soc/amd/merlinfalcon/sata.c A src/soc/amd/merlinfalcon/sb_util.c A src/soc/amd/merlinfalcon/sm.c A src/soc/amd/merlinfalcon/smbus.c A src/soc/amd/merlinfalcon/smbus_spd.c A src/soc/amd/merlinfalcon/smi.c A src/soc/amd/merlinfalcon/smi_util.c A src/soc/amd/merlinfalcon/smihandler.c A src/soc/amd/merlinfalcon/southbridge.c A src/soc/amd/merlinfalcon/spi.c A src/soc/amd/merlinfalcon/tsc_freq.c A src/soc/amd/merlinfalcon/uart.c A src/soc/amd/merlinfalcon/usb.c 66 files changed, 11,683 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/31233/1
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31233 )
Change subject: soc/amd: Add Merlin Falcon soc code ......................................................................
Patch Set 1:
(20 comments)
https://review.coreboot.org/#/c/31233/1/src/soc/amd/merlinfalcon/bootblock/b... File src/soc/amd/merlinfalcon/bootblock/bootblock.c:
https://review.coreboot.org/#/c/31233/1/src/soc/amd/merlinfalcon/bootblock/b... PS1, Line 83: void (*ap_romstage_entry)(void) = function definition argument 'void' should also have an identifier name
https://review.coreboot.org/#/c/31233/1/src/soc/amd/merlinfalcon/imc.c File src/soc/amd/merlinfalcon/imc.c:
https://review.coreboot.org/#/c/31233/1/src/soc/amd/merlinfalcon/imc.c@75 PS1, Line 75: ) please, no spaces at the start of a line
https://review.coreboot.org/#/c/31233/1/src/soc/amd/merlinfalcon/imc.c@77 PS1, Line 77: return (bool) (((Flag >> (func *4)) & 0xF) & ((UINT8 )1 << Zone)); need consistent spacing around '*' (ctx:WxV)
https://review.coreboot.org/#/c/31233/1/src/soc/amd/merlinfalcon/imc.c@77 PS1, Line 77: return (bool) (((Flag >> (func *4)) & 0xF) & ((UINT8 )1 << Zone)); space prohibited before that close parenthesis ')'
https://review.coreboot.org/#/c/31233/1/src/soc/amd/merlinfalcon/imc.c@120 PS1, Line 120: if ( Msgdata == 0xfa) space prohibited after that open parenthesis '('
https://review.coreboot.org/#/c/31233/1/src/soc/amd/merlinfalcon/imc.c@190 PS1, Line 190: if (!IsImcEnabled ()) space prohibited between function name and open parenthesis '('
https://review.coreboot.org/#/c/31233/1/src/soc/amd/merlinfalcon/imc.c@196 PS1, Line 196: for ( FunIndex = 1; FunIndex <= 3; FunIndex++ ) { space prohibited after that open parenthesis '('
https://review.coreboot.org/#/c/31233/1/src/soc/amd/merlinfalcon/imc.c@196 PS1, Line 196: for ( FunIndex = 1; FunIndex <= 3; FunIndex++ ) { space prohibited before that close parenthesis ')'
https://review.coreboot.org/#/c/31233/1/src/soc/amd/merlinfalcon/imc.c@198 PS1, Line 198: for (ZoneNum = 0; ZoneNum < MaxZone[FunIndex]; ZoneNum++ ) { space prohibited before that close parenthesis ')'
https://review.coreboot.org/#/c/31233/1/src/soc/amd/merlinfalcon/imc.c@256 PS1, Line 256: if (!(IsImcEnabled ())) space prohibited between function name and open parenthesis '('
https://review.coreboot.org/#/c/31233/1/src/soc/amd/merlinfalcon/include/soc... File src/soc/amd/merlinfalcon/include/soc/southbridge.h:
https://review.coreboot.org/#/c/31233/1/src/soc/amd/merlinfalcon/include/soc... PS1, Line 343: #define SPI_READ_MODE_DUAL112 ( BIT(29) ) space prohibited after that open parenthesis '('
https://review.coreboot.org/#/c/31233/1/src/soc/amd/merlinfalcon/include/soc... PS1, Line 343: #define SPI_READ_MODE_DUAL112 ( BIT(29) ) space prohibited before that close parenthesis ')'
https://review.coreboot.org/#/c/31233/1/src/soc/amd/merlinfalcon/include/soc... PS1, Line 344: #define SPI_READ_MODE_QUAD114 ( BIT(29) | BIT(18)) space prohibited after that open parenthesis '('
https://review.coreboot.org/#/c/31233/1/src/soc/amd/merlinfalcon/include/soc... PS1, Line 345: #define SPI_READ_MODE_DUAL122 (BIT(30) ) space prohibited before that close parenthesis ')'
https://review.coreboot.org/#/c/31233/1/src/soc/amd/merlinfalcon/include/soc... PS1, Line 347: #define SPI_READ_MODE_NORMAL66 (BIT(30) | BIT(29) ) space prohibited before that close parenthesis ')'
https://review.coreboot.org/#/c/31233/1/src/soc/amd/merlinfalcon/include/soc... PS1, Line 374: #define SPI_SPEED_33M ( BIT(0)) space prohibited after that open parenthesis '('
https://review.coreboot.org/#/c/31233/1/src/soc/amd/merlinfalcon/include/soc... PS1, Line 375: #define SPI_SPEED_22M ( BIT(1) ) space prohibited after that open parenthesis '('
https://review.coreboot.org/#/c/31233/1/src/soc/amd/merlinfalcon/include/soc... PS1, Line 375: #define SPI_SPEED_22M ( BIT(1) ) space prohibited before that close parenthesis ')'
https://review.coreboot.org/#/c/31233/1/src/soc/amd/merlinfalcon/include/soc... PS1, Line 376: #define SPI_SPEED_16M ( BIT(1) | BIT(0)) space prohibited after that open parenthesis '('
https://review.coreboot.org/#/c/31233/1/src/soc/amd/merlinfalcon/include/soc... PS1, Line 377: #define SPI_SPEED_100M (BIT(2) ) space prohibited before that close parenthesis ')'
Richard Spiegel has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/31233 )
Change subject: soc/amd: Add Merlin Falcon soc code ......................................................................
Abandoned
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