coreboot-gerrit December 2019

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Change in coreboot[master]: soc/qualcomm/sc7180: Adapt to recent API changes
by Patrick Georgi (Code Review) 05 Dec '19

05 Dec '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37534 ) Change subject: soc/qualcomm/sc7180: Adapt to recent API changes ...................................................................... soc/qualcomm/sc7180: Adapt to recent API changes Definitions were moved so that now device/mmio.h needs to be included instead of arch/mmio.h. Also, don't use le32 conversion. This follows the activities of commit 55009af42 (Change all clrsetbits_leXX() to clrsetbitsXX()) and commit 1c371572188 (mmio: Add clrsetbitsXX() API in place of updateX()). Change-Id: Ie3af0d4f0b3331fe5572fc56915952547b512db7 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/soc/qualcomm/sc7180/clock.c M src/soc/qualcomm/sc7180/usb.c 2 files changed, 17 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/37534/1 diff --git a/src/soc/qualcomm/sc7180/clock.c b/src/soc/qualcomm/sc7180/clock.c index 97b7b28..9092a4e 100644 --- a/src/soc/qualcomm/sc7180/clock.c +++ b/src/soc/qualcomm/sc7180/clock.c @@ -62,10 +62,10 @@ static int clock_configure_gpll0(void) { - setbits_le32(&gcc->gpll0.user_ctl_u, 1 << SCALE_FREQ_SHFT); + setbits32(&gcc->gpll0.user_ctl_u, 1 << SCALE_FREQ_SHFT); /* Keep existing GPLL0 configuration, in RUN mode @600Mhz. */ - setbits_le32(&gcc->gpll0.user_ctl, + setbits32(&gcc->gpll0.user_ctl, 1 << CLK_CTL_GPLL_PLLOUT_EVEN_SHFT | 1 << CLK_CTL_GPLL_PLLOUT_MAIN_SHFT | 1 << CLK_CTL_GPLL_PLLOUT_ODD_SHFT); @@ -77,7 +77,7 @@ uint32_t d_2) { struct sc7180_mnd_clock *mnd = (struct sc7180_mnd_clock *)clk; - setbits_le32(&clk->rcg_cfg, + setbits32(&clk->rcg_cfg, RCG_MODE_DUAL_EDGE << CLK_CTL_CFG_MODE_SHFT); write32(&mnd->m, m & CLK_CTL_RCG_MND_BMSK); @@ -111,7 +111,7 @@ clk_cfg[idx].d_2); /* Commit config to RCG*/ - setbits_le32(&clk->rcg_cmd, BIT(CLK_CTL_CMD_UPDATE_SHFT)); + setbits32(&clk->rcg_cmd, BIT(CLK_CTL_CMD_UPDATE_SHFT)); return 0; } @@ -125,7 +125,7 @@ uint32_t vote_bit) { /* Set clock vote bit */ - setbits_le32(vote_addr, BIT(vote_bit)); + setbits32(vote_addr, BIT(vote_bit)); /* Ensure clock is enabled */ while (clock_is_off(cbcr_addr)) @@ -137,7 +137,7 @@ static int clock_enable(void *cbcr_addr) { /* Set clock enable bit */ - setbits_le32(cbcr_addr, BIT(CLK_CTL_CBC_CLK_EN_SHFT)); + setbits32(cbcr_addr, BIT(CLK_CTL_CBC_CLK_EN_SHFT)); /* Ensure clock is enabled */ while (clock_is_off(cbcr_addr)) @@ -149,7 +149,7 @@ void clock_reset_aop(void) { /* Bring AOP out of RESET */ - clrbits_le32(&aoss->aoss_cc_apcs_misc, BIT(AOP_RESET_SHFT)); + clrbits32(&aoss->aoss_cc_apcs_misc, BIT(AOP_RESET_SHFT)); } void clock_configure_qspi(uint32_t hz) @@ -166,9 +166,9 @@ struct sc7180_bcr *bcr = bcr_addr; if (reset) - setbits_le32(bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT)); + setbits32(bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT)); else - clrbits_le32(bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT)); + clrbits32(bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT)); return 0; } diff --git a/src/soc/qualcomm/sc7180/usb.c b/src/soc/qualcomm/sc7180/usb.c index 4183e9b..639f401 100644 --- a/src/soc/qualcomm/sc7180/usb.c +++ b/src/soc/qualcomm/sc7180/usb.c @@ -13,10 +13,10 @@ * GNU General Public License for more details. */ -#include <arch/mmio.h> #include <stdlib.h> #include <console/console.h> #include <delay.h> +#include <device/mmio.h> #include <soc/usb.h> #include <soc/clock.h> #include <soc/addressmap.h> @@ -565,7 +565,7 @@ * tune parameters. */ if (tune_val) - clrsetbits_le32(&dwc3->qusb_phy_dig->tune1, + clrsetbits32(&dwc3->qusb_phy_dig->tune1, PORT_TUNE1_MASK, tune_val << 4); } @@ -602,7 +602,7 @@ static void hs_qusb_phy_init(struct usb_dwc3_cfg *dwc3) { /* PWR_CTRL: set the power down bit to disable the PHY */ - setbits_le32(&dwc3->qusb_phy_dig->pwr_ctrl1, POWER_DOWN); + setbits32(&dwc3->qusb_phy_dig->pwr_ctrl1, POWER_DOWN); write32(&dwc3->qusb_phy_pll->analog_controls_two, QUSB2PHY_PLL_ANALOG_CONTROLS_TWO); @@ -622,7 +622,7 @@ tune_phy(dwc3, dwc3->qusb_phy_dig); /* PWR_CTRL1: Clear the power down bit to enable the PHY */ - clrbits_le32(&dwc3->qusb_phy_dig->pwr_ctrl1, POWER_DOWN); + clrbits32(&dwc3->qusb_phy_dig->pwr_ctrl1, POWER_DOWN); write32(&dwc3->qusb_phy_dig->debug_ctrl2, DEBUG_CTRL2_MUX_PLL_LOCK_STATUS); @@ -688,7 +688,7 @@ static void setup_dwc3(struct usb_dwc3 *dwc3) { /* core exits U1/U2/U3 only in PHY power state P1/P2/P3 respectively */ - clrsetbits_le32(&dwc3->usb3pipectl, + clrsetbits32(&dwc3->usb3pipectl, DWC3_GUSB3PIPECTL_DELAYP1TRANS, DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX); @@ -698,18 +698,18 @@ * 2. Set USBTRDTIM to the corresponding value * according to the UTMI+ PHY interface. */ - clrsetbits_le32(&dwc3->usb2phycfg, + clrsetbits32(&dwc3->usb2phycfg, (DWC3_GUSB2PHYCFG_USB2TRDTIM_MASK | DWC3_GUSB2PHYCFG_PHYIF_MASK), (DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT))); - clrsetbits_le32(&dwc3->ctl, (DWC3_GCTL_SCALEDOWN_MASK | + clrsetbits32(&dwc3->ctl, (DWC3_GCTL_SCALEDOWN_MASK | DWC3_GCTL_DISSCRAMBLE), DWC3_GCTL_U2EXIT_LFPS | DWC3_GCTL_DSBLCLKGTNG); /* configure controller in Host mode */ - clrsetbits_le32(&dwc3->ctl, (DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)), + clrsetbits32(&dwc3->ctl, (DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)), DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_HOST)); printk(BIOS_SPEW, "Configure USB in Host mode\n"); } -- To view, visit https://review.coreboot.org/c/coreboot/+/37534 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3af0d4f0b3331fe5572fc56915952547b512db7 Gerrit-Change-Number: 37534 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [NOT FOR MERGE] - For Richard - hack the Makefile for testing
by Marshall Dawson (Code Review) 05 Dec '19

05 Dec '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37221 ) Change subject: [NOT FOR MERGE] - For Richard - hack the Makefile for testing ...................................................................... [NOT FOR MERGE] - For Richard - hack the Makefile for testing This will let you test WIP amd_blobs (and blobs) that you might want, without worrying the submodule will be updated when you use USE_AMD_BLOBS. Change-Id: Iaa6b1a3ed1fbeababb38aa5cdafd90e14fcac50f Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M Makefile.inc 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/37221/1 diff --git a/Makefile.inc b/Makefile.inc index dc5272e..b7170e2 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -199,14 +199,14 @@ ifeq ($(CONFIG_USE_BLOBS),y) # These items are necessary because each has update=none in .gitmodules. They are ignored # until expressly requested and enabled with --checkout -forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/blobs)) +# forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/blobs)) forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/intel-microcode)) ifeq ($(CONFIG_PLATFORM_USES_FSP1_0)$(CONFIG_PLATFORM_USES_FSP1_1)$(CONFIG_PLATFORM_USES_FSP2_0),y) forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/fsp)) endif -ifeq ($(CONFIG_USE_AMD_BLOBS),y) -forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/amd_blobs)) -endif +# ifeq ($(CONFIG_USE_AMD_BLOBS),y) +# forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/amd_blobs)) +# endif endif UPDATED_SUBMODULES:=1 COREBOOT_EXPORTS += UPDATED_SUBMODULES -- To view, visit https://review.coreboot.org/c/coreboot/+/37221 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa6b1a3ed1fbeababb38aa5cdafd90e14fcac50f Gerrit-Change-Number: 37221 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: soc/intel/braswell: Use common sb code for SPI lockdown configuration
by Arthur Heymans (Code Review) 05 Dec '19

05 Dec '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36007 ) Change subject: soc/intel/braswell: Use common sb code for SPI lockdown configuration ...................................................................... soc/intel/braswell: Use common sb code for SPI lockdown configuration This removes the weakly linked function to configure the SPI lockdown. Change-Id: I1e7be41a9470b37ad954d3120a67fc4d93633113 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/facebook/fbg1701/w25q64.c M src/mainboard/google/cyan/w25q64.c M src/mainboard/intel/strago/w25q64.c M src/mainboard/portwell/m107/w25q64.c M src/soc/intel/braswell/include/soc/spi.h M src/soc/intel/braswell/southcluster.c 6 files changed, 22 insertions(+), 186 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/36007/1 diff --git a/src/mainboard/facebook/fbg1701/w25q64.c b/src/mainboard/facebook/fbg1701/w25q64.c index bc908f0..2f131f4 100644 --- a/src/mainboard/facebook/fbg1701/w25q64.c +++ b/src/mainboard/facebook/fbg1701/w25q64.c @@ -20,57 +20,16 @@ #include <drivers/spi/spi_winbond.h> /* - * SPI lockdown configuration + * SPI VSCC configuration */ -#define SPI_OPMENU_0 CMD_W25_WRSR /* Write Status Register */ -#define SPI_OPTYPE_0 SPI_OPTYPE_WR_NOADDR /* Write, no address */ - -#define SPI_OPMENU_1 CMD_W25_PP /* BYPR: Byte Program */ -#define SPI_OPTYPE_1 SPI_OPTYPE_WR_ADDR /* Write, address required */ - -#define SPI_OPMENU_2 CMD_W25_READ /* Read Data */ -#define SPI_OPTYPE_2 SPI_OPTYPE_RD_ADDR /* Read, address required */ - -#define SPI_OPMENU_3 CMD_W25_RDSR /* Read Status Register */ -#define SPI_OPTYPE_3 SPI_OPTYPE_RD_NOADDR /* Read, no address */ - -#define SPI_OPMENU_4 CMD_W25_SE /* Sector Erase */ -#define SPI_OPTYPE_4 SPI_OPTYPE_WR_ADDR /* Write, address required */ - -#define SPI_OPMENU_5 CMD_W25_RDID /* Read ID */ -#define SPI_OPTYPE_5 SPI_OPTYPE_RD_NOADDR /* Read, no address */ - -#define SPI_OPMENU_6 CMD_W25_BE /* BE: Block Erase */ -#define SPI_OPTYPE_6 SPI_OPTYPE_WR_ADDR /* Write, address required */ - -#define SPI_OPMENU_7 CMD_W25_FAST_READ /* FAST: Fast Read */ -#define SPI_OPTYPE_7 SPI_OPTYPE_RD_ADDR /* Read, address required */ - -#define SPI_OPPREFIX CMD_W25_WREN /* WREN only to be inline */ - /* with flashrom */ - -#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ - (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ - (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ - (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0 << 0)) - -#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ - (SPI_OPMENU_5 << 8) | (SPI_OPMENU_4 << 0)) - -#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ - (SPI_OPMENU_1 << 8) | (SPI_OPMENU_0 << 0)) - #define SPI_VSCC (WG_64_BYTE | EO(0x20) | BES_4_KB) -static const struct spi_config spi_config = { - .preop = CMD_W25_WREN, - .optype = SPI_OPTYPE, - .opmenu = { SPI_OPMENU_LOWER, SPI_OPMENU_UPPER }, +static const struct vscc_config spi_config = { .lvscc = SPI_VSCC, .uvscc = SPI_VSCC, }; -int mainboard_get_spi_config(struct spi_config *cfg) +int mainboard_get_spi_vscc_config(struct vscc_config *cfg) { memcpy(cfg, &spi_config, sizeof(*cfg)); diff --git a/src/mainboard/google/cyan/w25q64.c b/src/mainboard/google/cyan/w25q64.c index 861a464..5eea802 100644 --- a/src/mainboard/google/cyan/w25q64.c +++ b/src/mainboard/google/cyan/w25q64.c @@ -18,52 +18,16 @@ #include <string.h> /* - * SPI lockdown configuration W25Q64FW. + * SPI VSCC configuration W25Q64FW. */ -#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */ -#define SPI_OPTYPE_0 0x01 /* Write, no address */ - -#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */ -#define SPI_OPTYPE_1 0x03 /* Write, address required */ - -#define SPI_OPMENU_2 0x03 /* READ: Read Data */ -#define SPI_OPTYPE_2 0x02 /* Read, address required */ - -#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */ -#define SPI_OPTYPE_3 0x00 /* Read, no address */ - -#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */ -#define SPI_OPTYPE_4 0x03 /* Write, address required */ - -#define SPI_OPMENU_5 0x9f /* RDID: Read ID */ -#define SPI_OPTYPE_5 0x00 /* Read, no address */ - -#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */ -#define SPI_OPTYPE_6 0x03 /* Write, address required */ - -#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */ -#define SPI_OPTYPE_7 0x02 /* Read, address required */ - -#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */ -#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ - (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ - (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ - (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0 << 0)) -#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ - (SPI_OPMENU_5 << 8) | (SPI_OPMENU_4 << 0)) -#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ - (SPI_OPMENU_1 << 8) | (SPI_OPMENU_0 << 0)) #define SPI_VSCC (WG_64_BYTE | EO(0x20) | BES_4_KB) -static const struct spi_config spi_config = { - .preop = SPI_OPPREFIX, - .optype = SPI_OPTYPE, - .opmenu = { SPI_OPMENU_LOWER, SPI_OPMENU_UPPER }, +static const struct vscc_config spi_config = { .lvscc = SPI_VSCC, .uvscc = SPI_VSCC, }; -int mainboard_get_spi_config(struct spi_config *cfg) +int mainboard_get_spi_vscc_config(struct vscc_config *cfg) { memcpy(cfg, &spi_config, sizeof(*cfg)); diff --git a/src/mainboard/intel/strago/w25q64.c b/src/mainboard/intel/strago/w25q64.c index 861a464..5598de4 100644 --- a/src/mainboard/intel/strago/w25q64.c +++ b/src/mainboard/intel/strago/w25q64.c @@ -18,52 +18,17 @@ #include <string.h> /* - * SPI lockdown configuration W25Q64FW. + * SPI VSCC configuration W25Q64FW. */ -#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */ -#define SPI_OPTYPE_0 0x01 /* Write, no address */ -#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */ -#define SPI_OPTYPE_1 0x03 /* Write, address required */ - -#define SPI_OPMENU_2 0x03 /* READ: Read Data */ -#define SPI_OPTYPE_2 0x02 /* Read, address required */ - -#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */ -#define SPI_OPTYPE_3 0x00 /* Read, no address */ - -#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */ -#define SPI_OPTYPE_4 0x03 /* Write, address required */ - -#define SPI_OPMENU_5 0x9f /* RDID: Read ID */ -#define SPI_OPTYPE_5 0x00 /* Read, no address */ - -#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */ -#define SPI_OPTYPE_6 0x03 /* Write, address required */ - -#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */ -#define SPI_OPTYPE_7 0x02 /* Read, address required */ - -#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */ -#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ - (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ - (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ - (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0 << 0)) -#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ - (SPI_OPMENU_5 << 8) | (SPI_OPMENU_4 << 0)) -#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ - (SPI_OPMENU_1 << 8) | (SPI_OPMENU_0 << 0)) #define SPI_VSCC (WG_64_BYTE | EO(0x20) | BES_4_KB) -static const struct spi_config spi_config = { - .preop = SPI_OPPREFIX, - .optype = SPI_OPTYPE, - .opmenu = { SPI_OPMENU_LOWER, SPI_OPMENU_UPPER }, +static const struct vscc_config spi_config = { .lvscc = SPI_VSCC, .uvscc = SPI_VSCC, }; -int mainboard_get_spi_config(struct spi_config *cfg) +int mainboard_get_spi_vscc_config(struct vscc_config *cfg) { memcpy(cfg, &spi_config, sizeof(*cfg)); diff --git a/src/mainboard/portwell/m107/w25q64.c b/src/mainboard/portwell/m107/w25q64.c index bc908f0..2f131f4 100644 --- a/src/mainboard/portwell/m107/w25q64.c +++ b/src/mainboard/portwell/m107/w25q64.c @@ -20,57 +20,16 @@ #include <drivers/spi/spi_winbond.h> /* - * SPI lockdown configuration + * SPI VSCC configuration */ -#define SPI_OPMENU_0 CMD_W25_WRSR /* Write Status Register */ -#define SPI_OPTYPE_0 SPI_OPTYPE_WR_NOADDR /* Write, no address */ - -#define SPI_OPMENU_1 CMD_W25_PP /* BYPR: Byte Program */ -#define SPI_OPTYPE_1 SPI_OPTYPE_WR_ADDR /* Write, address required */ - -#define SPI_OPMENU_2 CMD_W25_READ /* Read Data */ -#define SPI_OPTYPE_2 SPI_OPTYPE_RD_ADDR /* Read, address required */ - -#define SPI_OPMENU_3 CMD_W25_RDSR /* Read Status Register */ -#define SPI_OPTYPE_3 SPI_OPTYPE_RD_NOADDR /* Read, no address */ - -#define SPI_OPMENU_4 CMD_W25_SE /* Sector Erase */ -#define SPI_OPTYPE_4 SPI_OPTYPE_WR_ADDR /* Write, address required */ - -#define SPI_OPMENU_5 CMD_W25_RDID /* Read ID */ -#define SPI_OPTYPE_5 SPI_OPTYPE_RD_NOADDR /* Read, no address */ - -#define SPI_OPMENU_6 CMD_W25_BE /* BE: Block Erase */ -#define SPI_OPTYPE_6 SPI_OPTYPE_WR_ADDR /* Write, address required */ - -#define SPI_OPMENU_7 CMD_W25_FAST_READ /* FAST: Fast Read */ -#define SPI_OPTYPE_7 SPI_OPTYPE_RD_ADDR /* Read, address required */ - -#define SPI_OPPREFIX CMD_W25_WREN /* WREN only to be inline */ - /* with flashrom */ - -#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ - (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ - (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ - (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0 << 0)) - -#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ - (SPI_OPMENU_5 << 8) | (SPI_OPMENU_4 << 0)) - -#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ - (SPI_OPMENU_1 << 8) | (SPI_OPMENU_0 << 0)) - #define SPI_VSCC (WG_64_BYTE | EO(0x20) | BES_4_KB) -static const struct spi_config spi_config = { - .preop = CMD_W25_WREN, - .optype = SPI_OPTYPE, - .opmenu = { SPI_OPMENU_LOWER, SPI_OPMENU_UPPER }, +static const struct vscc_config spi_config = { .lvscc = SPI_VSCC, .uvscc = SPI_VSCC, }; -int mainboard_get_spi_config(struct spi_config *cfg) +int mainboard_get_spi_vscc_config(struct vscc_config *cfg) { memcpy(cfg, &spi_config, sizeof(*cfg)); diff --git a/src/soc/intel/braswell/include/soc/spi.h b/src/soc/intel/braswell/include/soc/spi.h index 2d27545..ddbe7b9 100644 --- a/src/soc/intel/braswell/include/soc/spi.h +++ b/src/soc/intel/braswell/include/soc/spi.h @@ -60,17 +60,14 @@ # define BCR_WPD (0x1 << 0) /* - * SPI lockdown configuration. + * SPI VSCC configuration. */ -struct spi_config { - uint16_t preop; - uint16_t optype; - uint32_t opmenu[2]; +struct vscc_config { uint32_t lvscc; uint32_t uvscc; }; /* Return 0 on success < 0 on failure. */ -int mainboard_get_spi_config(struct spi_config *cfg); +int mainboard_get_spi_vscc_config(struct vscc_config *cfg); #endif /* _SOC_SPI_H_ */ diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index c233dc8..8b13fd0 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -42,6 +42,7 @@ #include <soc/spi.h> #include <spi-generic.h> #include <stdint.h> +#include <southbridge/intel/common/spi.h> static void sc_set_serial_irqs_mode(struct device *dev, enum serirq_mode mode) { @@ -608,13 +609,6 @@ .device = LPC_DEVID, }; -int __weak mainboard_get_spi_config(struct spi_config *cfg) -{ - printk(BIOS_SPEW, "%s/%s (0x%p)\n", - __FILE__, __func__, (void *)cfg); - return -1; -} - static void finalize_chipset(void *unused) { void *bcr = (void *)(SPI_BASE_ADDRESS + BCR); @@ -622,7 +616,7 @@ void *gen_pmcon2 = (void *)(PMC_BASE_ADDRESS + GEN_PMCON2); void *etr = (void *)(PMC_BASE_ADDRESS + ETR); uint8_t *spi = (uint8_t *)SPI_BASE_ADDRESS; - struct spi_config cfg; + struct vscc_config cfg; printk(BIOS_SPEW, "%s/%s (0x%p)\n", __FILE__, __func__, unused); @@ -639,14 +633,12 @@ /* Set the CF9 lock. */ write32(etr, read32(etr) | CF9LOCK); - if (mainboard_get_spi_config(&cfg) < 0) { - printk(BIOS_DEBUG, "No SPI lockdown configuration.\n"); + spi_finalize_ops(); + write16(spi + HSFSTS, read16(spi + HSFSTS) | FLOCKDN); + + if (mainboard_get_spi_vscc_config(&cfg) < 0) { + printk(BIOS_DEBUG, "No SPI VSCC configuration.\n"); } else { - write16(spi + PREOP, cfg.preop); - write16(spi + OPTYPE, cfg.optype); - write32(spi + OPMENU0, cfg.opmenu[0]); - write32(spi + OPMENU1, cfg.opmenu[1]); - write16(spi + HSFSTS, read16(spi + HSFSTS) | FLOCKDN); write32(spi + UVSCC, cfg.uvscc); write32(spi + LVSCC, cfg.lvscc | VCL); } -- To view, visit https://review.coreboot.org/c/coreboot/+/36007 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e7be41a9470b37ad954d3120a67fc4d93633113 Gerrit-Change-Number: 36007 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

6 13

Change in coreboot[master]: mb/intel/icelake_rvp: Remove nested variant header references
by Aamir Bohra (Code Review) 05 Dec '19

05 Dec '19

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37356 ) Change subject: mb/intel/icelake_rvp: Remove nested variant header references ...................................................................... mb/intel/icelake_rvp: Remove nested variant header references Change-Id: I11b2d75dc0d4ff180b03324e5ce3d5590c8169a5 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/mainboard/intel/icelake_rvp/bootblock.c M src/mainboard/intel/icelake_rvp/chromeos.c M src/mainboard/intel/icelake_rvp/dsdt.asl M src/mainboard/intel/icelake_rvp/hda_verb.c M src/mainboard/intel/icelake_rvp/mainboard.c M src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/ec.h R src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/hda_verb.h M src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/variants.h D src/mainboard/intel/icelake_rvp/variants/icl_u/include/variant/ec.h D src/mainboard/intel/icelake_rvp/variants/icl_u/include/variant/gpio.h D src/mainboard/intel/icelake_rvp/variants/icl_y/include/variant/ec.h D src/mainboard/intel/icelake_rvp/variants/icl_y/include/variant/gpio.h D src/mainboard/intel/icelake_rvp/variants/icl_y/include/variant/hda_verb.h 13 files changed, 7 insertions(+), 798 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/37356/1 diff --git a/src/mainboard/intel/icelake_rvp/bootblock.c b/src/mainboard/intel/icelake_rvp/bootblock.c index 8655947..f982bf4 100644 --- a/src/mainboard/intel/icelake_rvp/bootblock.c +++ b/src/mainboard/intel/icelake_rvp/bootblock.c @@ -12,11 +12,10 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ - +#include <baseboard/gpio.h> #include <baseboard/variants.h> #include <bootblock_common.h> #include <soc/gpio.h> -#include <variant/gpio.h> void bootblock_mainboard_init(void) { diff --git a/src/mainboard/intel/icelake_rvp/chromeos.c b/src/mainboard/intel/icelake_rvp/chromeos.c index 785fe4a..da3f1d4 100644 --- a/src/mainboard/intel/icelake_rvp/chromeos.c +++ b/src/mainboard/intel/icelake_rvp/chromeos.c @@ -14,11 +14,10 @@ */ #include <arch/acpi.h> +#include <baseboard/gpio.h> #include <baseboard/variants.h> #include <boot/coreboot_tables.h> #include <gpio.h> -#include <soc/gpio.h> -#include <variant/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> void fill_lb_gpios(struct lb_gpios *gpios) diff --git a/src/mainboard/intel/icelake_rvp/dsdt.asl b/src/mainboard/intel/icelake_rvp/dsdt.asl index 152f038..f8fcd4d 100644 --- a/src/mainboard/intel/icelake_rvp/dsdt.asl +++ b/src/mainboard/intel/icelake_rvp/dsdt.asl @@ -14,8 +14,8 @@ */ #include <arch/acpi.h> -#include "variant/ec.h" -#include "variant/gpio.h" +#include <baseboard/ec.h> +#include <baseboard/gpio.h> DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/intel/icelake_rvp/hda_verb.c b/src/mainboard/intel/icelake_rvp/hda_verb.c index c87392d..c01530b 100644 --- a/src/mainboard/intel/icelake_rvp/hda_verb.c +++ b/src/mainboard/intel/icelake_rvp/hda_verb.c @@ -12,5 +12,4 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ - -#include "variant/hda_verb.h" +#include <baseboard/hda_verb.h> \ No newline at end of file diff --git a/src/mainboard/intel/icelake_rvp/mainboard.c b/src/mainboard/intel/icelake_rvp/mainboard.c index 8e51e45..edc27a9 100644 --- a/src/mainboard/intel/icelake_rvp/mainboard.c +++ b/src/mainboard/intel/icelake_rvp/mainboard.c @@ -14,11 +14,10 @@ */ #include <arch/acpi.h> +#include <baseboard/gpio.h> #include <baseboard/variants.h> #include <device/device.h> -#include <soc/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> -#include <variant/gpio.h> static void mainboard_init(void *chip_info) { diff --git a/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/ec.h b/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/ec.h index 03096ac..ed33547 100644 --- a/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/ec.h @@ -18,9 +18,7 @@ #include <ec/ec.h> #include <ec/google/chromeec/ec_commands.h> - -#include <variant/gpio.h> - +#include <baseboard/gpio.h> #define MAINBOARD_EC_SCI_EVENTS \ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_u/include/variant/hda_verb.h b/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/hda_verb.h similarity index 100% rename from src/mainboard/intel/icelake_rvp/variants/icl_u/include/variant/hda_verb.h rename to src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/hda_verb.h diff --git a/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/variants.h index 12d16bc..a00b344 100644 --- a/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/variants.h @@ -25,7 +25,6 @@ const struct pad_config *variant_gpio_table(size_t *num); const struct pad_config *variant_early_gpio_table(size_t *num); - const struct cros_gpio *variant_cros_gpios(size_t *num); #endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_u/include/variant/ec.h b/src/mainboard/intel/icelake_rvp/variants/icl_u/include/variant/ec.h deleted file mode 100644 index af41bf4..0000000 --- a/src/mainboard/intel/icelake_rvp/variants/icl_u/include/variant/ec.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MAINBOARD_EC_H__ -#define __MAINBOARD_EC_H__ - -#include <baseboard/ec.h> - -#endif /* __MAINBOARD_EC_H__ */ diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_u/include/variant/gpio.h b/src/mainboard/intel/icelake_rvp/variants/icl_u/include/variant/gpio.h deleted file mode 100644 index c34a9b3..0000000 --- a/src/mainboard/intel/icelake_rvp/variants/icl_u/include/variant/gpio.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2018 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ - -#ifndef __MAINBOARD_GPIO_H__ -#define __MAINBOARD_GPIO_H__ - -#include <baseboard/gpio.h> - -#endif /* __MAINBOARD_GPIO_H__ */ diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/include/variant/ec.h b/src/mainboard/intel/icelake_rvp/variants/icl_y/include/variant/ec.h deleted file mode 100644 index af41bf4..0000000 --- a/src/mainboard/intel/icelake_rvp/variants/icl_y/include/variant/ec.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MAINBOARD_EC_H__ -#define __MAINBOARD_EC_H__ - -#include <baseboard/ec.h> - -#endif /* __MAINBOARD_EC_H__ */ diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/include/variant/gpio.h b/src/mainboard/intel/icelake_rvp/variants/icl_y/include/variant/gpio.h deleted file mode 100644 index c34a9b3..0000000 --- a/src/mainboard/intel/icelake_rvp/variants/icl_y/include/variant/gpio.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2018 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ - -#ifndef __MAINBOARD_GPIO_H__ -#define __MAINBOARD_GPIO_H__ - -#include <baseboard/gpio.h> - -#endif /* __MAINBOARD_GPIO_H__ */ diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/include/variant/hda_verb.h b/src/mainboard/intel/icelake_rvp/variants/icl_y/include/variant/hda_verb.h deleted file mode 100644 index d821a26..0000000 --- a/src/mainboard/intel/icelake_rvp/variants/icl_y/include/variant/hda_verb.h +++ /dev/null @@ -1,700 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Intel Corporation - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef HDA_VERB_H -#define HDA_VERB_H - -#include <device/azalia_device.h> - -const u32 cim_verb_data[] = { - /* ALC 700 */ - 0x10EC0700, - 0xFFFFFFFF, - 0x00000023, - - AZALIA_SUBVENDOR(0, 0x10EC10F2), - AZALIA_PIN_CFG(0, 0x01, 0x00000000), - AZALIA_PIN_CFG(0, 0x12, 0x40000000), - AZALIA_PIN_CFG(0, 0x13, 0x40000000), - AZALIA_PIN_CFG(0, 0x14, 0x411111F0), - AZALIA_PIN_CFG(0, 0x15, 0x411111F0), - AZALIA_PIN_CFG(0, 0x16, 0x411111F0), - AZALIA_PIN_CFG(0, 0x17, 0x90170110), - AZALIA_PIN_CFG(0, 0x18, 0x411111F0), - AZALIA_PIN_CFG(0, 0x19, 0x04A11030), - AZALIA_PIN_CFG(0, 0x1A, 0x411111F0), - AZALIA_PIN_CFG(0, 0x1B, 0x411111F0), - AZALIA_PIN_CFG(0, 0x1D, 0x40622005), - AZALIA_PIN_CFG(0, 0x1E, 0x411111F0), - AZALIA_PIN_CFG(0, 0x1F, 0x411111F0), - AZALIA_PIN_CFG(0, 0x21, 0x04211020), - AZALIA_PIN_CFG(0, 0x29, 0x411111F0), - - /* Widget node 0x20 */ - 0x02050045, - 0x02045289, - 0x0205004A, - 0x0204201B, - /* Widget node 0x20 - 1 */ - 0x05850000, - 0x05843888, - 0x0205006F, - 0x02042C0B, - - //Widget node 0X20 for ALC1305 20160603 update - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040000, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040004, - 0x02050028, - 0x02040600, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204003C, - 0x02050028, - 0x0204FFD0, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040080, - 0x02050028, - 0x02040080, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040080, - 0x02050028, - 0x02040880, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204003A, - 0x02050028, - 0x02040DFE, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204006A, - 0x02050028, - 0x0204005D, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204006C, - 0x02050028, - 0x02040442, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040005, - 0x02050028, - 0x02040880, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040006, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040008, - 0x02050028, - 0x0204B000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204002E, - 0x02050028, - 0x02040800, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204006A, - 0x02050028, - 0x020400C3, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204006C, - 0x02050028, - 0x0204D4A0, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204006A, - 0x02050028, - 0x020400CC, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204006C, - 0x02050028, - 0x0204400A, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204006A, - 0x02050028, - 0x020400C1, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204006C, - 0x02050028, - 0x02040320, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040039, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204003B, - 0x02050028, - 0x0204FFFF, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204003C, - 0x02050028, - 0x0204FC20, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204003A, - 0x02050028, - 0x02041DFE, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400C0, - 0x02050028, - 0x020401FA, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400C1, - 0x02050028, - 0x0204DE23, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400C2, - 0x02050028, - 0x02041C00, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400C3, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400C4, - 0x02050028, - 0x02040200, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400C5, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400C6, - 0x02050028, - 0x020403F5, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400C7, - 0x02050028, - 0x0204AF1B, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400C8, - 0x02050028, - 0x02041E0A, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400C9, - 0x02050028, - 0x0204368E, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400CA, - 0x02050028, - 0x020401FA, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400CB, - 0x02050028, - 0x0204DE23, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400CC, - 0x02050028, - 0x02041C00, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400CD, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400CE, - 0x02050028, - 0x02040200, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400CF, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400D0, - 0x02050028, - 0x020403F5, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400D1, - 0x02050028, - 0x0204AF1B, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400D2, - 0x02050028, - 0x02041E0A, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400D3, - 0x02050028, - 0x0204368E, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040040, - 0x02050028, - 0x0204800F, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040062, - 0x02050028, - 0x02048000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040063, - 0x02050028, - 0x02044848, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040064, - 0x02050028, - 0x02040800, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040065, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040066, - 0x02050028, - 0x02044004, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040067, - 0x02050028, - 0x02040802, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040068, - 0x02050028, - 0x0204890F, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040069, - 0x02050028, - 0x0204E021, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040070, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040071, - 0x02050000, - 0x02043330, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040072, - 0x02050000, - 0x02043333, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040073, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040074, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040075, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040076, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040050, - 0x02050028, - 0x020402EC, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040051, - 0x02050028, - 0x02044909, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040052, - 0x02050028, - 0x020440B0, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040046, - 0x02050028, - 0x0204C22E, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040047, - 0x02050028, - 0x02040C00, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040048, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040049, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204004A, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204004B, - 0x02050028, - 0x02041C00, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204006A, - 0x02050028, - 0x02040090, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204006C, - 0x02050028, - 0x0204721F, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204009E, - 0x02050028, - 0x02040001, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040004, - 0x02050028, - 0x02040500, - 0x02050029, - 0x0204B024 -}; - -const u32 pc_beep_verbs[] = { -}; -AZALIA_ARRAY_SIZES; -#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/37356 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11b2d75dc0d4ff180b03324e5ce3d5590c8169a5 Gerrit-Change-Number: 37356 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

8 15

Change in coreboot[4.11_branch]: soc/intel/broadwell_de: Re-read SPD on CRC error
by Patrick Georgi (Code Review) 05 Dec '19

05 Dec '19

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37303 ) Change subject: soc/intel/broadwell_de: Re-read SPD on CRC error ...................................................................... soc/intel/broadwell_de: Re-read SPD on CRC error I2C bus does not guarantee data integrity. As result, sometimes we end up detecting CRC errors and not adding DIMMs to SMBIOS tables. This change adds re-tries on such errors. TEST=let OCP monolake run without fan and try reading SPD data in tight loop. CRC errors were reported but subsequent retries were error free. Change-Id: I650c8cd80f75b603db332024748a91af6171f096 Signed-off-by: Andrey Petrov <anpetrov(a)fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37303 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/soc/intel/fsp_broadwell_de/romstage/memory.c 1 file changed, 29 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved diff --git a/src/soc/intel/fsp_broadwell_de/romstage/memory.c b/src/soc/intel/fsp_broadwell_de/romstage/memory.c index afbf97b..b4bc097 100644 --- a/src/soc/intel/fsp_broadwell_de/romstage/memory.c +++ b/src/soc/intel/fsp_broadwell_de/romstage/memory.c @@ -20,6 +20,8 @@ #include <soc/memory.h> #include <spd_bin.h> +#define MAX_SPD_READ_TRIES 3 + static uint32_t get_memory_dclk(void) { uint32_t reg32 = @@ -30,7 +32,7 @@ void save_dimm_info(void) { int index = 0; - uint32_t dclk_mhz = 0; + uint32_t dclk_mhz = 0, tries; /* * When talking to SPD chips through IMC slave offset of 0x50 is automagically added @@ -53,9 +55,33 @@ for (int slot = 0; slot < CONFIG_DIMM_MAX / IMC_MAX_CHANNELS; slot++) { dimm_attr dimm = {0}; u8 *spd_data = blk.spd_array[index]; - if (spd_decode_ddr4(&dimm, spd_data) == SPD_STATUS_OK) - spd_add_smbios17_ddr4(channel, slot, dclk_mhz, &dimm); + int res = SPD_STATUS_OK; + tries = MAX_SPD_READ_TRIES; + /* + * SMBus controller can't validate data integrity. So on CRC + * error retry a few times. + */ + do { + res = spd_decode_ddr4(&dimm, spd_data); + if (res == SPD_STATUS_CRC_ERROR) { + printk(BIOS_ERR, + "SPD CRC error, channel %u slot %u " + "try %u\n", channel, slot, tries); + get_spd_smbus(&blk); + } + } while (tries-- && res == SPD_STATUS_CRC_ERROR); + index++; + + if (res == SPD_STATUS_CRC_ERROR) { + printk(BIOS_WARNING, "Gave up reading CRC on channel %u" + " slot %u\n", channel, slot); + continue; + } + + if (res == SPD_STATUS_OK) { + spd_add_smbios17_ddr4(channel, slot, dclk_mhz, &dimm); + } } } } -- To view, visit https://review.coreboot.org/c/coreboot/+/37303 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: I650c8cd80f75b603db332024748a91af6171f096 Gerrit-Change-Number: 37303 Gerrit-PatchSet: 4 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: arm64: Print a char to UART early in exception handler
by Julius Werner (Code Review) 05 Dec '19

05 Dec '19

Hello Hung-Te Lin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/37465 to review the following change. Change subject: arm64: Print a char to UART early in exception handler ...................................................................... arm64: Print a char to UART early in exception handler Over time our printk() seems to acquire more and more features... which is nice, but it also makes it a little less robust when something goes wrong. If the wrong global is trampled by some buffer overflow, it suddenly doesn't print anymore. It would be nice to have at least some way to tell that we triggered a real exception in that case. With this patch, arm64 exceptions will print a '!' straight to the UART before trying any of the more fancy printk() stuff. It's not much but it should tell the difference between an exception and a hang and hopefully help someone dig in the right direction sooner. This violates loglevels (which is part of the point), but presumably when you have a fatal exception you shouldn't care about that anymore. Change-Id: I3b08ab86beaee55263786011caa5588d93bbc720 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M src/arch/arm64/armv8/exception.c 1 file changed, 8 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/37465/1 diff --git a/src/arch/arm64/armv8/exception.c b/src/arch/arm64/armv8/exception.c index ec8fc05..c11ce57 100644 --- a/src/arch/arm64/armv8/exception.c +++ b/src/arch/arm64/armv8/exception.c @@ -34,6 +34,7 @@ #include <arch/exception.h> #include <arch/transition.h> #include <console/console.h> +#include <console/uart.h> #include <arch/lib_helpers.h> uint8_t exception_stack[1*KiB] __attribute__((aligned(16))); @@ -131,8 +132,13 @@ static void print_exception_info(struct exc_state *state, uint64_t idx) { - if (idx < NUM_EXC_VIDS) - printk(BIOS_DEBUG, "exception %s\n", exception_names[idx]); + /* Poor man's sign of life in case printk() is shot. */ + __uart_tx_byte('\r'); + __uart_tx_byte('\n'); + __uart_tx_byte('!'); + + printk(BIOS_DEBUG, "\nexception %s\n", + idx < NUM_EXC_VIDS ? exception_names[idx] : "_unknown"); print_regs(state); /* Few words below SP in case we need state from a returned function. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/37465 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b08ab86beaee55263786011caa5588d93bbc720 Gerrit-Change-Number: 37465 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: arm64: Bump exception stack size to 2KB
by Julius Werner (Code Review) 05 Dec '19

05 Dec '19

Hello Hung-Te Lin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/37464 to review the following change. Change subject: arm64: Bump exception stack size to 2KB ...................................................................... arm64: Bump exception stack size to 2KB To avoid trampling over interesting exception artifacts on the real stack, our arm64 systems switch to a separate exception stack when entering an exception handler. We don't want that to use up too much SRAM so we just set it to 512 bytes. I mean it just prints a bunch of registers, how much stack could it need, right? Quite a bit it turns out. The whole vtxprintf() call stack goes pretty deep, and aarch64 generally seems to be very generous with stack space. Just the varargs handling seems to require 128 bytes for some reason, and the other stuff adds up too. In the end the current implementation takes 1008 bytes, so bump the exception stack size to 2K to make sure it fits. Change-Id: I910be4c5f6b29fae35eb53929c733a1bd4585377 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M src/arch/arm64/armv8/exception.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/37464/1 diff --git a/src/arch/arm64/armv8/exception.c b/src/arch/arm64/armv8/exception.c index 579e104..ec8fc05 100644 --- a/src/arch/arm64/armv8/exception.c +++ b/src/arch/arm64/armv8/exception.c @@ -36,7 +36,7 @@ #include <console/console.h> #include <arch/lib_helpers.h> -uint8_t exception_stack[0x200] __attribute__((aligned(16))); +uint8_t exception_stack[1*KiB] __attribute__((aligned(16))); static const char *exception_names[NUM_EXC_VIDS] = { [EXC_VID_CUR_SP_EL0_SYNC] = "_sync_sp_el0", -- To view, visit https://review.coreboot.org/c/coreboot/+/37464 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I910be4c5f6b29fae35eb53929c733a1bd4585377 Gerrit-Change-Number: 37464 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: arm64: Correctly unmask asynchronous SError interrupts
by Julius Werner (Code Review) 05 Dec '19

05 Dec '19

Hello Hung-Te Lin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/37463 to review the following change. Change subject: arm64: Correctly unmask asynchronous SError interrupts ...................................................................... arm64: Correctly unmask asynchronous SError interrupts Arm CPUs have always had an odd feature that allows you to mask not only true interrupts, but also "external aborts" (memory bus errors from outside the CPU). CPUs usually have all of these masked after reset, which we quickly learned was a bad idea back when bringing up the first arm32 systems in coreboot. Masking external aborts means that if any of your firmware code does an illegal memory access, you will only see it once the kernel comes up and unmasks the abort (not when it happens). Therefore, we always unmask everything in early bootblock assembly code. When arm64 came around, it had very similar masking bits and we did the same there, thinking the issue resolved. Unfortunately Arm, in their ceaseless struggle for more complexity, decided that having a single bit to control this masking behavior is no longer enough: on AArch64, in addition to the PSTATE.DAIF bits that are analogous to arm32's CPSR, there are additional bits in SCR_EL3 that can override the PSTATE setting for some but not all cases (makes perfect sense, I know...). When aborts are unmasked in PSTATE, but SCR.EA is not set, then synchronous external aborts will cause an exception while asynchronous external aborts will not. It turns out we never intialize SCR in coreboot and on RK3399 it comes up with all zeroes (even the reserved-1 bits, which is super weird). If you get an asynchronous external abort in coreboot it will silently hide in the CPU until BL31 enables SCR.EA before it has its own console handlers registered and silently hangs. This patch resolves the issue by also intiializing SCR to a known good state early in the bootblock. It also cleans up some bit defintions and slightly reworks the DAIF unmasking... it doesn't actually make that much sense to unmask anything before our console and exception handlers are up. The new code will mask everything until the exception handler is installed and then unmask it, so that if there was a super early external abort we could still see it. (Of course there are still dozens of other processor exceptions that could happen which we have no way to mask.) Change-Id: I5266481a7aaf0b72aca8988accb671d92739af6f Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M src/arch/arm64/armv8/cpu.S M src/arch/arm64/include/armv8/arch/cache.h M src/arch/arm64/include/armv8/arch/lib_helpers.h M src/arch/arm64/transition.c M src/arch/arm64/transition_asm.S 5 files changed, 59 insertions(+), 129 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/37463/1 diff --git a/src/arch/arm64/armv8/cpu.S b/src/arch/arm64/armv8/cpu.S index 2bc4def..5f06c7e 100644 --- a/src/arch/arm64/armv8/cpu.S +++ b/src/arch/arm64/armv8/cpu.S @@ -99,15 +99,14 @@ /* * Bring an ARMv8 processor we just gained control of (e.g. from IROM) into a - * known state regarding caches/SCTLR/PSTATE. Completely invalidates + * known state regarding caches/SCTLR/SCR/PSTATE. Completely invalidates * icache/dcache, disables MMU and dcache (if active), and enables unaligned - * accesses, icache and branch prediction (if inactive). Seeds the stack and - * initializes SP_EL0. Clobbers R22 and R23. + * accesses, icache. Seeds stack and initializes SP_EL0. Clobbers R22 and R23. */ ENTRY(arm64_init_cpu) - /* Initialize PSTATE (unmask all exceptions, select SP_EL0). */ + /* Initialize PSTATE (mask all exceptions, select SP_EL0). */ msr SPSel, #0 - msr DAIFClr, #0xf + msr DAIFSet, #0xf /* TODO: This is where we'd put non-boot CPUs into WFI if needed. */ @@ -116,24 +115,25 @@ /* TODO: Assert that we always start running at EL3 */ mrs x22, sctlr_el3 - /* Activate ICache (12) already for speed during cache flush below. */ - orr x22, x22, #(1 << 12) + /* Activate ICache already for speed during cache flush below. */ + orr x22, x22, #SCTLR_I msr sctlr_el3, x22 isb /* Invalidate dcache */ bl dcache_invalidate_all - /* Deactivate MMU (0), Alignment Check (1) and DCache (2) */ - and x22, x22, # ~(1 << 0) & ~(1 << 1) & ~(1 << 2) - /* Activate Stack Alignment (3) because why not */ - orr x22, x22, #(1 << 3) - /* Set to little-endian (25) */ - and x22, x22, # ~(1 << 25) - /* Deactivate write-xor-execute enforcement (19) */ - and x22, x22, # ~(1 << 19) + /* Reinitialize SCTLR from scratch to known-good state. + This may disable MMU or DCache. */ + ldr w22, =(SCTLR_RES1 | SCTLR_I | SCTLR_SA) msr sctlr_el3, x22 + /* Initialize SCR to unmask all interrupts (so that if we get a spurious + IRQ/SError we'll see it when it happens, not hang in BL31). This will + only have an effect after we DAIFClr in exception_init(). */ + mov x22, #SCR_RES1 | SCR_IRQ | SCR_FIQ | SCR_EA + msr scr_el3, x22 + /* Invalidate icache and TLB for good measure */ ic iallu tlbi alle3 diff --git a/src/arch/arm64/include/armv8/arch/cache.h b/src/arch/arm64/include/armv8/arch/cache.h index 3de2e80..1168992 100644 --- a/src/arch/arm64/include/armv8/arch/cache.h +++ b/src/arch/arm64/include/armv8/arch/cache.h @@ -32,33 +32,13 @@ #ifndef ARM_ARM64_CACHE_H #define ARM_ARM64_CACHE_H -/* SCTLR_ELx common bits */ -#define SCTLR_M (1 << 0) /* MMU enable */ -#define SCTLR_A (1 << 1) /* Alignment check enable */ -#define SCTLR_C (1 << 2) /* Data/unified cache enable */ -#define SCTLR_SA (1 << 3) /* Stack alignment check enable */ -#define SCTLR_I (1 << 12) /* Instruction cache enable */ -#define SCTLR_WXN (1 << 19) /* Write permission implies XN */ -#define SCTLR_EE (1 << 25) /* Exception endianness */ - -/* SCTLR_EL1 bits */ -#define SCTLR_EL1_CP15B (1 << 5) /* CP15 barrier enable */ -#define SCTLR_EL1_ITD (1 << 7) /* IT disable */ -#define SCTLR_EL1_SED (1 << 8) /* SETEND disable */ -#define SCTLR_EL1_UMA (1 << 9) /* User mask access */ -#define SCTLR_EL1_DZE (1 << 14) /* DC ZVA instruction at EL0 */ -#define SCTLR_EL1_UCT (1 << 15) /* CTR_EL0 register EL0 access */ -#define SCTLR_EL1_NTWI (1 << 16) /* Not trap WFI */ -#define SCTLR_EL1_NTWE (1 << 18) /* Not trap WFE */ -#define SCTLR_EL1_E0E (1 << 24) /* Exception endianness at EL0 */ -#define SCTLR_EL1_UCI (1 << 26) /* EL0 access to cache instructions */ +#include <arch/lib_helpers.h> #ifndef __ASSEMBLER__ #include <stddef.h> #include <stdint.h> #include <arch/barrier.h> -#include <arch/lib_helpers.h> /* dcache clean by virtual address to PoC */ void dcache_clean_by_mva(void const *addr, size_t len); diff --git a/src/arch/arm64/include/armv8/arch/lib_helpers.h b/src/arch/arm64/include/armv8/arch/lib_helpers.h index 0afbf82..9d5b508 100644 --- a/src/arch/arm64/include/armv8/arch/lib_helpers.h +++ b/src/arch/arm64/include/armv8/arch/lib_helpers.h @@ -38,79 +38,46 @@ #define SPSR_DEBUG (1 << 9) #define SPSR_EXCEPTION_MASK (SPSR_FIQ | SPSR_IRQ | SPSR_SERROR | SPSR_DEBUG) -#define SCR_NS_SHIFT 0 -#define SCR_NS_MASK (1 << SCR_NS_SHIFT) -#define SCR_NS_ENABLE (1 << SCR_NS_SHIFT) -#define SCR_NS_DISABLE (0 << SCR_NS_SHIFT) -#define SCR_NS SCR_NS_ENABLE -#define SCR_RES1 (0x3 << 4) -#define SCR_IRQ_SHIFT 2 -#define SCR_IRQ_MASK (1 << SCR_IRQ_SHIFT) -#define SCR_IRQ_ENABLE (1 << SCR_IRQ_SHIFT) -#define SCR_IRQ_DISABLE (0 << SCR_IRQ_SHIFT) -#define SCR_FIQ_SHIFT 2 -#define SCR_FIQ_MASK (1 << SCR_FIQ_SHIFT) -#define SCR_FIQ_ENABLE (1 << SCR_FIQ_SHIFT) -#define SCR_FIQ_DISABLE (0 << SCR_FIQ_SHIFT) -#define SCR_EA_SHIFT 3 -#define SCR_EA_MASK (1 << SCR_EA_SHIFT) -#define SCR_EA_ENABLE (1 << SCR_EA_SHIFT) -#define SCR_EA_DISABLE (0 << SCR_EA_SHIFT) -#define SCR_SMD_SHIFT 7 -#define SCR_SMD_MASK (1 << SCR_SMD_SHIFT) -#define SCR_SMD_DISABLE (1 << SCR_SMD_SHIFT) -#define SCR_SMD_ENABLE (0 << SCR_SMD_SHIFT) -#define SCR_HVC_SHIFT 8 -#define SCR_HVC_MASK (1 << SCR_HVC_SHIFT) -#define SCR_HVC_DISABLE (0 << SCR_HVC_SHIFT) -#define SCR_HVC_ENABLE (1 << SCR_HVC_SHIFT) -#define SCR_SIF_SHIFT 9 -#define SCR_SIF_MASK (1 << SCR_SIF_SHIFT) -#define SCR_SIF_ENABLE (1 << SCR_SIF_SHIFT) -#define SCR_SIF_DISABLE (0 << SCR_SIF_SHIFT) -#define SCR_RW_SHIFT 10 -#define SCR_RW_MASK (1 << SCR_RW_SHIFT) -#define SCR_LOWER_AARCH64 (1 << SCR_RW_SHIFT) -#define SCR_LOWER_AARCH32 (0 << SCR_RW_SHIFT) -#define SCR_ST_SHIFT 11 -#define SCR_ST_MASK (1 << SCR_ST_SHIFT) -#define SCR_ST_ENABLE (1 << SCR_ST_SHIFT) -#define SCR_ST_DISABLE (0 << SCR_ST_SHIFT) -#define SCR_TWI_SHIFT 12 -#define SCR_TWI_MASK (1 << SCR_TWI_SHIFT) -#define SCR_TWI_ENABLE (1 << SCR_TWI_SHIFT) -#define SCR_TWI_DISABLE (0 << SCR_TWI_SHIFT) -#define SCR_TWE_SHIFT 13 -#define SCR_TWE_MASK (1 << SCR_TWE_SHIFT) -#define SCR_TWE_ENABLE (1 << SCR_TWE_SHIFT) -#define SCR_TWE_DISABLE (0 << SCR_TWE_SHIFT) +#define SCR_NS (1 << 0) /* EL0/1 are non-secure */ +#define SCR_IRQ (1 << 1) /* Take IRQs in EL3 */ +#define SCR_FIQ (1 << 2) /* Take FIQs in EL3 */ +#define SCR_EA (1 << 3) /* Take EA/SError in EL3 */ +#define SCR_SMD (1 << 7) /* Disable SMC instruction */ +#define SCR_HCE (1 << 8) /* Enable HVC instruction */ +#define SCR_SIF (1 << 9) /* Forbid insns from NS memory */ +#define SCR_RW (1 << 10) /* Lower ELs are AArch64 */ +#define SCR_ST (1 << 11) /* Don't trap secure CNTPS */ +#define SCR_TWI (1 << 12) /* Trap WFI to EL3 */ +#define SCR_TWE (1 << 13) /* Trap WFE to EL3 */ +#define SCR_TLOR (1 << 14) /* Trap LOR accesses to EL3 */ +#define SCR_TERR (1 << 15) /* Trap ERR accesses to EL3 */ +#define SCR_APK (1 << 16) /* Don't trap ptrauth keys */ +#define SCR_API (1 << 17) /* Don't trap ptrauth insn */ +#define SCR_EEL2 (1 << 18) /* Enable secure EL2 */ +#define SCR_EASE (1 << 19) /* Sync EAs use SError vector */ +#define SCR_NMEA (1 << 20) /* Disallow EL3 SError masking */ +#define SCR_FIEN (1 << 21) /* Don't trap EXRPFG */ +#define SCR_RES1 (3 << 4) #define HCR_RW_SHIFT 31 #define HCR_LOWER_AARCH64 (1 << HCR_RW_SHIFT) #define HCR_LOWER_AARCH32 (0 << HCR_RW_SHIFT) -#define SCTLR_MMU_ENABLE 1 -#define SCTLR_MMU_DISABLE 0 -#define SCTLR_ACE_SHIFT 1 -#define SCTLR_ACE_ENABLE (1 << SCTLR_ACE_SHIFT) -#define SCTLR_ACE_DISABLE (0 << SCTLR_ACE_SHIFT) -#define SCTLR_CACHE_SHIFT 2 -#define SCTLR_CACHE_ENABLE (1 << SCTLR_CACHE_SHIFT) -#define SCTLR_CACHE_DISABLE (0 << SCTLR_CACHE_SHIFT) -#define SCTLR_SAE_SHIFT 3 -#define SCTLR_SAE_ENABLE (1 << SCTLR_SAE_SHIFT) -#define SCTLR_SAE_DISABLE (0 << SCTLR_SAE_SHIFT) +#define SCTLR_M (1 << 0) /* MMU enable */ +#define SCTLR_A (1 << 1) /* Alignment check enable */ +#define SCTLR_C (1 << 2) /* Data/unified cache enable */ +#define SCTLR_SA (1 << 3) /* Stack alignment check enable */ +#define SCTLR_NAA (1 << 6) /* non-aligned access STA/LDR */ +#define SCTLR_I (1 << 12) /* Instruction cache enable */ +#define SCTLR_ENDB (1 << 13) /* Pointer auth (data B) */ +#define SCTLR_WXN (1 << 19) /* Write permission implies XN */ +#define SCTLR_IESB (1 << 21) /* Implicit error sync event */ +#define SCTLR_EE (1 << 25) /* Exception endianness (BE) */ +#define SCTLR_ENDA (1 << 27) /* Pointer auth (data A) */ +#define SCTLR_ENIB (1 << 30) /* Pointer auth (insn B) */ +#define SCTLR_ENIA (1 << 31) /* Pointer auth (insn A) */ #define SCTLR_RES1 ((0x3 << 4) | (0x1 << 11) | (0x1 << 16) | \ (0x1 << 18) | (0x3 << 22) | (0x3 << 28)) -#define SCTLR_ICE_SHIFT 12 -#define SCTLR_ICE_ENABLE (1 << SCTLR_ICE_SHIFT) -#define SCTLR_ICE_DISABLE (0 << SCTLR_ICE_SHIFT) -#define SCTLR_WXN_SHIFT 19 -#define SCTLR_WXN_ENABLE (1 << SCTLR_WXN_SHIFT) -#define SCTLR_WXN_DISABLE (0 << SCTLR_WXN_SHIFT) -#define SCTLR_ENDIAN_SHIFT 25 -#define SCTLR_LITTLE_END (0 << SCTLR_ENDIAN_SHIFT) -#define SCTLR_BIG_END (1 << SCTLR_ENDIAN_SHIFT) #define CPTR_EL3_TCPAC_SHIFT (31) #define CPTR_EL3_TTA_SHIFT (20) diff --git a/src/arch/arm64/transition.c b/src/arch/arm64/transition.c index 3e8d7f0..ac59d19 100644 --- a/src/arch/arm64/transition.c +++ b/src/arch/arm64/transition.c @@ -17,14 +17,6 @@ #include <arch/transition.h> #include <assert.h> -/* Litte-endian, No XN-forced, Instr cache disabled, - * Stack alignment disabled, Data and unified cache - * disabled, Alignment check disabled, MMU disabled - */ -#define SCTLR_MASK (SCTLR_MMU_DISABLE | SCTLR_ACE_DISABLE | \ - SCTLR_CACHE_DISABLE | SCTLR_SAE_DISABLE | SCTLR_RES1 | \ - SCTLR_ICE_DISABLE | SCTLR_WXN_DISABLE | SCTLR_LITTLE_END) - void __weak exc_dispatch(struct exc_state *exc_state, uint64_t id) { /* Default weak implementation does nothing. */ @@ -54,7 +46,6 @@ struct exc_state exc_state; struct elx_state *elx = &exc_state.elx; struct regs *regs = &exc_state.regs; - uint32_t sctlr; regs->x[X0_INDEX] = (uint64_t)arg; elx->elr = (uint64_t)entry; @@ -70,19 +61,10 @@ */ assert(get_el_from_spsr(spsr) == EL2 && !(spsr & SPSR_ERET_32)); - /* Initialize SCR with defaults for running without secure monitor. */ - raw_write_scr_el3(SCR_TWE_DISABLE | /* don't trap WFE */ - SCR_TWI_DISABLE | /* don't trap WFI */ - SCR_ST_ENABLE | /* allow secure timer access */ - SCR_LOWER_AARCH64 | /* lower level is AArch64 */ - SCR_SIF_DISABLE | /* disable secure ins. fetch */ - SCR_HVC_ENABLE | /* allow HVC instruction */ - SCR_SMD_ENABLE | /* disable SMC instruction */ - SCR_RES1 | /* reserved-1 bits */ - SCR_EA_DISABLE | /* disable ext. abort trap */ - SCR_FIQ_DISABLE | /* disable FIQ trap to EL3 */ - SCR_IRQ_DISABLE | /* disable IRQ trap to EL3 */ - SCR_NS_ENABLE); /* lower level is non-secure */ + /* Initialize SCR with defaults for running without secure monitor + (disable all traps, enable all instructions, run NS at AArch64). */ + raw_write_scr_el3(SCR_FIEN | SCR_API | SCR_APK | SCR_ST | SCR_RW | + SCR_HCE | SCR_SMD | SCR_RES1 | SCR_NS); /* Initialize CPTR to not trap anything to EL3. */ raw_write_cptr_el3(CPTR_EL3_TCPAC_DISABLE | CPTR_EL3_TTA_DISABLE | @@ -92,10 +74,8 @@ raw_write_elr_el3(elx->elr); raw_write_spsr_el3(elx->spsr); - /* SCTLR: Initialize EL with selected properties */ - sctlr = raw_read_sctlr_el2(); - sctlr &= SCTLR_MASK; - raw_write_sctlr_el2(sctlr); + /* SCTLR: Initialize EL with everything disabled */ + raw_write_sctlr_el2(SCTLR_RES1); /* SP_ELx: Initialize stack pointer */ raw_write_sp_el2(elx->sp_elx); diff --git a/src/arch/arm64/transition_asm.S b/src/arch/arm64/transition_asm.S index 718832b..bdb412f 100644 --- a/src/arch/arm64/transition_asm.S +++ b/src/arch/arm64/transition_asm.S @@ -154,7 +154,7 @@ /* * exception_init_asm: Initialize VBAR and point SP_EL3 to exception stack. - * x0 = end of exception stack + * Also unmask aborts now that we can report them. x0 = end of exception stack */ ENTRY(exception_init_asm) msr SPSel, #SPSR_USE_H @@ -163,6 +163,9 @@ adr x0, exc_vectors msr vbar_el3, x0 + + msr DAIFClr, #0xf + dsb sy isb ret -- To view, visit https://review.coreboot.org/c/coreboot/+/37463 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5266481a7aaf0b72aca8988accb671d92739af6f Gerrit-Change-Number: 37463 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: trogdor: libpayload USB support
by mturney mturney (Code Review) 05 Dec '19

05 Dec '19

mturney mturney has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36233 ) Change subject: trogdor: libpayload USB support ...................................................................... trogdor: libpayload USB support Change-Id: I26c28f9af8d819f4644e383e8d0293a3d5de9eef Signed-off-by: Sandeep Maheswaram <sanm(a)codeaurora.org> --- M payloads/libpayload/configs/config.trogdor 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/36233/1 diff --git a/payloads/libpayload/configs/config.trogdor b/payloads/libpayload/configs/config.trogdor index 0625ff5..7ca654b 100644 --- a/payloads/libpayload/configs/config.trogdor +++ b/payloads/libpayload/configs/config.trogdor @@ -3,3 +3,6 @@ CONFIG_LP_TIMER_ARM64_ARCH=y CONFIG_LP_SERIAL_CONSOLE=y CONFIG_LP_SC7180_SERIAL_CONSOLE=y +CONFIG_LP_USB=y +CONFIG_LP_USB_EHCI=y +CONFIG_LP_USB_XHCI=y -- To view, visit https://review.coreboot.org/c/coreboot/+/36233 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I26c28f9af8d819f4644e383e8d0293a3d5de9eef Gerrit-Change-Number: 36233 Gerrit-PatchSet: 1 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: trogdor: Add mainboard USB support
by mturney mturney (Code Review) 05 Dec '19

05 Dec '19

mturney mturney has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36232 ) Change subject: trogdor: Add mainboard USB support ...................................................................... trogdor: Add mainboard USB support Change-Id: I126d1d6b582ea95c97ac55784d44d3081aabdae7 Signed-off-by: Sandeep Maheswaram <sanm(a)codeaurora.org> --- M src/mainboard/google/trogdor/mainboard.c M src/mainboard/google/trogdor/romstage.c 2 files changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/36232/1 diff --git a/src/mainboard/google/trogdor/mainboard.c b/src/mainboard/google/trogdor/mainboard.c index dbdb4ed..170955a 100644 --- a/src/mainboard/google/trogdor/mainboard.c +++ b/src/mainboard/google/trogdor/mainboard.c @@ -19,10 +19,23 @@ #include <gpio.h> #include <timestamp.h> #include <soc/qupv3_fw_config.h> +#include <soc/usb.h> + +static struct usb_board_data usb0_board_data = { + .pll_bias_control_2 = 0x22, + .imp_ctrl1 = 0x08, + .port_tune1 = 0xc5, +}; + +static void setup_usb(void) +{ + setup_usb_host0(&usb0_board_data); +} static void mainboard_init(struct device *dev) { qupv3_fw_init(); + setup_usb(); } static void mainboard_enable(struct device *dev) diff --git a/src/mainboard/google/trogdor/romstage.c b/src/mainboard/google/trogdor/romstage.c index 7185387..872798a 100644 --- a/src/mainboard/google/trogdor/romstage.c +++ b/src/mainboard/google/trogdor/romstage.c @@ -14,10 +14,22 @@ */ #include <arch/stages.h> +#include <soc/usb.h> #include <soc/qclib_common.h> +static void prepare_usb(void) +{ + /* + * Do DWC3 core and phy reset. Kick these resets + * off early so they get at least 1ms to settle. + */ + reset_usb0(); +} + void platform_romstage_main(void) { + prepare_usb(); + /* QCLib: DDR init & train */ qclib_load_and_run(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/36232 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I126d1d6b582ea95c97ac55784d44d3081aabdae7 Gerrit-Change-Number: 36232 Gerrit-PatchSet: 1 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newchange

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coreboot-gerrit December 2019