coreboot-gerrit December 2019

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Change in coreboot[master]: Update vboot submodule to upstream master
by Julius Werner (Code Review) 06 Dec '19

06 Dec '19

Hello Joel Kitching, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/37472 to review the following change. Change subject: Update vboot submodule to upstream master ...................................................................... Update vboot submodule to upstream master Updating from commit id 1c4dbaa0: 2019-11-18 Julius Werner Makefile: Fix typo for MOCK_TPM to commit id 6ef33b99: 2019-11-22 Hung-Te Lin futility: updater: refactor: unify getting temp files for firmware images This brings in 13 new commits. Change-Id: Ia3a2724f1f10d205026e62c3653823813b49b460 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M 3rdparty/vboot 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/37472/1 diff --git a/3rdparty/vboot b/3rdparty/vboot index 1c4dbaa..6ef33b9 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit 1c4dbaa08419e13366db32ed20244f63c34388a0 +Subproject commit 6ef33b990578a9583a3ac53f2c835d4e16219b25 -- To view, visit https://review.coreboot.org/c/coreboot/+/37472 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia3a2724f1f10d205026e62c3653823813b49b460 Gerrit-Change-Number: 37472 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Joel Kitching <kitching(a)google.com> Gerrit-MessageType: newchange

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Change in em100[master]: Run closedir() only if opendir() succeeded
by Stefan Reinauer (Code Review) 06 Dec '19

06 Dec '19

Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/em100/+/37480 ) Change subject: Run closedir() only if opendir() succeeded ...................................................................... Run closedir() only if opendir() succeeded Otherwise we operate on a non-existing DIR * handle. Change-Id: Ib977b50cb61b5b396ecbc2d911a0876518115a81 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- M em100.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/80/37480/1 diff --git a/em100.c b/em100.c index ea93520..25d9732 100644 --- a/em100.c +++ b/em100.c @@ -720,7 +720,8 @@ DIR *dir = opendir(directory); if (dir) { - // success + /* success */ + closedir(dir); } else if (errno == ENOENT) { if (mkdir(directory, S_IRWXU | S_IRGRP | S_IXGRP | S_IROTH | S_IXOTH)) { perror(directory); @@ -733,7 +734,6 @@ return NULL; } - closedir(dir); return directory; } -- To view, visit https://review.coreboot.org/c/em100/+/37480 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: Ib977b50cb61b5b396ecbc2d911a0876518115a81 Gerrit-Change-Number: 37480 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

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Change in em100[master]: Add udev rules file for /etc/udev/rules.d
by Stefan Reinauer (Code Review) 06 Dec '19

06 Dec '19

Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/em100/+/37495 ) Change subject: Add udev rules file for /etc/udev/rules.d ...................................................................... Add udev rules file for /etc/udev/rules.d This will allow usage of the em100 tool without being root. Tested on Ubuntu. Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Change-Id: Ie440d3b280e0d57e61e9af553c0fa8c59964b03f --- A 60-dediprog-em100pro.rules 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/95/37495/1 diff --git a/60-dediprog-em100pro.rules b/60-dediprog-em100pro.rules new file mode 100644 index 0000000..080d295 --- /dev/null +++ b/60-dediprog-em100pro.rules @@ -0,0 +1,2 @@ +# drop this in /etc/udev/rules.d +ACTION=="add", SUBSYSTEM=="usb", ATTRS{idVendor}=="04b4", ATTRS{idProduct}=="1235", MODE="664", GROUP="plugdev" -- To view, visit https://review.coreboot.org/c/em100/+/37495 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: Ie440d3b280e0d57e61e9af553c0fa8c59964b03f Gerrit-Change-Number: 37495 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

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Change in em100[master]: Add test / code coverage script
by Stefan Reinauer (Code Review) 06 Dec '19

06 Dec '19

Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/em100/+/37496 ) Change subject: Add test / code coverage script ...................................................................... Add test / code coverage script Add a simple script that runs through most functions of the em100 tool and produces code coverage information. Currently does not look for errors in the output, or do any other analysis. Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Change-Id: I6f842f881e5b636eff061696f3eebf076e5f39c0 --- A gcov.sh 1 file changed, 69 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/96/37496/1 diff --git a/gcov.sh b/gcov.sh new file mode 100755 index 0000000..ff3656d --- /dev/null +++ b/gcov.sh @@ -0,0 +1,69 @@ +#!/bin/bash + +LOG=em100_test.log + +i=0 +banner_test() +{ + printf "\rRunning tests... %03d" $i +} + +next_test() +{ + lcov --no-external --capture --directory . -t TEST_$i --output-file coverage.info >> $LOG + i=$(( $i + 1)) +} + +printf "Building... " +echo "Test log" > $LOG +make clean >> $LOG +CFLAGS="-O2 -g -fomit-frame-pointer -fprofile-arcs -ftest-coverage" make >> $LOG +printf "ok\n"; + +banner_test +# some prep work +export EM100_HOME=$(mktemp -d) +i=$(( $i + 1)) + +banner_test +./em100 >>$LOG 2>&1 +next_test + +banner_test +./em100 --help >> $LOG 2>&1 +next_test + +banner_test +./em100 -U >> $LOG 2>&1 +next_test + +banner_test +./em100 --stop --set M25P80 -d file.bin -v --start >> $LOG 2>&1 +next_test + +banner_test +./em100 -U file.bin >> $LOG 2>&1 +next_test + +banner_test +./em100 --list-devices >> $LOG 2>&1 +next_test + +banner_test +./em100 --firmware-dump $EM100_HOME/test1.raw >> $LOG 2>&1 +next_test + +banner_test +./em100 --firmware-write $EM100_HOME/test2.dpfw >> $LOG 2>&1 +next_test + +banner_test +./em100 --firmware-update auto >> $LOG 2>&1 +next_test + +printf "\n\n" +printf "Now power cycle your EM100Pro\n" + +genhtml coverage.info --output-directory out >> $LOG +rm *.gcno *.gcda xz/*.gcno xz/*.gcda + -- To view, visit https://review.coreboot.org/c/em100/+/37496 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: I6f842f881e5b636eff061696f3eebf076e5f39c0 Gerrit-Change-Number: 37496 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

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Change in em100[master]: Database update: Sanitize first download
by Stefan Reinauer (Code Review) 06 Dec '19

06 Dec '19

Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/em100/+/37493 ) Change subject: Database update: Sanitize first download ...................................................................... Database update: Sanitize first download Output a sensible message with the new version number even when there is no old database downloaded already. Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Change-Id: If05a12715ea2813e1748dd9c5d96d739c82470e0 --- M curl.c 1 file changed, 10 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/93/37493/1 diff --git a/curl.c b/curl.c index 6895c62..747a98d 100644 --- a/curl.c +++ b/curl.c @@ -133,26 +133,20 @@ int update_all_files(void) { - long old_time, new_time; + long old_time = 0, new_time = 0; char old_version[256] = "<unknown>", new_version[256] = "<unknown>"; /* Read existing version and timestamp */ char *my_version_name = get_em100_file(version_name); FILE *old = fopen(my_version_name, "r"); - if (!old) { - free(my_version_name); - /* We probably don't have any files yet. Try to - * download everything. - */ - goto download_all; + if (old) { + if (fscanf(old, "Time: %ld\nVersion: %255s\n", + &old_time, old_version) != 2) + printf("Parse error in %s.\n", my_version_name); + fclose(old); } - if (fscanf(old, "Time: %ld\nVersion: %255s\n", - &old_time, old_version) != 2) - printf("Parse error in %s.\n", my_version_name); - free(my_version_name); - fclose(old); /* Read upstream version and timestamp */ char *tmp_version = get_em100_file(".VERSION.new"); @@ -177,9 +171,11 @@ return 0; } -download_all: /* Download everything */ - printf("Update available: %s (installed: %s)\n", new_version, old_version); + if (old_time == 0) + printf("Downloading latest version: %s\n", new_version); + else + printf("Update available: %s (installed: %s)\n", new_version, old_version); download(version_name, version_id); download(configs_name, configs_id); download(firmware_name, firmware_id); -- To view, visit https://review.coreboot.org/c/em100/+/37493 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: If05a12715ea2813e1748dd9c5d96d739c82470e0 Gerrit-Change-Number: 37493 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

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Change in em100[master]: trace.c: cosmetic coding style fixes
by Stefan Reinauer (Code Review) 06 Dec '19

06 Dec '19

Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/em100/+/37494 ) Change subject: trace.c: cosmetic coding style fixes ...................................................................... trace.c: cosmetic coding style fixes Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Change-Id: Ic8bd4c32c8f939aab9e1c22fc45f369e696f9380 --- M trace.c 1 file changed, 6 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/94/37494/1 diff --git a/trace.c b/trace.c index 31b6e06..5e98acb 100644 --- a/trace.c +++ b/trace.c @@ -50,7 +50,7 @@ #define REPORT_BUFFER_LENGTH 8192 #define REPORT_BUFFER_COUNT 8 -static int read_report_buffer(struct em100 *em100, +static int read_report_buffer(struct em100 *em100, unsigned char reportdata[REPORT_BUFFER_COUNT][REPORT_BUFFER_LENGTH]) { unsigned char cmd[16] = {0}; @@ -59,7 +59,7 @@ cmd[0] = 0xbc; /* read SPI trace buffer*/ - /* + /* * Trace length, unit is 4k according to specs * * cmd1..cmd4 are probably u32BE on how many @@ -128,7 +128,8 @@ {"unknown command", 0xff, 0, 0} }; -static struct spi_cmd_values * get_command_vals(uint8_t command) { +static struct spi_cmd_values * get_command_vals(uint8_t command) +{ /* cache last command so a search isn't needed every time */ static struct spi_cmd_values *spi_cmd = &spi_command_list[3]; /* init to read */ int i; @@ -265,7 +266,8 @@ * Multiple messages can be in a single uFIFO transfer, so loop through * the data looking for the signature. */ -int read_spi_terminal(struct em100 *em100, int show_counter) { +int read_spi_terminal(struct em100 *em100, int show_counter) +{ unsigned char data[UFIFO_SIZE] = { 0 }; static unsigned int msg_counter = 1; /* Number of messages */ uint16_t data_length; -- To view, visit https://review.coreboot.org/c/em100/+/37494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: Ic8bd4c32c8f939aab9e1c22fc45f369e696f9380 Gerrit-Change-Number: 37494 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: hatch: Fix FPMCU pwr/rst gpio handling
by Craig Hesling (Code Review) 05 Dec '19

05 Dec '19

Craig Hesling has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37459 ) Change subject: hatch: Fix FPMCU pwr/rst gpio handling ...................................................................... hatch: Fix FPMCU pwr/rst gpio handling 1. No gpio control in bootblock 2. Disable power and assert reset in ramstage gpio. 3. Power on and then deassert reset at the end of ramstage gpio. 4. Disable power and assert reset when entering S5. On "reboot", the amount of time the power is disabled for is equivalent to the amount of time between #4 and #3, which is about 400ms on Kohaku. Since #2 forces power off for FPMCU, S3 resume will still not work properly. Change-Id: I2e3ff42715611d519677a4256bdd172ec98687f9 Signed-off-by: Craig Hesling <hesling(a)chromium.org> --- M src/mainboard/google/hatch/ramstage.c M src/mainboard/google/hatch/variants/baseboard/gpio.c M src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/hatch/variants/helios/Makefile.inc M src/mainboard/google/hatch/variants/helios/gpio.c A src/mainboard/google/hatch/variants/helios/ramstage.c M src/mainboard/google/hatch/variants/kindred/gpio.c M src/mainboard/google/hatch/variants/kohaku/Makefile.inc M src/mainboard/google/hatch/variants/kohaku/gpio.c A src/mainboard/google/hatch/variants/kohaku/ramstage.c 10 files changed, 92 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/37459/1 diff --git a/src/mainboard/google/hatch/ramstage.c b/src/mainboard/google/hatch/ramstage.c index e9f5062..e84aa18 100644 --- a/src/mainboard/google/hatch/ramstage.c +++ b/src/mainboard/google/hatch/ramstage.c @@ -31,6 +31,11 @@ /* Override dev tree settings per board */ } +void __weak variant_ramstage_init(void) +{ + /* Default weak implementation */ +} + static void mainboard_init(struct device *dev) { mainboard_ec_init(); @@ -56,6 +61,8 @@ base_gpios, override_table, override_gpios); + + variant_ramstage_init(); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 598600b..976950f 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -38,7 +38,7 @@ /* A11 : PCH_SPI_FPMCU_CS_L */ PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2), /* A12 : FPMCU_RST_ODL */ - PAD_CFG_GPO(GPP_A12, 1, DEEP), + PAD_CFG_GPO(GPP_A12, 0, DEEP), /* A13 : SUSWARN_L */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* A14 : ESPI_RST_L */ @@ -133,7 +133,7 @@ /* C10 : GPP_10 ==> GPP_C10_TP */ PAD_NC(GPP_C10, NONE), /* C11 : GPP_11 ==> EN_FP_RAILS */ - PAD_CFG_GPO(GPP_C11, 1, DEEP), + PAD_CFG_GPO(GPP_C11, 0, DEEP), /* C12 : GPP_C12 ==> NC */ PAD_NC(GPP_C12, NONE), /* C13 : EC_PCH_INT_L */ @@ -398,20 +398,19 @@ } /* - * Default GPIO settings before entering sleep. Configure A12: FPMCU_RST_ODL - * as GPO before entering sleep. + * Default GPIO settings before entering sleep. */ static const struct pad_config default_sleep_gpio_table[] = { - PAD_CFG_GPO(GPP_A12, 1, DEEP), /* FPMCU_RST_ODL */ }; /* * GPIO settings before entering S5, which are same as * default_sleep_gpio_table but also, - * turn off EN_PP3300_WWAN. + * turn off EN_PP3300_WWAN and FPMCU. */ static const struct pad_config s5_sleep_gpio_table[] = { - PAD_CFG_GPO(GPP_A12, 1, DEEP), /* FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_A12, 0, DEEP), /* FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_C11, 0, DEEP), /* PCH_FP_PWR_EN */ PAD_CFG_GPO(GPP_A18, 0, DEEP), /* EN_PP3300_WWAN */ }; diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h index 920e428..1542d9b 100644 --- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h @@ -50,4 +50,7 @@ /* Modify devictree settings during ramstage. */ void variant_devtree_update(void); +/* Perform variant specific initialization early on in ramstage. */ +void variant_ramstage_init(void); + #endif /* BASEBOARD_VARIANTS_H */ diff --git a/src/mainboard/google/hatch/variants/helios/Makefile.inc b/src/mainboard/google/hatch/variants/helios/Makefile.inc index fbd69c4..be074b7 100644 --- a/src/mainboard/google/hatch/variants/helios/Makefile.inc +++ b/src/mainboard/google/hatch/variants/helios/Makefile.inc @@ -17,4 +17,6 @@ romstage-y += memory.c bootblock-y += gpio.c + ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/hatch/variants/helios/gpio.c b/src/mainboard/google/hatch/variants/helios/gpio.c index 85eb3fc..ef87876 100644 --- a/src/mainboard/google/hatch/variants/helios/gpio.c +++ b/src/mainboard/google/hatch/variants/helios/gpio.c @@ -117,8 +117,6 @@ * needed in this table. */ static const struct pad_config early_gpio_table[] = { - /* A12 : FPMCU_RST_ODL */ - PAD_CFG_GPO(GPP_A12, 0, DEEP), /* B15 : H1_SLAVE_SPI_CS_L */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* B16 : H1_SLAVE_SPI_CLK */ @@ -127,8 +125,6 @@ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* B18 : H1_SLAVE_SPI_MOSI_R */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), - /* C11 : GPP_C11 ==> EN_FP_RAILS */ - PAD_CFG_GPO(GPP_C11, 1, DEEP), /* C14 : BT_DISABLE_L */ PAD_CFG_GPO(GPP_C14, 0, DEEP), /* PCH_WP_OD */ @@ -149,15 +145,24 @@ return early_gpio_table; } +static const struct pad_config s5_sleep_gpio_table[] = { + PAD_CFG_GPO(GPP_A12, 0, DEEP), /* FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_C11, 0, DEEP), /* PCH_FP_PWR_EN */ +}; + /* * GPIO settings before entering all sleep states */ static const struct pad_config sleep_gpio_table[] = { - PAD_CFG_GPO(GPP_A12, 1, DEEP), /* FPMCU_RST_ODL */ }; const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num) { + if (slp_typ == ACPI_S5) { + *num = ARRAY_SIZE(s5_sleep_gpio_table); + return s5_sleep_gpio_table; + } + *num = ARRAY_SIZE(sleep_gpio_table); return sleep_gpio_table; } diff --git a/src/mainboard/google/hatch/variants/helios/ramstage.c b/src/mainboard/google/hatch/variants/helios/ramstage.c new file mode 100644 index 0000000..8e735d1 --- /dev/null +++ b/src/mainboard/google/hatch/variants/helios/ramstage.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <delay.h> +#include <gpio.h> +#include <baseboard/variants.h> +#include <soc/gpio.h> + +void variant_ramstage_init(void) +{ + gpio_output(GPP_C11, 1); + mdelay(1); + gpio_output(GPP_A12, 1); +} diff --git a/src/mainboard/google/hatch/variants/kindred/gpio.c b/src/mainboard/google/hatch/variants/kindred/gpio.c index 827ee0b..9e2d818 100644 --- a/src/mainboard/google/hatch/variants/kindred/gpio.c +++ b/src/mainboard/google/hatch/variants/kindred/gpio.c @@ -154,8 +154,6 @@ * needed in this table. */ static const struct pad_config early_gpio_table[] = { - /* A12 : FPMCU_RST_ODL */ - PAD_CFG_GPO(GPP_A12, 0, DEEP), /* B15 : H1_SLAVE_SPI_CS_L */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* B16 : H1_SLAVE_SPI_CLK */ diff --git a/src/mainboard/google/hatch/variants/kohaku/Makefile.inc b/src/mainboard/google/hatch/variants/kohaku/Makefile.inc index 9cdff32..6bd2973 100644 --- a/src/mainboard/google/hatch/variants/kohaku/Makefile.inc +++ b/src/mainboard/google/hatch/variants/kohaku/Makefile.inc @@ -17,4 +17,6 @@ romstage-y += memory.c bootblock-y += gpio.c + ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/hatch/variants/kohaku/gpio.c b/src/mainboard/google/hatch/variants/kohaku/gpio.c index 61d3375..a455141 100644 --- a/src/mainboard/google/hatch/variants/kohaku/gpio.c +++ b/src/mainboard/google/hatch/variants/kohaku/gpio.c @@ -97,8 +97,6 @@ * needed in this table. */ static const struct pad_config early_gpio_table[] = { - /* A12 : FPMCU_RST_ODL */ - PAD_CFG_GPO(GPP_A12, 0, DEEP), /* B15 : H1_SLAVE_SPI_CS_L */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* B16 : H1_SLAVE_SPI_CLK */ @@ -135,15 +133,24 @@ return early_gpio_table; } +static const struct pad_config s5_sleep_gpio_table[] = { + PAD_CFG_GPO(GPP_A12, 0, DEEP), /* FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_C11, 0, DEEP), /* PCH_FP_PWR_EN */ +}; + /* * GPIO settings before entering all sleep states */ static const struct pad_config sleep_gpio_table[] = { - PAD_CFG_GPO(GPP_A12, 1, DEEP), /* FPMCU_RST_ODL */ }; const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num) { + if (slp_typ == ACPI_S5) { + *num = ARRAY_SIZE(s5_sleep_gpio_table); + return s5_sleep_gpio_table; + } + *num = ARRAY_SIZE(sleep_gpio_table); return sleep_gpio_table; } diff --git a/src/mainboard/google/hatch/variants/kohaku/ramstage.c b/src/mainboard/google/hatch/variants/kohaku/ramstage.c new file mode 100644 index 0000000..8e735d1 --- /dev/null +++ b/src/mainboard/google/hatch/variants/kohaku/ramstage.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <delay.h> +#include <gpio.h> +#include <baseboard/variants.h> +#include <soc/gpio.h> + +void variant_ramstage_init(void) +{ + gpio_output(GPP_C11, 1); + mdelay(1); + gpio_output(GPP_A12, 1); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/37459 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e3ff42715611d519677a4256bdd172ec98687f9 Gerrit-Change-Number: 37459 Gerrit-PatchSet: 1 Gerrit-Owner: Craig Hesling <hesling(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/mb/intel/coffeelake_rvp: Move the base of DT to baseboard
by Gaggery Tsai (Code Review) 05 Dec '19

05 Dec '19

Gaggery Tsai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36794 ) Change subject: src/mb/intel/coffeelake_rvp: Move the base of DT to baseboard ...................................................................... src/mb/intel/coffeelake_rvp: Move the base of DT to baseboard This patch moves the base of devicetree settings into baseboard and creates overridetree.cb for each variant. TEST=build an image for each variant Change-Id: I067bdb3fcf1218b93e52801f6db093e24d7d2b62 Signed-off-by: Gaggery Tsai <gaggery.tsai(a)intel.com> --- M src/mainboard/intel/coffeelake_rvp/Kconfig R src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb R src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb R src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb D src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb A src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb D src/mainboard/intel/coffeelake_rvp/variants/cml_u/devicetree.cb A src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb A src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb 9 files changed, 268 insertions(+), 488 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/36794/1 diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig b/src/mainboard/intel/coffeelake_rvp/Kconfig index e7c5d36..299d072 100644 --- a/src/mainboard/intel/coffeelake_rvp/Kconfig +++ b/src/mainboard/intel/coffeelake_rvp/Kconfig @@ -63,7 +63,11 @@ config DEVICETREE string - default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + default "variants/baseboard/devicetree.cb" + +config OVERRIDE_DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" config FMDFILE string diff --git a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb similarity index 68% rename from src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb rename to src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb index 429d5da..aa245cf 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb @@ -7,20 +7,9 @@ # FSP configuration register "SaGv" = "SaGv_Enabled" register "ScsEmmcHs400Enabled" = "1" - register "HeciEnabled" = "1" - # Enable eDP device - register "DdiPortEdp" = "1" - # Enable HPD for DDI ports B/C/D/F - register "DdiPortBHpd" = "1" - register "DdiPortCHpd" = "1" - register "DdiPortDHpd" = "1" - register "DdiPortFHpd" = "1" - # Enable DDC for DDI ports B/C/D/F - register "DdiPortBDdc" = "1" - register "DdiPortCDdc" = "1" - register "DdiPortDDdc" = "1" - register "DdiPortFDdc" = "1" + # HECI + register "HeciEnabled" = "1" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" @@ -40,16 +29,6 @@ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" - register "SataSalpSupport" = "1" - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[1]" = "1" - register "SataPortsEnable[2]" = "1" - register "SataPortsEnable[3]" = "1" - register "SataPortsEnable[4]" = "1" - register "SataPortsEnable[5]" = "1" - register "SataPortsEnable[6]" = "1" - register "SataPortsEnable[7]" = "1" - register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHda" = "1" @@ -87,8 +66,8 @@ # Enable "Intel Speed Shift Technology" register "speed_shift_enable" = "1" - # GPIO for SD card detect - register "sdcard_cd_gpio" = "GPP_G5" + # Disable S0ix + register "s0ix_enable" = "0" device domain 0 on device pci 00.0 on end # Host Bridge @@ -99,41 +78,37 @@ device pci 12.6 off end # GSPI #2 device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) - chip drivers/intel/wifi - register "wake" = "PME_B0_EN_BIT" - device pci 14.3 on end # CNVi wifi - end device pci 14.5 on end # SDCard device pci 15.0 on end # I2C #0 device pci 15.1 on end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 off end # I2C #3 + device pci 15.2 on end # I2C #2 + device pci 15.3 on end # I2C #3 device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection device pci 16.4 off end # Management Engine Interface 3 device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 on end # SATA - device pci 19.0 on end # I2C #4 - device pci 19.1 off end # I2C #5 + device pci 17.0 off end # SATA + device pci 19.0 off end # I2C #4 (Not available on PCH-H) + device pci 19.1 off end # I2C #5 (Not available on PCH-H) device pci 19.2 on end # UART #2 - device pci 1a.0 on end # eMMC + device pci 1a.0 off end # eMMC device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1 device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 + device pci 1c.5 on end # PCI Express Port 6 + device pci 1c.6 on end # PCI Express Port 7 + device pci 1c.7 on end # PCI Express Port 8 device pci 1d.0 on end # PCI Express Port 9 - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 off end # PCI Express Port 13 - device pci 1d.5 off end # PCI Express Port 14 - device pci 1d.6 off end # PCI Express Port 15 - device pci 1d.7 off end # PCI Express Port 16 + device pci 1d.1 on end # PCI Express Port 10 + device pci 1d.2 on end # PCI Express Port 11 + device pci 1d.3 on end # PCI Express Port 12 + device pci 1d.4 on end # PCI Express Port 13 + device pci 1d.5 on end # PCI Express Port 14 + device pci 1d.6 on end # PCI Express Port 15 + device pci 1d.7 on end # PCI Express Port 16 device pci 1e.0 on end # UART #0 - device pci 1e.1 off end # UART #1 + device pci 1e.1 on end # UART #1 device pci 1e.2 off end # GSPI #0 device pci 1e.3 off end # GSPI #1 device pci 1f.0 on @@ -146,6 +121,6 @@ device pci 1f.3 on end # Intel HDA device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI - device pci 1f.6 on end # GbE + device pci 1f.6 off end # GbE end end diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb similarity index 62% rename from src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb rename to src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb index 9648ac3..e21a782 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb @@ -5,9 +5,7 @@ end # FSP configuration - register "SaGv" = "SaGv_Enabled" register "RMT" = "1" - register "ScsEmmcHs400Enabled" = "1" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC5)" register "usb2_ports[1]" = "USB2_PORT_MID(OC6)" @@ -48,22 +46,6 @@ register "PchHdaDspEnable" = "0" register "PchHdaAudioLinkHda" = "1" - register "PcieRpEnable[0]" = "1" - register "PcieRpEnable[1]" = "1" - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[5]" = "1" - register "PcieRpEnable[6]" = "1" - register "PcieRpEnable[7]" = "1" - register "PcieRpEnable[8]" = "1" - register "PcieRpEnable[9]" = "1" - register "PcieRpEnable[10]" = "1" - register "PcieRpEnable[11]" = "1" - register "PcieRpEnable[12]" = "1" - register "PcieRpEnable[13]" = "1" - register "PcieRpEnable[14]" = "1" - register "PcieRpEnable[15]" = "1" register "PcieRpEnable[16]" = "1" register "PcieRpEnable[17]" = "1" register "PcieRpEnable[18]" = "1" @@ -91,42 +73,14 @@ register "PcieClkSrcClkReq[8]" = "8" register "PcieClkSrcClkReq[9]" = "9" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - - # HECI - register "HeciEnabled" = "1" - device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on end # SA Thermal device - device pci 12.0 on end # Thermal Subsystem - device pci 12.5 off end # UFS SCS - device pci 12.6 off end # GSPI #2 - device pci 14.0 on end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) - device pci 14.5 on end # SDCard - device pci 15.0 on end # I2C #0 - device pci 15.1 on end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 16.5 off end # Management Engine Interface 4 device pci 17.0 on end # SATA - device pci 19.0 off end # I2C #4 - device pci 19.2 on end # UART #2 device pci 1a.0 on end # eMMC - device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1 - device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 device pci 1d.1 off end # PCI Express Port 10 device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 @@ -134,20 +88,9 @@ device pci 1d.5 off end # PCI Express Port 14 device pci 1d.6 off end # PCI Express Port 15 device pci 1d.7 off end # PCI Express Port 16 - device pci 1e.0 on end # UART #0 device pci 1e.1 off end # UART #1 device pci 1e.2 off end # GSPI #0 device pci 1e.3 off end # GSPI #1 - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - end # LPC Interface - device pci 1f.1 on end # P2SB - device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI device pci 1f.6 on end # GbE end end diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb similarity index 63% rename from src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb rename to src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb index 126cab0..618ac3b 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb @@ -5,9 +5,7 @@ end # FSP configuration - register "SaGv" = "SaGv_Enabled" register "RMT" = "1" - register "ScsEmmcHs400Enabled" = "1" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC4)" register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)" @@ -48,22 +46,6 @@ register "PchHdaDspEnable" = "0" register "PchHdaAudioLinkHda" = "1" - register "PcieRpEnable[0]" = "1" - register "PcieRpEnable[1]" = "1" - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[5]" = "1" - register "PcieRpEnable[6]" = "1" - register "PcieRpEnable[7]" = "1" - register "PcieRpEnable[8]" = "1" - register "PcieRpEnable[9]" = "1" - register "PcieRpEnable[10]" = "1" - register "PcieRpEnable[11]" = "1" - register "PcieRpEnable[12]" = "1" - register "PcieRpEnable[13]" = "1" - register "PcieRpEnable[14]" = "1" - register "PcieRpEnable[15]" = "1" register "PcieRpEnable[16]" = "1" register "PcieRpEnable[17]" = "1" register "PcieRpEnable[18]" = "1" @@ -95,46 +77,15 @@ register "PcieClkSrcClkReq[9]" = "9" register "PcieClkSrcClkReq[10]" = "10" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - - # HECI - register "HeciEnabled" = "1" - device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on end # SA Thermal device - device pci 12.0 on end # Thermal Subsystem - device pci 12.5 off end # UFS SCS - device pci 12.6 off end # GSPI #2 - device pci 14.0 on end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) chip drivers/intel/wifi register "wake" = "PME_B0_EN_BIT" device pci 14.3 on end # CNVi wifi end - device pci 14.5 on end # SDCard - device pci 15.0 on end # I2C 0 - device pci 15.1 on end # I2C #1 - device pci 15.2 on end # I2C #2 - device pci 15.3 on end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 16.5 off end # Management Engine Interface 4 device pci 17.0 on end # SATA - device pci 19.0 off end # I2C #4 - device pci 19.2 on end # UART #2 - device pci 1a.0 on end # eMMC - device pci 1c.0 on end # PCI Express Port 1 - device pci 1c.4 on end # PCI Express Port 5 device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 X4 SLOT 1 device pci 1d.1 off end # PCI Express Port 10 device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 @@ -144,20 +95,9 @@ device pci 1d.7 off end # PCI Express Port 16 device pci 1b.0 on end # PCI Express Port 17 device pci 1b.4 on end # PCI Express Port 21 X4 SLOT 2 - device pci 1e.0 on end # UART #0 device pci 1e.1 off end # UART #1 device pci 1e.2 off end # GSPI #0 device pci 1e.3 off end # GSPI #1 - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - end # LPC Interface - device pci 1f.1 on end # P2SB - device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI device pci 1f.6 on end # GbE end end diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb deleted file mode 100644 index e5f867c..0000000 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb +++ /dev/null @@ -1,156 +0,0 @@ -chip soc/intel/cannonlake - - device cpu_cluster 0 on - device lapic 0 on end - end - - # FSP configuration - register "SaGv" = "SaGv_Enabled" - register "ScsEmmcHs400Enabled" = "1" - - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" - register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[8]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[9]" = "USB2_PORT_MID(OC0)" - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" - - register "PchHdaDspEnable" = "1" - register "PchHdaAudioLinkHda" = "1" - - register "PcieRpEnable[0]" = "1" - register "PcieRpEnable[1]" = "1" - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[5]" = "1" - register "PcieRpEnable[6]" = "1" - register "PcieRpEnable[7]" = "1" - register "PcieRpEnable[8]" = "1" - register "PcieRpEnable[9]" = "1" - register "PcieRpEnable[10]" = "1" - register "PcieRpEnable[11]" = "1" - register "PcieRpEnable[12]" = "1" - register "PcieRpEnable[13]" = "1" - register "PcieRpEnable[14]" = "1" - register "PcieRpEnable[15]" = "1" - - register "PcieClkSrcUsage[0]" = "1" - register "PcieClkSrcUsage[1]" = "8" - register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN" - register "PcieClkSrcUsage[3]" = "13" - register "PcieClkSrcUsage[4]" = "4" - register "PcieClkSrcUsage[5]" = "14" - - register "PcieClkSrcClkReq[0]" = "0" - register "PcieClkSrcClkReq[1]" = "1" - register "PcieClkSrcClkReq[2]" = "2" - register "PcieClkSrcClkReq[3]" = "3" - register "PcieClkSrcClkReq[4]" = "4" - register "PcieClkSrcClkReq[5]" = "5" - - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - - # GPIO for SD card detect - register "sdcard_cd_gpio" = "GPP_G5" - - # Enable S0ix - register "s0ix_enable" = "1" - - # Intel Common SoC Config - #+-------------------+---------------------------+ - #| Field | Value | - #+-------------------+---------------------------+ - #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | - #| I2C3 | Audio | - #+-------------------+---------------------------+ - register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - .i2c[3] = { - .speed = I2C_SPEED_STANDARD, - .rise_time_ns = 104, - .fall_time_ns = 52, - }, - }" - - device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on end # SA Thermal device - device pci 12.0 on end # Thermal Subsystem - device pci 12.5 off end # UFS SCS - device pci 12.6 off end # GSPI #2 - device pci 14.0 on end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) - chip drivers/intel/wifi - register "wake" = "PME_B0_EN_BIT" - device pci 14.3 on end # CNVi wifi - end - device pci 14.5 on end # SDCard - device pci 15.0 on end # I2C #0 - device pci 15.1 on end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 on - chip drivers/i2c/max98373 - register "interleave_mode" = "1" - register "vmon_slot_no" = "4" - register "imon_slot_no" = "5" - register "uid" = "0" - register "desc" = ""Right Speaker Amp"" - register "name" = ""MAXR"" - device i2c 32 on end - end - end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 off end # SATA - device pci 19.0 on end # I2C #4 - device pci 19.1 off end # I2C #5 - device pci 19.2 on end # UART #2 - device pci 1a.0 on end # eMMC - device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1 - device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 off end # PCI Express Port 13 - device pci 1d.5 off end # PCI Express Port 14 - device pci 1d.6 off end # PCI Express Port 15 - device pci 1d.7 off end # PCI Express Port 16 - device pci 1e.0 on end # UART #0 - device pci 1e.1 off end # UART #1 - device pci 1e.2 off end # GSPI #0 - device pci 1e.3 off end # GSPI #1 - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - end # LPC Interface - device pci 1f.1 on end # P2SB - device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE - end -end diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb new file mode 100644 index 0000000..11d93f8 --- /dev/null +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb @@ -0,0 +1,81 @@ +chip soc/intel/cannonlake + + device cpu_cluster 0 on + device lapic 0 on end + end + + register "PchHdaDspEnable" = "1" + register "PchHdaAudioLinkHda" = "1" + + register "PcieClkSrcUsage[0]" = "1" + register "PcieClkSrcUsage[1]" = "8" + register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN" + register "PcieClkSrcUsage[3]" = "13" + register "PcieClkSrcUsage[4]" = "4" + register "PcieClkSrcUsage[5]" = "14" + + register "PcieClkSrcClkReq[0]" = "0" + register "PcieClkSrcClkReq[1]" = "1" + register "PcieClkSrcClkReq[2]" = "2" + register "PcieClkSrcClkReq[3]" = "3" + register "PcieClkSrcClkReq[4]" = "4" + register "PcieClkSrcClkReq[5]" = "5" + + # GPIO for SD card detect + register "sdcard_cd_gpio" = "GPP_G5" + + # Enable S0ix + register "s0ix_enable" = "1" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | + #| I2C3 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .i2c[3] = { + .speed = I2C_SPEED_STANDARD, + .rise_time_ns = 104, + .fall_time_ns = 52, + }, + }" + + device domain 0 on + chip drivers/intel/wifi + register "wake" = "PME_B0_EN_BIT" + device pci 14.3 on end # CNVi wifi + end + device pci 15.2 off end # I2C #2 + device pci 15.3 on + chip drivers/i2c/max98373 + register "interleave_mode" = "1" + register "vmon_slot_no" = "4" + register "imon_slot_no" = "5" + register "uid" = "0" + register "desc" = ""Right Speaker Amp"" + register "name" = ""MAXR"" + device i2c 32 on end + end + end # I2C #3 + device pci 19.0 on end # I2C #4 + device pci 1a.0 on end # eMMC + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 off end # PCI Express Port 13 + device pci 1d.5 off end # PCI Express Port 14 + device pci 1d.6 off end # PCI Express Port 15 + device pci 1d.7 off end # PCI Express Port 16 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/devicetree.cb deleted file mode 100644 index 241ac33..0000000 --- a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/devicetree.cb +++ /dev/null @@ -1,167 +0,0 @@ -chip soc/intel/cannonlake - - device cpu_cluster 0 on - device lapic 0 on end - end - - # FSP configuration - register "SaGv" = "SaGv_Enabled" - register "ScsEmmcHs400Enabled" = "1" - register "HeciEnabled" = "1" - register "s0ix_enable" = "1" - - # Enable eDP device - register "DdiPortEdp" = "1" - # Enable HPD for DDI ports B/C - register "DdiPortBHpd" = "1" - register "DdiPortCHpd" = "1" - register "DdiPortDHpd" = "1" - register "DdiPortFHpd" = "1" - # Enable DDC for DDI ports B/C - register "DdiPortBDdc" = "1" - register "DdiPortCDdc" = "1" - register "DdiPortDDdc" = "1" - register "DdiPortFDdc" = "1" - - register "SerialIoDevMode" = "{ - [PchSerialIoIndexI2C0] = PchSerialIoPci, - [PchSerialIoIndexI2C1] = PchSerialIoPci, - [PchSerialIoIndexI2C2] = PchSerialIoPci, - [PchSerialIoIndexI2C3] = PchSerialIoPci, - [PchSerialIoIndexI2C4] = PchSerialIoDisabled, - [PchSerialIoIndexI2C5] = PchSerialIoPci, - [PchSerialIoIndexSPI0] = PchSerialIoPci, - [PchSerialIoIndexSPI1] = PchSerialIoPci, - [PchSerialIoIndexSPI2] = PchSerialIoDisabled, - [PchSerialIoIndexUART0] = PchSerialIoSkipInit, - [PchSerialIoIndexUART1] = PchSerialIoDisabled, - [PchSerialIoIndexUART2] = PchSerialIoSkipInit, - }" - - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" - register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[8]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[9]" = "USB2_PORT_MID(OC0)" - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" - - register "SataSalpSupport" = "1" - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[1]" = "1" - register "SataPortsEnable[2]" = "1" - register "SataPortsEnable[3]" = "1" - register "SataPortsEnable[4]" = "1" - register "SataPortsEnable[5]" = "1" - register "SataPortsEnable[6]" = "1" - register "SataPortsEnable[7]" = "1" - - register "PchHdaDspEnable" = "1" - register "PchHdaAudioLinkHda" = "1" - - register "PcieRpEnable[0]" = "1" - register "PcieRpEnable[1]" = "1" - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[5]" = "1" - register "PcieRpEnable[6]" = "1" - register "PcieRpEnable[7]" = "1" - register "PcieRpEnable[8]" = "1" - register "PcieRpEnable[9]" = "1" - register "PcieRpEnable[10]" = "1" - register "PcieRpEnable[11]" = "1" - register "PcieRpEnable[12]" = "1" - register "PcieRpEnable[13]" = "1" - register "PcieRpEnable[14]" = "1" - register "PcieRpEnable[15]" = "1" - - register "PcieClkSrcUsage[0]" = "1" - register "PcieClkSrcUsage[1]" = "8" - register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN" - register "PcieClkSrcUsage[3]" = "13" - register "PcieClkSrcUsage[4]" = "4" - register "PcieClkSrcUsage[5]" = "14" - - register "PcieClkSrcClkReq[0]" = "0" - register "PcieClkSrcClkReq[1]" = "1" - register "PcieClkSrcClkReq[2]" = "2" - register "PcieClkSrcClkReq[3]" = "3" - register "PcieClkSrcClkReq[4]" = "4" - register "PcieClkSrcClkReq[5]" = "5" - - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - - # GPIO for SD card detect - register "sdcard_cd_gpio" = "GPP_G5" - - device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on end # SA Thermal device - device pci 12.0 on end # Thermal Subsystem - device pci 12.5 off end # UFS SCS - device pci 12.6 off end # GSPI #2 - device pci 14.0 on end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) - chip drivers/intel/wifi - register "wake" = "PME_B0_EN_BIT" - device pci 14.3 on end # CNVi wifi - end - device pci 14.5 on end # SDCard - device pci 15.0 on end # I2C #0 - device pci 15.1 on end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 off end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 on end # SATA - device pci 19.0 on end # I2C #4 - device pci 19.1 off end # I2C #5 - device pci 19.2 on end # UART #2 - device pci 1a.0 on end # eMMC - device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1 - device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 off end # PCI Express Port 13 - device pci 1d.5 off end # PCI Express Port 14 - device pci 1d.6 off end # PCI Express Port 15 - device pci 1d.7 off end # PCI Express Port 16 - device pci 1e.0 on end # UART #0 - device pci 1e.1 off end # UART #1 - device pci 1e.2 off end # GSPI #0 - device pci 1e.3 off end # GSPI #1 - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - end # LPC Interface - device pci 1f.1 on end # P2SB - device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI - device pci 1f.6 on end # GbE - end -end diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb new file mode 100644 index 0000000..76a8a1b --- /dev/null +++ b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb @@ -0,0 +1,86 @@ +chip soc/intel/cannonlake + + device cpu_cluster 0 on + device lapic 0 on end + end + + # Enable eDP device + register "DdiPortEdp" = "1" + # Enable HPD for DDI ports B/C + register "DdiPortBHpd" = "1" + register "DdiPortCHpd" = "1" + register "DdiPortDHpd" = "1" + register "DdiPortFHpd" = "1" + # Enable DDC for DDI ports B/C + register "DdiPortBDdc" = "1" + register "DdiPortCDdc" = "1" + register "DdiPortDDdc" = "1" + register "DdiPortFDdc" = "1" + + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexSPI0] = PchSerialIoPci, + [PchSerialIoIndexSPI1] = PchSerialIoPci, + [PchSerialIoIndexSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoSkipInit, + }" + + register "SataSalpSupport" = "1" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsEnable[2]" = "1" + register "SataPortsEnable[3]" = "1" + register "SataPortsEnable[4]" = "1" + register "SataPortsEnable[5]" = "1" + register "SataPortsEnable[6]" = "1" + register "SataPortsEnable[7]" = "1" + + register "PchHdaDspEnable" = "1" + register "PchHdaAudioLinkHda" = "1" + + register "PcieClkSrcUsage[0]" = "1" + register "PcieClkSrcUsage[1]" = "8" + register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN" + register "PcieClkSrcUsage[3]" = "13" + register "PcieClkSrcUsage[4]" = "4" + register "PcieClkSrcUsage[5]" = "14" + + register "PcieClkSrcClkReq[0]" = "0" + register "PcieClkSrcClkReq[1]" = "1" + register "PcieClkSrcClkReq[2]" = "2" + register "PcieClkSrcClkReq[3]" = "3" + register "PcieClkSrcClkReq[4]" = "4" + register "PcieClkSrcClkReq[5]" = "5" + + # GPIO for SD card detect + register "sdcard_cd_gpio" = "GPP_G5" + + device domain 0 on + chip drivers/intel/wifi + register "wake" = "PME_B0_EN_BIT" + device pci 14.3 on end # CNVi wifi + end + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 17.0 on end # SATA + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 off end # PCI Express Port 13 + device pci 1d.5 off end # PCI Express Port 14 + device pci 1d.6 off end # PCI Express Port 15 + device pci 1d.7 off end # PCI Express Port 16 + device pci 1e.1 off end # UART #1 + device pci 1f.6 on end # GbE + end +end diff --git a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb new file mode 100644 index 0000000..3e8baf7 --- /dev/null +++ b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb @@ -0,0 +1,74 @@ +chip soc/intel/cannonlake + + device cpu_cluster 0 on + device lapic 0 on end + end + + # Enable eDP device + register "DdiPortEdp" = "1" + # Enable HPD for DDI ports B/C/D/F + register "DdiPortBHpd" = "1" + register "DdiPortCHpd" = "1" + register "DdiPortDHpd" = "1" + register "DdiPortFHpd" = "1" + # Enable DDC for DDI ports B/C/D/F + register "DdiPortBDdc" = "1" + register "DdiPortCDdc" = "1" + register "DdiPortDDdc" = "1" + register "DdiPortFDdc" = "1" + + register "SataSalpSupport" = "1" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsEnable[2]" = "1" + register "SataPortsEnable[3]" = "1" + register "SataPortsEnable[4]" = "1" + register "SataPortsEnable[5]" = "1" + register "SataPortsEnable[6]" = "1" + register "SataPortsEnable[7]" = "1" + + register "PchHdaDspEnable" = "1" + register "PchHdaAudioLinkHda" = "1" + + register "PcieClkSrcUsage[0]" = "1" + register "PcieClkSrcUsage[1]" = "8" + register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN" + register "PcieClkSrcUsage[3]" = "13" + register "PcieClkSrcUsage[4]" = "4" + register "PcieClkSrcUsage[5]" = "14" + + register "PcieClkSrcClkReq[0]" = "0" + register "PcieClkSrcClkReq[1]" = "1" + register "PcieClkSrcClkReq[2]" = "2" + register "PcieClkSrcClkReq[3]" = "3" + register "PcieClkSrcClkReq[4]" = "4" + register "PcieClkSrcClkReq[5]" = "5" + + # GPIO for SD card detect + register "sdcard_cd_gpio" = "GPP_G5" + + device domain 0 on + chip drivers/intel/wifi + register "wake" = "PME_B0_EN_BIT" + device pci 14.3 on end # CNVi wifi + end + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 17.0 on end # SATA + device pci 19.0 on end # I2C #4 + device pci 1a.0 on end # eMMC + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 off end # PCI Express Port 13 + device pci 1d.5 off end # PCI Express Port 14 + device pci 1d.6 off end # PCI Express Port 15 + device pci 1d.7 off end # PCI Express Port 16 + device pci 1e.1 off end # UART #1 + device pci 1f.6 on end # GbE + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/36794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I067bdb3fcf1218b93e52801f6db093e24d7d2b62 Gerrit-Change-Number: 36794 Gerrit-PatchSet: 1 Gerrit-Owner: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[4.11_branch]: mainboard/facebook/watson: Reclaim unused flash space
by Andrey Petrov (Code Review) 05 Dec '19

05 Dec '19

Andrey Petrov has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37474 ) Change subject: mainboard/facebook/watson: Reclaim unused flash space ...................................................................... mainboard/facebook/watson: Reclaim unused flash space Currently FMAP does not allocate all the usable space. This change addresses that by removing unused section and expanding CBFS section. TEST=tested on actual watson HW Change-Id: I5f407c11031822d58f11f1a4684845d57653b190 Signed-off-by: Andrey Petrov <anpetrov(a)fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37474 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/mainboard/facebook/watson/board.fmd 1 file changed, 1 insertion(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved Frans Hendriks: Looks good to me, but someone else must approve diff --git a/src/mainboard/facebook/watson/board.fmd b/src/mainboard/facebook/watson/board.fmd index feeb799..e2b8f58 100644 --- a/src/mainboard/facebook/watson/board.fmd +++ b/src/mainboard/facebook/watson/board.fmd @@ -20,7 +20,6 @@ # This only exists to satisfy tools that specifically # look for RO_VPD. RO_VPD@0x30000 0x1000 - UNUSED_4@0x31000 0x1cf000 - COREBOOT(CBFS)@0x200000 0x800000 + COREBOOT(CBFS)@0x31000 0x9cf000 } } -- To view, visit https://review.coreboot.org/c/coreboot/+/37474 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: I5f407c11031822d58f11f1a4684845d57653b190 Gerrit-Change-Number: 37474 Gerrit-PatchSet: 2 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[4.11_branch]: [BACKPORT] arch/x86: SMBIOS: Improve core count reporting
by Andrey Petrov (Code Review) 05 Dec '19

05 Dec '19

Andrey Petrov has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37089 ) Change subject: [BACKPORT] arch/x86: SMBIOS: Improve core count reporting ...................................................................... [BACKPORT] arch/x86: SMBIOS: Improve core count reporting Current code uses CPUID leaf 0x1, EBX bits 16:23 to determine number for "core count". However, it turns out this number has little to do with real number of cores. According to SDM vol 2A, it stays for "maximum number of addressable IDs for logical processors in this physical package". This does not seem to take into account fusing of giving processor. The new code determines 'core count' by dividing thread-level cpus by reported logical cores. This seems to be the only way to arrive to number of cores as it is reported in official CPU datasheet. TEST=tested on OCP monolake Change-Id: Id4ba9e3079f92ffe38f9104ffcfafe62582dd259 Signed-off-by: Andrey Petrov <anpetrov(a)fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36941 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> (cherry picked from commit 515ef38db40cc44592770c00be8e4980bbaccc69) Reviewed-on: https://review.coreboot.org/c/coreboot/+/37089 --- M src/arch/x86/smbios.c 1 file changed, 20 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 725d808..7deac63 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -657,7 +657,26 @@ t->processor_version = smbios_processor_name(t->eos); t->processor_family = (res.eax > 0) ? 0x0c : 0x6; t->processor_type = 3; /* System Processor */ - t->core_count = (res.ebx >> 16) & 0xff; + /* + * If CPUID leaf 11 is available, calculate "core count" by dividing + * SMT_ID (logical processors in a core) by Core_ID (number of cores). + * This seems to be the way to arrive to a number of cores mentioned on + * ark.intel.com. + */ + if (cpu_have_cpuid() && cpuid_get_max_func() >= 0xb) { + uint32_t leaf_b_cores = 0, leaf_b_threads = 0; + res = cpuid_ext(0xb, 1); + leaf_b_cores = res.ebx; + res = cpuid_ext(0xb, 0); + leaf_b_threads = res.ebx; + /* if hyperthreading is not available, pretend this is 1 */ + if (leaf_b_threads == 0) { + leaf_b_threads = 1; + } + t->core_count = leaf_b_cores / leaf_b_threads; + } else { + t->core_count = (res.ebx >> 16) & 0xff; + } /* Assume we enable all the cores always, capped only by MAX_CPUS */ t->core_enabled = MIN(t->core_count, CONFIG_MAX_CPUS); t->l1_cache_handle = 0xffff; -- To view, visit https://review.coreboot.org/c/coreboot/+/37089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: Id4ba9e3079f92ffe38f9104ffcfafe62582dd259 Gerrit-Change-Number: 37089 Gerrit-PatchSet: 2 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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